Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a plurality of circuit units, each circuit unit comprises a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line, the pixel driving circuit at least comprises a first transistor, a seventh transistor and an eighth transistor, the first initial signal line is connected with a first electrode of the first transistor, and the second initial signal line is connected with a second electrode of the third transistor. The second initial signal line is connected with the first pole of the seventh transistor, and the third initial signal line is connected with the first pole of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share the first electrode of the eighth transistor. According to the invention, pixel driving circuit nodes are shared, so that high resolution can be realized.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field. Utility Model Content

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The technical problem to be solved by the present disclosure is to provide a display substrate and a display device to improve the resolution of the display device.

[0005] On the one hand, the present disclosure provides a display substrate, including a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, the driving structure layer including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; the pixel driving circuit includes at least a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initial signal line is connected to a first electrode of the first transistor, the second initial signal line is connected to a first electrode of the seventh transistor, and the third initial signal line is connected to a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share the first electrode of the eighth transistor.

[0006] In an exemplary embodiment, the first transistor includes at least a first active layer, the first initial signal line is connected to the first region of the first active layer through a sixth connection electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the sixth connection electrode.

[0007] In an exemplary embodiment, the seventh transistor includes at least a seventh active layer, and the second initial signal line is connected to the first region of the seventh active layer through a second initial connection block; in at least one unit row, the pixel driving circuits in adjacent circuit units share the second initial connection block.

[0008] In an exemplary embodiment, the eighth transistor includes at least an eighth active layer, the third initial signal line is connected to the first region of the eighth active layer through a seventh connecting electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the seventh connecting electrode.

[0009] In an exemplary embodiment, the first initial signal line, the second initial signal line and the third initial signal line extend along a first direction, the driving structure layer also includes a first initial connection line, a second initial connection line and a third initial connection line extending along a second direction, and the first direction intersects the second direction; the first initial connection line is connected to the first initial signal line through a sixth connection electrode to form a mesh connection structure for transmitting a first initial signal, or the second initial connection line is connected to the second initial signal line through an eighth connection electrode to form a mesh connection structure for transmitting a second initial signal, or the third initial connection line is connected to the third initial signal line through a seventh connection electrode to form a mesh connection structure for transmitting a third initial signal.

[0010] In an exemplary embodiment, the first initial connection line, the second initial connection line, and the third initial connection line are respectively disposed between adjacent cell columns, and the first initial connection line, the second initial connection line, the third initial connection line, and the second initial connection line are periodically disposed in the first direction.

[0011] In an exemplary embodiment, the light emitting structure layer includes at least a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light, and a plurality of second green light emitting units emitting green light, the red light emitting unit includes at least a first anode, the blue light emitting unit includes at least a second anode, the first green light emitting unit includes at least a third anode, and the second green light emitting unit includes at least a fourth anode, and at least one of the first anode, the second anode, the third anode, and the fourth anode includes a main body portion and a connecting portion connected to each other, a first end of the connecting portion is connected to the main body portion, and a second end of the connecting portion is connected to the anode connecting electrode in the pixel driving circuit through an anode via hole; the orthographic projections of the main body portions of the third anode and the fourth anode on the substrate at least partially overlap with the orthographic projections of the first initial connection line on the substrate, or the orthographic projections of the main body portions of the third anode and the fourth anode on the substrate at least partially overlap with the orthographic projections of the second initial connection line on the substrate, or the orthographic projections of the main body portions of the third anode and the fourth anode on the substrate at least partially overlap with the orthographic projections of the third initial connection line on the substrate.

[0012] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer includes at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the first initial signal line, the second initial signal line and the third initial signal line are respectively arranged in at least one layer of the second conductive layer and the third conductive layer, and the first initial connection line, the second initial connection line and the third initial connection line are arranged in the fourth conductive layer.

[0013] In an exemplary embodiment, the driving structure layer also includes a first flat layer arranged on a side of the third conductive layer away from the substrate, and the fourth conductive layer is arranged on a side of the first flat layer away from the substrate; at least one circuit unit also includes a connecting via, and the third initial connecting line is connected to the seventh connecting electrode through the connecting via; at least another circuit unit also includes a dummy via, and the first initial connecting line and / or the second initial connecting line are at least partially arranged in the dummy via.

[0014] In an exemplary embodiment, the light emitting structure layer includes at least a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light, and a plurality of second green light emitting units emitting green light, the red light emitting unit includes at least a first anode, the blue light emitting unit includes at least a second anode, the first green light emitting unit includes at least a third anode, the second green light emitting unit includes at least a fourth anode, at least one of the first anode, the second anode, the third anode and the fourth anode includes a main body and a connecting portion connected to each other, a first end of the connecting portion is connected to the main body, and a second end of the connecting portion is connected to an anode connecting electrode in the pixel driving circuit through an anode via hole; an orthographic projection of the main body of the third anode on the substrate at least partially overlaps with an orthographic projection of the connecting via hole on the substrate, and an orthographic projection of the main body of the fourth anode on the substrate at least partially overlaps with an orthographic projection of the dummy via hole on the substrate; or, an orthographic projection of the main body of the third anode on the substrate at least partially overlaps with an orthographic projection of the dummy via hole on the substrate, and an orthographic projection of the main body of the fourth anode on the substrate at least partially overlaps with an orthographic projection of the connecting via hole on the substrate.

[0015] In an exemplary embodiment, the light emitting structure layer includes at least a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light, and a plurality of second green light emitting units emitting green light, the red light emitting unit includes at least a first anode, the blue light emitting unit includes at least a second anode, the first green light emitting unit includes at least a third anode, the second green light emitting unit includes at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode includes a main body portion and a connecting portion connected to each other, and a first end of the connecting portion is connected to the main body portion. The second end of the connecting portion is connected to the anode connecting electrode in the pixel driving circuit through the anode via; the orthographic projection of the main portion of the third anode on the substrate and the orthographic projection of the connecting via on the substrate at least partially do not overlap, and the orthographic projection of the main portion of the fourth anode on the substrate and the orthographic projection of the dummy via on the substrate at least partially do not overlap; or, the orthographic projection of the main portion of the third anode on the substrate and the orthographic projection of the dummy via on the substrate at least partially do not overlap, and the orthographic projection of the main portion of the fourth anode on the substrate and the orthographic projection of the connecting via on the substrate at least partially do not overlap.

[0016] In an exemplary embodiment, the eighth connecting electrode includes a connecting electrode strip and a connecting electrode block, the connecting electrode strip is in the shape of a strip extending along the second direction, the connecting electrode block is in the shape of a block, the first end of the connecting electrode strip is connected to the second initial signal line, the second end of the connecting electrode strip extends in a direction away from the second initial signal line and is connected to the connecting electrode block, and the second initial connecting line is connected to the connecting electrode block through a via; at least one circuit unit also includes a dummy electrode strip, the first end of the dummy electrode strip is connected to the second initial signal line, the second end of the dummy electrode strip extends in a direction away from the second initial signal line; the connecting electrode strips and the dummy electrode strips are alternately arranged in the first direction.

[0017] In an exemplary embodiment, at least one circuit unit further includes a dummy electrode block and a dummy via, wherein the dummy electrode block is in a block shape and is connected to the second end of the dummy electrode strip, the orthographic projection of the dummy via on the substrate is within the range of the orthographic projection of the dummy electrode block on the substrate, and the first initial connection line and / or the third initial connection line are at least partially arranged in the dummy via.

[0018] In an exemplary embodiment, the connection electrode block and the dummy electrode block are located on a straight line extending along the first direction.

[0019] In an exemplary embodiment, the light emitting structure layer includes at least a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light, and a plurality of second green light emitting units emitting green light, the red light emitting unit includes at least a first anode, the blue light emitting unit includes at least a second anode, the first green light emitting unit includes at least a third anode, and the second green light emitting unit includes at least a fourth anode, and at least one of the first anode, the second anode, the third anode, and the fourth anode includes a main body and a connecting portion that are connected to each other, a first end of the connecting portion is connected to the main body, and a second end of the connecting portion is connected to an anode connecting electrode in the pixel driving circuit through an anode via hole; an orthographic projection of the main body of the third anode on the substrate at least partially overlaps with an orthographic projection of the connecting electrode strip on the substrate, and an orthographic projection of the main body of the fourth anode on the substrate at least partially overlaps with an orthographic projection of the dummy electrode strip on the substrate; or, an orthographic projection of the main body of the third anode on the substrate at least partially overlaps with an orthographic projection of the dummy electrode strip on the substrate, and an orthographic projection of the main body of the fourth anode on the substrate at least partially overlaps with an orthographic projection of the connecting electrode strip on the substrate.

[0020] In an exemplary embodiment, the pixel driving circuit also includes a second transistor as a compensation transistor and a third transistor as a driving transistor, the first electrode of the second transistor is respectively connected to the second electrode of the first transistor and the gate electrode of the third transistor, and the second electrode of the second transistor is connected to the second electrode of the third transistor; the first transistor and the second transistor are a dual-gate structure.

[0021] In an exemplary embodiment, the driving structure layer also includes a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, wherein the first direction and the second direction intersect; at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, the first ends of the plurality of first connecting lines are correspondingly connected to the plurality of data signal lines, and the second ends of the plurality of first connecting lines are correspondingly connected to the plurality of second connecting lines.

[0022] In an exemplary embodiment, the light-emitting structure layer includes at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting unit includes at least a first anode, the blue light-emitting unit includes at least a second anode, the first green light-emitting unit includes at least a third anode, and the second green light-emitting unit includes at least a fourth anode, and at least one of the first anode, the second anode, the third anode and the fourth anode includes a main body and a connecting part that are connected to each other, a first end of the connecting part is connected to the main body, and a second end of the connecting part is connected to the anode connecting electrode in the pixel driving circuit through an anode via; the orthographic projections of the main body of the first anode and the main body of the second anode on the substrate at least partially overlap with the orthographic projection of the second connecting line on the substrate.

[0023] In an exemplary embodiment, the driving structure layer also includes a data connection electrode, and the second connection line is connected to the data connection electrode through a via; the orthographic projection of the data connection electrode on the substrate is located within the range of the orthographic projection of the main body of the first anode on the substrate, and / or the orthographic projection of the data connection electrode on the substrate is located within the range of the orthographic projection of the main body of the second anode on the substrate.

[0024] On the other hand, the present disclosure also provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and at least one initial signal line; the pixel driving circuit comprising at least one initialization transistor, the initial signal line being connected to the initialization transistor via a connecting electrode; in at least one unit row, two initialization transistors in adjacent circuit units are connected to the connecting electrode via the same via, or, two connecting electrodes in adjacent circuit units are connected to the initial signal line via the same via.

[0025] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0026] In another aspect, the present disclosure further provides a method for preparing a display substrate, comprising:

[0027] A driving structure layer is formed on a substrate; the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; the pixel driving circuit includes at least a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initial signal line is connected to a first electrode of the first transistor, the second initial signal line is connected to a first electrode of the seventh transistor, and the third initial signal line is connected to a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share a first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share a first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share a first electrode of the eighth transistor;

[0028] A light emitting structure layer is formed on the driving structure layer.

[0029] The present disclosure provides a display substrate and a display device, which can effectively reduce layout space, reduce the number of vias and connecting electrodes, and reduce the occupied area of ​​the pixel driving circuit by sharing circuit nodes of the pixel driving circuit, which is conducive to achieving high resolution.

[0030] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0032] Figure 1 is a structural schematic diagram of a display device;

[0033] Figure 2 It is a structural schematic diagram of a display substrate;

[0034] Figure 3 It is a schematic diagram of the planar structure of a display area in a display substrate;

[0035] Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate;

[0036] Figure 5 is an equivalent circuit diagram of a pixel driving circuit;

[0037] Figure 6 It is a structural schematic diagram of a data connection line of an exemplary embodiment of the present disclosure;

[0038] Figure 7 It is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0039] Figure 8 It is a schematic structural diagram of another display substrate of an exemplary embodiment of the present disclosure;

[0040] Fig. 9 It is a schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0041] Fig. 10A and Fig. 10B It is a schematic diagram after forming a first conductive layer pattern according to an embodiment of the present disclosure;

[0042] Fig.11A and Fig. 11B It is a schematic diagram after forming a second conductive layer pattern according to an embodiment of the present disclosure;

[0043] Fig.12 It is a schematic diagram after forming a fourth insulating layer pattern according to an embodiment of the present disclosure;

[0044] Fig.13A , Fig. 13B and Fig. 13C It is a schematic diagram after forming a third conductive layer pattern according to an embodiment of the present disclosure;

[0045] Fig.14 It is a schematic diagram after forming the fifth insulating layer and the first planar layer pattern according to the embodiment of the present disclosure;

[0046] Fig.15A and Fig. 15B It is a schematic diagram after forming a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0047] Fig.16It is a schematic diagram after forming a second planar layer pattern according to an embodiment of the present disclosure;

[0048] Fig.17A and Fig. 17B It is a schematic diagram after forming an anode conductive layer pattern according to an embodiment of the present disclosure;

[0049] Fig. 17C for Fig.17A Schematic diagram of the positional relationship between the anode conductive layer and the third conductive layer.

[0050] Description of reference numerals:

[0051] 11—first active layer; 12—second active layer; 13—third active layer;

[0052] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0053] 17—seventh active layer; 18—eighth active layer; 21—first scanning signal line;

[0054] 22—second scanning signal line; 23—third scanning signal line; 24—light emitting signal line;

[0055] 31 - first electrode plate; 32 - second electrode plate; 33 - opening;

[0056] 34—plate connection bar; 41—first initial signal line; 42—second initial signal line;

[0057] 43—third initial signal line; 51—first connection electrode; 52—second connection electrode;

[0058] 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode;

[0059] 56—sixth connecting electrode; 57—seventh connecting electrode; 58—eighth connecting electrode;

[0060] 59—dummy electrode strip; 61—first shielding electrode; 62—second shielding electrode;

[0061] 63—third shielding electrode; 64—fourth shielding electrode; 71—first power line;

[0062] 72—data signal line; 73—anode connection electrode; 80—data lead line;

[0063] 81—first connection line; 82—second connection line; 83—data connection electrode;

[0064] 84—data connection block; 90A—first anode; 90B—second anode;

[0065] 90C—third anode; 90D—fourth anode; 91—first initial connection line;

[0066] 92—second initial connection line; 93—third initial connection line; 100—display area;

[0067] 101 - substrate; 102 - driving structure layer; 103 - light emitting structure layer;

[0068] 104—packaging structure layer; 200—binding area; 300—border area. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0070] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0071] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0072] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0073] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0074] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0075] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0076] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0077] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0078] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0079] In this specification, triangles, rectangles, trapezoids, pentagons or hexagons are not strictly defined, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc., and may have some small deformations caused by tolerances, chamfers, curved edges and deformations, etc. "About" in this disclosure means that the limits are not strictly defined, and the values ​​within the range of process and measurement errors are allowed.

[0080] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. The scan driver may be constructed in the form of a shift register, and may sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, where m may be a natural number. The light emitting driver may generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines EM1 to Eo. The light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0081] Figure 2 Schematic diagram of the structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including a plurality of sub-pixels Pxij constituting a pixel array, and the plurality of sub-pixels Pxij are configured to display dynamic pictures or still images, and the display area 100 may be referred to as an active area (ActiveArea, referred to as AA). In an exemplary embodiment, the display substrate may be a flexible substrate, so that the display substrate may be deformable, such as curling, bending, folding or rolling up.

[0082] In an exemplary embodiment, the binding area 200 may include a lead area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area, and the lead area is connected to the display area 100 and includes at least a data lead. The bending area is connected to the lead area and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include a binding pad (BondingPad), which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0083] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks arranged on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove arranged on the composite insulating layer, and the cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively.

[0084] In an exemplary embodiment, the lead line area in the binding area 200 and the power line area in the border area 300 may be provided with an isolation dam, which may extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100, and the edge of the display area is the edge of one side of the display area binding area or the border area.

[0085] Figure 3FIG. 1 is a schematic diagram of a planar structure of a display area in a display substrate. Figure 3 As shown, the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the light-emitting signal line, and the data signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0086] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, the third sub-pixel P3 may be a first green sub-pixel (G1) emitting green light, and the fourth sub-pixel P4 may be a second green sub-pixel (G2) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the four sub-pixels may be arranged in an RGBG manner.

[0087] In other exemplary embodiments, the pixel unit P may include three sub-pixels, and the three sub-pixels may be arranged in parallel horizontally or vertically, etc., which is not limited in the present disclosure.

[0088] Figure 4 FIG. 1 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region. Figure 4 As shown, on a plane perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0089] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, and the light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0090] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 5 As shown, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 9 signal lines (first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power line VDD).

[0091] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0092] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0093] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the second scan signal line S2 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor is connected to the first node N1 .

[0094] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0095] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0096] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0097] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0098] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0099] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the third scan signal line S3 , a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0100] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the third scan signal line S3 , a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3 , and a second electrode of the eighth transistor T8 is connected to the second node N2 .

[0101] In an exemplary embodiment, the pixel driving circuit can realize normal driving and low-frequency driving. In the scene where the refresh rate is not required, low-frequency refresh can be used to save power consumption. When driving normally, the driving timing of the pixel driving circuit can include four stages such as initialization, compensation, data writing and light emission. When driving at low frequency, the driving timing of the pixel driving circuit can include six stages such as initialization, compensation, data writing, light emission, adjustment and light emission again. In the adjustment stage, the third initial signal (bias voltage) is written to the first pole of the third transistor T3 by the eighth transistor T8, so that the bias state of the third transistor T3 can be maintained consistent with the bias state when the data signal is just written, which can not only improve the stability of the working state of the driving transistor and improve low-frequency flicker (Fliker), but also effectively improve the hysteresis of the third transistor, which is conducive to the improvement of residual image and the display effect.

[0102] In an exemplary embodiment, a first electrode of the light emitting device EL is connected to the fourth node N4, and a second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).

[0103] In an exemplary embodiment, the first power line VDD is configured to provide a constant first power signal to the pixel driving circuit, the second power line VSS is configured to provide a constant second power signal to the light emitting device, and the first power signal is a high level signal, and the second power signal is a low level signal. The first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 are configured to provide a constant first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively, and the present disclosure is not limited thereto.

[0104] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 in the pixel driving circuit may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include a P-type transistor and an N-type transistor.

[0105] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and an oxide transistor. The active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current. Low-temperature polysilicon transistors and oxide transistors are integrated on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0106] With the development of OLED display technology, consumers have higher and higher requirements for the display effect and display quality of display products, and narrow borders have become a new trend in the development of display products. Therefore, narrow borders or even borderless designs are increasingly valued in the design of OLED display products. In a display substrate, since the data signal of the integrated circuit in the binding area needs to be introduced into the wider display area through the data lead-out line in a fan-out manner, the lead-out line area occupies a large space, resulting in a larger width of the lower border.

[0107] In order to reduce the width of the lower frame, the exemplary embodiment of the present disclosure provides a display substrate, which adopts a fanout in panel (FIP) structure. A plurality of data connection lines are arranged in the display area, and the data connection lines may include a first connection line and a second connection line. The first ends of the plurality of first connection lines are correspondingly connected to the plurality of data signal lines in the display area, and the second ends of the plurality of first connection lines are correspondingly connected to the first ends of the plurality of second connection lines. After the second ends of the plurality of second connection lines extend to the binding area, they are correspondingly connected to the integrated circuit through the plurality of lead lines in the lead line area. Since the lead line area does not need to be provided with a fan-shaped oblique line, the width of the lead line area is reduced, thereby reducing the width of the lower frame.

[0108] Figure 6 FIG. 1 is a schematic diagram of a data connection line according to an exemplary embodiment of the present disclosure, wherein the data connection line adopts a FIP structure. Figure 6As shown, in a plane parallel to the display substrate, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The driving structure layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 72, a plurality of first connection lines 81, and a plurality of second connection lines 82, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer of the display area 100 may include a plurality of light-emitting units, at least one light-emitting unit may include a light-emitting device, the light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0109] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. In an exemplary embodiment, the position of the orthogonal projection of the light-emitting unit on the substrate may correspond to the position of the orthogonal projection of the circuit unit on the substrate, or the position of the orthogonal projection of the light-emitting unit on the substrate may not correspond to the position of the orthogonal projection of the circuit unit on the substrate.

[0110] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column, a plurality of unit rows and a plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects the second direction Y.

[0111] In an exemplary embodiment, the first direction X may be a cell row direction, the second direction Y may be a cell column direction, and the first direction X and the second direction Y may be perpendicular to each other.

[0112] In an exemplary embodiment, the shape of the first connection line 81 may be a straight line or a folded line extending along the first direction X, and the shape of the data signal line 72 and the second connection line 82 may be a straight line or a folded line extending along the second direction Y. A plurality of data signal lines 72 are sequentially arranged at set intervals in the first direction X, at least one data signal line 72 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 72 is configured to provide a data signal to the connected pixel driving circuit. A first end of at least one first connection line 81 is connected to a data signal line 72, and a second end is connected to a first end of a second connection line 82, and a second end of the second connection line 82 is connected to a data lead-out line 80 after extending to the binding area, so that the data signal line 72 in the display area is connected to the data lead-out line 80 in the binding area 200 through the first connection line 81 and the second connection line 82, forming a FIP structure (also referred to as a FIAA structure). In an exemplary embodiment, the first connection line 81 and the second connection line 82 are collectively referred to as a data connection line.

[0113] In an exemplary embodiment, the binding area 200 may include a lead-out area, a bending area, a driver chip area, and a binding pin area sequentially arranged in a direction away from the display area, the lead-out area is connected to the display area, and the bending area is connected to the lead-out area. The lead-out area may be provided with a plurality of data lead-out lines 80, and the plurality of data lead-out lines 80 extend in a direction away from the display area, the first ends of a portion of the data lead-out lines 80 are correspondingly connected to the second connection lines 82 in the display area 100, and the first ends of another portion of the data lead-out lines 80 are correspondingly connected to the data signal lines 72 in the display area 100, and the second ends of all the data lead-out lines 80 are connected to the integrated circuit of the driver chip area after crossing the bending area along the second direction Y, so that the integrated circuit applies the data signal to the data signal line through the data lead-out line and the data connection line. Since the first connection line 81 and the second connection line 82 are arranged in the display area, the length of the second direction Y of the lead-out area can be effectively reduced, the width of the lower frame can be greatly reduced, the screen ratio is improved, and it is conducive to achieving full-screen display.

[0114] In an exemplary embodiment, the number of data connection lines in the display area may be the same as the number of data signal lines, and each data signal line is connected to a corresponding lead line through a data connection line. Alternatively, the number of data connection lines in the display area may be less than the number of data signal lines, and a portion of the data signal lines in the display area are connected to the corresponding lead lines through the data connection lines, and another portion of the data signal lines are directly connected to the lead lines, which is not limited in the present disclosure.

[0115] An exemplary embodiment of the present disclosure provides a display substrate, comprising a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate, the driving structure layer comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; the pixel driving circuit comprising a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initial signal line being connected to a first electrode of the first transistor, the second initial signal line being connected to a first electrode of the seventh transistor, and the third initial signal line being connected to a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share a first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share a first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share a first electrode of the eighth transistor.

[0116] In an exemplary embodiment, the first transistor includes at least a first active layer, the first initial signal line is connected to the first region of the first active layer through a sixth connection electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the sixth connection electrode.

[0117] In an exemplary embodiment, the seventh transistor includes at least a seventh active layer, and the second initial signal line is connected to the first region of the seventh active layer through a second initial connection block; in at least one unit row, the pixel driving circuits in adjacent circuit units share the second initial connection block.

[0118] In an exemplary embodiment, the eighth transistor includes at least an eighth active layer, the third initial signal line is connected to the first region of the eighth active layer through a seventh connecting electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the seventh connecting electrode.

[0119] In an exemplary embodiment, the pixel driving circuit also includes a second transistor as a compensation transistor and a third transistor as a driving transistor, the first electrode of the second transistor is respectively connected to the second electrode of the first transistor and the gate electrode of the third transistor, and the second electrode of the second transistor is connected to the second electrode of the third transistor; the first transistor and the second transistor are a dual-gate structure.

[0120] In an exemplary embodiment, the driving structure layer also includes a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, wherein the first direction and the second direction intersect; at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, the first ends of the plurality of first connecting lines are correspondingly connected to the plurality of data signal lines, and the second ends of the plurality of first connecting lines are correspondingly connected to the plurality of second connecting lines.

[0121] Figure 7 FIG. 1 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating a structure of eight circuit units in one circuit row (the Mth unit row) and eight circuit columns (the Nth unit column to the N+7th unit column). Figure 7 As shown, in a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on the substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate. In a plane parallel to the substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23, the light emitting signal line 24, the first initial signal line 41, the second initial signal line 42, the third initial signal line 43, the first power line 71 and the data signal line 72. The first scanning signal line 21 to the third scanning signal line 23 are configured to provide the first scanning signal to the third scanning signal to the pixel driving circuit, respectively, the light emitting signal line 24 is configured to provide the light emitting control signal to the pixel driving circuit, the first initial signal line 41 to the third initial signal line 43 are configured to provide the first initial signal to the third initial signal to the pixel driving circuit, respectively, the first power line 71 is configured to provide the first power signal to the pixel driving circuit, and the data signal line 72 is configured to provide the data signal to the pixel driving circuit. Among them, a plurality of signal lines connected to the pixel driving circuit may be located in the circuit unit.

[0122] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light-emitting signal line 24, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 can be straight lines or folded lines with the main parts extending along the first direction X, and the shapes of the first power line 71 and the data signal line 72 can be straight lines or folded lines with the main parts extending along the second direction Y.

[0123] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" means "the main part of A extends along direction B".

[0124] In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and 8 polysilicon transistors. The 8 polysilicon transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emission control transistor, a sixth transistor T6 as a second light emission control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor, and the storage capacitor may include a first plate and a second plate stacked.

[0125] In an exemplary embodiment, the first transistor T1 and the second transistor T2 may be transistors of a dual gate structure.

[0126] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 22, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is respectively connected to the first electrode of the second transistor T2 and the first electrode plate of the storage capacitor (also the gate electrode of the third transistor T3). The gate electrode of the second transistor T2 is connected to the first scan signal line 21, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first electrode of the fourth transistor T4 is connected to the data signal line 72, and the second electrode of the fourth transistor T4 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8. The gate electrode of the fifth transistor T5 is connected to the light emitting signal line 24, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line 24, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the third scanning signal line 23, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the third scanning signal line 23, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0127] In an exemplary embodiment, in at least one circuit unit, the first scan signal line 21 may be arranged on the side of the storage capacitor (third transistor T3) in the opposite direction of the second direction Y, the first initial signal line 41 may be arranged on the side of the first scan signal line 21 away from the storage capacitor, and the second scan signal line 22 may be arranged on the side of the first initial signal line 41 away from the storage capacitor, that is, the first initial signal line 41 is arranged between the first scan signal line 21 and the second scan signal line 22. The light-emitting signal line 24 may be arranged on the side of the storage capacitor in the second direction Y, the third scan signal line 23 may be arranged on the side of the light-emitting signal line 24 away from the storage capacitor, the second initial signal line 42 may be arranged on the side of the third scan signal line 23 away from the storage capacitor, and the third initial signal line 43 may be arranged on the side of the second initial signal line 42 away from the storage capacitor, that is, the second initial signal line 42 and the third initial signal line 43 are both arranged on the side of the third scan signal line 23 away from the storage capacitor.

[0128] In an exemplary embodiment, in at least one unit row, the pixel driving circuits in adjacent circuit units may be symmetrically arranged relative to the column center line, and the column center line may be a straight line located between two adjacent unit columns and extending along the second direction Y. For example, the pixel driving circuits in the Nth unit column and the N+1th unit column may be symmetrically arranged relative to the column center line. For another example, the pixel driving circuits in the N+1th unit column and the N+2th unit column may be symmetrically arranged relative to the column center line. In an exemplary embodiment, N may be a positive integer greater than 1.

[0129] In an exemplary embodiment, in at least one unit row, the pixel driving circuits in adjacent circuit units may share the first electrode of the first transistor T1, the pixel driving circuits in adjacent circuit units may share the first electrode of the seventh transistor T7, and the pixel driving circuits in adjacent circuit units may share the first electrode of the eighth transistor T8. For example, the pixel driving circuits in the Nth unit column and the N+1th unit column may share the first electrode of the first transistor T1. The pixel driving circuits in the N+1th unit column and the N+2th unit column may share the first electrode of the seventh transistor T7, and the pixel driving circuits in the Nth unit column and the N+1th unit column may share the first electrode of the eighth transistor T8.

[0130] In an exemplary embodiment, in at least one circuit unit, the first transistor T1 may include at least a first active layer, the first initial signal line 41 may be connected to the first region of the first active layer through the sixth connection electrode 56, and the sixth connection electrode 56 may serve as the first electrode of the first transistor T1. In at least one unit row, the first active layers in adjacent circuit units may be an integrated structure connected to each other, the pixel driving circuits in adjacent circuit units share the first region of the first active layer, and the pixel driving circuits in adjacent circuit units share the sixth connection electrode 56.

[0131] In an exemplary embodiment, in at least one circuit unit, the seventh transistor T7 may include at least a seventh active layer, the second initial signal line 42 may be connected to the first region of the seventh active layer through the second initial connection block 42-1, and the second initial connection block 42-1 may serve as the first electrode of the seventh transistor T7. In at least one unit row, the seventh active layers in adjacent circuit units may be interconnected integral structures, the pixel driving circuits in adjacent circuit units share the first region of the seventh active layer, and the pixel driving circuits in adjacent circuit units share the second initial connection block 42-1.

[0132] In an exemplary embodiment, in at least one circuit unit, the eighth transistor T8 may include at least an eighth active layer, the third initial signal line 43 may be connected to the first region of the eighth active layer through the seventh connection electrode 57, and the seventh connection electrode 57 may serve as the first electrode of the eighth transistor T8. In at least one unit row, the first regions of the eighth active layers in adjacent circuit units may be symmetrically arranged with respect to the column center line, the seventh connection electrodes 57 in adjacent circuit units may be symmetrically arranged with respect to the column center line, and the seventh connection electrodes 57 in adjacent circuit units may be an integrated structure connected to each other.

[0133] In an exemplary embodiment, the driving structure layer may also include at least one first initial connection line 91, at least one second initial connection line 92 and at least one third initial connection line 93. The shapes of the first initial connection line 91, the second initial connection line 92 and the third initial connection line 93 can be straight lines or broken lines extending along the second direction Y, and can be respectively arranged between the data signal lines 72 of some adjacent unit columns. The two data signal lines 72 in adjacent unit columns can be symmetrically arranged relative to the corresponding initial connection lines.

[0134] In an exemplary embodiment, the first initial connection line 91 may be connected to the first initial signal line 41 through the sixth connection electrode 56 to form a meshed connection structure for transmitting the first initial signal. The second initial connection line 92 may be connected to the second initial signal line 42 through the eighth connection electrode 58 to form a meshed connection structure for transmitting the second initial signal. The third initial connection line 93 may be connected to the third initial signal line 43 through the seventh connection electrode 57 to form a meshed connection structure for transmitting the third initial signal.

[0135] In an exemplary embodiment, the first initial connection line 91, the second initial connection line 92, the third initial connection line 93, and the second initial connection line 92 may be periodically arranged in the first direction X. For example, the first initial connection line 91 may be arranged between the data signal lines 72 of the Nth unit column and the N+1th unit column, the second initial connection line 92 may be arranged between the data signal lines 72 of the N+2th unit column and the N+3th unit column, and between the data signal lines 72 of the N+6th unit column and the N+7th unit column, and the third initial connection line 93 may be arranged between the data signal lines 72 of the N+4th unit column and the N+5th unit column.

[0136] In an exemplary embodiment, two second initial connection lines 92 and one third initial connection line 93 may be arranged between two adjacent first initial connection lines 91 in the first direction X, one first initial connection line 91 or one third initial connection line 93 may be arranged between two adjacent second initial connection lines 92 in the first direction X, and one first initial connection line 91 and two second initial connection lines 92 may be arranged between two adjacent third initial connection lines 93 in the first direction X.

[0137] In an exemplary embodiment, the driving structure layer may further include at least one first connection line 81 and at least one second connection line 82. The first connection line 81 may be in a straight line or a folded line extending along the first direction X, and the second connection line 82 may be in a straight line or a folded line extending along the second direction Y. The at least one first connection line 81 is connected to the data signal line 72 and the second connection line 82, respectively, to form a structure in which the data connection line is located in the display area.

[0138] In an exemplary embodiment, in the second direction Y, at least one first connection line 81 may be disposed between the second scan signal line 22 and the first initial signal line 41. In the first direction X, at least one second connection line 82 may be disposed between the first power sources 71 of some adjacent unit columns, and two first power sources 71 in adjacent unit columns may be symmetrically disposed with respect to the second connection line 8.

[0139] In an exemplary embodiment, two circuit units may be spaced between the adjacent second connection lines 82 in the first direction X. For example, the second connection line 82 may be disposed between the first power supply 71 of the N-1th unit column and the Nth unit column. For another example, the second connection line 82 may be disposed between the first power supply 71 of the N+1th unit column and the N+2th unit column. For another example, the second connection line 82 may be disposed between the first power supply 71 of the N+3th unit column and the N+4th unit column. For another example, the second connection line 82 may be disposed between the first power supply 71 of the N+5th unit column and the N+6th unit column. For another example, the second connection line 82 may be disposed between the first power supply 71 of the N+7th unit column and the N+8th unit column.

[0140] In an exemplary embodiment, the second connection lines 82 and the initial connection lines (the first initial connection lines 91 , the second initial connection lines 92 , and the third initial connection lines 93 ) may be alternately disposed in the first direction X. As shown in FIG.

[0141] In an exemplary embodiment, at least one circuit unit may further include a first shielding electrode 61, and the first shielding electrode 61 may be connected to the third initial signal line 43. The orthographic projection of the first shielding electrode 61 on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate, and the first shielding electrode 61 forms a coupling capacitor with the first active layer between the two gate electrodes in the first transistor T1.

[0142] In an exemplary embodiment, at least one circuit unit may further include a second shielding electrode 62, and the second shielding electrode 62 is connected to the first initial signal line 41. The orthographic projection of the second shielding electrode 62 on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes in the second transistor T2 on the substrate, and the second shielding electrode 62 forms a coupling capacitor with the second active layer between the two gate electrodes in the second transistor T2.

[0143] In an exemplary embodiment, at least one circuit unit may further include a third shielding electrode 63, and the third shielding electrode 63 is connected to the first initial signal line 41. The orthographic projection of the third shielding electrode 63 on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer on the substrate, and the orthographic projection of the third shielding electrode 63 on the substrate at least partially overlaps with the orthographic projection of the first connecting line 81 on the substrate. The orthographic projection of the first connecting line 81 on the substrate has an overlapping area with the orthographic projection of the second region of the first active layer on the substrate, and the orthographic projection of the third shielding electrode 63 on the substrate may include the overlapping area.

[0144] In an exemplary embodiment, at least one circuit unit may further include a fourth shielding electrode 64 connected to the first initial signal line 41. In the first direction X, the fourth shielding electrode 64 may be located between the first electrode of the second transistor T2 (also the second electrode of the first transistor T1) and the first electrode of the fourth transistor T4.

[0145] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving structure layer may include at least a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate. The first initial signal line 41 and the second initial signal line 42 may be disposed in the second conductive layer, the third initial signal line 43 and the first connection line 81 may be disposed in the third conductive layer, and the second connection line 82, the first initial connection line 91, the second initial connection line 92, and the third initial connection line 93 may be disposed in the fourth conductive layer.

[0146] Figure 8 FIG. 2 is a schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of the fourth conductive layer and the anode conductive layer. Figure 8 As shown, in a direction perpendicular to the display substrate, the light emitting structure layer may at least include an anode conductive layer disposed on a side of the driving structure layer away from the substrate, a pixel definition layer disposed on a side of the anode conductive layer away from the substrate, an organic light emitting layer disposed on a side of the pixel definition layer away from the substrate, a cathode layer disposed on a side of the organic light emitting layer away from the substrate, and an encapsulation structure layer disposed on a side of the cathode layer away from the substrate. In a direction parallel to the display substrate, the light emitting structure layer may at least include a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light, and a plurality of second green light emitting units emitting green light, the red light emitting unit may at least include a first anode 90A, the blue light emitting unit may at least include a second anode 90B, the first green light emitting unit may at least include a third anode 90C, the second green light emitting unit may at least include a fourth anode 90D, and the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may all be disposed in the anode conductive layer.

[0147] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include a main body portion 90-1 and a connecting portion 90-2 that are connected to each other, wherein a first end of the connecting portion 90-2 is connected to the main body portion 90-1, and a second end of the connecting portion 90-2 extends in a direction away from the main body portion 90-1 and is connected to the anode connecting electrode 73 in the pixel driving circuit through an anode via.

[0148] In an exemplary embodiment, the orthographic projections of the main portion of the first anode 90A and the main portion of the second anode 90B on the substrate at least partially overlap with the orthographic projection of the second connecting line 82 on the substrate, while the orthographic projections of the main portion of the third anode 90C and the main portion of the fourth anode 90D on the substrate do not overlap with the orthographic projection of the second connecting line 82 on the substrate, that is, the second connecting line 82 is only arranged below the anodes of the red light-emitting unit and the blue light-emitting unit.

[0149] In an exemplary embodiment, the orthographic projections of the main body of the third anode 90C and the main body of the fourth anode 90D on the substrate overlap at least partially with the orthographic projection of the initial connection line on the substrate, while the orthographic projections of the main body of the first anode 90A and the main body of the second anode 90B on the substrate do not overlap with the orthographic projections of the initial connection line on the substrate, that is, the initial connection line is only disposed below the anodes of the first green light-emitting unit and the second green light-emitting unit. The initial connection line may be the first initial connection line 91, or may be the second initial connection line 92, or may be the third initial connection line 93.

[0150] The following is an exemplary explanation of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0151] In an exemplary embodiment, taking 8 circuit units of one unit row and 8 unit columns as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0152] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process, forming a first insulating layer disposed on the substrate, and a semiconductor layer pattern disposed on the first insulating layer, such as Fig. 9 shown.

[0153] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1 to the eighth active layer 18 of the eighth transistor T8, and the first active layer 11 to the seventh active layer 17 may be an integral structure connected to each other, and the eighth active layer 18 is provided separately.

[0154] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on the side of the third active layer 13 in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, the seventh active layer 17, and the eighth active layer 18 may be located on the side of the second direction Y of the third active layer 13.

[0155] In an exemplary embodiment, the third active layer 13 may be shaped like an "Ω", the first active layer 11 may be shaped like an "n", the second active layer 12, the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be shaped like an "L", and the fourth active layer 14 and the eighth active layer 18 may be shaped like an "I".

[0156] In an exemplary embodiment, the first to eighth active layers 11 to 18 may each include a first region, a second region, and a channel region between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer at the same time. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 12-2 of the second active layer may serve as the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer at the same time. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the first region 18-2 of the eighth active layer may be separately provided.

[0157] In an exemplary embodiment, the semiconductor layer patterns of adjacent unit columns may be arranged mirror-symmetrically with respect to the center line of the column. For example, the first active layer 11 to the eighth active layer 18 in the Nth unit column and the N+1th unit column may be arranged mirror-symmetrically with respect to the center line of the column. For another example, the first active layer 11 to the eighth active layer 18 in the N+1th unit column and the N+2th unit column may be arranged mirror-symmetrically with respect to the center line of the column.

[0158] In example embodiments, positions and shapes of the first to eighth active layers 11 to 18 of adjacent cell rows may be substantially the same.

[0159] In an exemplary embodiment, in at least one unit row, the first active layer 11 in some adjacent circuit units may be an integrated structure connected to each other, and the first active layers 11 in two circuit units may share the first region 11-1 of the same first active layer. For example, the two circuit units in the Nth unit column and the N+1th unit column may share the first region 11-1 of the same first active layer. For another example, the two circuit units in the N+2th unit column and the N+3th unit column may share the first region 11-1 of the same first active layer. For another example, the two circuit units in the N+4th unit column and the N+5th unit column may share the first region 11-1 of the same first active layer. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connecting electrodes, and reduce the occupied area of ​​the pixel driving circuit by setting the first transistors T1 in adjacent circuit units to be mirror-imaged and share the first region of the first active layer, which is conducive to achieving high resolution.

[0160] In an exemplary embodiment, the first region of the first active layer may serve as the first electrode of the first transistor T1, and the first electrode of the first transistor T1 shared by the pixel driving circuits in adjacent circuit units may be the first region of the first active layer shared by the pixel driving circuits in adjacent circuit units.

[0161] In an exemplary embodiment, in at least one unit row, the seventh active layer 17 in some adjacent circuit units may be an integrated structure connected to each other, and the seventh active layers 17 in two circuit units may share the first area 17-1 of the same seventh active layer. For example, the two circuit units in the N+1th unit column and the N+2th unit column may share the first area 17-1 of the same seventh active layer. For another example, the two circuit units in the N+3th unit column and the N+4th unit column may share the first area 17-1 of the same seventh active layer. For another example, the two circuit units in the N+5th unit column and the N+6th unit column may share the first area 17-1 of the same seventh active layer. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connecting electrodes, and reduce the occupied area of ​​the pixel driving circuit by setting the seventh transistor T7 in the adjacent circuit units to be mirrored and share the first area of ​​the seventh active layer, which is conducive to achieving high resolution.

[0162] In an exemplary embodiment, the first region of the seventh active layer may serve as the first electrode of the seventh transistor T7, and the pixel driving circuits in adjacent circuit units may share the first region of the seventh active layer.

[0163] In an exemplary embodiment, in at least one unit row, the eighth active layer 18 in some adjacent circuit units can be arranged in mirror symmetry with respect to the column center line and are all close to the column center line, which is beneficial for adjacent circuit units to share the first electrode of the eighth transistor T8, can effectively reduce the lateral wiring space, reduce the number of vias, reduce the area occupied by the pixel driving circuit, and is beneficial to achieve high resolution.

[0164] In an exemplary embodiment, the semiconductor layer may be polycrystalline silicon (p-Si), that is, the first transistor T1 to the eighth transistor T8 are LTPS transistors. In an exemplary embodiment, patterning the semiconductor film through a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a semiconductor layer pattern.

[0165] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate having the aforementioned pattern, patterning the first conductive film by a patterning process to form a second insulating layer covering the semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer, such as Fig. 10A and Fig. 10B As shown, Fig. 10B for Fig. 10A In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0166] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may include at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 24 , and a first plate 31 of a storage capacitor.

[0167] In an exemplary embodiment, the shape of the first electrode plate 31 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The first electrode plate 31 can simultaneously serve as the lower electrode plate of the storage capacitor and the gate electrode of the third transistor T3.

[0168] In an exemplary embodiment, the shape of the first scan signal line 21 can be a straight line or a broken line extending along the first direction X, and can be arranged on the side of the first electrode plate 31 in the opposite direction of the second direction Y. The area where the first scan signal line 21 overlaps with the fourth active layer can be used as the gate electrode of the fourth transistor T4, thereby realizing that the first scan signal line 21 can control the conduction or disconnection of the fourth transistor T4.

[0169] In an exemplary embodiment, a gate block 21-1 may be provided on the first scan signal line 21, and the shape of the gate block 21-1 may be a strip shape extending along the second direction Y, and a first end of the gate block 21-1 is connected to a side of the first scan signal line 21 away from the first electrode plate 31, and a second end of the gate block 21-1 extends in a direction away from the first electrode plate 31. The region where the first scan signal line 21 and the gate block 21-1 overlap with the second active layer may be used as a gate electrode of the second transistor T2 of the double-gate structure, thereby realizing that the first scan signal line 21 can control the conduction or disconnection of the second transistor T2. In an exemplary embodiment, the second transistor T2 of the double-gate structure can reduce the leakage of the second transistor T2, which is conducive to realizing low-frequency driving of the pixel driving circuit.

[0170] In an exemplary embodiment, the second scanning signal line 22 may be in the shape of a straight line or a folded line extending along the first direction X, and may be disposed on a side of the first scanning signal line 21 away from the first electrode plate 31. The region where the second scanning signal line 22 overlaps with the first active layer may be used as a gate electrode of the first transistor T1 of the double-gate structure, thereby realizing that the second scanning signal line 22 may control the conduction or disconnection of the first transistor T1. In an exemplary embodiment, the first transistor T1 of the double-gate structure may reduce the leakage of the first transistor T1, which is conducive to realizing low-frequency driving of the pixel driving circuit.

[0171] In an exemplary embodiment, the shape of the third scan signal line 23 can be a straight line or a broken line extending along the first direction X, and can be arranged on one side of the first electrode plate 31 in the second direction Y. The area where the third scan signal line 23 overlaps with the seventh active layer can be used as the gate electrode of the seventh transistor T7, and the area where the third scan signal line 23 overlaps with the eighth active layer can be used as the gate electrode of the eighth transistor T8, thereby achieving that the third scan signal line 23 can control the conduction or disconnection of the seventh transistor T7 and the eighth transistor T8.

[0172] In an exemplary embodiment, the shape of the light-emitting signal line 24 can be a straight line or a broken line extending along the first direction X, and can be arranged between the first electrode plate 31 and the third scanning signal line 23. The area where the light-emitting signal line 24 overlaps with the fifth active layer can be used as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 24 overlaps with the sixth active layer can be used as the gate electrode of the sixth transistor T6, thereby achieving that the light-emitting signal line 24 can control the conduction or disconnection of the fifth transistor T5 and the sixth transistor T6.

[0173] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 24 can be fold lines of unequal width, and the width of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 24 at the overlapping position with the semiconductor layer can be greater than the width at other positions.

[0174] In an exemplary embodiment, the first conductive layer patterns of adjacent unit columns may be arranged mirror-symmetrically with respect to the center line of the column. For example, the positions and shapes of the first conductive layers in the Nth unit column and the N+1th unit column may be arranged mirror-symmetrically with respect to the center line of the column. For another example, the positions and shapes of the first conductive layers in the N+1th unit column and the N+2th unit column may be arranged mirror-symmetrically with respect to the center line of the column.

[0175] In example embodiments, positions and shapes of the first conductive layers of adjacent cell rows may be substantially the same.

[0176] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer, and the first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first active layer to the eighth active layer are both conductorized.

[0177] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film through a patterning process to form a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, such as Fig.11A and Fig. 11B As shown, Fig. 11B for Fig.11A In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0178] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a second plate 32 of the storage capacitor, a first initial signal line 41, a third initial signal line 43, a first shielding electrode 61, a second shielding electrode 62, a third shielding electrode 63 and a fourth shielding electrode 64.

[0179] In an exemplary embodiment, the outline of the second electrode plate 32 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as the upper electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute a storage capacitor.

[0180] In an exemplary embodiment, an opening 33 is provided on the second electrode plate 32. The opening 33 may be in a block shape (e.g., rectangular) and may be located in the middle region of the second electrode plate 32, so that the second electrode plate 32 forms a ring shape. The opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a tenth via hole formed subsequently. The tenth via hole is located in the opening 33 and exposes the first electrode plate 31, so that the first connecting electrode formed subsequently is connected to the first electrode plate 31.

[0181] In an exemplary embodiment, the second electrode 32 may be provided with a plate connection bar 34. The plate connection bar 34 may be in the shape of a straight line or a broken line extending along the first direction X, and the plate connection bar 34 may be provided on one side of the second electrode 32 in the first direction X or on the side opposite to the first direction X, and the first end of the plate connection bar 34 is connected to the second electrode 32 in the current circuit unit, and the second end of the plate connection bar 34 is connected to the second electrode 32 in the adjacent circuit unit in the first direction X.

[0182] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 32 and the plate connecting bar 34 may be an integral structure connected to each other.

[0183] In an exemplary embodiment, in a unit row, the second plates 32 in some adjacent circuit units can be interconnected integral structures. For example, the second plates 32 of the Nth unit column and the second plates 32 of the N+1th unit column are interconnected through the plate electrode connection bar 34 to form an interconnected integral structure. For another example, the second plates 32 of the N+2th unit column and the second plates 32 of the N+3th unit column are interconnected through the plate electrode connection bar 34 to form an interconnected integral structure. For another example, the second plates 32 of the N+4th unit column and the second plates 32 of the N+5th unit column are interconnected through the plate electrode connection bar 34 to form an interconnected integral structure. Since the second plates 32 in each circuit unit are connected to the first power line formed subsequently, by forming the second plates 32 of some adjacent circuit units into an interconnected integral structure, the second plates of the integral structure can be reused as power signal lines, which can ensure that the second plates of adjacent circuit units have the same potential, which is conducive to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0184] In an exemplary embodiment, the shape of the first initial signal line 41 may be a straight line or a folded line extending along the first direction X, and may be disposed between the first scan signal line 21 and the second scan signal line 22. A first initial connection block 41-1 may be disposed on the first initial signal line 41, and the shape of the first initial connection block 41-1 may be a block (such as a rectangle). In the first direction X, the first initial connection block 41-1 may be disposed between some adjacent circuit units, and in the second direction Y, the first initial connection block 41-1 may be disposed on a side of the first initial signal line 41 close to the first scan signal line 21, and connected to the first initial signal line 41. In an exemplary embodiment, the first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a sixth connection electrode formed subsequently.

[0185] In an exemplary embodiment, the first preliminary signal line 41 and the plurality of first preliminary connection blocks 41 - 1 in one unit row may be an integral structure connected to each other.

[0186] In an exemplary embodiment, two partially adjacent circuit units in a unit row may share the same first initial connection block 41-1. For example, two circuit units in the Nth unit column and the N+1th unit column may share the same first initial connection block 41-1. For another example, two circuit units in the N+2th unit column and the N+3th unit column may share the same first initial connection block 41-1. For another example, two circuit units in the N+4th unit column and the N+5th unit column may share the same first initial connection block 41-1. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connecting electrodes, reduce the occupied area of ​​the pixel driving circuit, and facilitate the realization of high resolution by setting a partially adjacent circuit unit to share the first initial connection block 41-1.

[0187] In an exemplary embodiment, the shape of the third initial signal line 43 may be a straight line or a folded line extending along the first direction X, and may be arranged on the side of the third scan signal line 23 away from the second electrode plate 32. A third initial connection block 43-1 may be arranged on the third initial signal line 43, and the shape of the third initial connection block 43-1 may be a block shape (such as a rectangle). In the first direction X, the third initial connection block 43-1 may be arranged between some adjacent circuit units, and in the second direction Y, the third initial connection block 43-1 may be arranged on the side of the third initial signal line 43 away from the second electrode plate 32, and connected to the third initial signal line 43. In an exemplary embodiment, the third initial connection block 43-1 is configured to be connected to the first region of the eighth active layer through the seventh connection electrode formed subsequently.

[0188] In an exemplary embodiment, the third preliminary signal line 43 and the plurality of third preliminary connection blocks 43 - 1 in one cell row may be an integral structure connected to each other.

[0189] In an exemplary embodiment, two partially adjacent circuit units in a unit row may share the same third initial connection block 43-1. For example, two circuit units in the Nth unit column and the N+1th unit column may share the same third initial connection block 43-1. For another example, two circuit units in the N+2th unit column and the N+3th unit column may share the same third initial connection block 43-1. For another example, two circuit units in the N+4th unit column and the N+5th unit column may share the same third initial connection block 43-1. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connecting electrodes, reduce the occupied area of ​​the pixel driving circuit, and facilitate the realization of high resolution by setting up partially adjacent circuit units to share the third initial connection block 43-1.

[0190] In an exemplary embodiment, the first shielding electrode 61 may be in a block shape (such as a rectangle), may be disposed on the third initial signal line 43, and is connected to the third initial signal line 43. The orthographic projection of the first shielding electrode 61 on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate, and the first shielding electrode 61 forms a coupling capacitor with the first active layer between the two gate electrodes in the first transistor T1. In an exemplary embodiment, the first shielding electrode 61 is configured to, on the one hand, shield the node between the two gate electrodes in the first transistor T1, avoid the influence of the data voltage jump on the first transistor T1, and reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and on the other hand, reduce the leakage of the first transistor T1 by using the coupling capacitor to improve the display effect.

[0191] In an exemplary embodiment, in at least one circuit unit, the third preliminary signal line 43 and the first shielding electrode 61 may be an integral structure connected to each other.

[0192] In an exemplary embodiment, the second shielding electrode 62 may be in a block shape (such as a rectangle), and may be disposed on the first initial signal line 41. The first end of the second shielding electrode 62 is connected to the side of the first initial signal line 41 close to the first scanning signal line 21, and the second end of the second shielding electrode 62 extends in a direction close to the first scanning signal line 21. The positive projection of the second shielding electrode 62 on the substrate overlaps at least partially with the positive projection of the second active layer between the two gate electrodes in the second transistor T2 on the substrate, and the second shielding electrode 62 forms a coupling capacitor with the second active layer between the two gate electrodes in the second transistor T2. In an exemplary embodiment, the second shielding electrode 62 is configured to shield the node between the two gate electrodes in the second transistor T2, avoid the influence of the data voltage jump on the second transistor T2, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and on the other hand, reduce the leakage of the second transistor T2 by using the coupling capacitor to improve the display effect.

[0193] In an exemplary embodiment, in at least one circuit unit, the first preliminary signal line 41 and the second shielding electrode 62 may be an integral structure connected to each other.

[0194] In an exemplary embodiment, in at least one unit row, the second shielding electrodes 62 in some adjacent circuit units may be connected to each other to form an integrated structure connected to each other. For example, the second shielding electrode 62 in the N+1th unit column and the second shielding electrode 62 in the N+2th unit column may be an integrated structure connected to each other. For another example, the second shielding electrode 62 in the N+3th unit column and the second shielding electrode 62 in the N+4th unit column may be an integrated structure connected to each other. For another example, the second shielding electrode 62 in the N+5th unit column and the second shielding electrode 62 in the N+6th unit column may be an integrated structure connected to each other.

[0195] In an exemplary embodiment, the third shielding electrode 63 may be in a block shape (e.g., rectangular) and may be disposed on the first initial signal line 41 and connected to the first initial signal line 41. The orthographic projection of the third shielding electrode 63 on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer on the substrate. In an exemplary embodiment, the third shielding electrode 63 is configured to shield the first connecting line formed subsequently, to prevent the influence of the data voltage jump in the first connecting line on the first transistor T1 and the second transistor T2, to reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and to improve the display effect.

[0196] In an exemplary embodiment, in at least one circuit unit, the first preliminary signal line 41 and the third shielding electrode 63 may be an integral structure connected to each other.

[0197] In an exemplary embodiment, the fourth shielding electrode 64 may be in the shape of a strip extending along the second direction Y, the first end of the fourth shielding electrode 64 is connected to the side of the first initial signal line 41 close to the first scanning signal line 21, and the second end of the fourth shielding electrode 64 extends in the direction close to the first scanning signal line 21. In the first direction X, the fourth shielding electrode 64 may be located between the first region of the second active layer (also the second region of the first active layer) and the first region of the fourth active layer, that is, between the first electrode of the second transistor T2 (also the second electrode of the first transistor T1) and the first electrode of the fourth transistor T4. In an exemplary embodiment, since the first region of the fourth active layer is connected to the data signal line formed later, and the second region of the first active layer (also the first region of the second active layer) is connected to the first connection electrode formed later as the first node N1, the fourth shielding electrode 64 is disposed between the first node N1 and the data signal line, which can avoid the influence of the data signal line on the first node N1, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0198] In an exemplary embodiment, in at least one circuit unit, the first preliminary signal line 41 and the fourth shielding electrode 64 may be an integral structure connected to each other.

[0199] In an exemplary embodiment, in at least one unit row, the first preliminary signal line 41 , the plurality of second shielding electrodes 62 , the plurality of third shielding electrodes 63 , and the plurality of fourth shielding electrodes 64 may be an integral structure connected to each other.

[0200] In an exemplary embodiment, the second conductive layer patterns of adjacent unit columns may be arranged mirror-symmetrically with respect to the center line of the column. For example, the positions and shapes of the second conductive layers in the Nth unit column and the N+1th unit column may be arranged mirror-symmetrically with respect to the center line of the column. For another example, the positions and shapes of the second conductive layers in the N+1th unit column and the N+2th unit column may be arranged mirror-symmetrically with respect to the center line of the column.

[0201] In example embodiments, positions and shapes of the second conductive layers of adjacent cell rows may be substantially the same.

[0202] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of via holes are provided on the fourth insulating layer, such as Fig.12 shown.

[0203] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12 and a thirteenth via V13.

[0204] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed sixth connecting electrode to the first region of the first active layer through the via hole.

[0205] In an exemplary embodiment, since the first active layers in some adjacent circuit units share the same first region of the first active layer, two some adjacent circuit units can share the same first via V1. For example, two circuit units in the Nth unit column and the N+1th unit column can share the same first via V1. For another example, two circuit units in the N+2th unit column and the N+3th unit column can share the same first via V1. For another example, two circuit units in the N+4th unit column and the N+5th unit column can share the same first via V1. The present disclosure can effectively reduce the number of vias and reduce the occupied area of ​​the pixel driving circuit by setting the adjacent circuit units to share the first via V1, which is conducive to achieving high resolution.

[0206] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer), and the third via hole V3 is configured to connect a subsequently formed fifth connecting electrode to the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fourth via hole V4 are etched away to expose the surface of the first area of ​​the fourth active layer, and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of ​​the fifth active layer, and the fifth via hole V5 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0210] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the sixth via hole V6 is configured to connect a subsequently formed fourth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0211] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the seventh active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of ​​the seventh active layer, and the seventh via hole V7 is configured to connect a subsequently formed second initial connection block to the first area of ​​the seventh active layer through the via hole.

[0212] In an exemplary embodiment, since the seventh active layers in some adjacent circuit units share the same first region of the seventh active layer, two partially adjacent circuit units can share the same seventh via V7. For example, two circuit units in the N+1th unit column and the N+2th unit column can share the same seventh via V7. For another example, two circuit units in the N+3th unit column and the N+4th unit column can share the same seventh via V7. For another example, two circuit units in the N+5th unit column and the N+6th unit column can share the same seventh via V7. The present disclosure can effectively reduce the number of vias and reduce the occupied area of ​​the pixel driving circuit by setting the adjacent circuit units to share the seventh via V7, which is conducive to achieving high resolution.

[0213] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the eighth via hole V8 are etched away to expose the surface of the first region of the eighth active layer, and the eighth via hole V8 is configured to connect a subsequently formed seventh connecting electrode to the first region of the eighth active layer through the via hole.

[0214] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the ninth via hole V9 are etched away to expose the surface of the second region of the eighth active layer, and the ninth via hole V9 is configured to connect a subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.

[0215] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, the third insulating layer and the fourth insulating layer in the tenth via hole V10 are etched away to expose the surface of the first electrode plate 31, and the tenth via hole V10 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 31 through the via hole.

[0216] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the second electrode plate 32, and the eleventh via hole V11 is configured to connect a subsequently formed third connecting electrode to the second electrode plate 32 through the via hole.

[0217] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the fourth insulating layer in the twelfth via hole V12 is etched away to expose the surface of the first initial connection block 41-1, and the twelfth via hole V12 is configured to connect the subsequently formed sixth connection electrode to the first initial connection block 41-1 through the via hole.

[0218] In an exemplary embodiment, since the first initial signal lines 41 in some adjacent circuit units share the same first initial connection block 41-1, two partially adjacent circuit units can share the same twelfth via V12. For example, two circuit units in the Nth unit column and the N+1th unit column can share the same twelfth via V12. For another example, two circuit units in the N+2th unit column and the N+3th unit column can share the same twelfth via V12. For another example, two circuit units in the N+4th unit column and the N+5th unit column can share the same twelfth via V12. The present disclosure can effectively reduce the number of vias and reduce the occupied area of ​​the pixel driving circuit by setting the adjacent circuit units to share the twelfth via V12, which is conducive to achieving high resolution.

[0219] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the third initial connection block 43-1 of the third initial signal line 43 on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away to expose the surface of the third initial connection block 43-1, and the thirteenth via hole V13 is configured to connect the subsequently formed seventh connection electrode to the third initial connection block 43-1 through the via hole.

[0220] In an exemplary embodiment, since the third initial signal lines 43 in some adjacent circuit units share the same third initial connection block 43-1, two partially adjacent circuit units can share the same thirteenth via V13. For example, two circuit units in the Nth unit column and the N+1th unit column can share the same thirteenth via V13. For another example, two circuit units in the N+2th unit column and the N+3th unit column can share the same thirteenth via V13. For another example, two circuit units in the N+4th unit column and the N+5th unit column can share the same thirteenth via V13. The present disclosure can effectively reduce the number of vias and reduce the occupied area of ​​the pixel driving circuit by setting the adjacent circuit units to share the thirteenth via V13, which is conducive to achieving high resolution.

[0221] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, such as Fig.13A , Fig. 13B and Fig. 13C As shown, Fig. 13B for Fig.13A A schematic plan view of a third conductive layer, Fig. 13C for Fig.13A In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0222] In an exemplary embodiment, the third conductive layer of each circuit unit in the display substrate includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57 and a second initial signal line 42.

[0223] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip having a main portion extending along the second direction Y, a first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through a second via hole V2, and a second end of the first connection electrode 51 is connected to the first electrode plate 31 through a tenth via hole V10. Since the first electrode plate 31 serves as the gate electrode of the third transistor T3, the first connection electrode 51 realizes the mutual connection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the first electrode plate 31 of the storage capacitor, thereby forming a first node N1 of the pixel driving circuit.

[0224] In an exemplary embodiment, the second connection electrode 52 may be block-shaped (eg, rectangular) and connected to the first region of the fourth active layer through a fourth via hole V4. The second connection electrode 52 is configured to be connected to a subsequently formed data signal line.

[0225] In an exemplary embodiment, the third connection electrode 53 may be in the shape of a strip extending along the second direction Y, a first end of the third connection electrode 53 is connected to the first region of the fifth active layer through a fifth via hole V5, a second end of the third connection electrode 53 is connected to the second electrode plate 32 through an eleventh via hole V11, and the third connection electrode 53 is configured to be connected to a first power line formed subsequently. In an exemplary embodiment, the third connection electrode 53 realizes the mutual connection between the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor, and the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor have the same potential.

[0226] In an exemplary embodiment, an electrode connection line 53-1 is provided on the third connection electrode 53. The shape of the electrode connection line 53-1 can be a straight line or a folded line extending along the first direction X, and the electrode connection line 53-1 can be provided on one side of the third connection electrode 53 in the first direction X or on the side in the opposite direction of the first direction X, and the first end of the electrode connection line 53-1 is connected to the third connection electrode 53 in the current circuit unit, and the second end of the electrode connection line 53-1 is connected to the third connection electrode 53 in the adjacent circuit unit in the first direction X.

[0227] In an exemplary embodiment, in at least one circuit unit, the third connection electrode 53 and the electrode connection line 53 - 1 may be an integral structure connected to each other.

[0228] In an exemplary embodiment, in a unit row, the third connection electrodes 53 in some adjacent circuit units may be interconnected integral structures. For example, the third connection electrode 53 of the N+1th unit column and the third connection electrode 53 of the N+2th unit column are interconnected through the electrode connection line 53-1 to form an interconnected integral structure. For another example, the third connection electrode 53 of the N+3th unit column and the third connection electrode 53 of the N+4th unit column are interconnected through the electrode connection line 53-1 to form an interconnected integral structure. For another example, the third connection electrode 53 of the N+5th unit column and the third connection electrode 53 of the N+6th unit column are interconnected through the electrode connection line 53-1 to form an interconnected integral structure. Since the third connecting electrode 53 in each circuit unit is connected to the first power line formed subsequently, by forming the third connecting electrodes 53 of some adjacent circuit units into an integrated structure that is interconnected, the third connecting electrodes 53 of the integrated structure can be reused as a power signal line, which can ensure that the third connecting electrodes 53 of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0229] In an exemplary embodiment, in a unit row, since the second electrodes 32 in some adjacent circuit units are connected to each other through the plate connecting strips 34, the third connecting electrodes 53 in some adjacent circuit units are connected to each other through the electrode connecting line 53-1, and the third connecting electrode 53 is connected to the second electrode 32, the first electrodes of multiple fifth transistors T5 and the second electrodes 32 of multiple storage capacitors in one unit row have the same potential, which effectively improves the uniformity of the panel, avoids poor display of the display substrate, and ensures the display effect of the display substrate.

[0230] In an exemplary embodiment, the shape of the fourth connection electrode 54 can be block-shaped (such as rectangular), and the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the sixth via hole V6, and the fourth connection electrode 54 is configured to be connected to the subsequently formed anode connection electrode.

[0231] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a strip extending along the second direction Y, a first end of the fifth connection electrode 55 is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through a third via hole V3, and a second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer through a ninth via hole V9. In an exemplary embodiment, the fifth connection electrode 55 realizes the mutual connection between the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, forming a second node N2 of the pixel driving circuit.

[0232] In an exemplary embodiment, the sixth connection electrode 56 may be in a strip shape extending along the second direction Y, a first end of the sixth connection electrode 56 is connected to the first region of the first active layer through a first via hole V1, and a second end of the sixth connection electrode 56 is connected to the first initial connection block 41-1 through a twelfth via hole V12. The sixth connection electrode 56 may serve as a first electrode of the first transistor T1, and since the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal line 41 is implemented to write the first initial signal into the first region of the first active layer.

[0233] In an exemplary embodiment, since two partially adjacent circuit units share the same first region of the first active layer, the same first initial connection block 41-1, and the same twelfth via V12, the two partially adjacent circuit units can share the same sixth connection electrode 56, that is, the pixel driving circuits in the adjacent circuit units share the first electrode of the same first transistor T1. For example, the two circuit units in the Nth unit column and the N+1th unit column can share the same sixth connection electrode 56. For another example, the two circuit units in the N+2th unit column and the N+3th unit column can share the same sixth connection electrode 56. For another example, the two circuit units in the N+4th unit column and the N+5th unit column can share the same sixth connection electrode 56. The present disclosure can effectively reduce the number of connection electrodes and reduce the occupied area of ​​the pixel driving circuit by setting the adjacent circuit units to share the sixth connection electrode 56, which is conducive to achieving high resolution.

[0234] In some other embodiments, the first regions of the first active layers of two adjacent circuit units may not be connected, and the first active layers of two adjacent circuit units may not be an integrated structure, that is, the first active layers of two adjacent circuit units are disconnected, and the first regions of the first active layers of the two circuit units may be connected through a common sixth connecting electrode 56, and the sixth connecting electrode 56 may serve as the first electrode of the first transistor T1, so that the pixel driving circuits in adjacent circuit units share the same first electrode of the first transistor T1, and the present disclosure is not limited here.

[0235] In an exemplary embodiment, the seventh connection electrode 57 may be in a strip shape extending along the first direction X, a first end of the seventh connection electrode 57 is connected to the first region of the eighth active layer through an eighth via hole V8, and a second end of the seventh connection electrode 57 is connected to the third initial connection block 43-1 through a thirteenth via hole V13. The seventh connection electrode 57 may serve as a first electrode of the eighth transistor T8, and since the third initial connection block 43-1 is connected to the third initial signal line 43, the third initial signal line 43 is implemented to write the third initial signal into the first region of the eighth active layer.

[0236] In an exemplary embodiment, in at least one unit row, the seventh connection electrodes 57 in some adjacent circuit units may be mirror-symmetric with respect to the column center line, and the seventh connection electrodes 57 in two circuit units may be interconnected integral structures, and the two circuit units may share the second end of the same seventh connection electrode 57, that is, the pixel driving circuits in adjacent circuit units share the first electrode of the eighth transistor T8. For example, the seventh connection electrodes 57 of the two circuit units in the Nth unit column and the N+1th unit column may be interconnected integral structures. For another example, the seventh connection electrodes 57 of the two circuit units in the N+2th unit column and the N+3th unit column may be interconnected integral structures. For another example, the seventh connection electrodes 57 of the two circuit units in the N+4th unit column and the N+5th unit column may be interconnected integral structures. The present disclosure can effectively reduce the occupied space of the connection electrode and the occupied area of ​​the pixel driving circuit by setting the seventh connection electrodes 57 of the adjacent circuit units as an interconnected integral structure, which is conducive to achieving high resolution.

[0237] In some other embodiments, the first regions of the eighth active layer of two adjacent circuit units may be connected to each other, the eighth active layers of two adjacent circuit units may be an integrated structure connected to each other, and the first region of the eighth active layer may serve as the first electrode of the eighth transistor T8, so that the pixel driving circuits in adjacent circuit units share the same first electrode of the eighth transistor T8, which is not limited in the present disclosure.

[0238] In an exemplary embodiment, the second initial signal line 42 may be in the shape of a straight line or a folded line extending along the first direction X, and may be arranged on the side of the third initial signal line 43 close to the second electrode plate 32. A second initial connection block 42-1 may be arranged on the second initial signal line 42, and the shape of the second initial connection block 42-1 may be block-shaped (such as rectangular). In the first direction X, the second initial connection block 42-1 may be arranged between some adjacent circuit units, and in the second direction Y, the second initial connection block 42-1 may be arranged on the side of the second initial signal line 42 away from the second electrode plate 32, and connected to the second initial signal line 42, and the second initial connection block 42-1 is connected to the first area of ​​the seventh active layer through the seventh via V7. The second initial connection block 42-1 may serve as the first electrode of the seventh transistor T7, and since the second initial connection block 42-1 is connected to the second initial signal line 42, the second initial signal line 42 is realized to write the second initial signal into the first area of ​​the seventh active layer.

[0239] In an exemplary embodiment, the second preliminary signal line 42 and the plurality of second preliminary connection blocks 42 - 1 in one cell row may be an integral structure connected to each other.

[0240] In an exemplary embodiment, since two partially adjacent circuit units share the same first region of the seventh active layer and the same seventh via V7, two partially adjacent circuit units in a unit row can share the same second initial connection block 42-1, that is, the pixel driving circuits in the adjacent circuit units share the first electrode of the seventh transistor T7. For example, the two circuit units in the N+1th unit column and the N+2th unit column can share the same second initial connection block 42-1. For another example, the two circuit units in the N+3th unit column and the N+4th unit column can share the same second initial connection block 42-1. For another example, the two circuit units in the N+5th unit column and the N+6th unit column can share the same second initial connection block 42-1. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connecting electrodes, and reduce the occupied area of ​​the pixel driving circuit by setting the partially adjacent circuit units to share the second initial connection block 42-1, which is conducive to achieving high resolution.

[0241] In some other embodiments, the first regions of the seventh active layer of two adjacent circuit units may not be connected, and the seventh active layer of two adjacent circuit units may not be an integrated structure, that is, the seventh active layer of two adjacent circuit units is disconnected, and the first regions of the seventh active layer of the two circuit units may be connected through a common second initial connection block 42-1, and the second initial connection block 42-1 may serve as the first electrode of the seventh transistor T7, so that the pixel driving circuits in adjacent circuit units share the same first electrode of the seventh transistor T7, and the present disclosure is not limited here.

[0242] In exemplary embodiments, the third conductive layer may further include an eighth connection electrode 58 and a dummy connection electrode 59 .

[0243] In an exemplary embodiment, in the first direction X, the eighth connection electrode 58 may be disposed between some adjacent circuit units, and in the second direction Y, the eighth connection electrode 58 may be disposed on one side of the second initial signal line 42 close to the second electrode plate 32 .

[0244] In an exemplary embodiment, the eighth connection electrode 58 may include a connection electrode strip 58-1 and a connection electrode block 58-2. The connection electrode strip 58-1 may be in the shape of a strip extending along the second direction Y, and the connection electrode block 58-2 may be in the shape of a block (such as a rectangle). The first end of the connection electrode strip 58-1 is connected to the second initial signal line 42, and the second end of the connection electrode strip 58-1 is extended in the direction close to the second electrode plate 32, and then connected to the connection electrode block 58-2, and the connection electrode block 58-2 is configured to be connected to the second initial connection line formed subsequently.

[0245] In an exemplary embodiment, an orthographic projection of the connecting electrode block 58 - 2 on the substrate at least partially overlaps an orthographic projection of the plate connecting bar 34 on the substrate.

[0246] In an exemplary embodiment, in at least one circuit unit, the second initial signal line 42, the connection electrode bar 58-1, and the connection electrode block 58-2 may be an integral structure connected to each other.

[0247] In an exemplary embodiment, four circuit units may be spaced between the eighth connection electrodes 58 adjacent to each other in the first direction X. For example, the eighth connection electrode 58 may be disposed between the N+2th unit column and the N+3th unit column. For another example, the eighth connection electrode 58 may be disposed between the N+6th unit column and the N+7th unit column.

[0248] In an exemplary embodiment, in the first direction X, the dummy connection electrode 59 may be disposed between some adjacent circuit units, and in the second direction Y, the dummy connection electrode 59 may be disposed on one side of the second initial signal line 42 close to the second electrode plate 32 .

[0249] In an exemplary embodiment, the dummy connection electrode 59 may include a dummy electrode strip 59-1 and a dummy electrode block 59-2. The dummy electrode strip 59-1 may be in the shape of a strip extending along the second direction Y, and the dummy electrode block 59-2 may be in the shape of a block (such as a rectangle). The first end of the dummy electrode strip 59-1 is connected to the second initial signal line 42, and the second end of the dummy electrode strip 59-1 is extended in the direction close to the second electrode plate 32 and then connected to the dummy electrode block 59-2. In an exemplary embodiment, the dummy electrode strip 59-1 is configured to overlap with the anode formed subsequently to improve the uniformity of the anode.

[0250] In an exemplary embodiment, the orthographic projection of the dummy electrode block 59 - 2 on the substrate at least partially overlaps with the orthographic projection of the plate connecting bar 34 on the substrate.

[0251] In an exemplary embodiment, in at least one circuit unit, the second initial signal line 42, the dummy electrode bar 59-1, and the dummy electrode block 59-2.

[0252] In an exemplary embodiment, four circuit units may be spaced between adjacent dummy connection electrodes 59 in the first direction X. For example, the dummy connection electrode 59 may be disposed between the Nth unit column and the N+1th unit column. For another example, the dummy connection electrode 59 may be disposed between the N+4th unit column and the N+5th unit column.

[0253] In an exemplary embodiment, one dummy connection electrode 59 may be provided between adjacent eighth connection electrodes 58 in the first direction X, and one eighth connection electrode 58 may be provided between adjacent dummy connection electrodes 59 in the first direction X, that is, the eighth connection electrodes 58 and the dummy connection electrodes 59 are alternately provided in the first direction X.

[0254] In an exemplary embodiment, the position and shape of the eighth connection electrode 58 in one circuit unit may be substantially the same as the position and shape of the dummy connection electrode 59 in another circuit unit, and the connection electrode block 58-2 and the dummy electrode block 59-2 may be located on the same straight line extending along the first direction X.

[0255] In some other embodiments, the display substrate may be provided with only dummy electrode strips 59-1, but not dummy electrode blocks 59-2. Fig. 13C As shown, the present disclosure is not limited here.

[0256] In an exemplary embodiment, the third conductive layer may further include a first connection line 81 . The first connection line 81 may be in a straight line or a zigzag line shape extending along the first direction X, and may be located between the second scan signal line 22 and the first initial signal line 41 .

[0257] In an exemplary embodiment, the orthographic projection of the first connecting line 81 on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer on the substrate, and the orthographic projection of the first connecting line 81 on the substrate at least partially overlaps with the orthographic projection of the third shielding electrode 63 on the substrate, that is, the third shielding electrode 63 is arranged between the second region of the first active layer in the semiconductor layer and the first connecting line 81 in the third conductive layer.

[0258] In an exemplary embodiment, the orthographic projection of the first connecting line 81 on the substrate and the orthographic projection of the second area of ​​the first active layer on the substrate have an overlapping area, and the orthographic projection of the third shielding electrode 63 on the substrate may include the overlapping area, so that the third shielding electrode 63 can shield the first connecting line 81, thereby avoiding the influence of the data voltage jump in the first connecting line 81 on the first transistor T1 and the second transistor T2, reducing the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improving the display effect.

[0259] In an exemplary embodiment, the first connection line 81 in at least one circuit unit may be provided with a first break K1 , and the first break K1 may cut off the first connection line 81 , so that the first connection lines 81 on both sides of the first break K1 are insulated from each other.

[0260] In an exemplary embodiment, at least one first break K1 may be disposed in the circuit unit of the Nth unit column, and an orthographic projection of the first break K1 on the substrate at least partially overlaps an orthographic projection of the third shielding electrode 63 on the substrate.

[0261] In an exemplary embodiment, the orthographic projection of the first break K1 on the substrate can be located within the range of the orthographic projection of the third shielding electrode 63 on the substrate, so that the third shielding electrode 63 can pad the first break K1 from the bottom, which can effectively eliminate the film layer differences in different areas, facilitate shadow elimination, and avoid poor appearance of the display substrate.

[0262] In an exemplary embodiment, the first connection line 81 may include a first connection sub-line 81-1 located on one side of the first break K1 in the first direction X and a second connection sub-line 81-2 located on the other side of the first break K1 in the first direction X, the first connection sub-line 81-1 being configured to be connected to a data signal line in the display area, and the second connection sub-line 81-2 being configured as a first dummy line.

[0263] In an exemplary embodiment, the second connection sub-line 81 - 2 as the first dummy line may not be connected to any signal line, or may be connected to the first power line, or may be connected to the second power line, which is not limited in the present disclosure.

[0264] In an exemplary embodiment, the third conductive layer may further include a data connection electrode 83. The data connection electrode 83 may be in a strip shape extending along the second direction Y. In the first direction X, the data connection electrode 83 may be disposed between partially adjacent circuit units. In the second direction Y, the data connection electrode 83 may be disposed on a side of the first connection line 81 close to the second electrode plate 32, and the data connection electrode 83 is configured to be connected to a second connection line formed subsequently.

[0265] In an exemplary embodiment, two circuit units may be spaced between adjacent data connection electrodes 83 in the first direction X. For example, the data connection electrode 83 may be disposed between the N-1th unit column and the Nth unit column. For another example, the data connection electrode 83 may be disposed between the N+1th unit column and the N+2th unit column. For another example, the data connection electrode 83 may be disposed between the N+3th unit column and the N+4th unit column. For another example, the data connection electrode 83 may be disposed between the N+5th unit column and the N+6th unit column. For another example, the data connection electrode 83 may be disposed between the N+7th unit column and the N+8th unit column.

[0266] In an exemplary embodiment, the data connection electrode 83 may include at least a first connection sub-block 83-1, a second connection sub-block 83-2, and a connection sub-strip 83-3. The first connection sub-block 83-1 and the second connection sub-block 83-2 may be in a block shape (e.g., rectangular) and configured to be connected to a second connection line formed subsequently. The connection sub-strip 83-3 may be in a strip shape extending along the second direction Y and may be disposed between the first connection sub-block 83-1 and the second connection sub-block 83-2, one end of the connection sub-strip 83-3 being connected to the first connection sub-block 83-1, and the other end of the connection sub-strip 83-3 being connected to the second connection sub-block 83-2.

[0267] In an exemplary embodiment, in at least one circuit unit, the first connection sub-block 83 - 1 , the second connection sub-block 83 - 2 , and the connection sub-strip 83 - 3 may be an integral structure connected to each other.

[0268] In an exemplary embodiment, an orthographic projection of the data connection electrode 83 on the substrate at least partially overlaps an orthographic projection of the second shielding electrode 62 on the substrate.

[0269] In an exemplary embodiment, an orthographic projection of the first connection sub-block 83 - 1 of the data connection electrode 83 on the substrate may be located within a range of an orthographic projection of the second shielding electrode 62 on the substrate.

[0270] In an exemplary embodiment, at least one circuit unit may further include a data connection block 84. The data connection block 84 may be in the shape of a strip extending along the second direction Y. In the first direction X, the data connection block 84 may be disposed in the middle of some adjacent circuit units. In the second direction Y, the data connection block 84 may be disposed between the first connection sub-line 81-1 and the data connection electrode 83. A first end of the data connection block 84 is connected to the first connection sub-line 81-1, and a second end of the data connection block 84 is connected to the data connection electrode 83. Since the first connection sub-line 81-1 and the data connection electrode 83 are connected together through the data connection block 84, and the data connection electrode 83 is configured to be connected to a second connection line formed subsequently, the data connection block 84 can realize the mutual connection between the first connection sub-line 81-1 and the second connection line.

[0271] In an exemplary embodiment, in at least one circuit unit, the first connection sub-line 81 - 1 , the data connection electrode 83 , and the data connection block 84 may be an integral structure connected to each other.

[0272] In an exemplary embodiment, the data connection block 84 may be disposed between the N-1th cell column and the Nth cell column, while the data connection electrodes 83 between the N+1th cell column and the N+2th cell column, between the N+3th cell column and the N+4th cell column, between the N+5th cell column and the N+6th cell column, and between the N+7th cell column and the N+8th cell column are not connected to the second connection sub-line 81-2.

[0273] In an exemplary embodiment, the third conductive layer patterns of adjacent unit columns (except the data connection block and the first break) can be arranged in mirror symmetry with respect to the column center line. For example, the position and shape of the third conductive layer in the Nth unit column and the N+1th unit column can be arranged in mirror symmetry with respect to the column center line. For another example, the position and shape of the second conductive layer in the N+1th unit column and the N+2th unit column can be arranged in mirror symmetry with respect to the column center line.

[0274] In example embodiments, positions and shapes of the third conductive layers of adjacent cell rows may be substantially the same.

[0275] (6) Forming a fifth insulating layer and a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: first depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the fifth insulating layer, wherein a plurality of via holes are disposed on the first planar layer and the fifth insulating layer, such as Fig.14 shown.

[0276] In an exemplary embodiment, the plurality of via holes in each circuit unit in the display substrate includes at least a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 .

[0277] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer and the fifth insulating layer in the twenty-first via hole V21 are removed to expose the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the second connecting electrode 52 through the via hole.

[0278] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer and the fifth insulating layer in the twenty-second via hole V22 are removed to expose the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect a subsequently formed first power line to the third connecting electrode 53 through the via hole.

[0279] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer and the fifth insulating layer in the twenty-third via hole V23 are removed to expose the surface of the fourth connecting electrode 54, and the twenty-third via hole V23 is configured to connect a subsequently formed anode connecting electrode to the fourth connecting electrode 54 through the via hole.

[0280] In an exemplary embodiment, at least one circuit unit may further include a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the data connection electrode 83 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fourth via hole V24 are removed, and the surface of the data connection electrode 83 is exposed. The twenty-fourth via hole V24 is configured to connect the second connection line formed subsequently to the data connection electrode 83 through the via hole.

[0281] In an exemplary embodiment, two circuit units may be spaced between the twenty-fourth vias V24 adjacent to each other in the first direction X. For example, the twenty-fourth via V24 may be disposed between the N-1th unit column and the Nth unit column. For another example, the twenty-fourth via V24 may be disposed between the N+1th unit column and the N+2th unit column. For another example, the twenty-fourth via V24 may be disposed between the N+3th unit column and the N+4th unit column. For another example, the twenty-fourth via V24 may be disposed between the N+5th unit column and the N+6th unit column. For another example, the twenty-fourth via V24 may be disposed between the N+7th unit column and the N+8th unit column.

[0282] In an exemplary embodiment, there may be two twenty-fourth via holes V24. The orthographic projection of one twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the first connecting sub-block 83-1 on the substrate, and the orthographic projection of the other twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the second connecting sub-block 83-2 on the substrate.

[0283] In an exemplary embodiment, at least one circuit unit may further include a twenty-fifth via hole V25. The orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 56 on the substrate, the first flat layer and the fifth insulating layer in the twenty-fifth via hole V25 are removed, and the surface of the sixth connection electrode 56 is exposed, and the twenty-fifth via hole V25 is configured to connect the first initial connection line formed subsequently to the sixth connection electrode 56 through the via hole.

[0284] In an exemplary embodiment, eight circuit units may be spaced between the twenty-fifth via holes V25 adjacent to each other in the first direction X. For example, the twenty-fifth via hole V25 may be disposed between the Nth unit column and the N+1th unit column. For another example, the twenty-fifth via hole V25 may be disposed between the N+8th unit column and the N+9th unit column.

[0285] In an exemplary embodiment, at least one circuit unit may further include a twenty-sixth via hole V26. The orthographic projection of the twenty-sixth via hole V26 on the substrate is located within the range of the orthographic projection of the connection electrode block 58-2 of the eighth connection electrode 58 on the substrate, the first flat layer and the fifth insulating layer in the twenty-sixth via hole V26 are removed, exposing the surface of the connection electrode block 58-2, and the twenty-sixth via hole V26 is configured to connect the second initial connection line formed subsequently to the connection electrode block 58-2 through the via hole.

[0286] In an exemplary embodiment, four circuit units may be spaced between the twenty-sixth vias V26 adjacent to each other in the first direction X. For example, the twenty-sixth via V26 may be disposed between the N+2th unit column and the N+3th unit column. For another example, the twenty-sixth via V26 may be disposed between the N+6th unit column and the N+7th unit column.

[0287] In an exemplary embodiment, at least one circuit unit may further include a twenty-seventh via hole V27. The orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the seventh connection electrode 57 on the substrate, the first flat layer and the fifth insulating layer in the twenty-seventh via hole V27 are removed, and the surface of the seventh connection electrode 57 is exposed, and the twenty-seventh via hole V27 is configured to connect the third initial connection line formed subsequently to the seventh connection electrode 57 through the via hole.

[0288] In an exemplary embodiment, eight circuit units may be spaced between the twenty-seventh vias V27 adjacent to each other in the first direction X. For example, the twenty-seventh via V27 may be disposed between the N+4th unit column and the N+5th unit column. For another example, the twenty-seventh via V27 may be disposed between the N+12th unit column and the N+13th unit column.

[0289] In an exemplary embodiment, at least one circuit unit may further include a twenty-eighth via hole V28. The orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the seventh connection electrode 57 on the substrate, the first flat layer in the twenty-eighth via hole V28 is removed, and the surface of the fifth insulating layer covering the seventh connection electrode 57 is exposed, and the twenty-eighth via hole V28 is configured to make the morphology presented by the first initial connection line and the second initial connection line formed subsequently substantially the same as the morphology presented by the third initial connection line formed subsequently, which can not only improve the uniformity of the etching process, but also improve the uniformity of the anode formed subsequently.

[0290] In an exemplary embodiment, the twenty-seventh via V27 can be called a connecting via, and the twenty-eighth via V28 can be called a dummy via. The position and shape of the twenty-seventh via V27 in one circuit unit can be basically the same as the position and shape of the twenty-eighth via V28 in another circuit unit. The difference is that the first flat layer and the fifth insulating layer in the twenty-seventh via V27 are removed, exposing the surface of the seventh connecting electrode 57, so that the connection between the third initial connecting line and the seventh connecting electrode 57 can be realized, while only the first flat layer is removed in the twenty-eighth via V28, and the seventh connecting electrode 57 is still covered by the fifth insulating layer. Therefore, the first initial connecting line or the second initial connecting line formed subsequently will not be connected to the seventh connecting electrode 57.

[0291] In an exemplary embodiment, the twenty-seventh via hole V27 and the twenty-eighth via hole V28 may be located on the same straight line extending along the first direction X.

[0292] In an exemplary embodiment, for a layout in which the twenty-seventh via V27 is disposed between the N+4th unit column and the N+5th unit column, the twenty-eighth via V28 may be disposed between the Nth unit column and the N+1th unit column, between the N+2th unit column and the N+3th unit column, and between the N+6th unit column and the N+7th unit column, respectively.

[0293] In an exemplary embodiment, at least one circuit unit may further include a twenty-ninth via hole V29. The orthographic projection of the twenty-ninth via hole V29 on the substrate is located within the range of the orthographic projection of the dummy electrode block 59-2 of the dummy connecting electrode 59 on the substrate, the first flat layer in the twenty-ninth via hole V29 is removed, exposing the surface of the fifth insulating layer covering the dummy electrode block 59-2, and the twenty-ninth via hole V29 is configured to make the morphology presented by the first initial connecting line and the third initial connecting line formed subsequently substantially the same as the morphology presented by the second initial connecting line formed subsequently, which can not only improve the uniformity of the etching process, but also improve the uniformity of the anode formed subsequently.

[0294] In an exemplary embodiment, four circuit units may be spaced between the twenty-ninth vias V29 adjacent to each other in the first direction X. For example, the twenty-ninth via V29 may be disposed between the Nth unit column and the N+1th unit column. For another example, the twenty-ninth via V29 may be disposed between the N+4th unit column and the N+5th unit column.

[0295] In an exemplary embodiment, the twenty-sixth via V26 can be called a connecting via, and the twenty-ninth via V29 can be called a dummy via. The position and shape of the twenty-sixth via V26 in one circuit unit can be basically the same as the position and shape of the twenty-ninth via V29 in another circuit unit. The difference is that the first flat layer and the fifth insulating layer in the twenty-sixth via V26 are removed, exposing the surface of the eighth connecting electrode 58, so that the connection between the second initial connecting line and the eighth connecting electrode 58 can be realized, while only the first flat layer is removed in the twenty-ninth via V29, and the dummy connecting electrode 59 is still covered by the fifth insulating layer, so that the first initial connecting line or the third initial connecting line formed subsequently will not be connected to the dummy connecting electrode 59.

[0296] In an exemplary embodiment, the twenty-sixth via hole V26 and the twenty-ninth via hole V29 may be located on the same straight line extending along the first direction X.

[0297] In some other embodiments, the display substrate may not be provided with a fifth insulating layer, which is not limited in the present disclosure. For the case where the display substrate is not provided with a fifth insulating layer, this process may include: directly coating a first flat film on the substrate on which the aforementioned pattern is formed, patterning the first flat film using a halftone or gray tone patterning process, forming a first flat layer covering the pattern of the fourth conductive layer, and a plurality of vias are provided on the first flat layer. The first flat layer in the twenty-sixth via hole V26 and the twenty-seventh via hole V27 as connecting via holes is completely removed, exposing the surfaces of the seventh connecting electrode 57 and the eighth connecting electrode 58, respectively, so that the corresponding initial connecting lines can be connected to the seventh connecting electrode 57 and the eighth connecting electrode 58, respectively. The first flat layer in the twenty-eighth via hole V28 and the twenty-ninth via hole V29 as dummy via holes is partially removed, and the seventh connecting electrode 57 and the dummy connecting electrode 59 are still covered by the first flat layer, so that the corresponding initial connecting lines formed subsequently will not be connected to the seventh connecting electrode 57 and the dummy connecting electrode 59. The half-tone or gray-tone patterning process can achieve the goal of retaining a first planar layer of a certain thickness in the dummy via hole, while the first planar layers in other via holes are completely removed.

[0298] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first planar layer, such as Fig.15A and Fig. 15B As shown, Fig. 15B for Fig.15A In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0299] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate includes at least a first power line 71 , a data signal line 72 , and an anode connection electrode 73 .

[0300] In an exemplary embodiment, the shape of the first power line 71 may be a straight line or a folded line with the main portion extending along the second direction Y, and the first power line 71 is connected to the third connection electrode 53 through the twenty-second via hole V22. Since the third connection electrode 53 is respectively connected to the second electrode plate 32 and the first region of the fifth active layer through the via hole, the first power line 71 can write the first power signal to the second electrode plate 32 and the first electrode of the fifth transistor T5.

[0301] In an exemplary embodiment, the first power line 71 may be a folded line with a variable width, and the orthographic projection of the first power line 71 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the first power line 71 with a constant potential may shield the first node N1, thereby preventing the influence of the data voltage jump on the first node N1, improving the working stability of the pixel driving circuit, and improving the display effect.

[0302] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate may include the orthographic projection of the first connection electrode 51 on the substrate, that is, the first power line 71 may completely cover the first connection electrode 51 .

[0303] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate may include the orthographic projection of the first break K1 on the substrate, so that the first power line 71 can block the first break K1 from above, which can effectively eliminate the film layer differences in different areas, facilitate shadow elimination, and avoid poor appearance of the display substrate.

[0304] In an exemplary embodiment, the shape of the data signal line 72 may be a straight line or a folded line with the main portion extending along the second direction Y, and the data signal line 72 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 is connected to the first region of the fourth active layer through the via hole, the data signal line 72 can write the data signal to the first electrode of the fourth transistor T4.

[0305] In an exemplary embodiment, the orthographic projection of the data signal line 72 on the substrate does not overlap with the orthographic projection of the channel regions of the first transistor T1 to the eighth transistor T8 on the substrate, thereby avoiding signal crosstalk caused by data voltage jumps of the data signal line 72 and avoiding the influence of the data voltage jumps on the first transistor T1 to the eighth transistor T8, thereby improving the working stability of the pixel driving circuit and the display effect.

[0306] In an exemplary embodiment, the anode connection electrode 73 may be in the shape of a strip extending along the second direction Y, and the anode connection electrode 73 is connected to the fourth connection electrode 54 through the twenty-third via hole V23, and the anode connection electrode 73 is configured to be connected to the subsequently formed anode. Since the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, the pixel driving circuit can output a driving current to the light-emitting device.

[0307] In an exemplary embodiment, the fourth conductive layer may further include a second connection line 82. The second connection line 82 may be in the shape of a straight line or a folded line with a main portion extending along the second direction Y. In the first direction X, the second connection line 82 may be disposed between the first power lines 71 of some adjacent unit columns, and in the second direction Y, the second connection lines 82 may be disposed at intervals. One second connection line 82 may be connected to the first connection sub-block 83-1 through a twenty-fourth via hole V24, and another second connection line 82 may be connected to the second connection sub-block 83-2 through another twenty-fourth via hole V24, thereby realizing the connection of two second connection lines 82.

[0308] In an exemplary embodiment, the second connection line 82 in at least one circuit unit may be provided with a second break K2 , and the second break K2 may cut off the second connection line 82 , so that the second connection lines 82 on both sides of the second break K2 are insulated from each other.

[0309] In an exemplary embodiment, an orthographic projection of the at least one second break K2 on the substrate at least partially overlaps with an orthographic projection of the second initial connection block 42 - 1 on the substrate.

[0310] In an exemplary embodiment, the orthographic projection of the second break K2 on the substrate can be located within the range of the orthographic projection of the second initial connection block 42-1 on the substrate, so that the second initial connection block 42-1 can pad the second break K2 from the bottom, which can effectively eliminate the film layer differences in different areas, which is beneficial to eliminating shadows and avoiding poor appearance of the display substrate.

[0311] In an exemplary embodiment, the second connecting line 82 may include a third connecting sub-line 82-3 located on one side of the second direction Y of the second break K2 and a fourth connecting sub-line 82-4 located on the opposite side of the second direction Y of the second break K1, the third connecting sub-line 82-3 being configured to be connected to the data lead-out line in the binding area, and the fourth connecting sub-line 82-4 being configured as a second dummy line.

[0312] In an exemplary embodiment, the fourth connection sub-line 82 - 4 as the second dummy line may not be connected to any signal line, or may be connected to the first power line, or may be connected to the second power line, which is not limited in the present disclosure.

[0313] In an exemplary embodiment, two circuit units may be spaced between the adjacent second connection lines 82 in the first direction X. For example, the second connection line 82 may be disposed between the first power line 71 of the N-1th unit column and the Nth unit column. For another example, the second connection line 82 may be disposed between the first power line 71 of the N+1th unit column and the N+2th unit column. For another example, the second connection line 82 may be disposed between the first power line 71 of the N+3th unit column and the N+4th unit column. For another example, the second connection line 82 may be disposed between the first power line 71 of the N+5th unit column and the N+6th unit column. For another example, the second connection line 82 may be disposed between the first power line 71 of the N+7th unit column and the N+8th unit column.

[0314] In an exemplary embodiment, since the data connection electrode 83 arranged between the N-1th unit column and the Nth unit column is connected to the first connection sub-line 81-1 through the data connection block 84, the first connection sub-line 81-1 is configured to be connected to the data signal line in the display area, and the second connection line 82 is configured to be connected to the data lead-out line in the binding area, the first connection line 81 extending along the first direction X of the main part and the second connection line 82 extending along the second direction Y of the main part are interconnected, and the data lead-out line in the binding area is connected to the data signal line in the display area through the first connection line 81 and the second connection line 82.

[0315] In an exemplary embodiment, in the first direction X, the second connection line 82 can be arranged between adjacent first power lines 71, and the first power line 71 with a constant potential can shield the influence of the data voltage jump of the second connection line 82 on the key nodes of the pixel driving circuit, thereby improving the working stability of the pixel driving circuit and improving the display effect.

[0316] In an exemplary embodiment, the fourth conductive layer may further include a first initial connection line 91. The first initial connection line 91 may be in the shape of a straight line or a folded line with a main portion extending along the second direction Y, and may be disposed between the data signal lines 72 of some adjacent unit columns, and the first initial connection line 91 may be connected to the sixth connection electrode 56 through the twenty-fifth via hole V25. Since the sixth connection electrode 56 is connected to the first initial connection block 41-1, and the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal line 41 extending along the first direction X and the first initial connection line 91 extending along the second direction Y form a meshed connection structure for transmitting the first initial signal, which can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0317] In an exemplary embodiment, the first initial signal line 41 may be disposed in each unit row, the first initial connection line 91 may be disposed in a portion of the unit columns, and eight circuit units may be spaced between adjacent first initial connection lines 91 in the first direction X. For example, the first initial connection line 91 may be disposed between the data signal line 72 of the Nth unit column and the N+1th unit column. For another example, the first initial connection line 91 may be disposed between the data signal line 72 of the N+8th unit column and the N+9th unit column.

[0318] In an exemplary embodiment, the fourth conductive layer may further include a second initial connection line 92. The second initial connection line 92 may be in the shape of a straight line or a folded line with a main portion extending along the second direction Y, and may be disposed between the data signal lines 72 of some adjacent unit columns, and the second initial connection line 92 may be connected to the connection electrode block 58-2 through the twenty-sixth via hole V26. Since the connection electrode block 58-2 is connected to the connection electrode strip 58-1, and the connection electrode strip 58-1 is connected to the second initial signal line 42, the second initial signal line 42 extending along the first direction X and the second initial connection line 92 extending along the second direction Y form a meshed connection structure for transmitting the second initial signal, which can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0319] In an exemplary embodiment, the second initial signal line 42 may be disposed in each unit row, the second initial connection line 92 may be disposed in a portion of the unit columns, and four circuit units may be spaced between the adjacent second initial connection lines 92 in the first direction X. For example, the second initial connection line 92 may be disposed between the data signal line 72 of the N+2 unit column and the N+3 unit column. For another example, the second initial connection line 92 may be disposed between the data signal line 72 of the N+6 unit column and the N+7 unit column.

[0320] In an exemplary embodiment, the fourth conductive layer may further include a third initial connection line 93. The third initial connection line 93 may be in the shape of a straight line or a folded line with a main portion extending along the second direction Y, and may be disposed between the data signal lines 72 of some adjacent unit columns, and the third initial connection line 93 may be connected to the seventh connection electrode 57 through the twenty-seventh via hole V27. Since the seventh connection electrode 57 is connected to the third initial connection block 43-1, and the third initial connection block 43-1 is connected to the third initial signal line 43, the third initial signal line 43 extending along the first direction X and the third initial connection line 93 extending along the second direction Y form a meshed connection structure for transmitting the third initial signal, which can effectively reduce the resistance of the third initial signal line, reduce the voltage drop of the third initial signal, effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0321] In an exemplary embodiment, the third initial signal line 43 may be disposed in each unit row, the third initial connection line 93 may be disposed in a portion of the unit columns, and eight circuit units may be spaced between adjacent third initial connection lines 93 in the first direction X. For example, the third initial connection line 93 may be disposed between the data signal line 72 of the N+4th unit column and the N+5th unit column. For another example, the third initial connection line 93 may be disposed between the data signal line 72 of the N+12th unit column and the N+13th unit column.

[0322] In an exemplary embodiment, the first initial connection line 91, the second initial connection line 92, the third initial connection line 93, and the second initial connection line 92 may be periodically arranged in the first direction X, two second initial connection lines 92 and one third initial connection line 93 may be arranged between two adjacent first initial connection lines 91 in the first direction X, one first initial connection line 91 or one third initial connection line 93 may be arranged between two adjacent second initial connection lines 92 in the first direction X, and one first initial connection line 91 and two second initial connection lines 92 may be arranged between two adjacent third initial connection lines 93 in the first direction X. In the first direction X, the first initial connection line 91 may be arranged between two second initial connection lines 92, the second initial connection line 92 may be arranged between the first initial connection line 91 and the third initial connection line 93, and the third initial connection line 93 may be arranged between two second initial connection lines 92.

[0323] In an exemplary embodiment, the first initial connection line 91 and the second initial connection line 92 may also fill the twenty-eighth via hole V28, that is, the first initial connection line 91 and the second initial connection line 92 are at least partially disposed in the dummy via hole. Since only the first flat layer is removed from the twenty-eighth via hole V28, the seventh connection electrode 57 is still covered by the fifth insulating layer, or only a portion of the first flat layer is removed from the twenty-eighth via hole V28, the seventh connection electrode 57 is still covered by the first flat layer, and thus the first initial connection line 91 and the second initial connection line 92 are not connected to the seventh connection electrode 57.

[0324] In an exemplary embodiment, the morphology presented by the first initial connection line 91 and the second initial connection line 92 filling the twenty-eighth via hole V28 and the morphology presented by the third initial connection line 93 connecting the seventh connection electrode 57 through the twenty-seventh via hole V27 can be basically the same, which can not only enable different areas to achieve the same display effect under transmitted and reflected light, realize shadow elimination, effectively avoid the poor appearance of the display substrate and the occurrence of off-screen watermarks (mura), improve the display quality, but also improve the uniformity of the subsequently formed anode.

[0325] In an exemplary embodiment, the first initial connection line 91 and the third initial connection line 93 may also fill the twenty-ninth via hole V29, that is, the first initial connection line 91 and the third initial connection line 93 are at least partially disposed in the dummy via hole. Since only the first flat layer is removed from the twenty-ninth via hole V29, the dummy connection electrode 59 is still covered by the fifth insulating layer, or only a portion of the first flat layer is removed from the twenty-ninth via hole V29, the dummy connection electrode 59 is still covered by the first flat layer, and thus the first initial connection line 91 and the third initial connection line 93 are not connected to the dummy connection electrode 59.

[0326] In an exemplary embodiment, the morphology presented by the first initial connection line 91 and the third initial connection line 93 filling the twenty-ninth via hole V29 can be basically the same as the morphology presented by the second initial connection line 92 connecting the eighth connection electrode 58 through the twenty-sixth via hole V26. This can not only enable different areas to achieve the same display effect under transmitted and reflected light, realize shadow elimination, effectively avoid the poor appearance of the display substrate and the occurrence of off-screen watermarks (mura), improve display quality, but also improve the uniformity of the subsequently formed anode.

[0327] In an exemplary embodiment, the first initial connection line 91, the second initial connection line 92 and the third initial connection line 93 are arranged between adjacent data signal lines 72. The first initial connection line 91, the second initial connection line 92 and the third initial connection line 93 with a constant potential can shield the influence between the data signal lines 72, improve the working stability of the pixel driving circuit, and improve the display effect.

[0328] In an exemplary embodiment, the fourth conductive layer patterns of adjacent unit columns (except the second break) may be arranged mirror-symmetrically with respect to the center line of the column. For example, the position and shape of the fourth conductive layer in the Nth unit column and the N+1th unit column may be arranged mirror-symmetrically with respect to the center line of the column. For another example, the position and shape of the fourth conductive layer in the N+1th unit column and the N+2th unit column may be arranged mirror-symmetrically with respect to the center line of the column.

[0329] In example embodiments, positions and shapes of the fourth conductive layers of adjacent cell rows may be substantially the same.

[0330] (8) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer pattern, and providing a plurality of anode vias V30 on the second planar layer, such as Fig.16 shown.

[0331] In an exemplary embodiment, the orthographic projection of the anode via hole V30 of each circuit unit in the display substrate on the substrate is located within the range of the orthographic projection of the anode connecting electrode 73 on the substrate, the second flat layer in the anode via hole V30 is removed to expose the surface of the anode connecting electrode 73, and the anode via hole V30 is configured to connect a subsequently formed anode to the anode connecting electrode 73 through the via hole.

[0332] At this point, the driving structure layer of this embodiment is prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, each of which may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power line, and a data signal line connected to the pixel driving circuit.

[0333] In a direction perpendicular to the display substrate, the driving structure layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer and a second flat layer sequentially arranged on the substrate. The semiconductor layer may include at least an active layer of a plurality of polysilicon transistors, the first conductive layer may include at least a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line and a first plate of a storage capacitor, the second conductive layer may include at least a first initial signal line, a third initial signal line and a second plate of a storage capacitor, the third conductive layer may include at least a first connecting line, a second initial signal line and a plurality of connecting electrodes, and the fourth conductive layer may include at least a first power supply line, a second connecting line and a data signal line.

[0334] In some other embodiments, the first initial signal line, the second initial signal line, and the third initial signal line may be arranged in at least one of the second conductive layer and the third conductive layer, which is not limited in the present disclosure. For example, the second initial signal line may be arranged in the second conductive layer, and the first initial signal line and the third initial signal line may be arranged in the third conductive layer. For another example, the first initial signal line, the second initial signal line, and the third initial signal line may all be arranged in the second conductive layer. For another example, the first initial signal line, the second initial signal line, and the third initial signal line may all be arranged in the third conductive layer.

[0335] In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0336] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multilayer or a composite layer. The first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), etc., or may be made of alloy materials composed of metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc., and may be a single layer structure, or may be a multilayer composite structure, such as Ti / Al / Ti, etc. The first planar layer and the second planar layer may be made of organic materials, such as resin or polyimide.

[0337] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer may be prepared on the driving structure layer, and the preparation process of the light emitting structure layer may include the following operations.

[0338] (9) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate formed with the aforementioned pattern, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, such as Fig.17A and Fig. 17B As shown, Fig. 17B for Fig.17A Schematic diagram of the plan view of the anode conductive layer.

[0339] In an exemplary embodiment, the plurality of anode patterns may include a first anode 90A located at a red light emitting unit emitting red light, a second anode 90B located at a blue light emitting unit emitting blue light, a third anode 90C located at a first green light emitting unit emitting green light, and a fourth anode 90D located at a second green light emitting unit emitting green light. The first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may be respectively connected to the anode connecting electrode 73 of the circuit unit through the anode via V30.

[0340] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include a main body portion 90-1 and a connecting portion 90-2 that are connected to each other. The main body portion 90-1 may be in a rhombus shape, and the corners of the rhombus shape may be provided with arc-shaped chamfers. The connecting portion 90-2 may be in a strip shape. The first end of the connecting portion 90-2 is connected to the main body portion 90-1, and the second end of the connecting portion 90-2 extends in a direction away from the main body portion 90-1 and is connected to the anode connecting electrode 73 through the anode via V30.

[0341] In an exemplary embodiment, the orthographic projections of the main portion of the first anode 90A and the main portion of the second anode 90B on the substrate at least partially overlap with the orthographic projection of the second connecting line 82 on the substrate, while the orthographic projections of the main portion of the third anode 90C and the main portion of the fourth anode 90D on the substrate do not overlap with the orthographic projection of the second connecting line 82 on the substrate, that is, the second connecting line 82 is only arranged below the anodes of the red light-emitting unit and the blue light-emitting unit.

[0342] In an exemplary embodiment, the orthographic projections of the main body of the third anode 90C and the main body of the fourth anode 90D on the substrate overlap at least partially with the orthographic projection of the initial connection line on the substrate, while the orthographic projections of the main body of the first anode 90A and the main body of the second anode 90B on the substrate do not overlap with the orthographic projections of the initial connection line on the substrate, that is, the initial connection line is only disposed below the anodes of the first green light-emitting unit and the second green light-emitting unit. The initial connection line may be the first initial connection line 91, or may be the second initial connection line 92, or may be the third initial connection line 93.

[0343] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D may have a first center line O1 and a second center line O2, the first center line O1 may be a straight line passing through the geometric center of the main body of the corresponding anode and extending along the first direction X, and the second center line O2 may be a straight line passing through the geometric center of the main body of the corresponding anode and extending along the second direction Y.

[0344] In an exemplary embodiment, the orthographic projections of the main body of the first anode 90A and the main body of the second anode 90B on the substrate overlap at least partially with the orthographic projections of the three signal lines on the substrate. The three signal lines may be two first power lines 71 and one second connection line 82 located in the fourth conductive layer, the second connection line 82 may be located between the two first power lines 71, the orthographic projection of the second connection line 82 on the substrate overlaps at least partially with the orthographic projection of the second center line O2 on the substrate, and the positions of the two first power lines 71 may be substantially symmetrically arranged relative to the second connection line 82. In this way, the number of signal lines of the SD2 layer below the main body of the first anode 90A and the main body of the second anode 90B at multiple locations is substantially the same, and the signal lines under each anode are symmetrically arranged, which can ensure the flatness and uniformity of the first anode 90A and the second anode 90B, not only can the luminous performance of the two light-emitting devices be substantially the same, the asymmetry of the left and right color deviations can be improved, and defects such as screen-off watermarks caused by the height difference of the anodes can be avoided, thereby improving the quality of the display substrate.

[0345] In an exemplary embodiment, the orthographic projections of the main body of the third anode 90C and the main body of the fourth anode 90D on the substrate overlap at least partially with the orthographic projections of the three signal lines on the substrate. The three signal lines may be two data signal lines 72 and an initial connection line located in the fourth conductive layer, the initial connection line may be located between the two data signal lines 72, the orthographic projection of the initial connection line on the substrate overlaps at least partially with the orthographic projection of the second center line O2 on the substrate, and the positions of the two data signal lines 72 may be substantially symmetrically arranged relative to the initial connection line. The initial connection line may be the first initial connection line 91, or may be the second initial connection line 92, or may be the third initial connection line 93. In this way, the number of signal lines in the SD2 layer under the main body of the third anode 90C and the main body of the fourth anode 90D at multiple positions is basically the same, and the signal lines under each anode are symmetrically arranged, which can ensure the flatness and uniformity of the third anode 90C and the fourth anode 90D, not only ensuring that the luminous performance of the two light-emitting devices is basically the same, but also improving the asymmetry of the left and right color deviations, and avoiding defects such as off-screen watermarks caused by the height difference of the anodes, thereby improving the quality of the display substrate.

[0346] Fig. 17C for Fig.17A Schematic diagram of the positional relationship between the anode conductive layer and the third conductive layer. Fig. 17C As shown, the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D overlap with the signal line and the plurality of electrodes in the third conductive layer.

[0347] In an exemplary embodiment, the orthographic projections of the main body of the first anode 90A and the main body of the second anode 90B on the substrate overlap at least partially with the orthographic projections of the two transverse lines on the substrate. The two transverse lines may be the first connection line 81 and the electrode connection line 53-1 located in the third conductive layer. In the second direction Y, the first connection line 81 may be located on one side of the first center line O1, and the electrode connection line 53-1 may be located on the other side of the first center line O1. The positions of the first connection line 81 and the electrode connection line 53-1 may be substantially symmetrically arranged relative to the first center line O1. In this way, the number of transverse lines of the SD1 layer below the main body of the first anode 90A and the main body of the second anode 90B at multiple locations is substantially the same, and the transverse lines under each anode are symmetrically arranged, which can ensure the flatness and uniformity of the first anode 90A and the second anode 90B, not only can the luminous performance of the two light-emitting devices be substantially the same, the asymmetry of the upper and lower color deviations can be improved, and defects such as screen-off watermarks caused by the height difference of the anodes can be avoided, thereby improving the quality of the display substrate.

[0348] In an exemplary embodiment, the orthographic projections of the main body of the first anode 90A and the main body of the second anode 90B on the substrate overlap at least partially with the orthographic projections of the three vertical electrodes on the substrate. The three vertical electrodes may be two first connection electrodes 51 and one data connection electrode 83 located in the third conductive layer, and the data connection electrode 83 may be located between the two first connection electrodes 51. The orthographic projection of the data connection electrode 83 on the substrate overlaps at least partially with the orthographic projection of the second center line O2 on the substrate, and the positions of the two first connection electrodes 51 may be substantially symmetrically arranged relative to the data connection electrode 83. In this way, the number of vertical electrodes of the SD1 layer below the main body of the first anode 90A and the main body of the second anode 90B at multiple positions is substantially the same, and the vertical electrodes under each anode are symmetrically arranged, which can ensure the flatness and uniformity of the first anode 90A and the second anode 90B, not only can the luminous performance of the two light-emitting devices be substantially the same, the asymmetry of the left and right color deviations can be improved, and defects such as screen-off watermarks caused by the height difference of the anodes can be avoided, thereby improving the quality of the display substrate.

[0349] In an exemplary embodiment, the orthographic projections of the main body of the third anode 90C and the main body of the fourth anode 90D on the substrate at least partially overlap with the orthographic projection of a transverse line on the substrate, and the transverse line may be the second initial signal line 42 located in the third conductive layer. In this way, the number of transverse lines of the SD1 layer below the main body of the third anode 90C and the main body of the fourth anode 90D at multiple locations is substantially the same, which can ensure the uniformity of the third anode 90C and the fourth anode 90D, and can ensure that the light-emitting performance of the two light-emitting devices is substantially the same.

[0350] In an exemplary embodiment, the orthographic projections of the main body of the third anode 90C and the main body of the fourth anode 90D on the substrate overlap at least partially with the orthographic projections of the three vertical electrodes on the substrate. The three vertical electrodes may be two fifth connection electrodes 55 and a connection electrode strip 58-1 located in the third conductive layer, the connection electrode strip 58-1 may be located between the two fifth connection electrodes 55, the orthographic projection of the connection electrode strip 58-1 on the substrate overlaps at least partially with the orthographic projection of the second center line O2 on the substrate, and the two fifth connection electrodes 55 may be substantially symmetrically arranged relative to the connection electrode strip 58-1. Alternatively, the three vertical electrodes may be two fifth connection electrodes 55 and a dummy connection electrode 59 of a dummy electrode strip 59-1 located in the third conductive layer, the dummy electrode strip 59-1 may be located between the two fifth connection electrodes 55, the orthographic projection of the dummy electrode strip 59-1 on the substrate overlaps at least partially with the orthographic projection of the second center line O2 on the substrate, and the two fifth connection electrodes 55 may be substantially symmetrically arranged relative to the dummy electrode strip 59-1. In this way, the number of vertical electrodes of the SD1 layer under the main body of the third anode 90C and the main body of the fourth anode 90D at multiple positions is basically the same, and the vertical electrodes under each anode are symmetrically arranged, which can ensure the flatness and uniformity of the third anode 90C and the fourth anode 90D, not only can it ensure that the luminous performance of the two light-emitting devices is basically the same, but also can improve the asymmetry of the left and right color deviations, and can avoid defects such as off-screen watermarks caused by the height difference of the anodes, thereby improving the quality of the display substrate.

[0351] In an exemplary embodiment, orthographic projections of the body portion of the first anode 90A and the body portion of the second anode 90B on the substrate may include orthographic projections of the data connection electrode 83 on the substrate.

[0352] In an exemplary embodiment, the orthographic projection of the data connection electrode 83 on the substrate may be substantially symmetrically arranged relative to the orthographic projection of the first center line O1 on the substrate, and the orthographic projection of the data connection electrode 83 on the substrate may be substantially symmetrically arranged relative to the orthographic projection of the second center line O2 on the substrate.

[0353] In an exemplary embodiment, the orthographic projections of the first connection sub-block 83 - 1 , the second connection sub-block 83 - 2 , and the connection sub-strip 83 - 3 in the data connection electrode 83 on the substrate at least partially overlap with the orthographic projection of the second center line O2 on the substrate.

[0354] In an exemplary embodiment, the orthographic projections of the first connection sub-block 83-1 and the second connection sub-block 83-2 in the data connection electrode 83 on the substrate may be substantially symmetrically arranged with respect to the orthographic projection of the first center line O1 on the substrate. For the twenty-fourth via hole that realizes the connection between the second connection line 82 and the first connection sub-block 83-1 and the twenty-fourth via hole that realizes the connection between the second connection line 82 and the second connection sub-block 83-2, the orthographic projections of the two twenty-fourth via holes on the substrate may be substantially symmetrically arranged with respect to the orthographic projection of the first center line O1 on the substrate.

[0355] In an exemplary embodiment, the orthographic projection of the main body of the third anode 90C on the substrate at least partially overlaps with the orthographic projection of the twenty-seventh via V27 (connecting via) on the substrate, and the orthographic projection of the main body of the fourth anode 90D on the substrate at least partially overlaps with the orthographic projection of the twenty-eighth via V28 (dummy via) on the substrate; or, the orthographic projection of the main body of the third anode 90C on the substrate at least partially overlaps with the orthographic projection of the twenty-eighth via V28 (dummy via) on the substrate, and the orthographic projection of the main body of the fourth anode 90D on the substrate at least partially overlaps with the orthographic projection of the twenty-seventh via V27 (connecting via) on the substrate. The present invention discloses that by setting dummy vias, first flat layer vias (PLN vias) are provided under the main body of the third anode 90C and the main body of the fourth anode 90D at multiple positions. This can not only improve the uniformity of the third anode 90C and the fourth anode 90D, but also enable different areas to achieve the same display effect under transmitted and reflected light, realize shadow elimination, effectively avoid the poor appearance of the display substrate and the occurrence of off-screen watermarks, and improve the display quality.

[0356] In some other embodiments, the orthographic projection of the main body of the third anode 90C on the substrate at least partially does not overlap with the orthographic projection of the twenty-seventh via V27 (connecting via) on the substrate, and the orthographic projection of the main body of the fourth anode 90D on the substrate at least partially does not overlap with the orthographic projection of the twenty-eighth via V28 (dummy via) on the substrate; or, the orthographic projection of the main body of the third anode 90C on the substrate at least partially does not overlap with the orthographic projection of the twenty-eighth via V28 (dummy via) on the substrate, and the orthographic projection of the main body of the fourth anode 90D on the substrate at least partially does not overlap with the orthographic projection of the twenty-seventh via V27 (connecting via) on the substrate, and the present disclosure does not make any limitation thereto.

[0357] In an exemplary embodiment, the anode conductive layer may have a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0358] In an exemplary embodiment, the subsequent preparation process may include: first forming a pixel definition layer, the pixel definition layer is provided with a plurality of pixel openings, the plurality of pixel openings respectively exposing a first anode, a second anode, a third anode and a fourth anode. Then, an organic light-emitting layer is formed by evaporation or inkjet printing, and then a cathode is formed on the organic light-emitting layer, and then an encapsulation structure layer is formed, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, so as to ensure that external water vapor cannot enter the light-emitting structure layer.

[0359] The exemplary embodiments of the present disclosure provide a display substrate, which adopts a mirror-symmetric design of a pixel driving circuit and shares circuit nodes. The first transistors T1 in adjacent unit columns are mirror-set and share the first electrode of the first transistor T1, the seventh transistors T7 in adjacent unit columns are mirror-set and share the first electrode of the seventh transistor T7, and the eighth transistors T8 in adjacent unit columns are mirror-set and share the first electrode of the eighth transistor T8. This can effectively reduce layout space, reduce the number of vias and connecting electrodes, and reduce the occupied area of ​​the pixel driving circuit, which is conducive to achieving high resolution.

[0360] In the disclosed embodiment, a first connecting line and a second connecting line are arranged in the display area, and the data lead lines in the binding area are connected to the data signal lines through the first connecting line and the second connecting line, so that there is no need to arrange a fan-shaped oblique line in the lead line area, thereby effectively reducing the length of the lead line area, greatly reducing the width of the lower frame, and improving the screen-to-body ratio, which is conducive to achieving full-screen display.

[0361] The embodiment of the present disclosure can effectively reduce leakage of the first transistor T1 and the second transistor T2 by providing a dual-gate structure, which is conducive to meeting the demand for low-frequency display.

[0362] In the embodiment of the present disclosure, a first shielding electrode and a second shielding electrode are provided. The first shielding electrode and the first active layer between the two gate electrodes in the first transistor T1 form a coupling capacitor, and the first shielding electrode and the second active layer between the two gate electrodes in the second transistor T2 form a coupling capacitor, and the second shielding electrode and the second active layer between the two gate electrodes in the second transistor T2 form a coupling capacitor, and the second shielding electrode and the first initial signal line are connected. On the one hand, the node between the two gate electrodes in the first transistor T1 and the second transistor T2 can be shielded to avoid the influence of the data voltage jump on the first transistor T1 and the second transistor T2, and reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit. On the other hand, the coupling capacitor is used to further reduce the leakage of the first transistor T1 and the second transistor T2, thereby improving the display effect.

[0363] In the embodiment of the present disclosure, a third shielding electrode is provided. The third shielding electrode is provided between the second area of ​​the first active layer in the semiconductor layer and the first connecting line in the third conductive layer and is connected to the first initial signal line. The third shielding electrode can shield the first connecting line to avoid the influence of the data voltage jump in the first connecting line on the first transistor T1 and the second transistor T2, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0364] The embodiment of the present disclosure sets a fourth shielding electrode, which is set between the first node N1 and the data signal line and connected to the first initial signal line. This can avoid the influence of the data signal line on the first node N1, reduce the influence of data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0365] In the embodiment of the present disclosure, a first initial signal line extending along a first direction X of the main part and a first initial connection line extending along a second direction Y of the main part are provided, and the first initial signal line and the first initial connection line are connected to each other, so as to form a mesh connection structure for transmitting the first initial signal on the display substrate. This can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0366] In the embodiment of the present disclosure, a second initial signal line extending along the first direction X of the main part and a second initial connection line extending along the second direction Y of the main part are provided, and the second initial signal line and the second initial connection line are connected to each other, so as to form a mesh connection structure for transmitting the second initial signal on the display substrate. This can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0367] The embodiment of the present disclosure forms a mesh connection structure for transmitting the third initial signal on the display substrate by providing a third initial signal line whose main part extends along the first direction X and a third initial connection line whose main part extends along the second direction Y, and the third initial signal line and the third initial connection line are connected to each other. This can not only effectively reduce the resistance of the third initial signal line and reduce the voltage drop of the third initial signal, but also effectively improve the uniformity of the third initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0368] The embodiment of the present disclosure can ensure that the light-emitting performance of multiple light-emitting devices is basically the same by setting the second connecting line below the anodes of the red light-emitting unit and the blue light-emitting unit and setting the initial connecting line below the anodes of the first green light-emitting unit and the second green light-emitting unit.

[0369] In the embodiment of the present disclosure, the main bodies of the first anode and the second anode are arranged so that their orthographic projections on the substrate at least partially overlap with the orthographic projections of the two horizontal lines on the substrate, at least partially overlap with the orthographic projections of the three vertical electrodes on the substrate, and at least partially overlap with the orthographic projections of the three signal lines on the substrate, so that the metal wires under the first anode and the second anode are basically the same, and the metal wires under each anode are symmetrically arranged, which can ensure the flatness and uniformity of the first anode and the second anode, not only can it ensure that the luminous performances of the two light-emitting devices are basically the same, but also can improve the asymmetry of the left and right color deviations, and can avoid defects such as off-screen watermarks caused by height differences between the anodes, thereby improving the quality of the display substrate.

[0370] In the embodiment of the present disclosure, the main bodies of the third anode and the fourth anode are arranged so that their orthographic projections on the substrate at least partially overlap with the orthographic projections of a horizontal line on the substrate, at least partially overlap with the orthographic projections of three vertical electrodes on the substrate, and at least partially overlap with the orthographic projections of three signal lines on the substrate, so that the metal wires under the third anode and the fourth anode are basically the same, and the metal wires under each anode are symmetrically arranged, thereby ensuring the flatness and uniformity of the third anode and the fourth anode, not only ensuring that the luminous performances of the two light-emitting devices are basically the same, but also improving the asymmetry of the left and right color deviations, and avoiding defects such as off-screen watermarks caused by height differences between the anodes, thereby improving the quality of the display substrate.

[0371] The disclosed embodiment sets dummy vias so that first flat layer vias are provided under the third anode and the fourth anode 90D at multiple positions. This can not only improve the uniformity of the third anode and the fourth anode, but also enable different areas to achieve the same display effect under transmitted and reflected light, realize shadow elimination, effectively avoid the poor appearance of the display substrate and the occurrence of off-screen watermarks, and improve the display quality.

[0372] The present disclosure realizes the integration of 8T1C pixel driving circuit structure and 2SD FIP through the above structure, which can not only improve the flicker of low-frequency display, but also reduce the width of the lower frame and improve the screen-to-body ratio. The present disclosure optimizes the layout of the pixel driving circuit, which can not only improve the upper and lower color deviation and the left and right color deviation, but also reduce the occupied area of ​​the pixel driving circuit, thereby improving the resolution and transmittance.

[0373] The preparation process of the embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0374] The structure and preparation process shown above in the present disclosure are merely exemplary descriptions. In exemplary implementations, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs.

[0375] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0376] The present disclosure also provides another display substrate. In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit and at least one initial signal line; the pixel driving circuit includes at least one initialization transistor, and the initial signal line is connected to the initialization transistor through a connecting electrode; in at least one unit row, two initialization transistors in adjacent circuit units are connected to the connecting electrode through the same via hole, or two connecting electrodes in adjacent circuit units are connected to the initial signal line through the same via hole.

[0377] In an exemplary embodiment, at least one initial signal line may include a first initial signal line, and at least one initialization transistor may include a first transistor as a first initialization transistor. The first transistor includes at least a first active layer, and the first initial signal line is connected to a first region of the first active layer through a sixth connection electrode. The pixel driving circuits in adjacent circuit units share the first region of the first active layer, and the pixel driving circuits in adjacent circuit units share the sixth connection electrode, and the sixth connection electrode is connected to the first regions of two first active layers in adjacent circuit units through the same via.

[0378] In an exemplary embodiment, at least one initial signal line may include a second initial signal line, and at least one initialization transistor may include a seventh transistor as a second initialization transistor. The seventh transistor includes at least a seventh active layer, and the second initial signal line is connected to the first region of the seventh active layer through a second initial connection block. The pixel driving circuits in adjacent circuit units share the first region of the seventh active layer, and the pixel driving circuits in adjacent circuit units share the second initial connection block, and the second initial connection block is connected to the first regions of two seventh active layers in adjacent circuit units through the same via.

[0379] In an exemplary embodiment, at least one initial signal line may include a third initial signal line, and at least one initialization transistor may include an eighth transistor as the third initialization transistor. The eighth transistor includes at least an eighth active layer, and the third initial signal line is connected to the first region of the eighth active layer through a seventh connection electrode. The seventh connection electrodes in adjacent circuit units are interconnected integral structures, the pixel driving circuits in adjacent circuit units share the seventh connection electrode, and the third initial signal line is connected to two seventh connection electrodes in adjacent circuit units through the same via.

[0380] The present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment. In an exemplary embodiment, the preparation method may include:

[0381] A driving structure layer is formed on a substrate; the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; the pixel driving circuit includes at least a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initial signal line is connected to a first electrode of the first transistor, the second initial signal line is connected to a first electrode of the seventh transistor, and the third initial signal line is connected to a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share a first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share a first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share a first electrode of the eighth transistor;

[0382] A light emitting structure layer is formed on the driving structure layer.

[0383] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0384] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: The invention comprises a driving structure layer arranged on a substrate and a light emitting structure layer arranged on a side of the driving structure layer away from the substrate, wherein the driving structure layer comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit comprises a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; The pixel driving circuit includes at least a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor, and an eighth transistor as a third initialization transistor, the first initial signal line is connected to the first electrode of the first transistor, the second initial signal line is connected to the first electrode of the seventh transistor, and the third initial signal line is connected to the first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share the first electrode of the eighth transistor.

2. The display substrate according to claim 1, characterized in that: The first transistor at least includes a first active layer, and the first initial signal line is connected to the first region of the first active layer through a sixth connecting electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the sixth connecting electrode.

3. The display substrate according to claim 1, characterized in that: The seventh transistor at least includes a seventh active layer, and the second initial signal line is connected to the first area of ​​the seventh active layer through a second initial connection block; in at least one unit row, the pixel driving circuits in adjacent circuit units share the second initial connection block.

4. The display substrate according to claim 1, characterized in that: The eighth transistor at least includes an eighth active layer, and the third initial signal line is connected to the first region of the eighth active layer through a seventh connection electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the seventh connection electrode.

5. The display substrate according to claim 1, characterized in that: The first initial signal line, the second initial signal line and the third initial signal line extend along a first direction, and the driving structure layer also includes a first initial connection line, a second initial connection line and a third initial connection line extending along a second direction, and the first direction intersects with the second direction; the first initial connection line is connected to the first initial signal line through a sixth connection electrode to form a mesh connection structure for transmitting a first initial signal, or the second initial connection line is connected to the second initial signal line through an eighth connection electrode to form a mesh connection structure for transmitting a second initial signal, or the third initial connection line is connected to the third initial signal line through a seventh connection electrode to form a mesh connection structure for transmitting a third initial signal.

6. The display substrate according to claim 5, characterized in that: The first initial connection line, the second initial connection line and the third initial connection line are respectively arranged between adjacent unit columns, and the first initial connection line, the second initial connection line, the third initial connection line and the second initial connection line are periodically arranged in the first direction.

7. The display substrate according to claim 5, characterized in that: The light emitting structure layer at least includes a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light, and a plurality of second green light emitting units emitting green light, the red light emitting unit at least includes a first anode, the blue light emitting unit at least includes a second anode, the first green light emitting unit at least includes a third anode, the second green light emitting unit at least includes a fourth anode, at least one of the first anode, the second anode, the third anode and the fourth anode includes a main body and a connecting part connected to each other, a first end of the connecting part is connected to the main body, and a second end of the connecting part is connected to the anode connecting electrode in the pixel driving circuit through an anode via hole; the orthographic projections of the main body of the third anode and the main body of the fourth anode on the substrate at least partially overlap with the orthographic projections of the first initial connection line on the substrate, or the orthographic projections of the main body of the third anode and the main body of the fourth anode on the substrate at least partially overlap with the orthographic projections of the second initial connection line on the substrate, or the orthographic projections of the main body of the third anode and the main body of the fourth anode on the substrate at least partially overlap with the orthographic projections of the third initial connection line on the substrate.

8. The display substrate according to claim 5, characterized in that: In a direction perpendicular to the substrate, the driving structure layer includes at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the first initial signal line, the second initial signal line and the third initial signal line are respectively arranged in at least one layer of the second conductive layer and the third conductive layer, and the first initial connection line, the second initial connection line and the third initial connection line are arranged in the fourth conductive layer.

9. The display substrate according to claim 8, characterized in that: The driving structure layer also includes a first flat layer arranged on a side of the third conductive layer away from the substrate, and the fourth conductive layer is arranged on a side of the first flat layer away from the substrate; at least one circuit unit also includes a connecting via, and the third initial connecting line is connected to the seventh connecting electrode through the connecting via; at least another circuit unit also includes a dummy via, and the first initial connecting line and / or the second initial connecting line are at least partially arranged in the dummy via.

10. The display substrate according to claim 9, characterized in that: The light emitting structure layer at least comprises a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light and a plurality of second green light emitting units emitting green light, the red light emitting unit at least comprises a first anode, the blue light emitting unit at least comprises a second anode, the first green light emitting unit at least comprises a third anode, the second green light emitting unit at least comprises a fourth anode, at least one of the first anode, the second anode, the third anode and the fourth anode comprises a main body and a connecting part connected to each other, a first end of the connecting part is connected to the main body, and a second end of the connecting part is connected to an anode connecting electrode in the pixel driving circuit through an anode via hole; an orthographic projection of the main body of the third anode on the substrate at least partially overlaps with an orthographic projection of the connecting via hole on the substrate, and an orthographic projection of the main body of the fourth anode on the substrate at least partially overlaps with an orthographic projection of the dummy via hole on the substrate; Alternatively, the orthographic projection of the main body of the third anode on the substrate at least partially overlaps with the orthographic projection of the dummy via on the substrate, and the orthographic projection of the main body of the fourth anode on the substrate at least partially overlaps with the orthographic projection of the connecting via on the substrate.

11. The display substrate according to claim 9, characterized in that: The light emitting structure layer at least comprises a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light and a plurality of second green light emitting units emitting green light, the red light emitting unit at least comprises a first anode, the blue light emitting unit at least comprises a second anode, the first green light emitting unit at least comprises a third anode, the second green light emitting unit at least comprises a fourth anode, at least one of the first anode, the second anode, the third anode and the fourth anode comprises a main body and a connecting part connected to each other, a first end of the connecting part is connected to the main body, and a second end of the connecting part is connected to an anode connecting electrode in the pixel driving circuit through an anode via hole; an orthographic projection of the main body of the third anode on the substrate at least partially does not overlap with an orthographic projection of the connecting via hole on the substrate, and an orthographic projection of the main body of the fourth anode on the substrate at least partially does not overlap with an orthographic projection of the dummy via hole on the substrate; Alternatively, the orthographic projection of the main body of the third anode on the substrate does not overlap with the orthographic projection of the dummy via on the substrate at least partially, and the orthographic projection of the main body of the fourth anode on the substrate does not overlap with the orthographic projection of the connecting via on the substrate at least partially.

12. The display substrate according to claim 5, characterized in that: The eighth connecting electrode includes a connecting electrode strip and a connecting electrode block, the connecting electrode strip is in the shape of a strip extending along the second direction, the connecting electrode block is in the shape of a block, the first end of the connecting electrode strip is connected to the second initial signal line, the second end of the connecting electrode strip extends in the direction away from the second initial signal line and is connected to the connecting electrode block, and the second initial connecting line is connected to the connecting electrode block through a via; at least one circuit unit also includes a dummy electrode strip, the first end of the dummy electrode strip is connected to the second initial signal line, the second end of the dummy electrode strip extends in the direction away from the second initial signal line; the connecting electrode strip and the dummy electrode strip are alternately arranged in the first direction.

13. The display substrate according to claim 12, characterized in that: At least one circuit unit also includes a dummy electrode block and a dummy via, wherein the dummy electrode block is in a block shape and is connected to the second end of the dummy electrode strip, the orthographic projection of the dummy via on the substrate is within the range of the orthographic projection of the dummy electrode block on the substrate, and the first initial connection line and / or the third initial connection line are at least partially arranged in the dummy via.

14. The display substrate according to claim 13, characterized in that: The connecting electrode block and the dummy electrode block are located on a straight line extending along the first direction.

15. The display substrate according to claim 12, characterized in that: The light emitting structure layer at least comprises a plurality of red light emitting units emitting red light, a plurality of blue light emitting units emitting blue light, a plurality of first green light emitting units emitting green light and a plurality of second green light emitting units emitting green light, the red light emitting unit at least comprises a first anode, the blue light emitting unit at least comprises a second anode, the first green light emitting unit at least comprises a third anode, the second green light emitting unit at least comprises a fourth anode, at least one of the first anode, the second anode, the third anode and the fourth anode comprises a main body and a connecting part connected to each other, a first end of the connecting part is connected to the main body, and a second end of the connecting part is connected to an anode connecting electrode in the pixel driving circuit through an anode via hole; an orthographic projection of the main body of the third anode on the substrate at least partially overlaps with an orthographic projection of the connecting electrode strip on the substrate, and an orthographic projection of the main body of the fourth anode on the substrate at least partially overlaps with an orthographic projection of the dummy electrode strip on the substrate; Alternatively, the orthographic projection of the main body of the third anode on the substrate at least partially overlaps with the orthographic projection of the dummy electrode strip on the substrate, and the orthographic projection of the main body of the fourth anode on the substrate at least partially overlaps with the orthographic projection of the connecting electrode strip on the substrate.

16. The display substrate according to claim 1, characterized in that: The pixel driving circuit also includes a second transistor as a compensation transistor and a third transistor as a driving transistor, the first electrode of the second transistor is respectively connected to the second electrode of the first transistor and the gate electrode of the third transistor, and the second electrode of the second transistor is connected to the second electrode of the third transistor; the first transistor and the second transistor are a dual-gate structure.

17. The display substrate according to claim 1, characterized in that: The driving structure layer also includes a plurality of data signal lines extending along a second direction, a plurality of first connecting lines extending along a first direction, and a plurality of second connecting lines extending along the second direction, wherein the first direction and the second direction intersect; at least one data signal line is connected to a plurality of pixel driving circuits of a unit column, the first ends of the plurality of first connecting lines are correspondingly connected to the plurality of data signal lines, and the second ends of the plurality of first connecting lines are correspondingly connected to the plurality of second connecting lines.

18. The display substrate according to claim 17, characterized in that: The light-emitting structure layer includes at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting unit includes at least a first anode, the blue light-emitting unit includes at least a second anode, the first green light-emitting unit includes at least a third anode, and the second green light-emitting unit includes at least a fourth anode, and at least one of the first anode, the second anode, the third anode and the fourth anode includes a main body and a connecting part that are interconnected, a first end of the connecting part is connected to the main body, and a second end of the connecting part is connected to the anode connecting electrode in the pixel driving circuit through an anode via; the orthographic projections of the main body of the first anode and the main body of the second anode on the substrate at least partially overlap with the orthographic projection of the second connecting line on the substrate.

19. The display substrate according to claim 18, characterized in that: The driving structure layer also includes a data connection electrode, and the second connection line is connected to the data connection electrode through a via; the orthographic projection of the data connection electrode on the substrate is located within the range of the orthographic projection of the main body of the first anode on the substrate, and / or the orthographic projection of the data connection electrode on the substrate is located within the range of the orthographic projection of the main body of the second anode on the substrate.

20. A display substrate, characterized in that: It includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit and at least one initial signal line; the pixel driving circuit includes at least one initialization transistor, and the initial signal line is connected to the initialization transistor through a connecting electrode; in at least one unit row, two initialization transistors in adjacent circuit units are connected to the connecting electrode through the same via hole, or two connecting electrodes in adjacent circuit units are connected to the initial signal line through the same via hole.

21. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 19.

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