A low-pass filter based on IPD technology

Abstract

The utility model discloses a low-pass filter based on IPD technology, including a substrate and a low-pass filter circuit, wherein the low-pass filter circuit includes capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, inductor L1, inductor L2 and inductor L3; the GSG input end of the low-pass filter circuit is grounded through GND1 grounding copper pillar and GND2 grounding copper pillar; port1 is connected to capacitor C1, capacitor C2 and inductor L1 through a first metal layer transmission line; the other end of capacitor C1 is connected to GND3 through a second metal layer transmission line and grounded, and capacitor C2 and inductor L1 form a parallel LC resonator; the other end of capacitor C2 is connected to an interconnection hole through a second metal layer transmission line to achieve interconnection with the first metal layer. The utility model adds three more capacitors on the basis of a traditional third-order passive filter to achieve a steeper frequency cutoff characteristic and high out-of-band suppression, and the use of a circular inductor increases the Q value and reduces insertion loss.

Description

Technical Field

[0001] The utility model relates to the technical field of low-pass filters, in particular to a low-pass filter based on IPD technology. Background Art

[0002] With the development of 5G and wireless communication technologies centered on the Internet of Things, RF system modules are required to be increasingly miniaturized and integrated. Therefore, the low-pass filter in the RF front-end module must be miniaturized and have low insertion loss, high out-of-band suppression and steep frequency cutoff characteristics. Microwave filters produced by traditional low-temperature co-fired ceramics (LTCC) and printed circuit boards (PCB) processes are usually too large in size or occupy too large a chip area to meet the RF front-end's demand for device miniaturization, and are difficult to be compatible with CMOS processes for integrated mass production. Although the planar bandpass filter based on the microstrip line structure is small in size, it usually has a large insertion loss; filters produced by MEMS processes such as surface acoustic wave (SAW) and bulk acoustic wave (BAW) are small in size and have low insertion loss, but are difficult to be compatible with CMOS production processes, and integrated production is difficult.

[0003] Due to the characteristics of the IPD process, the performance of the inductor greatly affects the performance of the IPD filter. The smaller the planar inductor area, the worse the inductor Q value, which increases the difficulty of miniaturization and performance design of IPD passive components. Under the same process conditions of the IPD filter, the square inductor occupies the smallest chip area, but the inductor Q value is lower than that of the circular inductor, and the corresponding insertion loss will be relatively large. Utility Model Content

[0004] The purpose of the utility model is to provide a low-pass filter based on IPD technology to solve the problems in the prior art.

[0005] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: a low-pass filter based on IPD technology, comprising a substrate and a low-pass filter circuit, wherein the low-pass filter circuit comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an inductor L1, an inductor L2 and an inductor L3; the capacitor C1, the capacitor C2, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the inductor L1, the inductor L2 and the inductor L3 all comprise a gallium arsenide substrate, a first dielectric layer, a first metal layer, a second dielectric layer and a second metal layer, the gallium arsenide substrate, the first dielectric layer, the first metal layer, the second dielectric layer and the second metal layer are arranged in sequence from bottom to top, the first metal layer and the second metal layer are interconnected through interconnection holes, a bottom gold-plated layer is arranged at the bottom of the gallium arsenide substrate, and the first metal layer is connected to the bottom gold-plated layer of the gallium arsenide substrate through a grounding copper column;

[0006] The GSG input end of the low-pass filter circuit is grounded through the GND1 grounding copper column and the GND2 grounding copper column;

[0007] Port1 is connected to capacitor C1, capacitor C2, and inductor L1 through the first metal layer transmission line;

[0008] The other end of the capacitor C1 is connected to the ground through the second metal layer transmission line and GND3, and the capacitor C2 and the inductor L1 form a parallel LC resonator;

[0009] The other end of the capacitor C2 is connected to the interconnection hole through the second metal layer transmission line to achieve interconnection with the first metal layer;

[0010] The output end of capacitor C3 is connected to GND4 through the second metal layer transmission line, and the input end is connected to capacitor C2 through the first metal layer transmission line. The parallel LC resonant circuit composed of inductor L1 is connected to capacitor C2;

[0011] The inductor L2 and the capacitor C4 form a second LC parallel resonant circuit, the input end of the inductor L2 is connected to the capacitor C2 and the output end of the inductor L1 resonant circuit through the first metal layer transmission line, the input end of the capacitor C4 is connected to the capacitor C2 and the output end of the inductor L1 resonant circuit through the second metal layer transmission line and the interconnection hole, and the output end is connected to the output end of the inductor L2 and the capacitor C5 and the input end of the inductor L3 through the first metal layer transmission line;

[0012] The output end of capacitor C5 is interconnected and grounded to GND5 through a second metal layer transmission line;

[0013] Inductor L3 is connected in series with two LC resonant circuits, and the output end is interconnected with capacitor C6, port2 through the first metal layer transmission line;

[0014] Port2, GND6 and GND7 together form the GSG output terminal of the chip;

[0015] The output end of capacitor C6 is interconnected with GND6 through a second metal layer transmission line, and shares GND6 with the GSG output end of the chip.

[0016] Preferably, a protective layer is provided on the upper surface of the second metal layer.

[0017] Preferably, the inductor L1, the inductor L2 and the inductor L3 are all circular inductors.

[0018] Compared with the prior art, the beneficial effects of the utility model are:

[0019] 1. The circular inductor design is used to improve the Q value of the inductor and reduce the insertion loss of the filter. At the same time, the insertion loss is further reduced by streamlining and optimizing the number of LC resonators and the series-parallel structure, obtaining a low-pass filter with steep frequency cutoff characteristics, low insertion loss, wide bandwidth and high out-of-band suppression transmission characteristics, and realizing chip miniaturization.

[0020] 2. Three more capacitors are added to the traditional third-order passive filter to achieve steeper frequency cutoff characteristics and high out-of-band suppression. The use of circular inductors increases the Q value and reduces insertion loss. The IPD production process is used to miniaturize the filter size and facilitate mass production. This product can be applied to a wide range of fields such as mobile phones and smart watches. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0022] Figure 1 It is a structural schematic diagram of the utility model;

[0023] Figure 2 It is the internal structure interconnection diagram of the utility model;

[0024] Figure 3 It is the circuit layout diagram of the utility model;

[0025] Figure 4 This is an S parameter signal test diagram of the utility model.

[0026] In the figure: 1, substrate; 2, low-pass filter circuit; 21, bottom gold-plated layer; 22, gallium arsenide substrate; 23, first dielectric layer; 24, first metal layer; 25, second dielectric layer; 26, second metal layer; 27, protective layer; 28, grounding copper pillar; 29, interconnection hole. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model. Therefore, the following detailed description of the embodiments of the utility model provided in the drawings is not intended to limit the scope of the utility model for which protection is claimed, but merely represents selected embodiments of the utility model.

[0028] See also Figure 1-2In an embodiment of the utility model, a low-pass filter based on IPD technology includes a substrate 1 and a low-pass filter circuit 2, wherein the low-pass filter circuit 2 includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an inductor L1, an inductor L2 and an inductor L3; the inductor L1, the inductor L2 and the inductor L3 are all circular inductors; the circular inductor design is used to improve the Q value of the inductor and reduce the insertion loss of the filter. At the same time, the insertion loss is further reduced by streamlining and optimizing the number of LC resonators and the series-parallel structure, thereby obtaining a low-pass filter with steep frequency cutoff characteristics, low insertion loss, wide bandwidth and high out-of-band suppression transmission characteristics and realizing chip miniaturization.

[0029] The capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, inductor L1, inductor L2 and inductor L3 all include a gallium arsenide substrate 22, a first dielectric layer 23, a first metal layer 24, a second dielectric layer 25 and a second metal layer 26. The gallium arsenide substrate 22, the first dielectric layer 23, the first metal layer 24, the second dielectric layer 25 and the second metal layer 26 are arranged in sequence from bottom to top, the first metal layer 24 and the second metal layer 26 are interconnected through an interconnection hole 29, a bottom gold-plated layer 21 is arranged at the bottom of the gallium arsenide substrate 22, and the first metal layer 24 is connected to the bottom gold-plated layer 21 of the gallium arsenide substrate 22 through a grounding copper column 28; and a protective layer 27 is arranged on the upper surface of the second metal layer 26.

[0030] like Figure 3 As shown; the filter chip is connected to the ground signal through one or more corresponding ground electrodes G, so that each capacitor is grounded through the corresponding ground through hole to form a parallel resonant circuit;

[0031] The GSG input end of the low-pass filter circuit 2 is grounded through the GND1 grounding copper column and the GND2 grounding copper column;

[0032] Port1 is connected to capacitor C1, capacitor C2, and inductor L1 through the first metal layer 24 transmission line;

[0033] The other end of the capacitor C1 is connected to the ground through the second metal layer 26 transmission line and the GND3, and the capacitor C2 and the inductor L1 form a parallel LC resonator;

[0034] The other end of the capacitor C2 is connected to the interconnection hole 29 through the second metal layer 26 transmission line to achieve interconnection with the first metal layer 24;

[0035] The output end of capacitor C3 is connected to GND4 through the second metal layer 26 transmission line, and the input end is connected to capacitor C2 through the first metal layer 24 transmission line. The parallel LC resonant circuit composed of inductor L1 is connected to capacitor C2;

[0036] The inductor L2 and the capacitor C4 form a second LC parallel resonant circuit, the input end of the inductor L2 is connected to the capacitor C2 and the output end of the inductor L1 resonant circuit through the transmission line of the first metal layer 24, the input end of the capacitor C4 is connected to the capacitor C2 and the output end of the inductor L1 resonant circuit through the transmission line of the second metal layer 26 and the interconnection hole 29, and the output end is connected to the output end of the inductor L2 and the capacitor C5 and the input end of the inductor L3 through the transmission line of the first metal layer 24;

[0037] The output end of capacitor C5 is interconnected to GND5 through the second metal layer 26 transmission line and grounded;

[0038] The inductor L3 is connected in series with the two LC resonant circuits, and the output end is interconnected with the capacitor C6, port2 through the first metal layer 24 transmission line;

[0039] Port2, GND6 and GND7 together form the GSG output terminal of the chip;

[0040] The output end of the capacitor C6 is interconnected with GND6 through the transmission line of the second metal layer 26, and shares the grounding GND6 with the GSG output end of the chip.

[0041] S parameter test results are as follows Figure 4 As shown, the input return loss S11 of the low-pass filter chip is less than -23dB in the entire D capacitor C0Hz~2GHz frequency band, and S22 is also less than -20dB in the D capacitor C0Hz~2GHz frequency band, indicating that the loss of the RF signal input and output being reflected back is small, and the low-pass filter achieves impedance matching; S21 of the low-pass filter chip is greater than -1.2dB in the entire D capacitor C0Hz~2GHz frequency band, indicating that the insertion loss of the low-pass filter chip is small and the transmission characteristics are good; at 3GHz, S21<-20dB, indicating that the rectangular coefficient of the low-pass filter chip is good and has a steep cut-off frequency, and at 3.4GHz~20GHz, S21 is less than -40dB, indicating that the low-pass filter chip has a high out-of-band suppression characteristic; the low-pass filter chip is small in size, only 950*650*100 (um), showing that the present invention has the advantages of miniaturization, low insertion loss, high out-of-band suppression and steep frequency cut-off characteristics.

[0042] By streamlining and optimizing the number of LC resonators and the series-parallel structure, appropriately reducing the filter order, reducing the number of inductors used, and optimizing the inductor shape to increase the Q value, it is an important way to obtain a miniaturized, high out-of-band suppression, wide bandwidth, and steep frequency cutoff characteristic IPD low-pass filter.

[0043] Finally, it should be noted that the above description is only a preferred embodiment of the utility model and is not intended to limit the utility model. Although the utility model is described in detail with reference to the above embodiments, those skilled in the art can still modify the technical solutions recorded in the above embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A low-pass filter based on IPD technology, comprising a substrate (1) and a low-pass filter circuit (2), characterized in that: The low-pass filter circuit (2) comprises a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, an inductor L1, an inductor L2 and an inductor L3; The capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, inductor L1, inductor L2 and inductor L3 all comprise a gallium arsenide substrate (22), a first dielectric layer (23), a first metal layer (24), a second dielectric layer (25) and a second metal layer (26); the gallium arsenide substrate (22), the first dielectric layer (23), the first metal layer (24), the second dielectric layer (25) and the second metal layer (26) are arranged in sequence from bottom to top; the first metal layer (24) and the second metal layer (26) are interconnected via an interconnection hole (29); a bottom gold-plated layer (21) is arranged at the bottom of the gallium arsenide substrate (22); the first metal layer (24) is connected to the bottom gold-plated layer (21) of the gallium arsenide substrate (22) via a grounding copper column (28); The GSG input end of the low-pass filter circuit (2) is grounded via a GND1 grounding copper column and a GND2 grounding copper column; Port1 is connected to capacitor C1, capacitor C2, and inductor L1 through a transmission line of the first metal layer (24); The other end of the capacitor C1 is connected to the ground through a second metal layer (26) transmission line and GND3, and the capacitor C2 and the inductor L1 form a parallel LC resonator; The other end of the capacitor C2 is connected to the interconnection hole (29) through a transmission line of the second metal layer (26) to realize interconnection with the first metal layer (24); The output end of capacitor C3 is connected to GND4 through the second metal layer (26) transmission line, and the input end is connected to capacitor C2 through the first metal layer (24) transmission line. The parallel LC resonant circuit composed of inductor L1 is connected to capacitor C2; The inductor L2 and the capacitor C4 form a second LC parallel resonant circuit, the input end of the inductor L2 is connected to the capacitor C2 and the output end of the resonant circuit of the inductor L1 through the transmission line of the first metal layer (24), the input end of the capacitor C4 is connected to the capacitor C2 and the output end of the resonant circuit of the inductor L1 through the transmission line of the second metal layer (26) and the interconnection hole (29), and the output end is connected to the output end of the inductor L2 and the capacitor C5 and the input end of the inductor L3 through the transmission line of the first metal layer (24); The output end of capacitor C5 is interconnected and grounded to GND5 via a transmission line of the second metal layer (26); The inductor L3 is connected in series with the two LC resonant circuits, and the output end is interconnected with the capacitor C6, port 2 through the first metal layer (24) transmission line; Port2, GND6 and GND7 together form the GSG output terminal of the chip; The output end of capacitor C6 is interconnected with GND6 through a transmission line of the second metal layer (26), and shares GND6 with the GSG output end of the chip.

2. A low-pass filter based on IPD technology according to claim 1, characterized in that: A protective layer (27) is provided on the upper surface of the second metal layer (26).

3. The low-pass filter based on IPD technology according to claim 1, characterized in that: The inductor L1 , the inductor L2 and the inductor L3 are all circular inductors.

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