Display device

Abstract

A display device includes: a first pixel electrode disposed on a substrate and including a main portion and an edge portion; a pixel defining film disposed on the substrate, including a main portion and a protruding portion, and exposing the first pixel electrode; a first light emitting layer on the first pixel electrode; a first common electrode on the first light emitting layer; a first bank layer on the pixel defining film; and a second bank layer disposed on the first bank layer and including a side surface protruding further than a side surface of the first bank layer. The thickness of the edge portion of the first pixel electrode is greater than the thickness of the main portion of the first pixel electrode, and the width of the protruding portion of the pixel defining film is greater than the width of the edge portion of the first pixel electrode.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0082454, filed on June 27, 2023, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0003] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or an organic light emitting display device. Among such flat panel display devices, a light emitting display device can display an image without a backlight unit that provides light to a display panel, because each of the pixels of the display panel includes a light emitting element that can emit light by itself.

[0004] Recently, the display device is applied to a glasses-type device for providing virtual reality and augmented reality. The display device is implemented in a very small size of less than 2 inches so as to be applied to the glasses-type device, but should have a relatively high pixel integration so as to be implemented with a relatively high resolution. In an embodiment, the display device may have a relatively high pixel integration of more than 1000 pixels per inch ("PPI"). Utility Model Content

[0005] As described above, when a display device is implemented in a small size but with a relatively high pixel integration, the area of ​​the emission region where the light emitting element is provided is reduced, and thus, it is difficult to implement light emitting elements separated from each other for each emission region through a mask process.

[0006] Features of the present disclosure provide a display device capable of forming light emitting elements separated from each other for each emission region without a mask process.

[0007] Features of the present disclosure also provide a display device in which a work function of a pixel electrode is not reduced and hole injection capability is excellent even if the pixel electrode is exposed to plasma during a process for manufacturing the display device.

[0008] However, the features of the present disclosure are not limited to the features set forth herein. The above and other features of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] In an embodiment of the present disclosure, a display device includes: a first pixel electrode, which is arranged on a substrate and includes a main portion and an edge portion surrounding the main portion; a pixel defining film, which is arranged on the substrate, includes a main portion and a protruding portion protruding from the main portion, and exposes the first pixel electrode; a first light-emitting layer, which is arranged on the first pixel electrode; a first common electrode, which is arranged on the first light-emitting layer; a first embankment layer, which is arranged on the pixel defining film; and a second embankment layer, which is arranged on the first embankment layer and includes a side surface protruding more than a side surface of the first embankment layer, wherein a thickness of the edge portion of the first pixel electrode is greater than a thickness of the main portion of the first pixel electrode, and a width of the protruding portion of the pixel defining film is greater than a width of the edge portion of the first pixel electrode.

[0010] In an embodiment, the difference between the thickness of the edge portion of the first pixel electrode and the thickness of the main portion of the first pixel electrode may be about 150 angstroms. To about

[0011] In an embodiment, the first pixel electrode may include a lower transparent electrode layer disposed on the substrate, a metal electrode layer disposed on the lower transparent electrode layer, and an upper transparent electrode layer disposed on the metal electrode layer, and the thickness of an edge portion of the upper transparent electrode layer may be greater than the thickness of a main portion of the upper transparent electrode layer.

[0012] In an embodiment, the thickness of the edge portion of the upper transparent electrode layer may be approximately To about And the thickness of the main part of the upper transparent electrode layer can be about To about

[0013] In an embodiment, the thickness of the lower transparent electrode layer may be about To about And the thickness of the metal electrode layer can be about To about

[0014] In an embodiment, the lower transparent electrode layer and the upper transparent electrode layer may include indium tin oxide ("ITO"), and the metal electrode layer may include silver (Ag).

[0015] In an embodiment, a lower surface of the protruding portion of the pixel defining film may contact an edge portion of the first pixel electrode and the first light emitting layer.

[0016] In an embodiment, a width by which a side surface of the protruding portion of the pixel defining film protrudes from a side surface of the first bank layer may be greater than a width by which a side surface of the second bank layer protrudes from a side surface of the first bank layer.

[0017] In an embodiment, the first bank layer may include aluminum (Al), and the second bank layer may include titanium (Ti).

[0018] In an embodiment, the first common electrode may contact the first bank layer.

[0019] In an embodiment, a maximum distance from the substrate to the first common electrode may be smaller than a maximum distance from the substrate to the first bank layer.

[0020] In an embodiment, the display device may further include: a first inorganic layer disposed on an upper surface of the first common electrode, a side surface of the first bank layer, and a lower surface, an upper surface, and a side surface of the second bank layer.

[0021] In an embodiment, the display device may further include: a second pixel electrode, arranged on the substrate to be separated from the first pixel electrode and including a main portion and an edge portion surrounding the main portion; a second light-emitting layer, arranged on the second pixel electrode; a second common electrode, arranged on the second light-emitting layer and separated from the first common electrode; and a second inorganic layer, arranged on the upper surface of the second common electrode, the side surface of the first embankment layer, and the lower surface, upper surface and side surface of the second embankment layer, wherein the pixel defining film may further expose the second pixel electrode, the first inorganic layer and the second inorganic layer may be separated from each other, and in the space between the first inorganic layer and the second inorganic layer separated from each other, a portion of the second embankment layer may be exposed.

[0022] In an embodiment, the display device may further include: a first organic pattern, disposed on the second embankment layer and including a material that is the same as a material of the first light-emitting layer; and a first electrode pattern, disposed on the first organic pattern and including a material that is the same as a material of the first common electrode, wherein the first light-emitting layer and the first organic pattern may be separated from each other, and the first common electrode and the first electrode pattern may be separated from each other.

[0023] In an embodiment of the present disclosure, a method for manufacturing a display device includes: forming a plurality of pixel electrodes spaced apart from each other on a substrate; forming a pixel defining material layer on the plurality of pixel electrodes, forming a first embankment material layer on the pixel defining material layer, and forming a second embankment material layer on the first embankment material layer; defining a hole exposing a first pixel electrode among the plurality of pixel electrodes by etching the pixel defining material layer, the first embankment material layer, and the second embankment material layer; etching a portion of the first pixel electrode so that a portion of a lower surface of the pixel defining material layer is exposed, and at the same time etching a side surface of the first embankment material layer exposed by the hole so that a portion of a lower surface of the second embankment material layer is exposed; forming a first light-emitting layer on the first pixel electrode and forming a first common electrode on the first light-emitting layer; and forming a first inorganic material layer on the first common electrode.

[0024] In an embodiment, forming a plurality of pixel electrodes spaced apart from each other on a substrate may include forming an amorphous ITO electrode including hydrogen through a sputtering process under an atmosphere including a mixed gas of hydrogen and argon.

[0025] In an embodiment, the method for manufacturing a display device may further include: between etching a portion of the first pixel electrode while etching the side surface of the first embankment material layer and forming a first light-emitting layer on the first pixel electrode, crystallizing the ITO electrode by heat treating the first pixel electrode to remove hydrogen in the ITO electrode.

[0026] In an embodiment, when a portion of the first pixel electrode is etched so that a portion of the lower surface of the pixel defining material layer is exposed, and at the same time, the side surface of the first embankment material layer exposed through the hole is etched so that a portion of the lower surface of the second embankment material layer is exposed, a first pixel electrode including a main portion and an edge portion surrounding the main portion can be formed, and the thickness of the edge portion of the first pixel electrode can be greater than the thickness of the main portion of the first pixel electrode.

[0027] In an embodiment, when a first light-emitting layer is formed on a first pixel electrode and a first common electrode is formed on the first light-emitting layer, a first organic pattern material layer separated from the first light-emitting layer may be formed on the second embankment material layer, and a first electrode pattern material layer separated from the first common electrode may be formed on the first organic pattern material layer, and when a first inorganic material layer is formed on the first common electrode, a first inorganic material layer that is connected without being disconnected may be formed on the first common electrode and the first electrode pattern material layer.

[0028] In an embodiment, the method for manufacturing a display device may further include: forming a mask pattern on the first inorganic material layer overlapping the first pixel electrode, and etching the first organic pattern material layer, the first electrode pattern material layer and the first inorganic material layer not covered by the mask pattern through an etching process.

[0029] According to the display device and the method for manufacturing the display device in the embodiment, by providing a pixel defining film on a pixel electrode including an edge having a large thickness, unevenness can be prevented from occurring in the display device.

[0030] Furthermore, in the method for manufacturing the display device in the embodiment, a separate layer for protecting the pixel electrode is not required, so that the process can be simplified.

[0031] The effects of the present disclosure are not limited to the above-mentioned effects, and various other effects are included in the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0033] Figure 1 is a schematic perspective view of an embodiment of an electronic device;

[0034] Figure 2 is a perspective view illustrating an embodiment of a display device included in an electronic device;

[0035] Figure 3 Viewed from the side Figure 2 A cross-sectional view of a display device;

[0036] Figure 4 is a plan view illustrating an embodiment of a display layer of a display device;

[0037] Figure 5 is a plan view illustrating an embodiment of an arrangement of a light emitting element, a trace pattern, and a second bank layer of a display device;

[0038] Figure 6 is a cross-sectional view illustrating an embodiment of a portion of a display device;

[0039] Figure 7 It is a graphic Figure 6 The first emission area is specifically an enlarged view of area A1;

[0040] Figure 8 It is a graphic Figure 7 An enlarged view of area A2;

[0041] Fig. 9 is a flow chart illustrating an embodiment of a process for manufacturing a display device; and

[0042] Figures 10 to 18 are cross-sectional views sequentially illustrating an embodiment of a process for manufacturing a display device. DETAILED DESCRIPTION

[0043] The present invention will now be described more fully below with reference to the accompanying drawings in which various embodiments are shown. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0044] It will be understood that when an element is referred to as being "on" another element, the element can be directly on the other element or intervening elements can exist between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0045] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the first element, component, region, layer or portion discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings herein.

[0046] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "one" and "the" are intended to include plural forms, including "at least one", unless the context clearly indicates otherwise. "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in the association. It will be further understood that when used in this specification, the terms "comprising" and / or "including" indicate the presence of stated features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or their groups.

[0047] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element relative to another element as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, relative terms are intended to cover different orientations of the device. For example, if the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other elements will then be oriented to be on the "upper" side of the other elements. Therefore, depending on the specific orientation of the accompanying drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device in one of the accompanying drawings is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the term "below" or "below" can cover both upper and lower orientations.

[0048] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, a term such as "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0050] Figure 1 is a schematic perspective view of an embodiment of an electronic device.

[0051] refer to Figure 1 , the electronic device 1 displays a moving image or a still image. The electronic device 1 may refer to all electronic devices that provide a display screen. In an embodiment, a television, a laptop computer, a monitor, a billboard, an Internet of Things ("IoT") device, a mobile phone, a smart phone, a tablet personal computer ("PC"), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player ("PMP"), a navigation device, a game console, a digital camera or a video camera, etc. that provide a display screen may be included in the electronic device 1.

[0052] The electronic device 1 may include a display device 10 (see Figure 2 ). In an embodiment, the display device 10 may include an inorganic light emitting diode display device, an organic light emitting diode display device, a quantum dot light emitting display device, a plasma display device, or a field emission display device. Hereinafter, the case where the organic light emitting diode display device is applied to an embodiment of the display device will be described by way of example, but the present disclosure is not limited thereto, and when applicable, the same technical spirit may be applied to other display devices.

[0053] The shape of the electronic device 1 may be modified variously. In an embodiment, for example, the electronic device 1 may have a shape such as a quadrilateral shape (e.g., a rectangular shape with a width greater than a length, a rectangular shape with a length greater than a width, a square shape, a rectangular shape with rounded corners (vertices)), other polygonal shapes, or a circular shape in a plan view. The shape of the display area DA of the electronic device 1 may be similar to the overall shape of the electronic device 1. Figure 1 , the electronic device 1 having a rectangular shape having a large length in the second direction DR2 is illustrated.

[0054] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is an area in which an image is displayed, and the non-display area NDA is an area in which an image is not displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DA may substantially occupy the center of the electronic device 1.

[0055] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 may be areas where components for adding various functions to the electronic device 1 are provided, and may correspond to component areas. The components may be Figure 3 Optical device 500 is shown in FIG.

[0056] Figure 2 is a perspective view illustrating an embodiment of a display device included in an electronic device.

[0057] refer to Figure 2 In an embodiment, the electronic device 1 may include a display device 10. The display device 10 may provide an image displayed by the electronic device 1. In a plan view, the display device 10 may have a shape similar to that of the electronic device 1. In an embodiment, for example, the display device 10 may have a shape similar to a quadrilateral shape in a plan view, for example, a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2. The corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded with a curvature, but are not limited thereto, and may also be right angles. The shape of the display device 10 in a plan view is not limited to a rectangular shape, and may be a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0058] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0059] The display panel 100 may include a main area MA and a sub-area SBA.

[0060] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. In an embodiment, for example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining film defining an emission area or an opening area, and a self-luminous element.

[0061] In an embodiment, for example, the self-luminous element may include at least one of a micro LED, an organic light emitting diode ("LED") including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, and an inorganic LED including an inorganic semiconductor, but is not limited thereto.

[0062] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a scan driver 210 (refer to FIG. 1 ) that supplies scan signals to scan lines. Figure 4 ) and a fan-out line FOL (reference Figure 4 ).

[0063] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded or curled. In an embodiment, for example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (third direction DR3). The sub-area SBA may include a display driver 200 and a pad portion connected to the circuit board 300. In another embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be disposed in the non-display area NDA.

[0064] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a source voltage to a power line and supply a scan control signal to a scan driver. The display driver 200 may be formed as an integrated circuit ("IC") and may be disposed (e.g., mounted) on the display panel 100 in a chip on glass ("COG") manner, a chip on plastic ("COP") manner, or an ultrasonic bonding manner. In an embodiment, the display driver 200 may be disposed in the sub-area SBA and may overlap with the main area MA in a thickness direction (third direction DR3) by bending of the sub-area SBA. In another embodiment, the display driver 200 may be disposed (e.g., mounted) on a circuit board 300.

[0065] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film ("ACF"). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0066] The touch driver 400 may be disposed (e.g., mounted) on the circuit board 300. The touch driver 400 may be connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and sense the amount of change in capacitance between the plurality of touch electrodes. In an embodiment, for example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may determine whether a touch input has been generated and calculate touch coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch driver 400 may be formed as an IC.

[0067] Figure 3 Viewed from the side Figure 2 A cross-sectional view of a display device.

[0068] refer to Figure 3 The display panel 100 may include a display layer DU and a color filter layer CFL. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and a thin film encapsulation layer TFEL.

[0069] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. In an embodiment, for example, the substrate SUB may include a polymer resin such as polyimide ("PI"), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0070] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may further include a scan line, a data line, a power line, a scan control line, a fan-out line connecting the display driver 200 and the data line to each other, and a lead connecting the display driver 200 and the pad portion to each other. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In an embodiment, for example, when the scan driver is formed on one side of the non-display area NDA of the display panel 100, the scan driver may include a thin film transistor.

[0071] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The scan line, the data line, the power line, and the thin film transistor of each of the pixels of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control line and the fan-out line of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The lead line of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0072] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements each including a first electrode, a second electrode and a light emitting layer for emitting light, and a pixel defining film defining an emission region or an opening region. The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display region DA.

[0073] In an embodiment, the light emitting layer may be an organic light emitting layer including an organic material. The light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. When the first electrode receives a predetermined voltage through the thin film transistor of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and may be combined with each other in the organic light emitting layer to emit light.

[0074] In another embodiment, the light emitting element may include a micro light emitting diode, a quantum dot light emitting diode including a quantum dot light emitting layer, or an inorganic light emitting diode including an inorganic semiconductor.

[0075] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light emitting element layer EML and may protect the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light emitting element layer EML.

[0076] In an embodiment, the touch sensing layer may be disposed on the display layer DU. The touch sensing layer may obtain the coordinates of the touch input point in a capacitive manner. In a capacitive manner embodiment, the touch sensing layer may obtain the coordinate information of the touched point in a self-capacitive manner or a mutual-capacitive manner, but is not limited thereto.

[0077] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a predetermined wavelength band through the color filter and block or absorb light of other wavelength bands. The color filter layer CFL may absorb some of the light introduced from the outside of the display device 10 to reduce reflected light of the external light. Therefore, the color filter layer CFL may prevent distortion of color due to reflection of external light.

[0078] Since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, a separate substrate for the color filter layer CFL may not be required in the display device 10. Therefore, the thickness of the display device 10 may be relatively small.

[0079] In some embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed in the second display area DA2 or the third display area DA3. The optical device 500 may emit or receive infrared light, ultraviolet light, and / or light in the visible light band. In an embodiment, for example, the optical device 500 may be an optical sensor that senses light incident on the display device 10, such as a proximity sensor, an illumination sensor, a camera sensor, a fingerprint sensor, or an image sensor.

[0080] Figure 4 is a plan view illustrating an embodiment of a display layer of a display device.

[0081] refer to Figure 4 , the display layer DU may include a display area DA and a non-display area NDA.

[0082] The display area DA may be disposed at the center of the display panel 100. A plurality of pixels PX, a plurality of scan lines SL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in the display area DA. Each of the plurality of pixels PX may be defined as a minimum unit that emits light.

[0083] The plurality of scan lines SL may supply the plurality of pixels PX with scan signals received from the scan driver 210. The plurality of scan lines SL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1.

[0084] The plurality of data lines DL may supply the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0085] The plurality of power lines VL may supply a source voltage received from the display driver 200 to the plurality of pixels PX. Here, the source voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a relatively low potential voltage. The plurality of power lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0086] The non-display area NDA may surround the display area DA. The scan driver 210, the fan-out line FOL, and the scan control line SCL may be disposed in the non-display area NDA. The scan driver 210 may generate a plurality of scan signals based on the scan control signal, and may sequentially supply the plurality of scan signals to the plurality of scan lines SL according to a set order.

[0087] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0088] The scan control line SCL may extend from the display driver 200 to the scan driver 210. The scan control line SCL may supply the scan driver 210 with a scan control signal received from the display driver 200.

[0089] The sub area SBA may include the display driver 200 , the pad area PA, and first and second touch pad areas TPA1 and TPA2 .

[0090] The display driver 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driver 200 may supply a data voltage to the data line DL through the fan-out line FOL. The data voltage may be supplied to a plurality of pixels PX, and the brightness of the plurality of pixels PX may be controlled. The display driver 200 may supply a scan control signal to the scan driver 210 through the scan control line SCL.

[0091] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be disposed at an edge of the sub-area SBA. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 using a material such as ACF or a self-assembled anisotropic conductive paste ("SAP"). In an embodiment, the first touch pad area TPA1 may include a first touch pad portion TP1, and the second touch pad area TPA2 may include a second touch pad portion TP2.

[0092] The pad area PA may include a plurality of display pad portions DP. The plurality of display pad portions DP may be connected to a graphics system through the circuit board 300. The plurality of display pad portions DP may be connected to the circuit board 300 to receive digital video data, and may supply the digital video data to the display driver 200.

[0093] Figure 5 is a plan view illustrating an embodiment of a portion of a display device. Figure 5 1 is a plan view illustrating the arrangement of the light emitting elements ED1 , ED2 , and ED3 , the trace patterns TRP1 , TRP2 , and TRP3 , and the second bank layer BN2 in the display area DA of the display device 10 .

[0094] refer to Figure 5 , the second bank layer BN2 may cover the display area DA but expose multiple portions of the display area DA. Openings are defined in the exposed areas not covered by the second bank layer BN2, and the light emitting elements ED1, ED2, and ED3 are disposed in the corresponding openings. The trace patterns TRP1, TRP2, and TRP3 are disposed on the second bank layer BN2 along the contours of the exposed areas not covered by the second bank layer BN2. Figure 5 , the exposed area not covered by the second bank layer BN2 is illustrated to have a circular shape, but the exposed area may have a polygonal shape such as a triangular shape, a quadrilateral shape, or a hexagonal shape, and the shapes of the trace patterns TRP1, TRP2, and TRP3 provided along the contour of the exposed area may also be changed. The trace patterns TRP1, TRP2, and TRP3 are provided at a level above the second bank layer BN2, and the light emitting elements ED1, ED2, and ED3 are provided at a level below the second bank layer BN2.

[0095] The exposed regions not covered by the second bank layer BN2 may be spaced apart from each other in the fourth direction DR4, and may also be spaced apart from each other in the fifth direction DR5. The fourth direction DR4 is an arbitrary direction in a plan view including the first direction DR1 and the second direction DR2, and the fifth direction DR5 is a direction perpendicular to the fourth direction DR4. The shape and arrangement of the exposed regions not covered by the second bank layer BN2 are not limited to Figure 5 and the exposed area not covered by the second bank layer BN2 can be formed in the shape and arrangement shown in FIG. Type settings.

[0096] Figure 6 is a cross-sectional view of an embodiment of a portion of a display device. Specifically, Figure 6 is along Figure 5 A cross-sectional view taken along the line BB' of Figure 5 The organic encapsulation film TFE2, the second inorganic encapsulation film TFE3, the color filters CF1, CF2 and CF3, the light shielding layer BM and the overcoat layer OC are arranged on the plan view of FIG. Figure 6 The figure shows a cross section of a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, a thin film encapsulation layer TFEL, and a color filter layer CFL of a display layer DU.

[0097] refer to Figure 6 , the display panel 100 of the display device 10 may include a display layer DU and a color filter layer CFL. The display layer DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and a thin film encapsulation layer TFEL. The display panel 100 may include a light shielding layer BM disposed on the thin film encapsulation layer TFEL, and color filters CF1, CF2, and CF3 of the color filter layer CFL may be disposed on the light shielding layer BM.

[0098] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or curled. In an embodiment, the substrate SUB may include a polymer resin such as polyimide ("PI"), but is not limited thereto. In another embodiment, the substrate SUB may include a glass material or a metal material.

[0099] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2.

[0100] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic film capable of preventing penetration of air or moisture. In an embodiment, for example, the first buffer layer BF1 may include a plurality of inorganic films alternately stacked.

[0101] The bottom metal layer BML may be disposed on the first buffer layer BF1. In an embodiment, for example, the bottom metal layer BML may be formed as a single layer or multiple layers including any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0102] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic film capable of preventing penetration of air or moisture. In an embodiment, for example, the second buffer layer BF2 may include a plurality of inorganic films alternately stacked.

[0103] The thin film transistor TFT may be disposed on the second buffer layer BF2 and may constitute a pixel circuit of each of the plurality of pixels. In an embodiment, for example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0104] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the third direction DR3, and may be insulated from the gate electrode GE by the gate insulating layer GI. The material of the semiconductor layer ACT in portions of the semiconductor layer ACT may become a conductor to form a source electrode SE and a drain electrode DE.

[0105] The gate insulating layer GI may be disposed on the semiconductor layer ACT. In an embodiment, for example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT and the gate electrode GE from each other. The gate insulating layer GI may define a contact hole through which the first connection electrode CNE1 penetrates.

[0106] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT in the third direction DR3 with the gate insulating layer GI interposed therebetween.

[0107] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may define a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0108] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in the third direction DR3. The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0109] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may define a contact hole through which the first connection electrode CNE1 penetrates. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0110] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT and the second connection electrode CNE2 to each other. The first connection electrode CNE1 may be inserted into a contact hole defined in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0111] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may define a contact hole through which the second connection electrode CNE2 penetrates.

[0112] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED to each other. The second connection electrode CNE2 may be inserted into a contact hole defined in the first passivation layer PAS1 to contact the first connection electrode CNE1.

[0113] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may define contact holes through which the pixel electrodes AE1, AE2, and AE3 of the light emitting element ED penetrate.

[0114] The light emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light emitting element layer EML may include a light emitting element ED, a pixel defining layer PDL, a capping layer CAP (refer to Figure 7 ) and a bank structure BNS. The light emitting element ED may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3.

[0115] Figure 7 It is a graphic Figure 6 The first emission area is specifically an enlarged view of area A1.

[0116] Apart from Figure 6 In addition, reference Figure 7 , the display device 10 may include a plurality of emission areas EA1, EA2, and EA3 disposed in the display area DA. The emission areas EA1, EA2, and EA3 may include areas in which light is emitted from the light emitting elements ED1, ED2, and ED3 and travels to the color filter layer CFL in the third direction DR3. The emission areas EA1, EA2, and EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that are spaced apart from each other and emit light of different colors.

[0117] In an embodiment, the areas or sizes of the first to third emission areas EA1, EA2, and EA3 may be the same as each other. In an embodiment, for example, in the display device 10, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have the same area. However, the present disclosure is not limited thereto. In the display device 10, the areas or sizes of the first to third emission areas EA1, EA2, and EA3 may be different from each other. In an embodiment, the area of ​​the second emission area EA2 may be larger than the area of ​​the first emission area EA1 and the area of ​​the third emission area EA3, and the area of ​​the third emission area EA3 may be larger than the area of ​​the first emission area EA1. The intensity of light emitted from the emission areas EA1, EA2, and EA3 may be changed based on the areas of the emission areas EA1, EA2, and EA3, and the color perception of the image displayed on the display device 10 or the electronic device 1 may be controlled by adjusting the areas of the emission areas EA1, EA2, and EA3. Figure 6 In the embodiment of FIG. 5 , it is illustrated that the areas of the emission areas EA1 , EA2 , and EA3 are the same as each other, but the present disclosure is not limited thereto.

[0118] In the display device 10, one first emission area EA1, one second emission area EA2, and one third emission area EA3 disposed adjacent to each other may form one pixel group. One pixel group may include emission areas EA1, EA2, and EA3 that emit light of different colors to represent a white grayscale. However, the present disclosure is not limited thereto, and the combination of emission areas EA1, EA2, and EA3 constituting one pixel group may be modified differently depending on the arrangement of the emission areas EA1, EA2, and EA3 or the color of light emitted by the emission areas EA1, EA2, and EA3, etc.

[0119] The plurality of openings defined in the embankment structure BNS of the light emitting element layer EML are defined along the boundary of the embankment structure BNS. The first embankment layer BN1 and the second embankment layer BN2 of the embankment structure BNS may have a shape in which they surround the emission regions EA1, EA2, and EA3. The plurality of openings may include first to third openings corresponding to the first to third emission regions EA1, EA2, and EA3, respectively.

[0120] The display device 10 may include a plurality of light emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3. The light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1 disposed in a first emission area EA1, a second light emitting element ED2 disposed in a second emission area EA2, and a third light emitting element ED3 disposed in a third emission area EA3. The light emitting elements ED1, ED2, and ED3 may include pixel electrodes AE1, AE2, and AE3, light emitting layers EL1, EL2, and EL3, and common electrodes CE1, CE2, and CE3, respectively, and the light emitting elements ED1, ED2, and ED3 disposed in different emission areas EA1, EA2, and EA3 may emit light of different colors, respectively, depending on the materials of the light emitting layers EL1, EL2, and EL3. In an embodiment, a first light emitting element ED1 disposed in a first emission area EA1 may emit a first light having a peak wavelength in a range of about 610 nanometers (nm) to about 650 nm, which is red light, a second light emitting element ED2 disposed in a second emission area EA2 may emit a second light having a peak wavelength in a range of about 510 nm to about 550 nm, which is green light, and a third light emitting element ED3 disposed in a third emission area EA3 may emit a third light having a peak wavelength in a range of about 440 nm to about 480 nm, which is blue light. Light emitting elements ED1, ED2, and ED3 emitting light of different colors to represent a white grayscale may be included in the first to third emission areas EA1, EA2, and EA3 constituting one pixel group, respectively.

[0121] The pixel electrodes AE1, AE2, and AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1, AE2, and AE3 may be disposed in a plurality of emission areas EA1, EA2, and EA3, respectively. The pixel electrodes AE1, AE2, and AE3 may include a first pixel electrode AE1 disposed in a first emission area EA1, a second pixel electrode AE2 disposed in a second emission area EA2, and a third pixel electrode AE3 disposed in a third emission area EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other on the second passivation layer PAS2. Figure 6 4 illustrates that the first to third pixel electrodes AE1, AE2, and AE3 are spaced apart from each other in the fourth direction DR4.

[0122] The pixel electrodes AE1, AE2 and AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first and second connection electrodes CNE1 and CNE2. The edges of the pixel electrodes AE1, AE2 and AE3 spaced apart from each other are covered by a pixel defining film PDL so that the first to third pixel electrodes AE1, AE2 and AE3 may be insulated from each other.

[0123] Figure 8 It is a graphic Figure 7 The region A2 relates to a boundary between the first pixel electrode AE1 and the pixel defining film PDL.

[0124] The pixel defining film PDL may be disposed on the second passivation layer PAS2 and the pixel electrodes AE1, AE2, and AE3. The pixel defining film PDL is completely disposed on the second passivation layer PAS2, but a portion of the upper surface of the first to third pixel electrodes AE1, AE2, and AE3 is exposed to define emission areas EA1, EA2, and EA3. In an embodiment, for example, the pixel defining film PDL may expose the first pixel electrode AE1 in the first emission area EA1, and the first light emitting layer EL1 may be directly disposed on the first pixel electrode AE1. The pixel defining film PDL may cover the edge and side surface of the upper surface of the pixel electrodes AE1, AE2, and AE3.

[0125] The pixel defining film PDL may include a main body portion PDL_B and a protruding portion PDL_P protruding from the main body portion PDL_B toward each of the emission areas EA1, EA2, and EA3. The protruding portion PDL_P may be a portion of a side surface of the main body portion PDL_B that protrudes toward each of the emission areas EA1, EA2, and EA3. The thickness t42 of the protruding portion PDL_P may be less than the thickness t41 of the main body portion PDL_B. The width d2 of the protruding portion PDL_P is defined as the length of the protruding portion PDL_P protruding from the main body portion PDL_B. The protruding portion PDL_P may be disposed on an edge portion 601 of each of the pixel electrodes AE1, AE2, and AE3.

[0126] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include at least one of a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, a tantalum oxide layer, a hafnium oxide layer, a zinc oxide layer, and an amorphous silicon layer, but is not limited thereto.

[0127] Each of the pixel electrodes AE1, AE2, and AE3 includes a main portion 602 and an edge portion 601 surrounding the main portion 602. The main portion 602 may be a region including the center of each of the pixel electrodes AE1, AE2, and AE3 and the periphery of the center, and may be a flat portion having a constant thickness. The edge portion 601 may be an edge region of each of the pixel electrodes AE1, AE2, and AE3. Figures 6 to 8 6. Only the case where the boundary between the edge portion 601 and the main portion 602 is a right angle is illustrated in FIG. 6, but the boundary between the edge portion 601 and the main portion 602 may be rounded.

[0128] The thickness (t1+t2+t3) of the edge portion 601 may be greater than the thickness (t1+t2+t31) of the main portion 602. In this case, among the thickness of the edge portion 601 and the thickness of the main portion 602, the thickness of the portion of the pixel electrodes AE1, AE2, and AE3 penetrating the second passivation layer PAS2 and connected to the second connection electrode CNE2 is not considered, but the thickness from the upper surface of the second passivation layer PAS2 is considered.

[0129] When the pixel electrodes AE1, AE2, and AE3 support the pixel defining film PDL in a state where they have a relatively large thickness at the edge portion 601, a decrease in work function and degradation of hole injection capability can be prevented without a separate protective layer. Since a separate protective layer is not included between the pixel electrodes AE1, AE2, and AE3 and the pixel defining film PDL, a process for manufacturing a display device can be simplified, and occurrence of unevenness (mura) due to the protective layer can be prevented.

[0130] In defining a hole HOL (refer to Fig.12 ), the upper surface of the pixel electrodes AE1, AE2 and AE3 that is not covered by the pixel definition film PDL may be exposed to plasma. The work function of the pixel electrodes AE1, AE2 and AE3 in the area exposed to the plasma is reduced, and the hole injection capability of the pixel electrodes AE1, AE2 and AE3 in the area exposed to the plasma is degraded. The pixel electrodes AE1, AE2 and AE3 in the area damaged by exposure to the plasma may be removed, while the undercut structure of the first bank layer BN1 is formed by a subsequent wet etching process. The upper portion of the pixel electrodes AE1, AE2 and AE3 corresponding to the main portion 602 that is not covered by the pixel definition film PDL and exposed may be removed by part of the thickness, and the edge portion 601 of the pixel electrodes AE1, AE2 and AE3 that is set under the protruding portion PDL_P of the pixel definition film PDL may not be etched. Therefore, the thickness (t1+t2+t3) of the edge portion 601 may be greater than the thickness (t1+t2+t31) of the main portion 602. Furthermore, the pixel electrodes AE1, AE2, and AE3 in the regions where the work function is reduced and the hole injection capability is deteriorated are removed, so that the overall hole injection capability of the pixel electrodes AE1, AE2, and AE3 can be maintained.

[0131] When a portion of the pixel electrodes AE1, AE2, and AE3 is etched by isotropic wet etching, the pixel electrodes AE1, AE2, and AE3 may be etched even in a region covered with the pixel defining film PDL. Therefore, a width d2 of the protruding portion PDL_P of the pixel defining film PDL may be greater than a width d1 of an edge portion 601 of each of the pixel electrodes AE1, AE2, and AE3.

[0132] The protruding portion PDL_P of the pixel defining film PDL may be disposed on a portion of the main portion 602 of the pixel electrodes AE1, AE2, and AE3 and on the edge portion 601 of the pixel electrodes AE1, AE2, and AE3. Spaces may be formed between the protruding portion PDL_P of the pixel defining film PDL and the main portion 602 of the pixel electrodes AE1, AE2, and AE3, and the light emitting layers EL1, EL2, and EL3 to be described later may be filled in these spaces. The lower surface of the protruding portion PDL_P of the pixel defining film PDL may contact the edge portion 601 of the pixel electrodes AE1, AE2, and AE3 and a portion of the light emitting layers EL1, EL2, and EL3.

[0133] The exposed side surface of the body portion PDL_B of the pixel defining film PDL may contact the side surfaces of the pixel electrodes AE1 , AE2 , and AE3 , specifically, the outer side surface of the edge portion 601 .

[0134] The difference (t32) between the thickness (t1+t2+t3) of the edge portion 601 and the thickness (t1+t2+t31) of the main portion of each of the pixel electrodes AE1, AE2, and AE3 may be approximately To about The difference (t32) between the thickness (t1+t2+t31) of the main portion 602 of each of the pixel electrodes AE1, AE2 and AE3 and the thickness (t1+t2+t3) of the edge portion 601 corresponds to the thickness of each of the pixel electrodes AE1, AE2 and AE3 removed by isotropic wet etching.

[0135] The pixel electrodes AE1, AE2, and AE3 may include a transparent electrode material and a conductive metal material. The conductive metal material may be one or more of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), and lanthanum (La). The transparent electrode material may be one or more of indium tin oxide ("ITO"), indium zinc oxide ("IZO"), and indium tin zinc oxide ("ITZO").

[0136] Each of the pixel electrodes AE1, AE2, and AE3 may have a multi-layer structure. Each of the pixel electrodes AE1, AE2, and AE3 may have a structure of three or more layers in which a lower transparent electrode layer 610, a metal electrode layer 620, and an upper transparent electrode layer 630 are sequentially stacked. In an embodiment, the lower transparent electrode layer 610 and the upper transparent electrode layer 630 may include ITO, and the metal electrode layer 620 may include silver (Ag).

[0137] The lower transparent electrode layer 610 and the metal electrode layer 620 may be flat in the main portion 602 and the edge portion 601. That is, the lower transparent electrode layer 610 may have the same thickness in the main portion 602 and the edge portion 601. Similarly, the metal electrode layer 620 may also have the same thickness in the main portion 602 and the edge portion 601.

[0138] In an embodiment, the thickness t1 of the lower transparent electrode layer 610 may be approximately To about The metal electrode layer 620 should reflect light emitted from each of the light emitting layers EL1, EL2, and EL3, and thus may be relatively thicker than the lower transparent electrode layer 610. The thickness of the metal electrode layer 620 may be approximately To about

[0139] The upper transparent electrode layer 630 may have different thicknesses in the main portion 602 and the edge portion 601. The thickness t3 of the edge portion 601 of the upper transparent electrode layer 630 may be greater than the thickness t31 of the upper transparent electrode layer 630 in the main portion 602. That is, a difference (t32) between the thickness (t1+t2+t3) of each of the pixel electrodes AE1, AE2, and AE3 in the edge portion 601 and the thickness (t1+t2+t31) in the main portion may be formed in the upper transparent electrode layer 630.

[0140] When the transparent electrode is formed by a sputtering process in an atmosphere of a mixed gas of hydrogen and argon, the thickness of the electrode maintaining the amorphous property can be large compared to when the transparent electrode is formed in an atmosphere of only argon. The edge portion 601 of the upper transparent electrode layer 630 is not etched, and thus can have the same thickness as each of the pixel electrodes AE1, AE2, and AE3 manufactured initially, and the thickness of the edge portion 601 of the upper transparent electrode layer 630 can be greater than the thickness of the transparent electrode manufactured in an atmosphere of only argon.

[0141] In an embodiment, the thickness t3 of the edge portion 601 of the upper transparent electrode layer 630 may be approximately To about The thickness t31 of the main portion 602 of the upper transparent electrode layer 630 may be approximately To about

[0142] The lower transparent electrode layer 610 and the upper transparent electrode layer 630 may be crystalline. The lower transparent electrode layer 610 and the upper transparent electrode layer 630 may include or consist of an amorphous material containing hydrogen therein, and then be crystallized by removing hydrogen through heat treatment.

[0143] The light-emitting layers EL1, EL2, and EL3 may be disposed on the pixel electrodes AE1, AE2, and AE3, respectively. The light-emitting layers EL1, EL2, and EL3 may be organic light-emitting layers including an organic material, and may be formed on the pixel electrodes AE1, AE2, and AE3, respectively, by a deposition process. When the thin film transistor TFT applies a predetermined voltage to the pixel electrodes AE1, AE2, and AE3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 of the light-emitting elements ED1, ED2, and ED3 receive a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layers EL1, EL2, and EL3, respectively, through the hole transport layer and the electron transport layer, and may be recombined with each other in the light-emitting layers EL1, EL2, and EL3 to emit light.

[0144] The light-emitting layers EL1, EL2, and EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively arranged in different emission areas EA1, EA2, and EA3. The first light-emitting layer EL1 may be arranged in the first emission area EA1 and on the first pixel electrode AE1, the second light-emitting layer EL2 may be arranged in the second emission area EA2 and on the second pixel electrode AE2, and the third light-emitting layer EL3 may be arranged in the third emission area EA3 and on the third pixel electrode AE3. The first to third light-emitting layers EL1, EL2, and EL3 may be light-emitting layers of the first to third light-emitting elements ED1, ED2, and ED3, respectively. The first light-emitting layer EL1 may be a light-emitting layer that emits red light, which is light of a first color, the second light-emitting layer EL2 may be a light-emitting layer that emits green light, which is light of a second color, and the third light-emitting layer EL3 may be a light-emitting layer that emits blue light, which is light of a third color.

[0145] The deposition process of the light emitting layers EL1, EL2, and EL3 may be performed such that the materials for forming the light emitting layers EL1, EL2, and EL3 are deposited in a direction inclined relative to the upper surface of the substrate SUB rather than in a direction perpendicular to the upper surface of the substrate SUB. Therefore, the light emitting layers EL1, EL2, and EL3 may be disposed on the upper surfaces of the pixel electrodes AE1, AE2, and AE3 exposed by the openings, respectively, and may be disposed to fill the space between the main portions 602 of the pixel electrodes AE1, AE2, and AE3 and the protruding portion PDL_P of the pixel defining film PDL.

[0146] Common electrodes CE1, CE2, and CE3 may be disposed on the light emitting layers EL1, EL2, and EL3, respectively. Common electrodes CE1, CE2, and CE3 may include a transparent conductive material to transmit light generated from the light emitting layers EL1, EL2, and EL3. Common electrodes CE1, CE2, and CE3 may receive a common voltage or a relatively low potential voltage. When pixel electrodes AE1, AE2, and AE3 receive a voltage corresponding to a data voltage and common electrodes CE1, CE2, and CE3 receive a relatively low potential voltage, a potential difference is formed between pixel electrodes AE1, AE2, and AE3 and common electrodes CE1, CE2, and CE3, so that the light emitting layers EL1, EL2, and EL3 may emit light.

[0147] The common electrodes CE1, CE2, and CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 respectively disposed in different emission areas EA1, EA2, and EA3. The first common electrode CE1 may be disposed in the first emission area EA1 and on the first light emitting layer EL1, the second common electrode CE2 may be disposed in the second emission area EA2 and on the second light emitting layer EL2, and the third common electrode CE3 may be disposed in the third emission area EA3 and on the third light emitting layer EL3. The first to third common electrodes CE1, CE2, and CE3 may be spaced apart from each other.

[0148] Similar to the light emitting layers EL1, EL2 and EL3, the common electrodes CE1, CE2 and CE3 may be formed by a deposition process. The deposition process of the common electrodes CE1, CE2 and CE3 may be performed such that the electrode material is deposited in a direction inclined relative to the upper surface of the substrate SUB rather than in a direction perpendicular to the upper surface of the substrate SUB.

[0149] The capping layer CAP may be disposed on the common electrodes CE1, CE2, and CE3. The capping layer CAP may include an organic insulating material or an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3. The capping layer CAP may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. In an embodiment, the capping layer CAP may include an organic insulating material or an inorganic insulating material and may include an organic insulating material or an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3. 3 and / or CuPc, or an inorganic material such as LiF, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0150] The display device 10 may include a plurality of embankment structures BNS disposed on the pixel definition film PDL. The embankment structure BNS may have a structure in which embankment layers BN1 and BN2 including different materials are sequentially stacked, may define a plurality of openings corresponding to emission areas EA1, EA2, and EA3, and may be disposed to overlap with a light shielding layer BM to be described later. The light emitting elements ED1, ED2, and ED3 of the display device 10 may overlap with the openings of the embankment structure BNS.

[0151] The bank structure BNS may include a first bank layer BN1 disposed on the pixel defining layer PDL and a second bank layer BN2 disposed on the first bank layer BN1.

[0152] The first bank layer BN1 may be disposed on the pixel defining film PDL. A side surface of the first bank layer BN1 may be further recessed than a side surface of the pixel defining film PDL in a direction opposite to a direction toward the emission regions EA1, EA2, and EA3. A side surface of the first bank layer BN1 may be further recessed than a side surface of a second bank layer BN2 to be described later in a direction opposite to a direction toward the emission regions EA1, EA2, and EA3.

[0153] In an embodiment, the first bank layer BN1 may include a metal material. The metal material of the first bank layer BN1 may be any material that is removed together with the second bank layer BN2 by dry etching, but can form an undercut structure by exhibiting an etching rate different from that of the second bank layer BN2 relative to wet etching with an alkali-based etchant. In an embodiment, the first bank layer BN1 may include aluminum (Al).

[0154] In an embodiment, the thickness of the first bank layer BN1 may be about To about When the thickness of the first bank layer BN1 is within the above range, the light emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 separated from each other may be formed by a deposition process and an etching process instead of a mask process.

[0155] In an embodiment, the common electrodes CE1, CE2 and CE3 may be in direct contact with the side surface of the first bank layer BN1. The common electrodes CE1, CE2 and CE3 of different light emitting elements ED1, ED2 and ED3 may be in direct contact with the first bank layer BN1, respectively, and the first bank layer BN1 may include a metal material so that the common electrodes CE1, CE2 and CE3 may be electrically connected to each other through the first bank layer BN1.

[0156] The light-emitting layers EL1, EL2, and EL3 may be in direct contact with the side surface of the first bank layer BN1. The contact area between the common electrodes CE1, CE2, and CE3 and the side surface of the first bank layer BN1 may be greater than the contact area between the light-emitting layers EL1, EL2, and EL3 and the side surface of the first bank layer BN1. The common electrodes CE1, CE2, and CE3 may be arranged to have a larger area than the light-emitting layers EL1, EL2, and EL3 on the side surface of the first bank layer BN1, or may be arranged to reach a greater height than the light-emitting layers EL1, EL2, and EL3 on the side surface of the first bank layer BN1. Since the common electrodes CE1, CE2, and CE3 of different light-emitting elements ED1, ED2, and ED3 are electrically connected to each other through the first bank layer BN1, it may be advantageous for the common electrodes CE1, CE2, and CE3 to contact the first bank layer BN1 with a larger area. Although in Figure 6 and Figure 7Although not shown in the figure, the light emitting layers EL1, EL2 and EL3 may not be in direct contact with the side surface of the first bank layer BN1.

[0157] The second bank layer BN2 may be disposed on the first bank layer BN1. The second bank layer BN2 may include a tip TIP which is a region protruding from the first bank layer BN1. A side surface of the second bank layer BN2 may protrude toward the emission areas EA1, EA2, and EA3 from a side surface of the first bank layer BN1.

[0158] The side surface of the second bank layer BN2 has a shape in which the side surface of the second bank layer BN2 protrudes toward the emission areas EA1, EA2, and EA3 more than the side surface of the first bank layer BN1, and thus, an undercut structure of the first bank layer BN1 may be formed under the tip TIP of the second bank layer BN2. The second bank layer BN2 includes the tip TIP, and thus, light emitting elements ED1, ED2, and ED3 separated from each other may be formed without a mask process.

[0159] Because the first bank layer BN1 and the second bank layer BN2 include materials different from each other, the shape of the side surface of the first bank layer BN1 and the second bank layer BN2 may be a structure formed due to the difference in etching rates in the etching process. In an embodiment, the second bank layer BN2 may include a material having an etching rate slower than that of the first bank layer BN1, and the first bank layer BN1 may be further etched in the etching process so that an undercut may be formed under the tip TIP of the second bank layer BN2. In an embodiment, the second bank layer BN2 may include titanium (Ti).

[0160] In the process for manufacturing the display device 10, a mask process is required in order to form the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 for the emission areas EA1, EA2, and EA3, respectively. A structure for mounting a mask in the display device 10 to perform the mask process may be required or an unnecessary large area of ​​the non-display area NDA may be required to control dispersion according to the mask process. When such a mask process is minimized, unnecessary components such as a structure for mounting a mask can be omitted from the display device 10, and the area of ​​the non-display area NDA for controlling dispersion can be minimized.

[0161] In the display device 10 in the embodiment, the embankment structure BNS includes a tip TIP protruding toward the emission areas EA1, EA2, and EA3, and therefore, the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 can be formed by a deposition process and an etching process instead of a mask process. In addition, even by a deposition process, different layers can be formed separately in different emission areas EA1, EA2, and EA3. In an embodiment, for example, even if the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3 are formed by a deposition process without using a mask, the deposited materials can be disconnected from each other by the tip TIP of the second embankment layer BN2 using the embankment structure BNS interposed therebetween, rather than being connected to each other between the emission areas EA1, EA2, and EA3. By forming a material for forming a predetermined layer on the entire surface of the display device 10 and then etching and removing the layer formed in the unnecessary area, different layers can be formed separately in different emission areas EA1, EA2, and EA3. In the display device 10, different light emitting elements ED1, ED2, and ED3 may be formed respectively for the emission areas EA1, EA2, and EA3 through a deposition process and an etching process without using a mask process, unnecessary components may be omitted from the display device 10, and the area of ​​the non-display area NDA may be minimized.

[0162] In an embodiment, the thickness of the second bank layer BN2 may be about To about In an embodiment, a tip TIP of the second bank layer BN2 protruding from the first bank layer BN1 toward the emission areas EA1, EA2, and EA3 may have a width of about 0.1 micrometers (μm) to about 1.0 μm.

[0163] The tip TIP of the second bank layer BN2 may overlap with the common electrodes CE1, CE2, and CE3 in the thickness direction (third direction DR3) of the substrate SUB. In addition, the tip TIP of the second bank layer BN2 may overlap with the light-emitting layers EL1, EL2, and EL3 in the thickness direction (third direction DR3) of the substrate SUB. In addition, the tip TIP of the second bank layer BN2 may overlap with the pixel defining film PDL in the thickness direction (third direction DR3) of the substrate SUB. The common electrodes CE1, CE2, and CE3 may be formed below the lower surface of the tip TIP of the second bank layer BN2. The maximum distance from the substrate SUB to each of the common electrodes CE1, CE2, and CE3 may be less than the maximum distance from the substrate SUB to the second bank layer BN2.

[0164] In an embodiment, a width of a side surface of the protruding portion PDL_P of the pixel defining film PDL protruding from a side surface of the first bank layer BN1 may be greater than a width of a side surface of the second bank layer BN2 protruding from a side surface of the first bank layer BN1 (ie, a width of the tip TIP).

[0165] The display device 10 may include trace patterns TRP1, TRP2, and TRP3 that are traces deposited on the embankment structure BNS. The trace patterns TRP1, TRP2, and TRP3 may include organic patterns ELP1, ELP2, and ELP3, electrode patterns CEP1, CEP2, and CEP3, and a cap pattern CLP, respectively, and may have shapes of their contours around the emission areas EA1, EA2, and EA3 on the second embankment layer BN2. When forming the cap layer CAP and the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3, the cap pattern CLP, the organic patterns ELP1, ELP2, and ELP3, and the electrode patterns CEP1, CEP2, and CEP3 may be formed simultaneously with the cap layer CAP and the light-emitting layers EL1, EL2, and EL3 of the light-emitting elements ED1, ED2, and ED3 and the common electrodes CE1, CE2, and CE3, respectively.

[0166] Because the embankment structure BNS includes a tip TIP, such trace patterns TRP1, TRP2, and TRP3 may be traces formed when the deposited material is disconnected from the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer CAP within the emission areas EA1, EA2, and EA3 instead of being connected to the light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer CAP within the emission areas EA1, EA2, and EA3. The light-emitting layers EL1, EL2, and EL3, the common electrodes CE1, CE2, and CE3, and the capping layer CAP may be formed within the openings, the organic patterns ELP1, ELP2, and ELP3, and the light-emitting layers EL1, EL2, and EL3 may be disconnected from each other by the tip TIP of the embankment structure BNS, the electrode patterns CEP1, CEP2, and CEP3, and the common electrodes CE1, CE2, and CE3 may be disconnected from each other by the tip TIP of the embankment structure BNS, and the capping pattern CLP and the capping layer CAP may be disconnected from each other by the tip TIP of the embankment structure BNS. The trace patterns TRP1, TRP2, and TRP3 may be formed by performing patterning around the corresponding emission areas EA1, EA2, and EA3 or the openings.

[0167] The display device 10 in the embodiment may include a plurality of organic patterns ELP1, ELP2, and ELP3 including the same material as that of the light-emitting layers EL1, EL2, and EL3 and disposed on the embankment structure BNS. Since the light-emitting layers EL1, EL2, and EL3 are formed by a process of depositing a material on the entire surface of the display device 10, the material forming the light-emitting layers EL1, EL2, and EL3 may be deposited on the embankment structure BNS and in the emission areas EA1, EA2, and EA3.

[0168] In an embodiment, for example, the display device 10 may include organic patterns ELP1, ELP2, and ELP3 disposed above the bank structure BNS. The organic patterns ELP1, ELP2, and ELP3 may include first, second, and third organic patterns ELP1, ELP2, and ELP3 disposed on the second bank layer BN2 of the bank structure BNS.

[0169] The first organic pattern ELP1 may include the same material as that of the first light emitting layer EL1 of the first light emitting element ED1. The second organic pattern ELP2 may include the same material as that of the second light emitting layer EL2 of the second light emitting element ED2, and the third organic pattern ELP3 may include the same material as that of the third light emitting layer EL3 of the third light emitting element ED3. The organic patterns ELP1, ELP2, and ELP3 may be formed in a process of forming light emitting layers EL1, EL2, and EL3 including the same material as that of the organic patterns ELP1, ELP2, and ELP3, respectively. The organic patterns ELP1, ELP2, and ELP3 may be disposed adjacent to emission areas EA1, EA2, and EA3 provided with the corresponding light emitting layers EL1, EL2, and EL3.

[0170] The display device 10 in the embodiment may include a plurality of electrode patterns CEP1, CEP2, and CEP3 including the same material as the common electrodes CE1, CE2, and CE3 and disposed on the embankment structure BNS. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be directly disposed on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship between the electrode patterns CEP1, CEP2, and CEP3 and the organic patterns ELP1, ELP2, and ELP3 may be the same as the arrangement relationship between the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3 and the light emitting layers EL1, EL2, and EL3.

[0171] The display device 10 may include a cap pattern CLP disposed above the embankment structure BNS. The cap pattern CLP may be directly disposed on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 disposed on the second embankment layer BN2 of the embankment structure BNS. The arrangement relationship between the cap pattern CLP and the electrode patterns CEP1, CEP2, and CEP3 may be the same as the arrangement relationship between the cap layer CAP and the common electrodes CE1, CE2, and CE3 of the light emitting elements ED1, ED2, and ED3.

[0172] A plurality of organic patterns ELP1, ELP2 and ELP3, electrode patterns CEP1, CEP2 and CEP3, and a cover pattern CLP may be disposed on the embankment structure BNS and may be disposed to surround the emission areas EA1, EA2 and EA3 or an opening. The stacked structure of the organic patterns ELP1, ELP2 and ELP3, the electrode patterns CEP1, CEP2 and CEP3, and the cover pattern CLP disposed around the emission areas EA1, EA2 and EA3 may be partially etched in a process for manufacturing the display device 10 so that the pattern shape may be changed. Therefore, a portion of the upper surface of the second embankment layer BN2 of the embankment structure BNS may not be covered by the organic patterns ELP1, ELP2 and ELP3, the electrode patterns CEP1, CEP2 and CEP3, and the cover pattern CLP.

[0173] The thin film encapsulation layer TFEL may be disposed on the light emitting elements ED1, ED2, and ED3 and the embankment structure BNS, and may cover the plurality of light emitting elements ED1, ED2, and ED3 and the embankment structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust.

[0174] In an embodiment, the thin film encapsulation layer TFEL may include a first inorganic encapsulation film TFE1 , an organic encapsulation film TFE2 , and a second inorganic encapsulation film TFE3 , which are sequentially stacked.

[0175] Each of the first inorganic encapsulating film TFE1 and the second inorganic encapsulating film TFE3 may include one or more inorganic insulating materials. The inorganic insulating material may be any one of silicon oxide, silicon nitride and silicon oxynitride, and may be, for example, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride.

[0176] The organic encapsulation film TFE2 may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, a polyimide, or polyethylene, etc. In an embodiment, for example, the organic encapsulation film TFE2 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The organic encapsulation film TFE2 may be formed by curing a monomer or coating a polymer.

[0177] The first inorganic encapsulation film TFE1 may be disposed on the light emitting elements ED1, ED2, and ED3, the plurality of patterns ELP1, ELP2, ELP3, CEP1, CEP2, CEP3, and CLP, and the embankment structure BNS. The first inorganic encapsulation film TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3 disposed to correspond to different emission areas EA1, EA2, and EA3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material and cover the light emitting elements ED1, ED2, and ED3, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent the light emitting elements ED1, ED2, and ED3 from being damaged by external air. The first inorganic layer TL1, the second inorganic layer TL2 and the third inorganic layer TL3 can be set to cover the organic patterns ELP1, ELP2 and ELP3, the electrode patterns CEP1, CEP2 and CEP3 and the cover pattern CLP to prevent the patterns ELP1, ELP2, ELP3, CEP1, CEP2, CEP3 and CLP set on the embankment structure BNS from being peeled off during the process for manufacturing the display device 10.

[0178] The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be formed by chemical vapor deposition ("CVD"), and thus may be formed along the steps of the layers on which they are deposited. In an embodiment, for example, the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may form a thin film even under the undercut of the tip TIP of the dam structure BNS.

[0179] The first inorganic layer TL1 may be disposed on the first light emitting element ED1 and the first electrode pattern CEP1. The first inorganic layer TL1 may be disposed along the side surfaces of the first light emitting element ED1, the cap layer CAP, and the second bank layer BN2 adjacent to the first common electrode CE1 so as to cover the first light emitting element ED1, the cap layer CAP, and the side surfaces of the second bank layer BN2 adjacent to the first common electrode CE1, and may also be disposed to cover the first organic pattern ELP1, the first electrode pattern CEP1, and the cap pattern CLP. However, the first inorganic layer TL1 may not overlap with the second opening and the third opening, and may be disposed only on the bank structure BNS in and around the first opening. Figure 6 and Figure 7The diagram shows that the first inorganic layer TL1 seals the first trace pattern TRP1 and the first light emitting element ED1 with uneven thickness along the outer surfaces of the first trace pattern TRP1 and the first light emitting element ED1, but the first inorganic layer TL1 can be set with uniform thickness along the upper surface and side surfaces of the first trace pattern TRP1, the side surface and lower surface of the second bank layer BN2, the side surface of the first bank layer BN1, and the upper surface of the first common electrode CE1.

[0180] The second inorganic layer TL2 may be disposed on the second light emitting element ED2 and the second electrode pattern CEP2. However, the second inorganic layer TL2 may not overlap the first opening and the third opening, and may be disposed only on the bank structure BNS in and around the second opening.

[0181] The third inorganic layer TL3 may be disposed on the third light emitting element ED3 and the third electrode pattern CEP3. However, the third inorganic layer TL3 may not overlap the first and second openings, and may be disposed only on the bank structure BNS in and around the third opening.

[0182] The first inorganic layer TL1 may be formed after forming the first common electrode CE1, the second inorganic layer TL2 may be formed after forming the second common electrode CE2, and the third inorganic layer TL3 may be formed after forming the third common electrode CE3. Therefore, the first to third inorganic layers TL1, TL2, and TL3 may be disposed to cover different electrode patterns CEP1, CEP2, and CEP3 and organic patterns ELP1, ELP2, and ELP3, respectively. Figure 5 In the plan view of , the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may have the same area as the first to third trace patterns TRP1, TRP2, and TRP3, respectively, and may have a larger area than the opening or emission area EA1, EA2, and EA3 of the embankment structure BNS, respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may be spaced apart from each other on the embankment structure BNS. Therefore, a portion of the second embankment layer BN2 may not overlap with the first to third inorganic layers TL1, TL2, and TL3, and in the space between the first to third inorganic layers TL1, TL2, and TL3 spaced apart from each other, a portion of the upper surface of the second embankment layer BN2 may be exposed without being covered by the first to third inorganic layers TL1, TL2, and TL3. The exposed upper surface of the second embankment layer BN2 may be in direct contact with the organic encapsulation film TFE2 of the thin film encapsulation layer TFEL.

[0183] The light shielding layer BM may be disposed on the thin film encapsulation layer TFEL. The light shielding layer BM may define a plurality of holes OPT1, OPT2, and OPT3 that are disposed to overlap with the emission areas EA1, EA2, and EA3, respectively. In an embodiment, for example, the first hole OPT1 may overlap with the first emission area EA1. The second hole OPT2 may overlap with the second emission area EA2, and the third hole OPT3 may overlap with the third emission area EA3. The area or size of each of the holes OPT1, OPT2, and OPT3 may be larger than the area or size of the corresponding emission area in the emission areas EA1, EA2, and EA3. The holes OPT1, OPT2, and OPT3 of the light shielding layer BM are larger than the emission areas EA1, EA2, and EA3, and therefore, the user can view the light emitted from the emission areas EA1, EA2, and EA3 not only from the front surface of the display device 10 but also from the side surface of the display device 10.

[0184] The light shielding layer BM may include a light absorbing material. In an embodiment, for example, the light shielding layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the present disclosure is not limited thereto. The light shielding layer BM may prevent color mixing caused by visible light passing through the first to third emission areas EA1, EA2, and EA3 to improve the color gamut of the display device 10.

[0185] The display device 10 may include a plurality of color filters CF1, CF2, and CF3 disposed in the emission areas EA1, EA2, and EA3. The plurality of color filters CF1, CF2, and CF3 may be disposed to correspond to the emission areas EA1, EA2, and EA3, respectively. In an embodiment, for example, the color filters CF1, CF2, and CF3 may be disposed on a light shielding layer BM defining a plurality of holes OPT1, OPT2, and OPT3 disposed to correspond to the emission areas EA1, EA2, and EA3. The holes OPT1, OPT2, and OPT3 of the light shielding layer BM may overlap with the emission areas EA1, EA2, and EA3 or the opening of the embankment structure BNS, and may define a light emitting area through which light emitted from the emission areas EA1, EA2, and EA3 is emitted. Each of the color filters CF1, CF2, and CF3 may have a larger area than the corresponding holes in the holes OPT1, OPT2, and OPT3 of the light shielding layer BM, and may completely cover the light emitting area formed by the corresponding holes in the holes OPT1, OPT2, and OPT3.

[0186] The color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3 that are respectively arranged to correspond to different emission areas EA1, EA2, and EA3. The color filters CF1, CF2, and CF3 may include a colorant such as a dye or a pigment that absorbs light of a wavelength band other than a predetermined wavelength band, and may be arranged to correspond to the color of the light emitted from the emission areas EA1, EA2, and EA3. In an embodiment, for example, the first color filter CF1 may be a red color filter that is arranged to overlap with the first emission area EA1 and transmits only the first light that is red light. The second color filter CF2 may be a green color filter that is arranged to overlap with the second emission area EA2 and transmits only the second light that is green light, and the third color filter CF3 may be a blue color filter that is arranged to overlap with the third emission area EA3 and transmits only the third light that is blue light.

[0187] A plurality of color filters CF1, CF2, and CF3 may be spaced apart from adjacent color filters CF1, CF2, and CF3 on the light shielding layer BM. The color filters CF1, CF2, and CF3 may have a larger area than the holes OPT1, OPT2, and OPT3 of the light shielding layer BM, while covering the holes OPT1, OPT2, and OPT3 of the light shielding layer BM, respectively, but may have an area sufficient to be spaced apart from adjacent color filters CF1, CF2, and CF3 on the light shielding layer BM. However, the present disclosure is not limited thereto. A plurality of color filters CF1, CF2, and CF3 may be arranged to partially overlap adjacent color filters CF1, CF2, and CF3. Different color filters CF1, CF2, and CF3 may overlap each other on the light shielding layer BM in an area not overlapping with the emission areas EA1, EA2, and EA3 to be described later. In the display device 10, the color filters CF1, CF2, and CF3 are arranged to overlap each other, and therefore, the intensity of the reflected light of the external light may be reduced. Furthermore, the color perception of the reflected light of the external light may be controlled by adjusting the arrangement, shape, or area of ​​the color filters CF1 , CF2 , and CF3 in a plan view, and the like.

[0188] An overcoat layer OC may be disposed on the color filters CF1, CF2, and CF3 to flatten the upper ends of the color filters CF1, CF2, and CF3. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. In an embodiment, for example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0189] Hereinafter, a process for manufacturing the display device 10 in the embodiment will be described with reference to other drawings.

[0190] Fig. 9 is a flow chart illustrating an embodiment of a process for manufacturing a display device, and Figures 10 to 18are detailed cross-sectional views sequentially illustrating an embodiment of a process for manufacturing a display device.

[0191] exist Figures 9 to 17 , a process of forming a dam structure BNS and a light emitting element ED (e.g., a first light emitting element ED1) as a light emitting element layer EML of a display device 10 and a thin film encapsulation layer TFEL is schematically illustrated. Hereinafter, a description of a process of forming each layer among the processes for manufacturing the display device 10 will be omitted, and an order of forming each layer will be described.

[0192] refer to Fig.10 , a plurality of pixel electrodes AE1 , AE2 , and AE3 , a pixel defining material layer PDLL, and a plurality of bank material layers BNL1 and BNL2 , which are spaced apart from each other, are formed on the thin film transistor layer TFTL.

[0193] Despite Fig.10 Although not shown in the figure, the thin film transistor layer TFTL may be disposed on the substrate SUB, and the structure of the thin film transistor TFTL is the same as that of the above reference Figure 6 The structures described are the same. A detailed description thereof will be omitted.

[0194] A plurality of pixel electrodes AE1, AE2, and AE3 spaced apart from each other are formed by integrally forming a pixel electrode material on the substrate SUB and then patterning the pixel electrode material (operation S10). When the pixel electrodes are formed on the substrate SUB, a sputtering process may be used.

[0195] The pixel electrodes AE1, AE2, and AE3 may have a multi-layer structure as described above. In an embodiment, the upper transparent electrode layer 630 and the lower transparent electrode layer 610 may include ITO.

[0196] In the case where the upper transparent electrode layer 630 is formed by a sputtering process under an atmosphere of a mixed gas including hydrogen and argon, the thickness of the electrode can be increased while maintaining the amorphous characteristics, compared with the case where the upper transparent electrode layer 630 is formed only under an atmosphere of argon. The thickness of the amorphous transparent electrode layer formed only under an atmosphere of argon can be about Below, but the thickness of the amorphous transparent electrode layer formed in the atmosphere of a mixed gas including hydrogen and argon may be about To about In an embodiment, the mixed gas may include hydrogen gas at a concentration of about 0.1% to about 5.0%.

[0197] Fig.11 The cross section of the first pixel electrode AE1 among the plurality of pixel electrodes AE1, AE2 and AE3 formed is shown, and Fig.11The portion of the first pixel electrode AE1 that penetrates the second passivation layer PAS2 and is connected to the second connection electrode CNE2 is omitted. Fig.11 , it can be seen that the upper transparent electrode layer 630 has a constant thickness t3 and has a flat upper surface.

[0198] The pixel defining material layer PDLL and the bank material layers BNL1 and BNL2 may be disposed on the pixel electrodes AE1, AE2, and AE3 (operation S20). The pixel defining material layer PDLL may be disposed to cover the entire thin film transistor layer TFTL, and the first bank material layer BNL1 and the second bank material layer BNL2 may be disposed to cover the entire pixel defining material layer PDLL. The bank material layers BNL1 and BNL2 may be partially etched in a subsequent process to form Figure 6 The bank layers BN1 and BN2 of the bank structure BNS are shown in FIG.

[0199] Next, refer to Fig.12 , a photoresist PR is formed on the bank material layers BNL1 and BNL2, and a first etching process (first etching) is performed using the photoresist PR as a mask to etch a portion of the first bank material layer BNL1 and a portion of the second bank material layer BNL2 and a portion of the pixel defining material layer PDLL to define a hole HOL. The hole HOL may be defined in a region overlapping with the plurality of pixel electrodes AE1, AE2, and AE3, and may define an opening of the bank structure BNS.

[0200] The photoresists PR may be spaced apart from each other on the bank material layers BNL1 and BNL2. The photoresist PR may be disposed on the second bank material layer BNL2 to expose a portion overlapping the first pixel electrode AE1.

[0201] In an embodiment, dry etching may be performed as a first etching process (first etching). The bank material layers BNL1 and BNL2 and the pixel defining material layer PDLL may be anisotropically etched, but due to the difference between the materials of the bank material layers BNL1 and BNL2 and the material of the pixel defining material layer PDLL, the etching area of ​​the pixel defining material layer PDLL may be smaller than the etching area of ​​the bank material layers BNL1 and BNL2. In this process, a portion of the upper surface of the pixel electrodes AE1, AE2, and AE3 may be exposed (operation S30). The upper surface of the first pixel electrode AE1 that is not covered by the pixel defining material layer PDLL is exposed to plasma, so that the work function is reduced and the hole injection capability is degraded.

[0202] Next, refer to Fig.13, a portion of the upper portion of the first pixel electrode AE1 is etched by a second etching process (second etching), and an undercut structure of the first bank material layer BNL1 is formed at the same time (operation S40). When a separate protective layer is provided on the pixel electrodes AE1, AE2, and AE3, an etching process for the undercut structure of the first bank material layer BNL1 and an etching process for removing the separate protective layer should be performed separately. When the amorphous transparent metal layer including hydrogen is formed thick, the formation of the undercut structure of the first bank material layer BNL1 and the removal of a portion of the thickness of the first pixel electrode AE1 can be performed simultaneously by one etching process. Therefore, the process can be simplified without a separate protective layer.

[0203] In an embodiment, the second etching process may be an isotropic wet etch.

[0204] The first bank material layer BNL1 may have a faster etching rate than the second bank material layer BNL2, and a side surface of the second bank material layer BNL2 may be formed to protrude more than a side surface of the first bank material layer BNL1. A side surface of the second bank material layer BNL2 protrudes toward the hole HOL more than a side surface of the first bank material layer BNL1 to form a tip TIP, and an undercut may be formed under the tip TIP.

[0205] The first pixel electrode AE1 in the region damaged in the first etching process may be removed in the second etching process. The first pixel electrode AE1 may be removed by a thickness corresponding to a difference (t32) between a thickness (t1+t2+t3) of an edge portion 601 of each of the pixel electrodes AE1, AE2, and AE3 and a thickness (t1+t2+t31) of the main portion 602. The first pixel electrode AE1 may also be etched in a partial region under the protruding portion PDL_P of the pixel defining film PDL by isotropic wet etching. Fig.14 is a cross section of the first pixel electrode AE1 after the second etching process, and an edge portion 601 of the first pixel electrode AE1 has a greater thickness than a main portion 602 of the first pixel electrode AE1. A width d1 of the edge portion 601 may be smaller than a width d2 of the protruding portion PDL_P of the pixel defining film PDL.

[0206] Then, if Fig.15 As illustrated in FIG. 5 , the photoresist PR formed on the second bank material layer BNL2 is removed, and the exposed first pixel electrode AE1 is heat-treated (operation S50 ).

[0207] The amorphous first pixel electrode AE1 manufactured under the mixed gas including hydrogen may include hydrogen therein, and then may be crystallized by removing the hydrogen included therein through a heat treatment process. After the heat treatment process, the transmittance of the transparent electrode layer may be increased, and the predetermined resistance of the transparent electrode layer may be reduced. In an embodiment, the heat treatment process may be performed at about 260 degrees Celsius (° C.) or less within about 2 hours.

[0208] Next, refer to Fig.16 , the first light emitting layer EL1, the first common electrode CE1 and the capping layer CAP are deposited on the first pixel electrode AE1 to form the first light emitting element ED1. In this case, since the first light emitting layer EL1, the first common electrode CE1 and the capping layer CAP are formed on the entire surface of the bank structure BNS, the first light emitting layer EL1, the first common electrode CE1 and the capping layer CAP are formed in the opening overlapping the first pixel electrode AE1. The material forming the first light emitting layer EL1, the first common electrode CE1 and the capping layer CAP may also be formed on the second bank material layer BNL2 to form a trace pattern.

[0209] The first light emitting layer EL1 and the first common electrode CE1 may be formed by a deposition process. Due to the tip TIP of the second bank material layer BNL2, the material may not be smoothly deposited in the first opening. However, the material of the first light emitting layer EL1 and the first common electrode CE1 is deposited in a direction inclined to the upper surface of the substrate SUB rather than in a direction perpendicular to the upper surface of the substrate SUB, and thus may be deposited even in an area blocked by the tip TIP of the second bank material layer BNL2.

[0210] The deposition process (operation S70) of forming the common electrodes CE1, CE2, and CE3 may be performed in an inclined direction relatively closer to the horizontal direction than the deposition process (operation S60) of forming the light emitting layers EL1, EL2, and EL3. Therefore, the common electrodes CE1, CE2, and CE3 may contact the side surface of the first bank material layer BNL1 with a larger area than the light emitting layers EL1, EL2, and EL3. In an alternative embodiment, the common electrodes CE1, CE2, and CE3 may be deposited at a higher position on the side surface of the first bank material layer BNL1 than the light emitting layers EL1, EL2, and EL3. Different common electrodes CE1, CE2, and CE3 may contact the first bank material layer BNL1 having a relatively high conductivity to be electrically connected to each other. In an embodiment, an organic pattern material layer forming organic patterns ELP1, ELP2 and ELP3 may be formed together with light emitting layers EL1, EL2 and EL3, and an electrode pattern material layer forming electrode patterns CEP1, CEP2 and CEP3 may be formed together with common electrodes CE1, CE2 and CE3, but the present disclosure is not limited thereto.

[0211] Subsequently, a first inorganic material layer TLL1 is formed to cover the first light emitting element ED1 and the cap layer CAP (operation S80). The first inorganic material layer TLL1 may be formed to completely cover the first light emitting element ED1, the bank material layers BNL1 and BNL2, the cap layer CAP, and the outer surface of the trace pattern. Specifically, the first inorganic material layer TLL1 is formed on the upper surface of the first common electrode CE1, the side surface of the first bank material layer BNL1, the lower surface and the side surface of the second bank material layer BNL2, and the upper surface and the side surface of the trace pattern.

[0212] Next, refer to Fig.17 , a photoresist PR of a mask pattern is formed on the first inorganic material layer TLL1, and a third etching process (third etching) of removing the first inorganic material layer TLL1 and the trace pattern (e.g., the organic pattern material layer and the electrode pattern material layer) not covered by the mask pattern is performed (operation S90) to form the first inorganic layer TL1. In this case, the photoresist PR may be disposed to overlap the first emission region EA1 and an edge region surrounding the first emission region EA1.

[0213] Then, similarly execute Figures 12 to 17 The process shown in the figure is as follows Fig.18 As shown in the figure, a second light-emitting layer EL2, a second common electrode CE2 and a cover layer CAP are formed on the second pixel electrode AE2, a second trace pattern TRP2 is formed around the second light-emitting layer EL2, the second common electrode CE2 and the cover layer CAP, and a second inorganic layer TL2 is formed covering the second light-emitting element ED2 and the second trace pattern TRP2.

[0214] Subsequently, although not shown in the drawings, the display device 10 forms an organic encapsulation film TFE2 and a second inorganic encapsulation film TFE3 of a thin film encapsulation layer TFEL, a light shielding layer BM, a color filter layer CFL, and an overcoat layer OC (see FIG. 1 ) on the light emitting elements ED1, ED2, and ED3 and the bank structure BNS. Figure 6 The structures of the thin film encapsulation layer TFEL, the light shielding layer BM, the color filter layer CFL, and the overcoat layer OC are the same as those described above, and thus a detailed description thereof will be omitted.

[0215] The embodiments of the present disclosure are described above with reference to the accompanying drawings, but those skilled in the art will appreciate that various modifications and changes may be made without departing from the technical spirit or basic features of the present disclosure. Therefore, it will be understood that the embodiments described above are illustrative rather than restrictive in all features.

Claims

1. A display device, comprising: A first pixel electrode is disposed on the substrate and includes a main portion and an edge portion surrounding the main portion; a pixel defining film, disposed on the substrate, including a main body portion and a protruding portion protruding from the main body portion, and exposing the first pixel electrode; A first light-emitting layer is disposed on the first pixel electrode; A first common electrode, disposed on the first light-emitting layer; A first bank layer is disposed on the pixel definition film; as well as a second bank layer disposed on the first bank layer and including a side surface protruding from a side surface of the first bank layer, wherein the thickness of the edge portion of the first pixel electrode is greater than the thickness of the main portion of the first pixel electrode, and A width of the protruding portion of the pixel defining film is greater than a width of the edge portion of the first pixel electrode.

2. The display device according to claim 1, wherein: A difference between the thickness of the edge portion of the first pixel electrode and the thickness of the main portion of the first pixel electrode is 150 angstroms to 300 angstroms.

3. The display device according to claim 1, wherein: The first pixel electrode includes a lower transparent electrode layer disposed on the substrate, a metal electrode layer disposed on the lower transparent electrode layer, and an upper transparent electrode layer disposed on the metal electrode layer, and The edge portion of the upper transparent electrode layer has a thickness greater than a thickness of the main portion of the upper transparent electrode layer.

4. The display device according to claim 3, wherein: The thickness of the edge portion of the upper transparent electrode layer is 400 angstroms to 700 angstroms, and The thickness of the main portion of the upper transparent electrode layer is 100 angstroms to 500 angstroms.

5. The display device according to claim 3, wherein: The thickness of the lower transparent electrode layer is 30 angstroms to 100 angstroms, and The thickness of the metal electrode layer is 700 angstroms to 1000 angstroms.

6. The display device according to claim 1, wherein: A lower surface of the protruding portion of the pixel defining film contacts the edge portion of the first pixel electrode and the first light emitting layer.

7. The display device according to claim 1, wherein: A width by which a side surface of the protruding portion of the pixel defining film protrudes from a side surface of the first bank layer is greater than a width by which a side surface of the second bank layer protrudes from a side surface of the first bank layer.

8. The display device according to claim 1, wherein: The first common electrode contacts the first bank layer.

9. The display device according to any one of claims 1 to 8, further comprising: A first inorganic layer is disposed on an upper surface of the first common electrode, the side surface of the first bank layer, and a lower surface, an upper surface, and the side surface of the second bank layer.

10. The display device according to claim 9, further comprising: a second pixel electrode spaced apart from the first pixel electrode on the substrate and comprising a main portion and an edge portion surrounding the main portion; A second light emitting layer is disposed on the second pixel electrode; a second common electrode, disposed on the second light emitting layer and spaced apart from the first common electrode; as well as a second inorganic layer disposed on an upper surface of the second common electrode, the side surface of the first bank layer, and the lower surface, the upper surface, and the side surface of the second bank layer; The pixel defining film further exposes the second pixel electrode. The first inorganic layer and the second inorganic layer are spaced apart from each other, and A portion of the second bank layer is exposed in a space between the first inorganic layer and the second inorganic layer which are spaced apart from each other.

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