Display substrate and display panel

Abstract

The embodiment of the utility model provides a display substrate and a display panel, relates to the technical field of display, and is used for improving the efficiency of the display panel. The light-emitting device comprises a substrate, an insulating film group, a reflecting layer, a pixel defining layer and a plurality of first grooves. The insulating film group comprises a first passivation layer and a plurality of flat layers which are stacked; the surface, away from the substrate, of the insulating film set comprises a plurality of first grooves arranged in the first direction. The reflecting layer covers the side wall and the bottom wall of the first groove. The pixel defining layer is located on the side, away from the insulating film set, of the reflecting layer and comprises a plurality of pixel openings. Each of the plurality of first grooves surrounds one of the pixel openings. The first groove penetrates from the pixel defining layer to the first flat layer. Wherein the first passivation layer comprises a first pattern, the part, extending out of the side wall of the first groove, of the first pattern is close to the surface of the substrate, and a gap is formed between the part and the bottom of the first groove. The display substrate is used for the display device.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display panel. Background Art

[0002] OLED (Organic Light Emitting Diode) display panels are widely used in display screens such as mobile phones, tablets, and car displays due to their advantages such as full solid state, fast response speed, and wide operating temperature range. Summary of the invention

[0003] An object of the embodiments of the present disclosure is to provide a display substrate and a display panel, so as to improve the efficiency of the display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display substrate is provided. The display substrate includes a substrate, an insulating film group, a reflective layer, a pixel defining layer, and a plurality of first grooves. The insulating film group is located on one side of the substrate and includes a first passivation layer and a multi-layer flat layer that are stacked; the multi-layer flat layer includes a first flat layer; the first passivation layer is located on a side of the first flat layer away from the substrate and in contact with the first flat layer; the surface of the insulating film group away from the substrate includes a plurality of first grooves arranged along a first direction; the first direction intersects with the stacking direction of the multi-layer flat layer. The reflective layer is located on a side of the insulating film group away from the substrate and covers the sidewalls and bottom walls of the first grooves. The pixel defining layer is located on a side of the reflective layer away from the insulating film group and includes a plurality of pixel openings; each of the plurality of first grooves surrounds a pixel opening. The first groove runs from the pixel defining layer to the first flat layer and is located between two adjacent first grooves in the plurality of first grooves. The first passivation layer includes a first pattern, the first pattern includes a portion extending from the sidewall of the first groove, the portion of the first pattern extending from the sidewall of the first groove is close to the surface of the substrate, and there is a gap between the portion and the bottom of the first groove.

[0006] It can be understood that when the reflective layer covers the side wall and the bottom wall of the first groove, the portion of the reflective layer covering the side wall and the bottom wall of the first groove can continue the concave morphology of the multiple first grooves, so that the reflective layer can include multiple reflective cup structures. Moreover, when each first groove surrounds a pixel opening, the reflective cup structure can surround the pixel opening, so that the light emitted from the side of the light emitting device can be reflected on the surface of the reflective cup structure and emitted from the pixel opening after reflection. In this way, the light extraction efficiency of the light emitting device can be improved, so that the light emitting efficiency of the display panel can be improved.

[0007] Moreover, when the first groove penetrates from the pixel defining layer to the first flat layer, a common film layer (for example, an electron generating layer, and / or a hole generating layer) of multiple light-emitting devices will be formed in the first groove. Moreover, when the first groove is located between two adjacent first grooves, and the portion of the first pattern extending from the side wall of the first groove is close to the surface of the substrate and has a gap with the bottom of the first groove, when a common film layer is formed at the first groove, the common film layer formed on the portion of the first pattern extending from the side wall of the first groove is disconnected from the common film layer formed in the first groove. In this way, the transmission of lateral current between adjacent light-emitting devices can be reduced, and color crosstalk can be avoided. In this way, the light-emitting devices included in the display panel can be series-connected light-emitting devices, so that the luminous efficiency and life of the display panel are improved, and the power consumption of the display panel is reduced.

[0008] In some embodiments, the first planar layer includes the second pattern. The sidewall of the first groove includes a surface of the first pattern; or the sidewall of the first groove includes a surface of the first pattern and a surface of the second pattern.

[0009] In some embodiments, the first passivation layer includes a plurality of first openings arranged along a first direction, and the first openings constitute at least a portion of the first groove.

[0010] In some embodiments, when the first opening forms a first groove, a size of the first passivation layer along the second direction ranges from 0.5 μm to 1.5 μm, and the second direction is a stacking direction of the multiple planar layers.

[0011] In some embodiments, when the first opening constitutes a part of the first groove, the first flat layer includes a plurality of first sub-grooves correspondingly connected to the plurality of first openings, and the first sub-grooves constitute the rest of the first groove except the first openings. Alternatively, the first flat layer includes a plurality of second openings correspondingly connected to the plurality of first openings, and the second openings constitute the rest of the first groove except the first openings. The bottom surface of the first groove is closer to the substrate than the bottom surface of the first groove.

[0012] In some embodiments, when the first planar layer includes a plurality of first sub-grooves, a size of the first planar layer along the second direction ranges from 1.5 μm to 3.0 μm, and the second direction is a stacking direction of the plurality of planar layers.

[0013] In some embodiments, the first planar layer further includes a plurality of third openings arranged along the first direction, and the first pattern and the reflective layer are sequentially layered on the side walls and bottom walls of the third openings.

[0014] In some embodiments, the pixel defining layer further includes a first portion located on a side of the first passivation layer close to the substrate; a surface of the first portion close to the substrate is flush with a bottom surface of the first groove; and an edge portion of the first portion overlaps an edge portion of the first passivation layer.

[0015] In some embodiments, the insulating film group further includes a second flat layer located on a side of the first flat layer away from the first passivation layer; the display substrate further includes a first source-drain metal layer located on a side of the second flat layer away from the first flat layer.

[0016] In some embodiments, the display substrate further includes a third flat layer. The third flat layer is disposed on a side of the first passivation layer away from the first flat layer and includes a plurality of fourth openings arranged along the first direction; the plurality of fourth openings are reused as a plurality of first grooves.

[0017] In some embodiments, the insulating film group further includes a second flat layer, and the display substrate further includes a first source-drain metal layer. The second flat layer and the first source-drain metal layer are located between the first flat layer and the third flat layer; the second flat layer is farther away from the substrate than the first source-drain metal layer. The surface of the first source-drain metal layer close to the substrate is closer to the substrate than the surface of the first passivation layer close to the substrate. The second flat layer further includes a second portion located on a side of the first passivation layer close to the substrate; an edge portion of the second portion overlaps an edge portion of the first passivation layer.

[0018] In some embodiments, the display substrate further comprises a first source-drain metal layer. The first source-drain metal layer is located on a side of the first flat layer close to the substrate; the first source-drain metal layer is away from the surface of the substrate and closer to the substrate than the surface of the first groove close to the substrate.

[0019] In some embodiments, the orthographic projection of the first passivation layer on the substrate does not overlap with the orthographic projection of the reflective layer on the substrate; the surface of the portion of the reflective layer covering the bottom wall of the first groove close to the substrate is closer to the substrate than the surface of the first passivation layer close to the substrate.

[0020] In some embodiments, the reflective layer contacts the first passivation layer. The third planar layer further includes a third portion located on a side of the first passivation layer close to the substrate; an edge portion of the third portion overlaps an edge portion of the first passivation layer.

[0021] In some embodiments, the pixel defining layer includes a fourth portion located on a side of the first passivation layer close to the substrate, and a side surface of the fourth portion constitutes a portion of a sidewall of the first trench.

[0022] In some embodiments, the portion of the first pattern extending from the sidewall of the first groove is away from the surface of the substrate, and has a first distance along the second direction from the bottom surface of the first groove. The surface of the insulating film group away from the substrate has a second distance along the second direction from the bottom surface of the first groove. The first distance is less than or equal to the second distance; and the second direction is the stacking direction of the multiple planar layers.

[0023] In another aspect, a display panel is provided, wherein the display panel comprises a plurality of light emitting devices and a display substrate as described in any one of the above embodiments, wherein the light emitting device is located in a pixel opening.

[0024] In some embodiments, the light-emitting device includes at least two light-emitting layers and a charge generating unit located between two adjacent light-emitting layers. The charge generating units of the multiple light-emitting devices are of the same layer and material and constitute a common unit. The common unit includes a fifth portion and a sixth portion. The fifth portion is located at a portion of the first pattern extending from the sidewall of the first groove, on one side along the second direction. The sixth portion is located in the first groove and on one side of the first pattern along the second direction; the second direction is the stacking direction of the multiple planar layers. There is a spacing between the fifth portion and the sixth portion along the second direction.

[0025] The beneficial effects that can be achieved by the method for preparing the display panel are the same as the beneficial effects that can be achieved by the display substrate, and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0027] Figure 1A is a structural diagram of a display panel according to some embodiments;

[0028] Figure 1B for Figure 1A A partial enlarged view of the M in the middle;

[0029] Figure 1C is a focused ion beam-transmission electron microscope image of a display panel according to some embodiments;

[0030] Figure 2 is a structural diagram of a display panel according to some further embodiments;

[0031] Figure 3is a structural diagram of a display substrate according to some embodiments;

[0032] Figure 4 is a structural diagram of a display substrate according to some further embodiments;

[0033] Figure 5 is a structural diagram of a display substrate according to some further embodiments;

[0034] Figure 6 is a structural diagram of a display substrate according to some further embodiments;

[0035] Figure 7 is a structural diagram of a display substrate according to some further embodiments;

[0036] Figure 8 is a structural diagram of a display substrate according to some further embodiments;

[0037] Fig. 9 is a structural diagram of a display substrate according to some further embodiments;

[0038] Fig.10 is a flow chart of preparing a display substrate according to some embodiments;

[0039] Fig.11A is a step diagram of a method for preparing a display substrate according to some embodiments;

[0040] Fig. 11B are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0041] Fig. 11C are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0042] Fig.11D are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0043] Fig.11E are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0044] Fig.11F are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0045] Fig.11G are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0046] Fig.11H are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0047] Fig. 12A are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0048] Fig. 12B are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0049] Fig. 12C are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0050] Fig.12D are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0051] Fig.13A are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0052] Fig. 13B are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0053] Fig. 13C are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0054] Fig.13D are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0055] Fig.13E are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0056] Fig.13F are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0057] Figure 13G are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0058] Fig.14A are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0059] Fig. 14B are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0060] Fig. 14C are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0061] Fig.14D are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0062] Fig.14E are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0063] Fig.14Fare step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0064] Fig.15A are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0065] Fig. 15B are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0066] Fig. 15C are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0067] Fig.15D are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0068] Fig.15E are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0069] Fig.15F are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0070] Figure 15G are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0071] Fig.16A are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0072] Fig. 16B are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0073] Fig. 16C are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0074] Fig.16D are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0075] Fig.16E are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0076] Fig.17A are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0077] Fig. 17B are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0078] Fig. 17C are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0079] Fig.17D are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0080] Fig.17E are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0081] Fig.17F are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0082] Figure 17G are step diagrams of a method for preparing a display substrate according to yet other embodiments;

[0083] Fig.18 is a structural diagram of a display panel according to some further embodiments. DETAILED DESCRIPTION

[0084] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0085] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0086] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0087] When describing some embodiments, the expression "connection" and its derivatives may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0088] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0089] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0090] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0091] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0092] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0093] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0094] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0095] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0096] It should be noted that, for example, 11-1 in the drawings of the present disclosure indicates that component 11 belongs to component 1, for example, Figure 4 111-110 indicates that the substrate 111 belongs to the base 110, and other similar reference numerals in the drawings also follow the above description. For example, 1 / 2 in the drawings of the present disclosure indicates that structure 1 and structure 2 can refer to the structure, for example, Figure 3 The 121a / 121 in the figure indicates that both the first pattern 121a and the first passivation layer 121 can be represented by this structure. Other similar reference numerals appearing in the drawings also follow the above description.

[0097] like Figure 1A As shown, some embodiments of the present disclosure provide a display panel 200 , which includes a plurality of light emitting devices 210 and a display substrate 100 .

[0098] The display panel 200 may be, for example, an OLED (Organic Light Emitting Diode) display panel 200 .

[0099] The display panel 200 described above can be any display panel that displays either motion (e.g., video) or fixed (e.g., still images) and whether text or images. More specifically, it is expected that the display panel 200 of the embodiment described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0100] In some examples, such as Figure 1A As shown, the display panel 200 further includes an encapsulation layer 220 located on a side of the plurality of light emitting devices 210 away from the display substrate 100 .

[0101] In some examples, the encapsulation layer 220 includes a first sublayer 221, a second sublayer 222, and a third sublayer 223 arranged in sequence in a direction away from the plurality of light emitting devices 210. The materials of the first sublayer 221 and the third sublayer 223 are, for example, inorganic materials; the material of the second sublayer 222 is, for example, organic materials.

[0102] By such arrangement, the encapsulation layer 220 can cover the light emitting device 210 and encapsulate the light emitting device 210 to prevent moisture and oxygen in the external environment from entering the light emitting device 210 and damaging the organic material in the light emitting device 210 to shorten the life of the display panel 200 .

[0103] Exemplarily, the plurality of light emitting devices 210 may be arranged along a first direction X, and the first direction X intersects with a thickness direction of the display substrate 100. For example, the first direction X is perpendicular to the thickness direction of the display substrate 100.

[0104] In some examples, such as Figure 2As shown, the plurality of light emitting devices 210 include a first light emitting device 210A for emitting a first color light, a second light emitting device 210B for emitting a second color light, and a third light emitting device 210C for emitting a third color light. In this way, the brightness (gray scale) of the first light emitting device 210A, the second light emitting device 210B, and the third light emitting device 210C can be adjusted respectively, and a plurality of colors can be displayed by color combination and superposition, thereby realizing full-color display of the display panel 200. Exemplarily, the first color light is blue light; the second color light is green light; and the third color light is red light.

[0105] In some examples, the plurality of light emitting devices 210 further include a fourth light emitting device (not shown) for emitting white light.

[0106] It should be noted that Figure 2 It is a simplified schematic diagram obtained after removing all film layers in the display panel 200 except the film layers related to the light emitting device 210.

[0107] In some embodiments, Figure 1A and Figure 2 As shown, the light emitting device 210 includes an anode 211 and a cathode 212 disposed opposite to each other along the thickness direction of the display substrate 100, and a plurality of light emitting functional layers disposed between the anode 211 and the cathode 212, and the plurality of light emitting functional layers are arranged along the thickness direction of the display substrate 100. The plurality of light emitting functional layers include at least one light emitting layer 213.

[0108] In some examples, such as Figure 1A As shown, the anode 211 may be located on a side of the plurality of light-emitting functional layers close to the display substrate 100, and the cathode 212 may be located on a side of the plurality of light-emitting functional layers away from the display substrate 100. In other examples, the anode 211 may be located on a side of the plurality of light-emitting functional layers away from the display substrate 100, and the cathode 212 may be located on a side of the plurality of light-emitting functional layers close to the display substrate 100.

[0109] In some examples, the light emitting device 210 includes a light emitting layer 213. In this case, the light emitting device 210 is a single-layer light emitting device (a single light emitting device, such as a single OLED light emitting device). Figure 1A and Figure 2 As shown, the light emitting device 210 includes a plurality of (for example, two) light emitting layers 213 arranged along the thickness direction of the display substrate 100. At this time, the light emitting device 210 is a tandem light emitting device (Tandem light emitting device, for example, a Tandem OLED light emitting device). The tandem light emitting device has the advantages of longer life, lower power consumption, and higher efficiency.

[0110] In some embodiments, Figure 1A and Figure 2 As shown, in the case where the light emitting device 210 includes a plurality of light emitting layers 213 , the plurality of light emitting functional layers further include a charge generating unit 214 , and the charge generating unit 214 is located between two adjacent light emitting layers 213 .

[0111] In some examples, such as Figure 2 As shown, the charge generating unit 214 includes a stacked electron generating layer 2141 (also referred to as N-CGL) and a hole generating layer 2142 (also referred to as P-CGL); the electron generating layer 2141 is closer to the anode 211 than the hole generating layer 2142 .

[0112] In some embodiments, Figure 1A and Figure 2 As shown, in order to improve the luminous efficiency of the light-emitting device 210, the multiple light-emitting functional layers also include a hole transport functional layer 215 located on the side of the light-emitting layer 213 close to the anode 211, and / or, an electron transport functional layer 216 located on the side of the light-emitting layer 213 close to the cathode 212. The hole transport functional layer 215, for example, includes at least one of a stacked hole injection layer 2151 (Hole Inject Layer, HIL), a hole transport layer 2152 (Hole Transport Layer, HTL) and an electron blocking layer 2153 (Electron Blocking Layer, EBL). The electron transport functional layer 216, for example, includes at least one of a stacked electron injection layer 2161 (Electron Inject Layer, EIL), an electron transport layer 2162 (Electron Transport Layer, ETL), and a hole blocking layer 2163 (Hole Blocking Layer, EBL).

[0113] In some embodiments, Figure 1A As shown, the cathode 212 of the multiple light-emitting devices 210 can be a structure in which the entire layer is connected, that is, the cathode 212 can be a common electrode shared by the multiple light-emitting devices 210. The electron generation layer 2141 of the multiple light-emitting devices 210 can also be a structure in which the entire layer is connected, that is, the electron generation layer 2141 can be a common film layer shared by the multiple light-emitting devices 210. The hole injection layer 2151, the hole transport layer 2152, the electron blocking layer 2153, the electron injection layer 2161, the electron transport layer 2162, the hole blocking layer 2163, and the hole generation layer 2142 can also be a common film layer shared by the multiple light-emitting devices 210, which will not be described in detail here.

[0114] As mentioned in the background, in the field of organic semiconductors, OLED light-emitting devices have the advantages of self-luminescence, large viewing angle, large contrast, fast response speed, wide operating temperature range, and can be prepared into flexible products. Moreover, compared with liquid crystal displays (LCD), OLED display panels containing OLED light-emitting devices also have the advantages of not requiring a backlight source, thin panel thickness, and light weight.

[0115] With the increasing demand for long-life, low-power products such as AUTO (car module), notebook (NB) & foldable (foldable) panels, Single OLED display panels cannot meet the demand. Therefore, in order to meet the demand for long-life, low-power products, Tandem OLED display panels need to be applied to the above products.

[0116] In some implementations, the electron generation layer and the hole generation layer in the Tandem OLED light-emitting device are common film layers. Due to the high doping concentration, lateral leakage is easily generated, resulting in color crosstalk when a single sub-pixel is lit, and adjacent sub-pixels are also lit. This makes the color purity of the light emitted by the Tandem OLED light-emitting device poor, and the display effect is poor, which limits the application of the Tandem OLED light-emitting device.

[0117] In some other implementations, the light emitted by the light-emitting device includes a portion emitted from the front of the light-emitting device and a portion emitted from the side of the light-emitting device, wherein the light emitted from the front of the light-emitting device will be emitted from the sub-pixel area to form effective emitted light, while the portion emitted from the side of the light-emitting device may not be able to emit light from the sub-pixel area, resulting in low light output efficiency of the display panel.

[0118] Based on this, some embodiments of the present disclosure provide a display substrate 100 to solve one or more of the above problems. Figure 3 to Figure 9 As shown, the display substrate 100 includes a base 110 , an insulating film group 120 , a reflective layer 130 , a pixel defining layer 140 and a plurality of first grooves 150 .

[0119] The insulating film group 120 is located on one side of the substrate 110 and includes a first passivation layer 121 and a multi-layer flat layer 122 which are stacked; the multi-layer flat layer 122 includes a first flat layer 122A; the first passivation layer 121 is located on a side of the first flat layer 122A away from the substrate 110 and contacts the first flat layer 122A; the surface of the insulating film group 120 away from the substrate 110 includes a plurality of first grooves 160 arranged along a first direction X; the first direction X intersects with the stacking direction of the multi-layer flat layer 122.

[0120] The reflective layer 130 is located on a side of the insulating film group 120 away from the substrate 110 and covers the sidewalls and bottom wall of the first groove 160. The pixel defining layer 140 is located on a side of the reflective layer 130 away from the insulating film group 120 and includes a plurality of pixel openings Q1; each of the plurality of first grooves 160 surrounds a pixel opening Q1.

[0121] The first groove 150 penetrates from the pixel defining layer 140 to the first planar layer 122A, and is located between two adjacent first grooves 160 in the first grooves 160. The first passivation layer 121 includes a first pattern 121a, and the first pattern 121a includes a portion G extending from the sidewall of the first groove 150. The portion G of the first pattern 121a extending from the sidewall of the first groove 150 is close to the surface of the substrate 110, and there is a gap E between the portion G and the bottom of the first groove 150.

[0122] In some examples, such as Figure 3 to Figure 9 As shown, the base 110 includes a substrate 111 .

[0123] Exemplarily, the substrate 111 may be a rigid substrate, such as a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0124] Exemplarily, the substrate 111 may be a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.

[0125] For example, the substrate 111 may be a single-layer structure, or may be a stacked-layer structure. Figure 3 to Figure 9 As shown, when the substrate 111 is a laminated structure, the substrate 111 includes, for example, a first polyimide layer PI1, a first barrier layer Barrier1, a second polyimide layer PI2, and a second barrier layer Barrier2 stacked in sequence in a direction close to the insulating film group 120. Of course, the substrate 111 can also be a laminated structure of other forms.

[0126] In some examples, such as Figure 3 to Figure 9As shown, the base 110 also includes a multi-layer backplane film layer disposed between the substrate 111 and the insulating film group 120. The multi-layer backplane film layer includes any combination of one or more of a buffer layer Buffer, a shielding layer LS, an active layer AL, a gate metal layer Gate, a gate insulating layer GI, a source and drain metal layer SD, a passivation layer PVX, and an interlayer dielectric layer ILD. Among these backplane film layers, some backplane film layers are continuous whole-layer paved film layers, some backplane film layers are patterned film layers, some backplane film layers are only located in the display area, some backplane film layers extend from the display area to the peripheral area, and some backplane film layers include a portion located in the display area and a portion located in the peripheral area, and these two portions are separated.

[0127] Among them, the gate metal layer Gate, the source-drain metal layer SD, and the shielding layer LS are conductive film layers, and the materials of these conductive film layers are, for example, aluminum (Al), silver (Ag), copper (Cu), or chromium (Cr). The gate insulating layer GI, the interlayer dielectric layer ILD, and the passivation layer PVX are insulating film layers, and the materials of these insulating film layers are, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0128] For example, Figure 3 to Figure 9 As shown, the multi-layer backplane film layer includes a shielding layer LS, a first buffer layer Buffer1 (for example, Buffer-S), a second buffer layer Buffer2 (for example, Buffer-L), a first active layer AL1, a first gate insulating layer GI1, a first gate metal layer Gate1, a second gate insulating layer GI2, a second gate metal layer Gate2, a third buffer layer Buffer3 (for example, Buffer-O), a second active layer AL2, a third gate insulating layer GI3 (for example, GI3-O), a third gate metal layer Gate3, an interlayer dielectric layer ILD (for example, O-ILD-O), a second source and drain metal layer SD1, and a second passivation layer PVX. In some examples, such as Figure 3 to Figure 8 As shown, the multi-layer backplane film layer also includes a fourth planar layer PLN arranged on the side of the second passivation layer PVX away from the substrate 111.

[0129] The material of the first active layer AL1 is, for example, polysilicon (Poly). The material of the second active layer AL2 is, for example, low temperature polysilicon (LTPS). The second source-drain metal layer SD1 is a patterned film layer, and includes a pattern coupled to the shielding layer LS, a pattern coupled to the first active layer AL1, and a pattern coupled to the second active layer AL2.

[0130] It should be understood that these backplane film layers can constitute a part of the film layer structure of the pixel driving circuit, so that the display substrate 100 can include multiple pixel driving circuits, and the multiple pixel driving circuits are used to drive multiple light-emitting devices 210 to emit light.

[0131] In some embodiments, the light emitting device 210 is located at a pixel opening Q1 . In this way, the pixel defining layer 140 can be used to locate the position of each light emitting device 210 , so as to facilitate the subsequent preparation of each light emitting functional layer in the light emitting device 210 .

[0132] In some examples, the display substrate 100 further includes a spacer layer located on a side of the pixel defining layer 140 away from the reflective layer 130; the spacer layer includes a plurality of spaced-apart heat insulators PS. The spacers PS can be used to support FMM (Fine Metal Mask) when evaporating the light-emitting material.

[0133] Here, the insulating film group 120 includes a stacked first passivation layer 121 and a multi-layer planarization layer 122. For example, similar to the aforementioned gate insulating layer GI, interlayer dielectric layer ILD, and passivation layer PVX, the first passivation layer 121 and the multi-layer planarization layer 122 may be insulating film layers, and the materials of the first passivation layer 121 and the multi-layer planarization layer 122 may be, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0134] The surface of the insulating film group 120 away from the substrate 110 (hereinafter referred to as the first surface) includes a plurality of first grooves 160 arranged along the first direction X; it can be understood that the first surface is formed with a plurality of first grooves 160 opening in a direction away from the substrate 110, so that the side walls and bottom walls of the plurality of first grooves 160 can constitute a part of the first surface.

[0135] It should be noted that the manner in which the first surface is formed with the plurality of first grooves 160 is not limited herein. Figures 5 to 9 As shown, a plurality of first grooves 160 may be formed by patterning a film layer or a plurality of film layers in the insulating film group 120 away from the substrate 110. For another example, Figure 3 and Figure 4 As shown, a plurality of recessed structures can be formed in the area where the plurality of first grooves 160 are to be formed by patterning a film layer or a plurality of film layers located in the middle position of the insulating film group 120, and the insulating film group 120 located on the side of the plurality of recessed structures away from the substrate 110 continues the morphology of the plurality of recessed structures to form the plurality of first grooves 160.

[0136] Here, the reflective layer 130 covers the sidewalls and bottom wall of the first groove 160, which means that the reflective layer 130 includes a portion covering the sidewalls and bottom wall of the first groove 160. Of course, in addition to the portion covering the sidewalls and bottom wall of the first groove 160, Figure 3 to Figure 9 As shown, the reflective layer 130 may further include a portion covering other portions of the first surface except the first groove 160 .

[0137] In some examples, such as Figure 3 to Figure 9 As shown, the portion of the reflective layer 130 covering the bottom wall of the first groove 160 is reused as the anode 211. By such a configuration, firstly, the reflective layer 130 and the anode 211 can be formed at the same time, which can simplify the manufacturing process of the display panel 200. Secondly, the anode 211 can have a certain reflective property, so that the anode 211 can be used to reflect the portion of the light emitted by the light-emitting layer 131 that is directed toward the anode 211, thereby improving the light extraction efficiency of the light-emitting device 210.

[0138] Exemplarily, the material of the reflective layer 130 includes, for example, a magnesium-silver alloy, and the mass ratio of magnesium to silver in the magnesium-silver alloy may be in a range of 1:9 to 2:8.

[0139] In some examples, such as Figure 3 to Figure 9 As shown, the material of the pixel defining layer 140 covers the portion of the sidewall of the reflective layer 130 away from the first groove 160. At this time, the material of the pixel defining layer 140 is in contact with the portion of the reflective layer 130 covering the sidewall of the first groove 160. In this case, the side surface of the pixel defining layer 140 constitutes the sidewall of the pixel opening Q1. At this time, the light emitted by the light emitting device 210 can pass through the material of the pixel defining layer 140 and be emitted to the surface of the reflective layer 130.

[0140] The display substrate 100 includes a plurality of first grooves 150. In some embodiments, the first grooves 150 are arc-shaped grooves, and the plurality of arc-shaped grooves can be divided into a plurality of groups of arc-shaped grooves, each group of arc-shaped grooves surrounding a first groove 160. Here, the first grooves 150 are arc-shaped grooves, which means that the cross-section of the first grooves 150 parallel to the first direction X is arc-shaped.

[0141] It can be understood that, in the first aspect, when the reflective layer 130 covers the sidewalls and the bottom wall of the first groove 160, the portion of the reflective layer 130 covering the sidewalls and the bottom wall of the first groove 160 can continue the concave morphology of the plurality of first grooves 160, so that the reflective layer 130 can include a plurality of reflective cup structures 130a. Moreover, when each first groove 160 surrounds a pixel opening Q1, the reflective cup structure 130a can surround the pixel opening Q1. In this way, Figure 3 to Figure 9As shown, the light emitted from the side of the light emitting device 210 can be reflected on the surface of the reflective cup structure 130a and emitted from the pixel opening Q1 after reflection. In this way, the light extraction efficiency of the light emitting device 210 can be improved, so that the light emission efficiency of the display panel 200 is improved.

[0142] On the other hand, when the first groove 150 penetrates from the pixel defining layer 140 to the first flat layer 122A, the common film layer of the plurality of light-emitting devices 210 (for example, the electron generating layer 2141 and / or the hole generating layer 2142) is formed in the first groove 150. Furthermore, when the first groove 150 is located between two adjacent first recesses 160, and the portion G of the first pattern 121a extending from the sidewall of the first groove 150 is close to the surface of the substrate 110 and has a gap E between the portion G and the bottom of the first groove 150, when the common film layer is formed at the first groove 150, the common film layer formed on the portion G of the first pattern 121a extending from the sidewall of the first groove 150 is disconnected from the common film layer formed in the first groove 150 (see Figure 1A ), thus, the lateral current transmission between adjacent light-emitting devices 210 can be reduced, and the color crosstalk phenomenon can be avoided. In this way, the light-emitting devices 210 included in the display panel 200 can be series-type light-emitting devices, so that the luminous efficiency and life of the display panel 200 are improved, and the power consumption of the display panel 200 is reduced.

[0143] In some embodiments, the first trench 150 is filled with materials of multiple light-emitting functional layers and materials of the encapsulation layer 220. For example, Figure 1A As shown, the portion of the first groove 150 located in the first passivation layer 121 and the first flat layer 122A can be divided into a portion 151 (hereinafter referred to as the first portion 151) located beside the portion G of the first pattern 121a extending from the sidewall of the first groove 150 and the remaining portion 152 (hereinafter referred to as the second portion 152) except the first portion 151. The first portion 151 is filled with the material of the first sublayer 221 of the encapsulation layer 220; and the second portion 152 is filled with the material of the light-emitting functional layer. In this case, the material of the first sublayer 221 located in the first portion 151 can form a barrier between the materials of the light-emitting functional layer, which can improve the effect of preventing color crosstalk.

[0144] Figure 1B for Figure 1A A partial enlarged view of the M in the middle. Figure 1C This is a partial picture of the display panel obtained using a focused ion beam (FIB)-transmission electron microscope (TEM). Figure 1C EV in the figure represents the light-emitting functional layer.

[0145] Based on the above structure of the display substrate 100, in some embodiments, as Figure 1A , Figure 1B and Figure 1C As shown, the light emitting device 210 includes at least two light emitting layers 213 and a charge generating unit 214 located between two adjacent light emitting layers 213. The charge generating units 214 of the plurality of light emitting devices 210 are of the same layer and material and constitute a common unit 214G. The common unit 214G includes a fifth portion 214A and a sixth portion 214B. The fifth portion 214A is located at a portion G of the first pattern 121a extending from the sidewall of the first groove 150, on one side along the second direction Y. The sixth portion 214B is located in the first groove 150 and on one side of the first pattern 121a along the second direction Y; the second direction Y is the stacking direction of the multi-layer flat layer 122; and along the second direction Y, there is a gap between the fifth portion 214A and the sixth portion 214B.

[0146] Here, for understanding the charge generating unit 214 , reference may be made to the aforementioned exemplary description of the partial charge generating unit 214 , which will not be repeated here.

[0147] It can be understood that, through the above arrangement, the fifth portion 214A and the sixth portion 214B can be disconnected (see Figure 1A ), thus, the lateral current transmission between adjacent light-emitting devices 210 can be reduced, and the color crosstalk phenomenon can be avoided. In this way, the light-emitting devices 210 included in the display panel 200 can be series-type light-emitting devices, so that the luminous efficiency and life of the display panel 200 are improved, and the power consumption of the display panel 200 is reduced.

[0148] Fig.10 A flow chart of a method for preparing a display substrate 100 provided for some embodiments of the present disclosure. Figures 11A to 11H The present invention provides steps for preparing the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 in some embodiments. Figures 11A to 11C and FIG. 12A to FIG. 12D The present disclosure provides steps for preparing the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 . Figures 13A to 13G The present disclosure provides steps for preparing the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 . Fig.13A and Figures 14A to 14F The present disclosure provides steps for preparing the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 . Figures 15A to 15GThe present disclosure provides steps for preparing the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 . Fig.15A , Fig. 15B , Figures 16A to 16E The present disclosure provides steps for preparing the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 . Figures 17A to 17G The steps for preparing the insulating film group 120 and the pixel defining layer 140 in the display substrate 100 provided in some other embodiments of the present disclosure are described together below. Fig.10 , Figures 11A to 11H , FIG. 12A to FIG. 12D , Figures 13A to 13G , Figures 14A to 14F , Figures 15A to 15G , Figures 16A to 16E and Figures 17A to 17G It should be understood that the operations shown in the preparation method are not exhaustive, and other operations may be performed before, after or between any of the operations shown. In the following preparation method, the process of patterning the film layer is, for example, an etching process.

[0149] like Fig.10 As shown, some embodiments of the present disclosure further provide a method for preparing a display substrate 100. The preparation method includes S1-S5.

[0150] S1: forming a substrate 110 .

[0151] S2: An insulating film group 120 is formed on one side of the substrate 110; the insulating film group 120 includes a first passivation layer 121 and a multi-layer flat layer 122 which are stacked; the multi-layer flat layer 122 includes a first flat layer 122A; the first passivation layer 121 is located on a side of the first flat layer 122A away from the substrate 110 and contacts the first flat layer 122A. The surface of the insulating film group 120 away from the substrate 110 includes a plurality of first grooves 160 arranged along a first direction X; the first direction X intersects with the stacking direction of the multi-layer flat layer 122.

[0152] S3 : forming a reflective layer 130 on a side of the insulating film group 120 away from the substrate 110 , wherein the reflective layer 130 covers the sidewall and the bottom wall of the first groove 160 .

[0153] S4: forming a pixel defining layer 140 on a side of the reflective layer 130 away from the substrate 110 ; the pixel defining layer 140 includes a plurality of pixel openings Q1 ; each of the plurality of first grooves 160 surrounds a pixel opening Q1 .

[0154] In some examples, while forming the pixel defining layer 140 , a plurality of spacers PS disposed at intervals are also formed.

[0155] S5: forming a plurality of first grooves 150, so that the first grooves 150 penetrate from the pixel definition layer 140 to the first planar layer 122A; the first groove 150 is located between two adjacent first grooves 160 among the plurality of first grooves 160. The first passivation layer 121 includes a first pattern 121a, and the first pattern 121a includes a portion extending from the sidewall of the first groove 150. The portion G of the first pattern 121a extending from the sidewall of the first groove 150 is close to the surface of the substrate, and has a gap E between it and the bottom of the first groove 150.

[0156] The beneficial effects that can be achieved by the method for preparing the display substrate 100 are the same as the beneficial effects that can be achieved by the display substrate 100 , and will not be described in detail herein.

[0157] In the above manufacturing method, the process of forming the plurality of first recesses 160 and the plurality of first trenches 150 is, for example, an etching process.

[0158] On the one hand, as described above, in S3, a plurality of first grooves 160 can be formed by patterning a film layer or a plurality of film layers in the insulating film group 120 away from the substrate 110; or, a plurality of first grooves 160 can be formed by patterning a film layer or a plurality of film layers in the middle position of the insulating film group 120, and making the insulating film group 120 located on the side of the plurality of recessed structures away from the substrate 110 continue the morphology of the plurality of recessed structures.

[0159] It should be understood that when a plurality of first grooves 160 are formed in the above manner, one or more film layers in the insulating film group 120 need to be patterned.

[0160] On the other hand, in S5, when the first groove 150 penetrates from the pixel defining layer 140 to the first planar layer 122A, at least the pixel defining layer 140, the first passivation layer 121 and the first planar layer 122A need to be patterned to form a plurality of first grooves 150; that is, Figure 3 to Figure 9 As shown, the first trench 150 includes at least a fifth opening Q6 located in the pixel defining layer 140, a sixth opening Q7 located in the first passivation layer 121, and a seventh opening or a second groove K2 located in the first planar layer 122A. Moreover, when other planar layers 122 exist between the pixel defining layer 140 and the first planar layer 122A, these planar layers 122 also need to be patterned.

[0161] Therefore, when forming a plurality of first grooves 150, it is also necessary to pattern one or more film layers in the insulating film group 120. In this case, when the display panel 200 includes a plurality of first grooves 160 and a plurality of first grooves 150, the number of patterning times of the insulating film group 120 may increase, and the process difficulty of the manufacturing method of the display panel 200 may increase.

[0162] In some embodiments, in order to reduce the number of patterning times when forming the plurality of first recesses 160 and the plurality of first trenches 150 , the method of forming the plurality of first recesses 160 and the plurality of first trenches 150 includes steps R1 to R7 .

[0163] R1: Fig. 13B and Fig.14A As shown, a first preliminary planarization layer 122Ai is formed.

[0164] R2: Fig. 11C , Fig.11H , Fig. 12B , Figure 13G , Fig. 14B and Fig.14F As shown, the first initial planar layer 122Ai is patterned to form a first planar layer 122A, and the first planar layer 122A includes a plurality of seventh openings (not shown in the figure) or a plurality of second grooves K2.

[0165] R3: Fig.11D , Fig. 12A , Fig. 13C and Fig. 14B As shown, an initial passivation layer is formed on a side of the first planar layer 122A away from the substrate 110 .

[0166] R4: Fig.11D , Fig. 12A , Fig. 13C and Fig. 14B As shown, the initial passivation layer is patterned to form a first passivation layer 121 , and the first passivation layer 121 includes a plurality of sixth openings Q7 .

[0167] R5: Fig.11E , Fig. 12B , Fig.13D and Fig. 14C As shown, the reflective layer 130 is formed on one side of the first passivation layer 121 away from the first planar layer 122A.

[0168] R6: Fig.11F , Fig. 12C , Fig.13E and Fig.14D As shown, an initial pixel defining layer 140 i is formed on a side of the reflective layer 130 away from the first passivation layer 121 .

[0169] R7: Fig.11G , Fig.12D , Fig.13F and Fig.14E As shown, the patterned initial pixel definition layer 140i (see Fig.11F , Fig. 12C , Fig.13E and Fig.14D) to form a pixel defining layer 140, the pixel defining layer 140 includes a plurality of pixel openings Q1 and a plurality of fifth openings Q6.

[0170] Among them, Fig. 11C , Fig.11D , Fig. 12A , Fig. 13C and Fig. 14B As shown, in R2 and R4, the first initial planar layer 122Ai is patterned to form a plurality of seventh openings (not shown) or a plurality of second grooves K2, and the initial passivation layer is patterned to form a plurality of sixth openings Q7, and a plurality of first grooves 160 are also formed.

[0171] It can be understood that when the above method is used to form multiple first grooves 160 and multiple first grooves 150, in the process of patterning the first passivation layer 121 and the first flat layer 122A, the parts of the multiple first grooves 150 located in the insulating film group 120 (i.e., the sixth opening Q7 and the seventh opening, or the sixth opening Q7 and the second groove K2) are formed, and multiple first grooves 160 are also formed. In this way, the number of patterning times when forming multiple first grooves 160 and multiple first grooves 150 can be reduced, thereby simplifying the preparation process of the display panel 200.

[0172] In some embodiments, Fig.11D , Fig. 12A , Fig. 13C and Fig. 14B As shown, when the plurality of first grooves 160 and the plurality of first trenches 150 are formed by the method including R1 to R7, the first planar layer 122A includes the second pattern 122A-a. The sidewall of the first groove 160 includes the surface of the first pattern 121a; or, the sidewall of the first groove 160 includes the surface of the first pattern 121a and the surface of the second pattern 122A-a.

[0173] It should be noted that the surface of the first pattern 121a includes the first type of surface and the second type of surface of the first pattern 121a. Similarly, the surface of the second pattern 122A-a includes the first type of surface and the second type of surface of the second pattern 122A-a.

[0174] Among them, the first type of surface of the first pattern 121a refers to the surface formed when the initial passivation layer is formed, and the first type of surface of the first pattern 121a can be a plane or a non-plane; the second type of surface of the first pattern 121a refers to the surface connected to the first type of surface of the first pattern 121a that is exposed after the patterned initial passivation layer forms a plurality of openings or grooves; it can also be understood that the second type of surface of the first pattern 121a is the side walls and bottom walls of these openings or grooves.

[0175] For the understanding of the first type of surface and the second type of surface of the second pattern 122A-a, reference may be made to the description of the first type of surface and the second type of surface of the first pattern 121a, which will not be repeated here.

[0176] It should be understood that, through the above configuration, the beneficial effects that can be achieved by the display substrate 100 are the same as the beneficial effects that can be achieved when the multiple first recesses 160 and the multiple first grooves 150 are formed by the method including R1 to R7, and will not be repeated here.

[0177] When the sidewall of the first groove 160 includes the surface of the first pattern 121 a ; or, the sidewall of the first groove 160 includes the surface of the first pattern 121 a and the surface of the second pattern 122A-a, the following three cases may be included.

[0178] The first case: Fig. 13C As shown, the sidewall of the first groove 160 includes the second type surface of the first pattern 121a and does not include the surface of the second pattern 122A-a. At this time, the first groove 160 can be formed by patterning the initial passivation layer.

[0179] The second case: Fig.14F As shown, the sidewall of the first groove 160 includes the second type surface of the first pattern 121a and the second type surface of the second pattern 122A-a. At this time, the first groove 160 can be formed by patterning the initial passivation layer and the first initial planarization layer 122Ai.

[0180] The third situation: Fig.11H and Fig. 12A As shown, the sidewall of the first groove 160 includes the first type of surface of the first pattern 121a and does not include the surface of the second pattern 122A-a. At this time, the first groove 160 can be formed by patterning the first initial flat layer to form openings or grooves, and making the first passivation layer 121 continue the morphology of these openings or grooves.

[0181] The first case and the second case are described below as examples.

[0182] In some embodiments, Fig. 13C and Fig. 14B As shown, in the first case or the second case, during the process of patterning the initial passivation layer in R4 , a plurality of first openings Q2 are formed. The first openings Q2 constitute at least a portion of the first grooves 160 .

[0183] In this case, the first passivation layer 121 includes a plurality of first openings Q2 arranged along the first direction X, and the first openings Q2 constitute at least a portion of the first groove 160 .

[0184] It can be understood that through the above-mentioned settings, multiple sixth openings Q7 and multiple first openings Q2 can be formed in the process of patterning the initial passivation layer, and the first openings Q2 can constitute part or all of the first groove 160. In this way, the number of patterning times when forming multiple first grooves 160 and multiple first grooves 150 can be reduced, thereby simplifying the preparation process of the display panel 200.

[0185] In some examples, such as Fig. 13C As shown, in the first case, the first opening Q2 is the first groove 160, that is, the first opening Q2 constitutes the entire first groove 160. In this case, the first groove 160 can be formed by patterning the initial passivation layer, and the dimension L1 of the first passivation layer 121 along the second direction Y is consistent with the dimension H of the first groove 160 along the second direction Y. Therefore, the dimension L1 of the formed first passivation layer 121 along the second direction Y can be controlled to make the dimension H of the first groove 160 along the second direction Y within a reasonable range.

[0186] In some embodiments, Fig. 13C As shown, when the first opening Q2 forms the first groove 160 , the dimension L1 of the first passivation layer 121 along the second direction Y ranges from 0.5 μm to 1.5 μm, and the second direction Y is the stacking direction of the multiple planar layers 122 .

[0187] For example, the dimension L1 of the first passivation layer 121 along the second direction Y may be 0.5 μm, 0.7 μm, 0.9 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.5 μm, or the like.

[0188] It can be understood that by such configuration, the dimension L1 of the first passivation layer 121 along the second direction Y can be relatively large, and the dimension H of the first groove 160 along the second direction Y can be relatively large, which can enhance the reflection effect of the reflective layer 130 on the light emitted by the light-emitting device 210 to a certain extent.

[0189] In some other examples, in the second case, the first opening Q2 constitutes a portion of the first groove 160. In this case, the other portions of the first groove 160 except the first opening Q2 may be an opening formed in the first flat layer 122A or a groove formed in the first flat layer 122A.

[0190] For example, Fig.18 As shown, the first opening Q2 constitutes a portion of the first groove 160, the first flat layer 122A includes a plurality of second openings Q3 correspondingly connected to the plurality of first openings Q2, and the second openings Q3 constitute the remaining portion of the first groove 160 except the first openings Q2. The bottom surface of the first trench 150 is closer to the substrate 110 than the bottom surface of the first groove 160.

[0191] It should be understood that when the bottom surface of the first trench 150 is closer to the substrate 110 than the bottom surface of the first groove 160 , the first trench 150 includes the second groove K2 .

[0192] For example, when patterning the first planar layer 122A, a half-tone mask may be used so that the second groove K2 may be formed in the process of forming the second opening Q3 .

[0193] For example, Fig. 14B and Fig.14F As shown, the first opening Q2 constitutes a portion of the first groove 160 , the first planar layer 122A includes a plurality of first sub-grooves K1 correspondingly connected to the plurality of first openings Q2 , and the first sub-grooves K1 constitute the remaining portion of the first groove 160 except the first opening Q2 .

[0194] It can be understood that through the above-mentioned arrangement, when patterning the first flat layer 122A, a plurality of seventh openings (not shown in the figure) or a plurality of second grooves K2 contained in the first groove 150, as well as the remaining parts of the first groove 160 except the first opening Q2 (the second opening Q3 or the first sub-groove K1) can be formed. In this way, the number of patterning times when forming a plurality of first grooves 160 and a plurality of first grooves 150 can be reduced, thereby simplifying the preparation process of the display panel 200.

[0195] In some embodiments, Fig. 14B and Fig.14F As shown, in the case where the first planar layer 122A includes a plurality of first sub-grooves K1 , a dimension L2 of the first planar layer 122A along the second direction Y ranges from 1.5 μm to 3.0 μm.

[0196] For example, the dimension L2 of the first planar layer 122A along the second direction Y may be 1.5 μm, 1.8 μm, 2.0 μm, 2.3 μm, 2.5 μm, 2.7 μm, 3.0 μm, or the like.

[0197] It can be understood that by such a configuration, the dimension L2 of the first flat layer 122A along the second direction Y can be relatively large, the dimension of the first sub-groove K1 along the second direction Y can be relatively large, and the dimension of the first groove 160 along the second direction Y can also be relatively large. In this way, as described above, the anti-crosstalk effect of the pixel defining layer 140 can be increased.

[0198] For a clearer description, the method of forming a plurality of first recesses 160 and a plurality of first grooves 150 in the first case and the second case are exemplarily described below.

[0199] In some embodiments, in the first case, the method of forming the plurality of first recesses 160 and the plurality of first trenches 150 includes steps V1 to V6.

[0200] V1: As Fig. 13B As shown, a first preliminary planarization layer 122Ai is formed.

[0201] V2: As Fig. 13C As shown, an initial passivation layer is formed on a side of the first initial planar layer 122Ai away from the substrate 110 .

[0202] V3: Fig. 13C As shown, the initial passivation layer is patterned by an etching process to form a first passivation layer 121 . The first passivation layer 121 includes a plurality of sixth openings Q7 and a plurality of first openings Q2 .

[0203] V4: Fig.13D As shown, a patterned reflective layer 130 is formed on a side of the first passivation layer 121 away from the first preliminary planarization layer 122Ai.

[0204] V5: Fig.13E and Fig.13F As shown, a patterned pixel defining layer 140 is formed on a side of the reflective layer 130 away from the first passivation layer 121 .

[0205] V6: Figure 13G As shown, the first initial planar layer 122Ai is patterned to form a plurality of second grooves K2 and a plurality of gaps E.

[0206] It should be understood that when the method for forming multiple first grooves 160 and multiple first trenches 150 includes V1 to V6, in the aforementioned preparation method, patterning the first initial flat layer 122Ai in R2 is V6. In other words, R2 is performed after patterning the initial pixel defining layer 140i in R7.

[0207] In some embodiments, in the second case, the method of forming the plurality of first recesses 160 and the plurality of first trenches 150 includes W1 ˜ W6 .

[0208] W1: If Fig.14A As shown, a first preliminary planarization layer 122Ai is formed.

[0209] W2: If Fig. 14B As shown, an initial passivation layer is formed on a side of the first initial planar layer 122Ai away from the substrate 110 .

[0210] W3: If Fig. 14BAs shown, an etching process is used to pattern the initial passivation layer and the first initial flat layer 122Ai to form a first passivation layer 121 and a first initial pattern 122Aii. The first passivation layer 121 includes a plurality of sixth openings Q7 and a plurality of first openings Q2. The first initial pattern 122Aii includes a fourth groove K4 and a first sub-groove K1. The sixth opening Q7 is connected to the fourth groove K4 to constitute a part of the first groove 150. The first opening Q2 is connected to the first sub-groove K1 to constitute a first groove 160.

[0211] W4: If Fig. 14C As shown, a patterned reflective layer 130 is formed on a side of the first passivation layer 121 away from the first preliminary planarization layer 122Ai.

[0212] W5: If Fig.14D and Fig.14E As shown, a patterned pixel defining layer 140 is formed on a side of the reflective layer 130 away from the first passivation layer 121 .

[0213] W6: If Fig.14F As shown, the first initial pattern 122Aii is patterned so that the fourth groove K4 is expanded into the second groove K2 and a plurality of gaps E are formed.

[0214] It should be understood that when the method of forming the plurality of first recesses 160 and the plurality of first trenches 150 includes W1 to W6 , in the aforementioned preparation method, patterning the first initial planarization layer 122Ai in R2 may include R2.1A and R2.2B.

[0215] R2.1A: Patterning the first preliminary planarization layer 122Ai to form a first preliminary pattern 122Aii, wherein the first preliminary pattern 122Aii includes a fourth groove K4 and a first sub-groove K1.

[0216] R2.2B: Patterning the first initial pattern 122Aii, so that the fourth groove K4 is expanded into the second groove K2, and a plurality of gaps E are formed.

[0217] That is, W3 includes R2.1A, and W6 is R2.2B; in other words, R2 includes the part performed during R4 and the part performed after R7.

[0218] The above is an exemplary description of the first and second situations. The following is an exemplary description of the third situation.

[0219] In some embodiments, in the above preparation method, S2 includes: forming an initial planar layer, and forming an initial passivation layer on a side of the initial planar layer away from the substrate 110. S5 includes patterning the initial passivation layer by using an etching process.

[0220] In the process of patterning the initial passivation layer, the etching parameters are controlled so that a portion of the initial flat layer close to the initial passivation layer is removed to form a portion of the first groove 150 located on the side of the first passivation layer 121 close to the substrate 110, and to form a portion G of the first pattern 121a extending from the side wall of the first groove 150 and a gap E with the bottom of the first groove 150.

[0221] It can be understood that, through the above arrangement, the gap E can be formed by over-etching the initial passivation layer, thus simplifying the process of forming the gap E.

[0222] In some embodiments, the initial planar layer is the second initial pattern 122Aiii. This case will be described exemplarily below.

[0223] In some embodiments, in the aforementioned preparation method, patterning the first initial planar layer in R2 may include R2.1a.

[0224] R2.1a: If Fig. 11C As shown, the first initial planar layer is patterned to form a second initial pattern 122Aiii, and the second initial pattern 122Aiii includes a plurality of third openings Q4. The region where the plurality of third openings Q4 are located is directly opposite to the region where the plurality of first grooves 160 are located along the second direction Y.

[0225] In this case, when the initial passivation layer is formed in R3, the initial passivation layer continues the morphology of the plurality of third openings Q4 of the second initial pattern 122Aiii. In some examples, when the initial passivation layer is patterned in R4, the portion of the initial passivation layer covering the plurality of third openings Q4 is retained.

[0226] In this case, in some embodiments, Fig.11H and Fig. 12B As shown, the first planar layer 122A further includes a plurality of third openings Q4 arranged along the first direction X, and the first pattern 121a and the reflective layer 130 are sequentially layered on the sidewalls and bottom walls of the third openings Q4.

[0227] It can be understood that, through the above configuration, the area of ​​the first planar layer 122A opposite to the plurality of grooves 160 along the second direction Y can be covered by the first passivation layer 121. Fig. 12A As shown, the gap E can be formed by over-etching the initial passivation layer in the process of forming a plurality of seventh openings (not shown in the figure) or a plurality of second grooves K2. In this way, the process of forming the gap E can be simplified.

[0228] For a clearer description, the method of forming a plurality of second grooves K2 and a plurality of gaps E by over-etching the first passivation layer 121 is exemplarily introduced below by taking the case where the first trench 150 includes the second groove K2 as an example.

[0229] In some embodiments, a method of forming a plurality of first recesses 160 and a plurality of first trenches 150 includes T1 to T7.

[0230] T1: forming a first initial planarization layer.

[0231] T2: Fig. 11C As shown, the first preliminary planarization layer is patterned to form a second preliminary pattern 122Aiii, and the second preliminary pattern 122Aiii includes a plurality of third openings Q4.

[0232] T3: Fig. 12A As shown, an initial passivation layer is formed on a side of the second initial pattern 122Aiii away from the substrate 110 .

[0233] T4: Fig. 12A As shown, the initial passivation layer and the second initial pattern 122Aiii are patterned by an etching process to form a first passivation layer 121 and a first planar layer 122. The first passivation layer 121 includes a plurality of sixth openings Q7, and the first planar layer 122A includes a plurality of second grooves K2 and a plurality of gaps E.

[0234] In some examples, in the process of patterning the initial passivation layer to form a plurality of sixth openings Q7, one or more eighth openings Q8 are also formed in the first passivation layer 121; in the process of patterning the second initial pattern 122Aiii to form a plurality of second grooves K2 and a plurality of gaps E, one or more third grooves K3 and a plurality of first gaps J1 are also formed in the first flat layer 122, wherein the plurality of third grooves K3 are correspondingly connected to the plurality of eighth openings Q8. The groove depth of the second groove K2 is consistent with the groove depth of the third groove K3. The first gap J1 is a cavity located on the side of the first pattern 121a close to the substrate 110 and connected to the third groove K3.

[0235] T5: Fig. 12B As shown, a patterned reflective layer 130 is formed on a side of the first passivation layer 121 away from the first planar layer 122A.

[0236] T6: Fig. 12C As shown, an initial pixel defining layer 140 i is formed on a side of the reflective layer 130 away from the first passivation layer 121 .

[0237] In some examples, such as Fig. 12CAs shown, the material of the initial pixel defining layer 140 i is also filled in the plurality of sixth openings Q7 , the plurality of second grooves K2 , and the plurality of gaps E. As shown in FIG.

[0238] In some examples, such as Fig. 12C As shown, the material of the initial pixel defining layer 140 i is also filled in one or more eighth openings Q8 , one or more third grooves K3 , and a plurality of first gaps J1 .

[0239] T7: Fig.12D As shown, the patterned initial pixel definition layer 140i (see Fig. 12C ) to form a pixel defining layer 140, the pixel defining layer 140 includes a plurality of pixel openings Q1 and a plurality of fifth openings Q6.

[0240] In some examples, such as Fig.12D As shown, during the process of patterning the initial pixel defining layer 140 i , the material of the initial pixel defining layer 140 i located in the plurality of sixth openings Q7 , the plurality of second grooves K2 , and the plurality of gaps E is removed.

[0241] In some examples, such as Fig.12D As shown, during the patterning of the initial pixel defining layer 140 i , the material of the initial pixel defining layer 140 i located in one or more third grooves K3 and a plurality of first gaps J1 is not removed and constitutes a portion of the pixel defining layer 140 .

[0242] In this case, in some embodiments, Fig.12D As shown, the pixel defining layer 140 also includes a first portion 141 located on a side of the first passivation layer 121 close to the substrate 110; a surface of the first portion 141 close to the substrate 110 is flush with the bottom surface of the first groove 150; and an edge portion of the first portion 141 overlaps an edge portion of the first passivation layer 121.

[0243] It should be understood that the portion of the initial pixel defining layer 140i filled in one or more third grooves K3 and multiple first gaps J1 is the first portion 141; the edge portion of the first portion 141 is the portion of the initial pixel defining layer 140i filled in the multiple first gaps J1.

[0244] Moreover, when the first gap J1 is a cavity located at the side of the first pattern 121a close to the substrate 110 and communicating with the third groove K3, the edge of the first portion 141 overlaps with the edge of the first passivation layer 121. When the depth of the second groove K2 is consistent with the depth of the third groove K3, the surface of the first portion 141 close to the substrate 110 is flush with the bottom surface of the first groove 150.

[0245] It should be understood that, through the above configuration, the beneficial effects that can be achieved by the display substrate 100 are the same as the beneficial effects that can be achieved when the multiple first recesses 160 and the multiple first grooves 150 are formed by the method including T1 to T7, and will not be repeated here.

[0246] In some embodiments, the aforementioned method further includes R1A before R1.

[0247] R1A: Fig.13A As shown, a first source-drain metal layer SD2 is formed on one side of the substrate 110 .

[0248] It should be understood that in the case where R1A is included before R1, Fig. 13B and Fig.14A As shown, in R1 , the first initial planar layer 122Ai is formed on a side of the first source / drain metal layer SD2 away from the substrate 110 .

[0249] In some embodiments, when R1A is included before R1, Fig. 13B and Fig.14A As shown, the first initial planar layer 122Ai formed in R1 includes vias connected to the pattern of the first source-drain metal layer SD2.

[0250] To this end, in some embodiments, such as Figure 5 and Figure 6 As shown, a first source-drain metal layer SD2 is disposed on one side of the first planar layer 122A away from the first passivation layer 121. The reflective layer 130 is coupled to the pattern of the first source-drain metal layer SD2 through via holes in the first planar layer 122A and / or via holes in the first passivation layer 121.

[0251] It should be understood that when part of the bottom wall of the reflective layer 130 covering the first groove 160 is reused as the anode 211, the anode 211 can be coupled to the pixel driving circuit through the pattern of the first source-drain metal layer SD2 and the pattern of the second source-drain metal layer SD1 in sequence to achieve control of the light-emitting device by the pixel driving circuit.

[0252] Exemplarily, the pixel driving circuit includes a light emission control transistor. The anode 211 may be coupled to the source or drain of the light emission control transistor of the pixel driving circuit through the pattern of the first source-drain metal layer SD2 and the pattern of the second source-drain metal layer SD1 in sequence.

[0253] It can be understood that when the first source-drain metal layer SD2 is arranged on the side of the first planar layer 122A away from the first passivation layer 121, the distance between the first source-drain metal layer SD2 and the reflective layer 130 is relatively close, so that the reliability of the coupling between the first source-drain metal layer SD2 and the reflective layer 130 can be improved.

[0254] In some embodiments, in the aforementioned method, after R1A and before R1, R1B is further included.

[0255] R1B: Fig. 11B As shown, a second planar layer 122B is formed on a side of the first source / drain metal layer SD2 away from the substrate 110 .

[0256] It should be understood that in the case where R1A is followed by R1B and R1 is preceded by R1, Fig. 11C As shown, in R1, the first initial planar layer is formed on a side of the second planar layer 122B away from the first source-drain metal layer SD2.

[0257] In some embodiments, when R1A is followed by R1B and R1 is preceded by R1, Fig. 11C As shown, the first initial planar layer formed in R1 includes vias connected to the pattern of the first source-drain metal layer SD2.

[0258] To this end, in some embodiments, such as Figure 3 and Figure 4 As shown, the insulating film group 120 further includes a second flat layer 122B located on a side of the first flat layer 122A away from the first passivation layer 121; the display substrate 100 further includes a first source-drain metal layer SD2 located on a side of the second flat layer 122B away from the first flat layer 122A.

[0259] It can be understood that through the above-mentioned setting, the second flat layer 122B is located between the first flat layer 122A and the first source and drain metal layer SD2. In this way, when a plurality of seventh openings (not shown in the figure) or a plurality of second grooves K2 are formed by over-etching the initial passivation layer, the etching process has relatively little impact on the first source and drain metal layer SD2.

[0260] The above is an exemplary description of patterning the first passivation layer 121 and the first planar layer 122A to form a plurality of first grooves 150 located in the insulating film group 120 and a plurality of first recesses 160. Other methods for forming a plurality of first grooves 150 and a plurality of first recesses 160 will be exemplarily introduced below.

[0261] As described above, when the gap E is formed by over-etching the initial passivation layer, in some examples, the initial planar layer may be the second initial pattern 122Aiii. In some other embodiments, the initial planar layer is the first initial planar layer 122Ai, which will be described below.

[0262] In some embodiments, a method of forming a plurality of first recesses 160 and a plurality of first trenches 150 includes U1 ˜ U7 .

[0263] U1: Fig. 15B As shown, a first preliminary planarization layer 122Ai is formed.

[0264] U2: forming an initial passivation layer on a side of the first initial planarization layer 122Ai away from the substrate 110 .

[0265] U3: Fig. 15C , Fig.16A and Fig.17A As shown, an etching process is used to pattern the initial passivation layer and the first initial flat layer 122Ai (see Fig. 15B ) to form a first passivation layer 121 and a first planar layer 122, the first passivation layer 121 includes a plurality of sixth openings Q7, and the first planar layer 122 includes a plurality of second grooves K2 and a plurality of gaps E.

[0266] In some examples, in the process of patterning the initial passivation layer to form a plurality of sixth openings Q7, one or more eighth openings Q8 are also formed in the first passivation layer 121; in the process of patterning the first initial flat layer 122Ai to form a plurality of second grooves K2 and a plurality of gaps E, one or more third grooves K3 and a plurality of first gaps J1 are also formed in the first flat layer 122, wherein the plurality of third grooves K3 are correspondingly connected to the plurality of eighth openings Q8. The groove depth of the second groove K2 is consistent with the groove depth of the third groove K3. The first gap J1 is a cavity located on the side of the first pattern 121a close to the substrate 110 and connected to the third groove K3.

[0267] U4: forming a third initial planar layer on a side of the first passivation layer 121 away from the first planar layer 122A.

[0268] U5: Fig.15D , Fig. 16B and Fig.17D As shown, the third initial flat layer is patterned to form a third flat layer 122C, the third flat layer 122C includes a plurality of fourth openings Q5 and a plurality of ninth openings Q9, the plurality of fourth openings Q5 are reused as a plurality of first grooves 160, and the plurality of ninth openings Q9 are correspondingly connected to the plurality of sixth openings Q7.

[0269] U6: Fig.15E , Fig. 16C and Fig.17E As shown, the reflective layer 130 is formed on a side of the third planar layer 122C away from the first passivation layer 121 .

[0270] U7: Fig.15F , Figure 15G , Fig.16D , Fig.16E , Fig.17F and Figure 17GAs shown, a patterned pixel defining layer 140 is formed on one side of the reflective layer 130 away from the first passivation layer 121 , and the pixel defining layer 140 includes a plurality of pixel openings Q1 and a plurality of fifth openings Q6 .

[0271] Based on the above method, in some embodiments, Figure 7 to Figure 9 As shown, the display substrate 100 further includes a third flat layer 122C. The third flat layer 122C is disposed on a side of the first passivation layer 121 away from the first flat layer 122A and includes a plurality of fourth openings Q5 arranged along the first direction X; the plurality of fourth openings Q5 are reused as a plurality of first grooves 160.

[0272] It can be understood that, in the first aspect, the method of forming a plurality of first grooves 160 and a plurality of first grooves 150 includes the settings of U1 to U7, and the gap E can be formed in the process of forming a plurality of seventh openings (not shown in the figure) or a plurality of second grooves K2 by overetching the initial passivation layer, so that the formation process of the gap E can be simplified. In the second aspect, through the above-mentioned settings, the bottom surface of the first groove 160 is farther away from the substrate 110 than the bottom surface of the second groove K2, so that the groove depth of the first groove 150 can be deeper, which can enhance the blocking effect of the first groove 150 on the common film layer to a certain extent, and can reduce the transmission of the lateral current between adjacent light-emitting devices 210.

[0273] In some embodiments, Fig. 15C , Fig.15D , Fig.16A and Fig. 16B As shown, the third initial planarization layer contacts the first passivation layer 121 , so that the material of the third initial planarization layer is also filled in the plurality of sixth openings Q7 , the plurality of second grooves K2 , and the plurality of gaps E. As shown in FIG.

[0274] In some examples, such as Fig. 15C , Fig.15D , Fig.16A and Fig. 16B As shown, the material of the third initial planar layer is also filled in one or more third grooves K3 and a plurality of first gaps J1 .

[0275] At this time, if Fig. 15C , Fig.15D , Fig.16A and Fig. 16B As shown, in the process of patterning the third initial planar layer by U5, the material of the third initial planar layer located in the plurality of sixth openings Q7, the plurality of second grooves K2, and the plurality of gaps E is removed. In the process of patterning the third initial planar layer, the material of the third initial planar layer located in one or more third grooves K3 and the plurality of first gaps J1 is retained to constitute a portion of the third planar layer 122C.

[0276] To this end, in some embodiments, such as Figure 7 and Figure 8 As shown, the third planar layer 122C further includes a third portion 122C1 located on a side of the first passivation layer 121 close to the substrate 110 ; an edge portion of the third portion 122C1 overlaps an edge portion of the first passivation layer 121 .

[0277] Here, the portion of the third initial flat layer filled in one or more third grooves K3 and the plurality of first gaps J1 is the third portion 122C1; the edge portion of the third portion 122C1 is the portion of the third initial flat layer filled in the plurality of first gaps J1. When the first gap J1 is a cavity located on the side of the first pattern 121a close to the substrate 110 and connected to the third groove K3, the edge portion of the third portion 122C1 overlaps with the edge portion of the first passivation layer 121.

[0278] It should be understood that in the above method, when the etching process is used in U3 to pattern the initial passivation layer and the first initial flat layer 122Ai, the portion of the initial passivation layer directly opposite to the first groove 160 along the second direction Y can be etched away or retained. The above two situations will be exemplarily described below.

[0279] In some embodiments, Fig.16A As shown, in the above method, when the etching process is used in U3 to pattern the initial passivation layer and the first initial flat layer 122Ai, the portion of the initial passivation layer that is directly opposite to the first groove 160 along the second direction Y is also etched away, so that the orthographic projection of the first passivation layer 121 on the substrate 110 is aligned with the reflective layer 130 (see Fig. 16C ) have no overlap in their orthographic projections onto the substrate 110.

[0280] At this time, if Fig. 16B As shown, during the process of forming the third preliminary planar layer in U4, the portion of the third preliminary planar layer that does not cover the first pattern 121a will contact the first planar layer 122A.

[0281] like Fig. 16B As shown, in the process of patterning the third initial planar layer in U5 , the bottom walls of the plurality of fourth openings Q5 formed are flush with the bottom wall of the third groove K3 , and both are located between the first pattern 121 a and the substrate 110 .

[0282] like Fig. 16CAs shown, during the process of forming the reflective layer 130 in U6, the material of the reflective layer 130 will be formed on the bottom walls of multiple fourth openings Q5 (i.e., the first grooves 160), so that the surface of the portion of the reflective layer 130 covering the bottom wall of the first groove 160 close to the substrate 110 is closer to the substrate 110 than the surface of the first passivation layer 121 close to the substrate.

[0283] In this case, in some embodiments, Figure 8 As shown, the orthographic projection of the first passivation layer 121 on the substrate 110 does not overlap with the orthographic projection of the reflective layer 130 on the substrate 110; the surface of the portion of the reflective layer 130 covering the bottom wall of the first groove 160 close to the substrate 110 is closer to the substrate 110 than the surface of the first passivation layer 121 close to the substrate.

[0284] It should be understood that, through the above arrangement, the beneficial effects that can be achieved by the display substrate 100 are the same as the beneficial effects that can be achieved when a plurality of first grooves 160 and a plurality of first trenches 150 are formed using the method including U1 to U7. First, the formation process of the gap E can be simplified, and second, the transmission of lateral current between adjacent light-emitting devices 210 can be reduced.

[0285] In some other embodiments, Fig. 15B and Fig. 15C As shown, in the above method, in U3, when the initial passivation layer and the first initial flat layer 122Ai are patterned by an etching process, a portion of the initial passivation layer that is directly opposite to the first groove 160 along the second direction Y is retained, so that the orthographic projection of the first passivation layer 121 on the substrate 110 and the orthographic projection of the reflective layer 130 on the substrate 110 are at least in the first groove 160 (see Figure 7 ) areas overlap.

[0286] At this time, if Fig.15D As shown, in the process of patterning the third initial planar layer in U5 , the bottom walls of the plurality of fourth openings Q5 formed are flush with the surface of the first pattern 121 a away from the substrate 110 .

[0287] like Fig.15E As shown, during the process of forming the reflective layer 130 in U6 , the material of the reflective layer 130 is formed on the bottom walls of the fourth openings Q5 (ie, the first grooves 160 ), so that the reflective layer 130 contacts the first passivation layer 121 (or the first pattern 121 a ).

[0288] To this end, in some embodiments, such as Figure 7As shown, the reflective layer 130 contacts the first passivation layer 121. The third flat layer 122C further includes a third portion 122C1 located on a side of the first passivation layer 121 close to the substrate 110;

[0289] It can be understood that, on the one hand, through the above arrangement, the beneficial effects that can be achieved by the display substrate 100 are the same as the beneficial effects that can be achieved when the plurality of first grooves 160 and the plurality of first trenches 150 are formed by the method including U1 to U7, that is, the formation process of the gap E can be simplified, and the transmission of the lateral current between adjacent light-emitting devices 210 can be reduced. On the other hand, through the above arrangement, the reflective layer 130 can be formed on the surface of the first passivation layer 121, compared with the reflective layer 130 formed on the third groove K3 (see Fig. 16C ) on the bottom wall, the surface of the formed reflective layer 130 close to the substrate 110 can be made smoother, and the bottom surface of the anode 211 can be made smoother, which is beneficial to improving the uniformity of light emission.

[0290] In some embodiments, in the above method, before U1, it also includes U1F.

[0291] U1F: Fig.15A As shown, a patterned first source-drain metal layer SD2 is formed on the substrate 110 .

[0292] In some examples, such as Fig. 15B , Fig. 15C and Fig.16A As shown, in the case where U1F is also included before U1, in U3, when an etching process is used to pattern the initial passivation layer and the first initial flat layer 122Ai, the parameters of the etching process can be controlled to make the etching depth shallower. For example, the surface of the first source and drain metal layer SD2 away from the substrate 110 is located between the surface of the second groove K2 close to the substrate 110 and the substrate 110. In this way, the etching process can avoid the first source and drain metal layer SD2 from being affected by the etching process.

[0293] To this end, in some embodiments, such as Figure 7 and Figure 8 As shown, the display substrate 100 further includes a first source-drain metal layer SD2. The first source-drain metal layer SD2 is located on a side of the first flat layer 122A close to the substrate 110; the first source-drain metal layer SD2 is away from the surface of the substrate 110 and closer to the substrate 110 than the surface of the first groove 150 close to the substrate 110.

[0294] It can be understood that, through the above configuration, the influence of the process of over-etching the initial passivation layer on the first source-drain metal layer SD2 can be reduced.

[0295] In some embodiments, in the above method, after U3 and before U4, U3A~U3C are also included.

[0296] U3A: Fig. 17B As shown, a patterned first source-drain metal layer SD2 is formed on one side of the first passivation layer 121 away from the first flat layer 122A, and the orthographic projections of the plurality of gaps E on the substrate 110 do not overlap with the orthographic projections of the first source-drain metal layer SD2 on the substrate 110, and a space is left between the two.

[0297] When the first planar layer 122 includes a plurality of first gaps J1 , the orthographic projections of the plurality of first gaps J1 on the substrate 110 do not overlap with the orthographic projections of the first source / drain metal layer SD2 on the substrate 110 , and a space is left between the two.

[0298] U3B: forming a second initial planarization layer on a side of the first source / drain metal layer SD2 away from the first passivation layer 121 .

[0299] In some examples, such as Fig. 17B and Fig. 17C As shown, the material of the second initial planarization layer is also filled in the plurality of sixth openings Q7 , the plurality of second grooves K2 , and the plurality of gaps E. As shown in FIG.

[0300] In some examples, such as Fig. 17B and Fig. 17C As shown, the material of the second initial planar layer is also filled in one or more third grooves K3 and a plurality of first gaps J1 .

[0301] U3C: Fig. 17B and Fig. 17C As shown, the second initial planar layer is patterned to form a second planar layer 122B. The second planar layer 122B includes a plurality of tenth openings Q10. The plurality of tenth openings Q10 are correspondingly connected to the plurality of sixth openings Q7.

[0302] In some examples, such as Fig. 17B and Fig. 17C As shown, in the process of patterning the second preliminary planarizing layer to form the second planarizing layer 122B, the material of the second preliminary planarizing layer located in the plurality of sixth openings Q7 , the plurality of second grooves K2 , and the plurality of gaps E is removed.

[0303] In some examples, such as Fig. 17B and Fig. 17C As shown, during the process of patterning the second initial planar layer, the material of the second initial planar layer 122Bi located in one or more third grooves K3 and a plurality of first gaps J1 is retained to constitute a portion of the second planar layer 122B.

[0304] It should be understood that Fig.17DAs shown, when U3A to U3C are included after U3 and before U4, in U4, the third initial planar layer is formed on a side of the second planar layer 122B away from the first source-drain metal layer SD2.

[0305] Therefore, in some embodiments, Fig. 9 As shown, the insulating film group 120 further includes a second flat layer 122B. The display substrate 100 further includes a first source-drain metal layer SD2. The second flat layer 122B and the first source-drain metal layer SD2 are located between the first flat layer 122A and the third flat layer 122C; the second flat layer 122B is further away from the substrate 110 than the first source-drain metal layer SD2. The surface SD2a of the first source-drain metal layer SD2 close to the substrate 110 is closer to the substrate 110 than the surface 121b of the first passivation layer 121 close to the substrate 110. The second flat layer 122B further includes a second portion 122B1 located on a side of the first passivation layer 121 close to the substrate 110; the edge portion of the second portion 122B1 overlaps the edge portion of the first passivation layer 121.

[0306] It should be understood that Fig.17A and Fig. 17B As shown, in U3, when one or more third grooves K3 are formed in the first flat layer 122, the first source-drain metal layer SD2 can be formed on the bottom surface of the first groove K3, so that the surface SD2a of the source-drain metal layer SD1 close to the substrate 110 is closer to the substrate 110 relative to the surface 121b of the first passivation layer 121 close to the substrate 110.

[0307] Moreover, if Fig.17A , Fig. 17B and Fig. 17C As shown, the portion of the second initial flat layer filled in one or more third grooves K3 and the plurality of first gaps J1 is the second portion 122B1; the edge portion of the second portion 122B1 is the portion of the second initial flat layer filled in the plurality of first gaps J1. In the case where the first gap J1 is a cavity located on the side of the first pattern 121a close to the substrate 110 and connected to the third groove K3, the edge portion of the second portion 122B1 overlaps the edge portion of the first passivation layer 121.

[0308] It should be understood that, through the above configuration, the beneficial effects that can be achieved by the display substrate 100 are the same as the beneficial effects that can be achieved when the multiple first recesses 160 and the multiple first grooves 150 are formed by the method including U1 to U7, and will not be repeated here.

[0309] The above is an exemplary description of the case where the initial planar layer is the first initial planar layer 122Ai. The following is an exemplary description of the relative position of the material of the pixel defining layer 140 and the first trench 150.

[0310] In some embodiments, Fig.14E and Fig.14F As shown, during the process of forming the initial pixel defining layer 140i in R6, the material of the initial pixel defining layer 140i is filled in the plurality of fourth grooves K4, and during the process of patterning the initial pixel defining layer 140i in R7, the material of the initial pixel defining layer 140i filled in the plurality of fourth grooves K4 is partially removed.

[0311] In some other embodiments, Fig. 12C and Fig.12D As shown, during the process of forming the initial pixel defining layer 140i at T6, the material of the initial pixel defining layer 140i is filled in the multiple second grooves K2 and the multiple gaps E, and during the process of patterning the initial pixel defining layer 140i at T7, the material of the initial pixel defining layer 140i filled in the multiple second grooves K2 and the multiple gaps E is partially removed.

[0312] In some other embodiments, during the process of U7 forming the patterned pixel defining layer 140, the material of the initial pixel defining layer 140i is filled in the multiple second grooves K2 and the multiple gaps E, and the material of the initial pixel defining layer 140i filled in the multiple second grooves K2 and the multiple gaps E is partially removed during the patterning process.

[0313] Based on the above situation, the material of the initial pixel defining layer 140i will be retained in the plurality of second grooves K2. Figure 4 and Figure 6 As shown, the pixel defining layer 140 includes a fourth portion 142 located on a side of the first passivation layer 121 close to the substrate 110 , and a side surface of the fourth portion 142 constitutes a portion of a sidewall of the first trench 150 .

[0314] It should be understood that, when the pixel defining layer 140 includes the fourth portion 142 , in the prepared display substrate, the size of the first groove 150 along the first direction X is smaller than the size of the second groove K2 .

[0315] In some examples, the gap G is formed before the pixel definition layer 140 is formed (eg, Figure 15C to Figure 15G Corresponding situation), and the ring side of the second groove K2 is provided with a gap G. At this time, when patterning the initial pixel defining layer 140i, the position of the opening area of ​​the mask can be controlled so that part of the material filled in the gap G is removed and the rest of the material filled in the gap G is retained to form the fourth portion 142.

[0316] In some examples, the pixel definition layer 140 is formed before the spacer G (eg, Figures 14A to 14F In this case, when the initial pixel defining layer 140i is patterned, the position of the opening area of ​​the mask can be controlled so that at least a portion of the edge of the first pattern 121a corresponding to the first groove 150 can be exposed after the initial pixel defining layer 140i is patterned (see Fig.14E ), so that if Fig.14F As shown, after the pixel defining layer 140 is formed, the edge of the exposed first pattern 121 a is over-etched to form a gap G.

[0317] It can be understood that, through the above configuration, the size of the first groove 150 along the first direction X can be made relatively small, which can improve the design space of the pixel defining layer 140 and is conducive to improving the pixel density.

[0318] In some embodiments, Figure 3 and Figure 6 As shown, a portion G of the first pattern 121a extending from the sidewall of the first trench 150 is away from the surface of the substrate 110, and has a first distance L3 from the bottom surface of the first trench 150 along the second direction Y. A surface of the insulating film group 120 away from the substrate 110 is away from the bottom surface of the first groove 160, and has a second distance L4 along the second direction Y. The first distance L3 is less than or equal to the second distance L4; the second direction Y is the stacking direction of the multi-layer planar layer 122.

[0319] It should be understood that, as described above, by setting the first distance L3, the common film layer formed on the portion G of the first pattern 121a extending from the sidewall of the first groove 150 can be disconnected from the common film layer formed in the first groove 150, and the first distance L3 needs to be greater than the first threshold. By setting the second distance L4, the light emitted by the light-emitting layer 213 of the light-emitting device 210 can be reflected on the surface of the reflective layer 130, and the second distance L4 needs to be greater than the second threshold. In some embodiments, the first threshold is less than the second threshold.

[0320] It can be understood that through the above-mentioned settings, the size of the gap E along the second direction Y can be made relatively small, and the size of the first groove 160 along the second direction Y can be made relatively large, so that the size of the gap E along the second direction Y and the size of the first groove 160 along the second direction Y can match the corresponding functions, and at the same time, the process difficulty of forming the gap E can be reduced.

[0321] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: substrate; An insulating film group, located on one side of the substrate, and comprising a first passivation layer and a plurality of flat layers stacked in layers; the plurality of flat layers comprising a first flat layer; The first passivation layer is located on a side of the first flat layer away from the substrate and in contact with the first flat layer; the surface of the insulating film group away from the substrate includes a plurality of first grooves arranged along a first direction; the first direction intersects with a stacking direction of the multiple flat layers; A reflective layer, located on a side of the insulating film group away from the substrate and covering the sidewall and bottom wall of the first groove; A pixel defining layer is located on a side of the reflective layer away from the insulating film group and includes a plurality of pixel openings; each of the plurality of first grooves surrounds one of the pixel openings; as well as, a plurality of first grooves; The first groove extends from the pixel definition layer to the first planar layer and is located between two adjacent first grooves among the plurality of first grooves; The first passivation layer includes a first pattern, the first pattern includes a portion extending from a sidewall of the first groove, the portion of the first pattern extending from the sidewall of the first groove is close to the surface of the substrate and has a gap with the bottom of the first groove.

2. The display substrate according to claim 1, characterized in that: The first planar layer includes a second pattern; The sidewall of the first groove includes a surface of the first pattern; or, A sidewall of the first groove includes a surface of the first pattern and a surface of the second pattern.

3. The display substrate according to claim 2, characterized in that: The first passivation layer includes a plurality of first openings arranged along the first direction, and the first openings constitute at least a portion of the first groove.

4. The display substrate according to claim 3, characterized in that: In the case where the first opening constitutes the first groove, a size of the first passivation layer along a second direction ranges from 0.5 μm to 1.5 μm, and the second direction is a stacking direction of the plurality of planar layers.

5. The display substrate according to claim 3, characterized in that: In the case where the first opening constitutes a part of the first groove, the first flat layer includes a plurality of first sub-grooves correspondingly connected to the plurality of first openings, and the first sub-grooves constitute the remaining part of the first groove except the first opening; or The first flat layer includes a plurality of second openings correspondingly connected to the plurality of first openings, and the second openings constitute the remaining portion of the first groove except the first openings; Wherein, the bottom surface of the first groove is closer to the substrate than the bottom surface of the first recess.

6. The display substrate according to claim 5, characterized in that: In the case where the first planar layer includes a plurality of first sub-grooves, a size of the first planar layer along a second direction ranges from 1.5 μm to 3.0 μm, and the second direction is a stacking direction of the plurality of planar layers.

7. The display substrate according to claim 2, characterized in that: The first planar layer further includes a plurality of third openings arranged along the first direction, and the first pattern and the reflective layer are sequentially arranged on the side walls and bottom walls of the third openings.

8. The display substrate according to claim 7, characterized in that: The pixel defining layer further includes a first portion located on a side of the first passivation layer close to the substrate; a surface of the first portion close to the substrate is flush with a bottom surface of the first groove; and an edge portion of the first portion overlaps an edge portion of the first passivation layer.

9. The display substrate according to claim 7, characterized in that: The insulating film group further includes a second flat layer located on a side of the first flat layer away from the first passivation layer; and the display substrate further includes a first source-drain metal layer located on a side of the second flat layer away from the first flat layer.

10. The display substrate according to claim 1, characterized in that: The insulating film group further includes: The third planar layer is disposed on a side of the first passivation layer away from the first planar layer, and includes a plurality of fourth openings arranged along the first direction; the plurality of fourth openings are reused as the plurality of first grooves.

11. The display substrate according to claim 10, characterized in that: The insulating film group further includes a second flat layer, and the display substrate further includes a first source-drain metal layer; the second flat layer and the first source-drain metal layer are located between the first flat layer and the third flat layer; the second flat layer is farther away from the substrate than the first source-drain metal layer; The surface of the first source-drain metal layer close to the substrate is closer to the substrate than the surface of the first passivation layer close to the substrate; The second planar layer further includes a second portion located on a side of the first passivation layer close to the substrate; an edge portion of the second portion overlaps an edge portion of the first passivation layer.

12. The display substrate according to claim 10, characterized in that: Also includes: A first source-drain metal layer, located on a side of the first planar layer close to the substrate; The first source-drain metal layer is far away from the surface of the substrate and closer to the substrate than the first trench is close to the surface of the substrate.

13. The display substrate according to claim 12, characterized in that: The orthographic projection of the first passivation layer on the substrate has no overlap with the orthographic projection of the reflective layer on the substrate; the surface of the portion of the reflective layer covering the bottom wall of the first groove close to the substrate is closer to the substrate than the surface of the first passivation layer close to the substrate.

14. The display substrate according to claim 12, characterized in that: The reflective layer contacts the first passivation layer; the third flat layer further comprises a third portion located on a side of the first passivation layer close to the substrate; an edge portion of the third portion overlaps an edge portion of the first passivation layer.

15. The display substrate according to any one of claims 1 to 14, characterized in that: The pixel defining layer includes a fourth portion located on a side of the first passivation layer close to the substrate, and a side surface of the fourth portion constitutes a portion of a sidewall of the first groove.

16. The display substrate according to any one of claims 1, 2 and 7 to 14, characterized in that: The portion of the first pattern extending from the sidewall of the first groove is away from the surface of the substrate and has a first distance from the bottom surface of the first groove along the second direction; the surface of the insulating film group away from the substrate and has a second distance from the bottom surface of the first groove along the second direction; The first distance is less than or equal to the second distance; and the second direction is the stacking direction of the multiple planar layers.

17. A display panel, characterized in that: The display device comprises a plurality of light emitting devices and the display substrate as claimed in any one of claims 1 to 16, wherein the light emitting device is located in one of the pixel openings.

18. The display panel according to claim 17, characterized in that: The light emitting device comprises: at least two light-emitting layers; and, A charge generating unit is located between two adjacent light-emitting layers; The charge generating units of the plurality of light-emitting devices are of the same layer and material and constitute a common unit; the common unit comprises a fifth portion and a sixth portion, the fifth portion is located at a portion of the first pattern extending from the sidewall of the first groove, on one side along the second direction; the sixth portion is located in the first groove, and on one side of the first pattern along the second direction; the second direction is the stacking direction of the plurality of planar layers; Wherein, along the second direction, there is a distance between the fifth portion and the sixth portion.

Images