Display device

Abstract

The present disclosure may provide a display device. According to an embodiment, the display device includes a substrate including a display area and a pad area. The display device includes a data conductive layer disposed in the pad area and on the substrate. The data conductive layer includes a data base layer, a data main metal layer disposed on the data base layer, a first data capping layer disposed on the data main metal layer, a second data capping layer disposed on the first data capping layer, and a plurality of metal aggregates disposed on the second data capping layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0074037, filed on June 9, 2023, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0004] As multimedia is developed, display devices are becoming more and more important. In response, various types of display devices such as, for example, organic light emitting display devices (OLEDs) and liquid crystal display devices (LCDs) are being used.

[0005] The device for displaying an image of the display device may include a display panel (such as, for example, an organic light emitting display panel or a liquid crystal display panel). In the display panel, the light emitting display panel may include a light emitting element. For example, a light emitting diode (LED) may include an organic light emitting diode using an organic material as a fluorescent material and an inorganic light emitting diode using an inorganic material as a fluorescent material, etc. Utility Model Content

[0006] Aspects and features of embodiments of the present disclosure provide a display device including a wiring structure that improves bonding characteristics of a pad region of the display device.

[0007] However, aspects of the present disclosure are not limited to the examples set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given herein.

[0008] According to an embodiment, a display device includes a substrate including a display area and a pad area, and a data conductive layer arranged in the pad area and on the substrate, wherein the data conductive layer includes a data base layer, a data main metal layer arranged on the data base layer, a first data capping layer arranged on the data main metal layer, a second data capping layer arranged on the first data capping layer, and a plurality of metal aggregates arranged on the second data capping layer.

[0009] A plurality of metal aggregates are formed from the inert metal.

[0010] The inert metal includes at least one metal selected from the group consisting of silver (Ag), gold (Au), and platinum (Pt).

[0011] The second data capping layer is formed of a transparent conductive oxide.

[0012] The second data capping layer includes indium gallium zinc oxide (IGZO).

[0013] The second data capping layer has a to about Thickness.

[0014] The first data capping layer includes titanium nitride (TiN).

[0015] The first data capping layer has a to about Thickness.

[0016] The data main metal layer includes aluminum (Al).

[0017] The data base layer includes titanium (Ti).

[0018] The data main metal layer is thicker than each of the data base layer, the first data capping layer and the second data capping layer, or thicker than the total thickness of the data base layer, the first data capping layer and the second data capping layer.

[0019] The data main metal layer has to Thickness.

[0020] The data base layer has to Thickness.

[0021] The substrate is any one of a rigid substrate, a flexible substrate and an ultra-thin glass (UTG) substrate.

[0022] According to an embodiment, a method for manufacturing a display device includes sequentially forming a patterned data base layer, a data main metal layer, a first data capping layer, and a second data capping layer on a substrate, forming a metal material layer on the second data capping layer, and forming a metal aggregate by applying heat to the metal material layer so that the metal included in the metal material layer aggregates.

[0023] The metallic material layer includes an inert metal.

[0024] The inert metal includes at least one selected from the group consisting of silver (Ag), gold (Au), and platinum (Pt).

[0025] Wherein, when the metal included in the metal material layer is aggregated to form the metal aggregate by applying heat of a preset temperature to the metal material layer, the preset temperature is in the range of 100°C to 250°C.

[0026] The metal aggregate includes at least one metal selected from the group consisting of silver (Ag), gold (Au), and platinum (Pt).

[0027] The second data capping layer includes indium gallium zinc oxide (IGZO), the first data capping layer includes titanium nitride (TiN), the data main metal layer includes aluminum (Al), and the patterned data base layer includes titanium (Ti).

[0028] According to example embodiments described herein, a display device having improved bonding characteristics of a pad region can be realized using a technique implemented with relatively low pressure and without a conductive ball. According to aspects of the present disclosure described herein, the technique includes heat treating a metal (e.g., a metal material included in a metal material layer) at a relatively low temperature to form metal aggregates on a data conductive layer.

[0029] However, the effects of the present disclosure are not limited to the aforementioned effects, and include various other effects in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0031] Figure 2 Based on Figure 1 Schematic cross-sectional view of a display device.

[0032] Figure 3 is a schematic plan view of a circuit layer of a first display substrate of a display device according to an embodiment.

[0033] Figure 4 is an equivalent circuit diagram of a pixel of a display device according to an embodiment.

[0034] Figure 5 is an equivalent circuit diagram of a pixel of a display device according to another embodiment.

[0035] Figure 6 is an equivalent circuit diagram of a pixel of a display device according to another embodiment.

[0036] Figure 7 is a cross-sectional view of a first display substrate of a display device according to an embodiment.

[0037] Figure 8 for Figure 7 Magnified view of area A.

[0038] Fig. 9 To illustrate the setting Figure 8 A plan view of the metal aggregates on the second data capping layer.

[0039] Figures 10 to 12 For manufacturing Figure 7 A cross-sectional view of a process for forming a data conductive layer in a third region of a display device.

[0040] Fig.13 is a schematic diagram for explaining the bonding characteristics of the data conductive layer.

[0041] Fig.14 is an electron micrograph of the surface of the data conductive layer having metal aggregates.

[0042] Fig.15 is an electron micrograph of a cross section of a data conductive layer having metal aggregates. DETAILED DESCRIPTION

[0043] In the following description, for the purpose of explanation, many specific details are stated in order to provide a thorough understanding of various embodiments or implementations of the utility model. As used herein, "embodiment" and "aspect" are interchangeable words as non-limiting examples of the device or method disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Here, it should be understood that the various embodiments described in this article are not necessarily exclusive and do not limit the present disclosure. For example, the specific shape, configuration and characteristics of the embodiment can be used or implemented in another embodiment.

[0044] When an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, connected to, or bonded to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. When an element is referred to as being "in contact," "contacting," etc., with another element, the element may be "electrically in contact" or "physically in contact" with the other element or may be "indirectly in contact" or "directly in contact" with the other element.

[0045] Throughout the application, the same reference numerals or symbols denote the same elements. Further, in the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes.

[0046] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0047] As used herein, the term "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0048] Unless otherwise indicated, the illustrated embodiments should be understood to provide exemplary features of the present invention. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0049] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an ideal or overly formal sense unless clearly defined in the specification.

[0050] Figure 1 is a schematic plan view of a display device 1 according to an embodiment.

[0051] refer to Figure 1 The display device 1 according to the embodiment may be applied to various consumer electronic devices or Internet of Things (IoT) devices, such as, for example, smart phones, cellular phones, tablet personal computers, personal digital assistants (PDAs), portable multimedia players (PMPs), televisions, game devices, watch-type electronic devices, head-mounted displays, monitors of personal computers, laptop computers, car navigation, car instrument panels, digital cameras, video cameras, billboards (e.g., exterior billboards), medical devices, inspection devices, refrigerators, washing machines, etc. A television is described herein as an example of the display device 1, and the television may have a high resolution or an ultra-high resolution (e.g., HD, UHD, 4K, 8K, etc.).

[0052] In addition, the display device 1 according to some embodiments may be variously classified based on how the display device 1 displays. For example, the classification of the display device 1 may include an organic light-emitting display device (OLED), an inorganic light-emitting display device (inorganic LED), a quantum dot light-emitting display device (QED), a micro-LED display device (micro-LED), a nano-LED display device (nano-LED), a plasma display device (PDP), a field emission display device (FED), a cathode ray display device (CRT), a liquid crystal display device (LCD), and an electrophoretic display device (EPD), etc. In the examples described herein, an organic light-emitting display device is described as an example of the display device 1, and unless otherwise indicated, the organic light-emitting display device applied in the example embodiments of this article will be abbreviated or simply referred to as a display device. However, the embodiment of the display device 1 is not limited to the organic light-emitting display device, and within the scope of the shared technical idea, other display devices listed herein or known in the art may be used as the display device 1.

[0053] The display device 1 according to the embodiment may have a quadrilateral shape, for example, a rectangular shape in a plan view. In the example, the display device 1 is a TV, and the display device 1 is arranged so that the long side of the rectangular shape is in the horizontal direction. However, aspects of the present disclosure are not limited thereto. For example, the long side may be set in the vertical direction, and the display device 1 may be rotatably mounted so that the long side is variably set in the horizontal direction or the vertical direction.

[0054] The display device 1 may include a display area DPA and a non-display area NDA. The display area DPA may be an active area in which a video is displayed. The display area DPA may have a square shape similar to the rectangular shape of the display device 1 in a plan view, but is not limited thereto. For example, in a plan view, the shape of the display area DPA (e.g., a square shape or a rectangular shape, etc.) may correspond to the shape of the display device 1 (e.g., a square shape or a rectangular shape, etc.).

[0055] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix direction. The shape of each pixel PX may be a rectangle or a square in a plan view, but is not limited thereto. For example, the shape of each pixel PX may be a rhombus with each side tilted toward one side of the display device 1. The plurality of pixels PX may include a plurality of color pixels PX. For example, the plurality of pixels PX may include a first color pixel PX capable of emitting red light, a second color pixel PX capable of emitting green light, and a third color pixel PX capable of emitting blue light, but is not limited thereto. In some embodiments, each color pixel PX may be arranged alternately in a stripe type or a pentile type.

[0056] The non-display area NDA may be disposed on the periphery of the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may be in a rectangular shape, and the non-display area NDA may be arranged adjacent to four sides of the display area DPA. The non-display area NDA may form a frame of the display device 1.

[0057] A driving circuit or a driving element for driving the display area DPA may be provided in the non-display area NDA. In an embodiment, the pad portion is provided on the display substrate of the display device 1 and provided at a position disposed at a first long side ( Figure 1 The first non-display area NDA adjacent to the lower side of the second long side ( Figure 1 In the second non-display area NDA adjacent to the upper side of the display device 1, an external device EXD may be mounted on the pad electrode of the pad portion. Examples of the external device EXD include a connection film, a printed circuit board, a driver chip DIC, a connector, and a wiring connection film. Figure 1 In the third non-display area NDA adjacent to the left side of the display device 1, a scan driving unit SDR and the like may be disposed. In some examples, the scan driving unit SDR may be directly formed on the display substrate of the display device 1.

[0058] Figure 2 Based on Figure 1 Schematic cross-sectional view of a display device 1.

[0059] Reference Figure 2 In the illustrated example, the display device 1 is a top emission type display device in which light L is emitted in a direction opposite to the direction of the first substrate 110 on which the light emitting layer EML is formed (toward the second substrate 210). However, the embodiments of the present disclosure are not limited thereto, and the display device 1 may be a bottom emission type display device capable of emitting light L in the direction of the first substrate 110 on which the light emitting layer EML is formed. In some other embodiments, the display device 1 may be a double-sided emission type display device capable of emitting light L in both the direction of the first substrate 110 and the direction of the second substrate 210.

[0060] refer to Figure 2 The display device 1 may include a first display substrate 100 , a second display substrate 200 opposite to the first display substrate 100 , and a filling layer 300 bonding the first display substrate 100 and the second display substrate 200 .

[0061] The first display substrate 100 may include a first substrate 110. The first substrate 110 may be an insulating substrate. The first substrate 110 may include a transparent material. For example, the first substrate 110 may include a transparent insulating material (such as, for example, glass or quartz, etc.). The first substrate 110 may be a rigid substrate. However, the first substrate 110 is not limited thereto. For example, the first substrate 110 may include plastic (such as, for example, polyimide, etc.), and the first substrate 110 may have a flexible property that enables the first substrate 110 to be bent, folded, or rolled up. In some embodiments, the first substrate 110 may be an ultra-thin glass (UTG) substrate.

[0062] refer to Figure 1 and Figure 2 , a plurality of pixel electrodes PXE may be disposed on the first substrate 110. Each of the plurality of pixel electrodes PXE may be disposed for a given pixel PX. The pixel electrodes PXE of adjacent pixels PX may be separated from each other. For example, each pixel electrode PXE may be spaced apart from an adjacent pixel electrode PXE. A circuit layer CCL for driving the pixel PX may be disposed on the first substrate 110. The circuit layer CCL may be disposed between the first substrate 110 and the pixel electrode PXE. A detailed description of the circuit layer CCL will be described later in this document.

[0063] Each pixel electrode PXE may be a first electrode of a light emitting diode (such as, for example, an anode electrode). The pixel electrode PXE may have a multi-layer stacked structure having: indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) of one or more material layers having a high work function (e.g., a work function greater than or equal to a target threshold); and one or more reflective material layers (such as, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof). In some embodiments, the material layer having a high work function may be disposed on the reflective material layer and close to the light emitting layer EML, respectively (e.g., in the third direction DR3). In some examples, the pixel electrode PXE may have ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO multilayer structure, but not limited thereto.

[0064] The pixel defining layer PDL may be disposed on one side (e.g., the upper side) of the first substrate 110 along the boundary of the pixel PX. The pixel defining layer PDL may be disposed on the pixel electrode PXE and may include an opening exposing the pixel electrode PXE. The emission area EMA may be separated from the non-emission area NEM by the pixel defining layer PDL and the opening included in the pixel defining layer PDL. The pixel defining layer PDL may include an organic insulating material (such as, for example, a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, benzocyclobutene (BCB) or any combination thereof). In some alternative and / or additional embodiments, the pixel defining layer PDL may include an inorganic material.

[0065] The light-emitting layer EML may be disposed on the pixel electrode PXE exposed by the pixel defining layer PDL. In an embodiment in which the display device 1 is an organic light-emitting display device, the light-emitting layer EML may include an organic layer including an organic material. In some cases, the organic layer may include an organic light-emitting layer and may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer as an auxiliary layer to assist in light emission. In another embodiment in which the display device 1 is a micro-LED display device or a nano-LED display device, etc., the light-emitting layer EML may include an inorganic material (such as, for example, an inorganic semiconductor).

[0066] In some embodiments, the light-emitting layer EML may have a series structure including a plurality of organic light-emitting layers stacked in a thickness direction (e.g., a third direction DR3) and a charge generation layer disposed between the stacked organic light-emitting layers. Each of the overlapping organic light-emitting layers may emit light of the same wavelength. In some other embodiments, the organic light-emitting layers may emit light of different wavelengths. In some embodiments, in a pixel PX, at least some layers of the light-emitting layer EML of the pixel PX may be separated or different from at least some layers of the light-emitting layer EML of an adjacent pixel PX. For example, the series structure of the light-emitting layer EML of the pixel PX may be different from the series structure of the light-emitting layer EML of the adjacent pixel PX (e.g., the difference is due to differences in one or more layers).

[0067] In an embodiment, the wavelength of light emitted by the light emitting layer EML may be the same for each color pixel PX. For example, the light emitting layer EML of each color pixel PX may emit blue light or ultraviolet light, and the color control structure described later below may include a wavelength conversion layer WCL. In an example, based on the wavelength conversion layer WCL, the color of each pixel PX may be displayed.

[0068] In other embodiments, the wavelength of light emitted by the light emitting layer EML may be different for each color pixel PX. For example, the light emitting layer EML of the first color pixel PX may emit light of a first color, the light emitting layer EML of the second color pixel PX may emit light of a second color, and the light emitting layer EML of the third color pixel PX may emit light of a third color.

[0069] The common electrode CME may be disposed on the light emitting layer EML. In some embodiments, the common electrode CME contacts the light emitting layer EML and contacts an upper surface of the pixel defining layer PDL.

[0070] The common electrode CME may be connected to each pixel PX without distinction. For example, the common electrode CME may be common or shared across the pixels PX. In an example, the common electrode CME may be a surface electrode disposed across the surface of each pixel PX without distinction of the pixels PX. The common electrode CME may be a second electrode (such as, for example, a cathode electrode) of the light emitting diode.

[0071] The common electrode CME may include a material layer having a small work function (e.g., a work function lower than a target threshold) (e.g., Li, Ca, Al, Mg, Ag, Pt, Pd, Ni, Au Nd, Ir, Cr, Ba, or a compound thereof, or a mixture thereof (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al). In some embodiments, the common electrode CME may further include a transparent metal oxide layer disposed on the material layer having a small work function.

[0072] The pixel electrode PXE, the light emitting layer EML, and the common electrode CME may be formed together and constitute a light emitting device (eg, an organic light emitting device). Light emitted from the light emitting layer EML may be emitted in an upward direction through the common electrode CME.

[0073] The thin film encapsulation structure 170 may be disposed on the common electrode CME. The thin film encapsulation structure 170 may include at least one thin film encapsulation layer. For example, the thin film encapsulation layer may include a first inorganic film 171, an organic film 172, and a second inorganic film 173. The first inorganic film 171 and the second inorganic film 173 may each include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y In some embodiments, the first inorganic film 171 and / or the second inorganic film 173 may each include silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N yThe organic film 172 may include an organic insulating material (such as, for example, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) or any combination thereof).

[0074] The second display substrate 200 may be disposed on top of the thin film encapsulation structure 170 and face the thin film encapsulation structure 170. The second substrate 210 of the second display substrate 200 may include a transparent material. In some embodiments, the second substrate 210 may include a transparent insulating material (such as, for example, glass or quartz, etc.). The second substrate 210 may be a rigid substrate. However, the second substrate 210 is not limited thereto, and the second substrate 210 may include plastic (such as, for example, polyimide, etc.), and may have a flexible property that enables the second substrate 210 to be bent, folded, or rolled up.

[0075] In some embodiments, the second substrate 210 may be the same substrate as the first substrate 110. For example, the second substrate 210 may have the same material, thickness, or transmittance as the first substrate 110. In some other embodiments, the second substrate 210 may have a different material, thickness, or transmittance than the first substrate 110. For example, the second substrate 210 may have a transmittance higher than that of the first substrate 110. The second substrate 210 may be thicker than the first substrate 110, or the second substrate 210 may be thinner than the first substrate 110.

[0076] The light blocking member BML may be disposed on a surface of the second substrate 210 facing the first substrate 110 along a boundary of the pixel PX. The light blocking member BML may overlap the pixel defining layer PDL of the first display substrate 100 and may be located in the non-emission area NEM. The light blocking member BML may include an opening exposing one surface of the second substrate 210 overlapping the emission area EMA. The light blocking member BML may be formed in a lattice shape in a plan view.

[0077] The light blocking member BML may include an organic material. The light blocking member BML may absorb external light, which may reduce color distortion due to external light reflection. In some embodiments, the light blocking member BML may prevent light emitted from the light emitting layer EML from penetrating into adjacent pixels PX.

[0078] In an embodiment, the light blocking member BML may absorb light of all visible wavelengths. The light blocking member BML may include a light absorbing material. For example, the light blocking member BML may be formed of a material used as a black matrix of the display device 1 .

[0079] In another embodiment, the light blocking member BML may absorb light of a specific wavelength among light of visible wavelengths and transmit light of another specific wavelength. For example, the light blocking member BML may be formed of the same material as the material of a single color filter layer CFL (e.g., CFL1, CFL2, or CFL3). Specifically, in an example embodiment, the light blocking member BML may be formed of the same material as the material of the third color filter layer CFL3 described later in this document. In some embodiments, the light blocking member BML may be formed integrally with the third color filter layer CFL3. In some example implementations, the third color filter layer CFL3 may be a blue color filter layer. In some embodiments, the light blocking member BML may be omitted. In an example in which the light blocking member BML is omitted, the first capping layer 220 (to be described later in this document) may directly contact the second substrate 210.

[0080] The color filter layer CFL may be disposed on the surface of the second substrate 210 on which the light blocking member BML is disposed. For example, the color filter layer CFL and the light blocking member BML may be disposed on the lower surface (e.g., in the third direction DR3) of the second substrate 210. The color filter layer CFL may be disposed on the surface of the second substrate 210 exposed by the opening of the light blocking member BML. In some embodiments, the color filter layer CFL may also be partially disposed on the adjacent light blocking member BML.

[0081] The color filter layer CFL may include a first color filter layer CFL1 disposed in the first color pixel PX, a second color filter layer CFL2 disposed in the second color pixel PX, and a third color filter layer CFL3 disposed in the third color pixel PX. Each color filter layer CFL (e.g., the first color filter layer CFL1, the second color filter layer CFL2, the third color filter layer CFL3) may include a colorant (such as, for example, a dye or pigment that transmits light of a wavelength corresponding to the dye or pigment and absorbs light of other wavelengths). For example, the first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer. Although Figure 2 The example explains the case in which the adjacent color filter layers CFL are spaced apart from each other on the light blocking member BML, but the adjacent color filter layers CFL may at least partially overlap on the light blocking member BML.

[0082] The first capping layer 220 may be disposed on the color filter layer CFL. The first capping layer 220 may prevent impurities such as, for example, moisture or air from penetrating from the outside and thereby damaging or contaminating the color filter layer CFL. In some embodiments, the first capping layer 220 may prevent the colorant of the color filter layer CFL from diffusing to other components.

[0083] The first capping layer 220 may directly contact the surface of the color filter layer CFL ( Figure 2 The first capping layer 220 may be formed of an inorganic material. For example, the first capping layer 220 may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, and silicon oxynitride.

[0084] The partition wall PTL may be disposed on the first capping layer 220. The partition wall PTL may be disposed in the non-emission area NEM. The partition wall PTL may be disposed so that the partition wall PTL overlaps with the light blocking member BML. The partition wall PTL may include an opening exposing the color filter layer CFL. In some examples, the opening of the partition wall PTL may expose a portion of the first capping layer 220 overlapping with the color filter layer CFL. The partition wall PTL may include a photosensitive organic material, but is not limited thereto. In some examples, the partition wall PTL may further include a light blocking material.

[0085] The wavelength conversion layer WCL and / or the light-transmitting layer TPL may be disposed in the space exposed by the opening of the partition wall PTL. In some embodiments, the wavelength conversion layer WCL and the light-transmitting layer TPL may be formed by an inkjet process using the partition wall PTL as a dam. However, the formation of the wavelength conversion layer WCL and the light-transmitting layer TPL is not limited thereto.

[0086] In an example embodiment in which the light emitting layer EML of each pixel PX emits a third color, the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 disposed in the first color pixel PX (e.g., a first wavelength conversion pattern WCL1 for converting the third color into the first color as described later herein) and a second wavelength conversion pattern WCL2 disposed in the second color pixel PX (e.g., a second wavelength conversion pattern WCL2 for converting the third color into the second color as described later herein). In an example embodiment, the light-transmitting layer TPL may be disposed in the third color pixel PX.

[0087] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 disposed in the first base resin BRS1. The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 disposed in the second base resin BRS2. The light transmitting layer TPL may include a third base resin BRS3 and a scatterer SCP disposed therein.

[0088] The first to third base resins BRS1, BRS2 and BRS3 may each include a light-transmitting organic material. For example, the first to third base resins BRS1, BRS2 and BRS3 may each include an epoxy resin, an acrylic resin, a cardo resin or an imide resin. In some embodiments, the first to third base resins BRS1, BRS2 and BRS3 may each include at least one of an epoxy resin, an acrylic resin, a cardo resin and an imide resin. The first to third base resins BRS1, BRS2 and BRS3 may all be formed of the same material, but are not limited thereto. For example, the first to third base resins BRS1, BRS2 and BRS3 may be formed of different materials or by different combinations of materials.

[0089] The scatterer SCP may be metal oxide particles or organic particles. In some example embodiments, titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO) or tin oxide (SnO 2 ) as the metal oxide, and an acrylic resin or a urethane resin can be exemplified as the organic particle material.

[0090] In an example, the first wavelength conversion material WCP1 may convert light of a third color into light of a first color, and the second wavelength conversion material WCP2 may convert light of a third color into light of a second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be in the form of quantum dots, quantum rods, or phosphors. The quantum dots may include Group IV nanocrystals, Group II-VI compound nanocrystals, Group III-V compound nanocrystals, Group IV-VI compound nanocrystals, or a combination thereof. In some embodiments, the first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may further include a scatterer SCP to increase the wavelength conversion efficiency. For example, the scatterer SCP may control the emission paths of light incident on the first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2, respectively.

[0091] The light-transmitting layer TPL disposed in the third color pixel PX transmits light of the third color. For example, the light-transmitting layer TPL may transmit light (of the third color) incident on the light-transmitting layer TPL from the light-emitting layer EML while maintaining the wavelength of the light. The scatterer SCP of the light-transmitting layer TPL may control the emission path of light incident and emitted through the light-transmitting layer TPL. Figure 2 In the illustrated example, no wavelength converting material is present in the light-transmitting layer TPL.

[0092] The second capping layer 230 is disposed on the wavelength conversion layer WCL, the light-transmitting layer TPL, and the partition wall PTL. The second capping layer 230 may be formed of an inorganic material. The second capping layer 230 may include a material selected from the materials listed herein with reference to the first capping layer 220. The second capping layer 230 and the first capping layer 220 may be formed of the same material, but are not limited thereto. For example, the second capping layer 230 and the first capping layer 220 may be formed of different materials or a combination of different materials.

[0093] The filling layer 300 may be disposed between the first display substrate 100 and the second display substrate 200. The filling layer 300 may be disposed so that the filling layer 300 fills the space between the first display substrate 100 and the second display substrate 200, and the filling layer 300 may adhere and combine the first display substrate 100 and the second display substrate 200 to each other. The filling layer 300 may be disposed between the thin film encapsulation structure 170 of the first display substrate 100 and the second capping layer 230 of the second display substrate 200. In some embodiments, the filling layer 300 may be formed of a Si-based organic material or an epoxy-based organic material, etc., but is not limited thereto.

[0094] Hereinafter, example aspects of the circuit layer CCL of the display device 1 described herein will be described in detail.

[0095] Figure 3 FIG. 1 is a schematic plan view of a circuit layer of a first display substrate of a display device 1 according to an embodiment.

[0096] refer to Figure 2 and Figure 3 , a plurality of lines are disposed on the first substrate 110. The plurality of lines may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, a first power line ELVDL, etc. For example, although not shown, the plurality of lines may include lines other than the scan line SCL, the sensing signal line SSL, the data line DTL, the reference voltage line RVL, and the first power line ELVDL.

[0097] The scan line SCL and the sensing signal line SSL may extend in the first direction DR1. The scan line SCL and the sensing signal line SSL may be connected to the scan driving unit SDR. The scan driving unit SDR may include a driving circuit formed by a circuit layer CCL. The scan driving unit SDR may be disposed in the third non-display area NDA on the first substrate 110, but is not limited thereto. For example, the scan driving unit SDR may be disposed in the fourth non-display area NDA or in both the third non-display area NDA and the fourth non-display area NDA. The fourth non-display area NDA may be disposed adjacent to the second short side ( Figure 1The scan driving unit SDR may be connected to the signal connection line CWL, and at least one end of the signal connection line CWL may be connected to an external device ( Figure 1 For example, the technology described herein may include forming a pad WPD_CW in the first non-display area NDA and / or the second non-display area NDA for connecting the signal connection line CWL to an external device.

[0098] The data line DTL and the reference voltage line RVL may extend in a second direction DR2 intersecting the first direction DR1. The first power line ELVDL may include a portion extending in the second direction DR2. The first power line ELVDL may further include a portion extending in the first direction DR1. The first power line ELVDL may have a mesh structure, but is not limited thereto.

[0099] The wiring pad WPD may be disposed at one or more ends of each of the data line DTL, the reference voltage line RVL, and the first power line ELVDL. Each wiring pad WPD may be disposed in a pad area PDA of the non-display area NDA. In an embodiment, the wiring pad WPD_DT (hereinafter referred to as a "data pad") of the data line DTL may be disposed in a pad area PDA of a first non-display area NDA (e.g., a lower non-display area NDA), and the wiring pad WPD_RV (hereinafter referred to as a "reference voltage pad") of the reference voltage line RVL and the wiring pad WPD_ELVD (hereinafter referred to as a "first power pad") of the first power line ELVDL may be disposed in a pad area PDA of a second non-display area NDA (e.g., an upper non-display area NDA). As another example, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power pad WPD_ELVD may all be disposed in the same area (e.g., the first non-display area NDA). External device ( Figure 1 The external device EXD may be mounted on the wiring pad WPD as described herein. The external device EXD may be mounted on the wiring pad WPD by an anisotropic conductive film or ultrasonic bonding or the like.

[0100] Each pixel PX on the first substrate 110 includes a pixel driving circuit. The wiring described herein may pass through each pixel PX or around each pixel PX and apply a driving signal to each pixel driving circuit. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors in each pixel driving circuit may vary. Hereinafter, an example implementation is described in which the pixel driving circuit is a 3T1C structure including three transistors and one capacitor. The pixel driving circuit is not limited thereto, and aspects of the present disclosure support various other deformed pixel PX structures of the pixel driving circuit (such as, for example, a 2T1C structure, a 7T1C structure, a 6T1C structure, etc.).

[0101] Figure 4 is an equivalent circuit diagram of a pixel of the display device 1 according to the embodiment.

[0102] refer to Figure 2 and Figure 4 Each pixel PX of the display device 1 according to the embodiment includes three transistors DTR, STR1 and STR2 and one capacitor CST in addition to the light emitting element LE. The capacitor CST may be a storage capacitor, example aspects of which are described later herein.

[0103] The light emitting element LE emits light in response to the current supplied through the driving transistor DTR. The light emitting element LE may be implemented as an inorganic light emitting diode, an organic light emitting diode, a micro light emitting diode, a nano light emitting diode, or the like.

[0104] A first electrode (i.e., an anode electrode) of the light emitting element LE can be connected to a source electrode of the driving transistor DTR, and a second electrode (i.e., a cathode electrode) of the light emitting element LE can be connected to a second power line ELVSL that provides a low potential voltage (second power supply voltage) lower than a high potential voltage (first power supply voltage) of the first power line ELVDL.

[0105] The driving transistor DTR adjusts the current flowing from the first power line ELVDL supplied with the first power voltage to the light emitting element LE according to the voltage difference between the gate electrode and the source electrode of the driving transistor DTR. The gate electrode of the driving transistor DTR may be connected to the first electrode of the first transistor STR1, the source electrode of the driving transistor DTR may be connected to the first electrode of the light emitting element LE, and the drain electrode of the driving transistor DTR may be connected to the first power line ELVDL to which the first power voltage is applied.

[0106] The first transistor STR1 is turned on by a scan signal on the scan line SCL. In an example, in the on state, the first transistor STR1 connects the data line DTL to the gate electrode of the drive transistor DTR. The gate electrode of the first transistor STR1 may be connected to the scan line SCL, the first electrode of the first transistor STR1 may be connected to the gate electrode of the drive transistor DTR, and the second electrode of the first transistor STR1 may be connected to the data line DTL.

[0107] The second transistor STR2 is turned on by the sensing signal on the sensing signal line SSL, and in the turned-on state, the second transistor STR2 connects the initialization voltage line to the source electrode of the driving transistor DTR. The gate electrode of the second transistor ST2 may be connected to the sensing signal line SSL, the first electrode of the second transistor STR2 may be connected to the initialization voltage line, and the second electrode of the second transistor STR2 may be connected to the source electrode of the driving transistor DTR.

[0108] In an embodiment, the first electrode of each of the first transistor STR1 and the second transistor STR2 may be a source electrode, and the second electrode of each of the first transistor STR1 and the second transistor STR2 may be a drain electrode, but is not limited thereto. For example, the first electrode of each of the first transistor STR1 and the second transistor STR2 may be a drain electrode, and the second electrode of each of the first transistor STR1 and the second transistor STR2 may be a source electrode.

[0109] The capacitor CST is formed between the gate electrode and the source electrode of the driving transistor DTR. Figure 4 In the example of FIG. 4 , the capacitor CST is a storage capacitor capable of storing a voltage difference between a gate voltage of the driving transistor DTR and a source voltage of the driving transistor DTR.

[0110] The driving transistor DTR and the first and second transistors STR1 and STR2 may be formed as thin film transistors. In some aspects, although the Figure 6 The driving transistor DTR and the first transistor STR1 and the second transistor STR2 are described as N-type MOSFETs (metal oxide semiconductor field effect transistors), but the embodiments of the present disclosure are not limited thereto. For example, the driving transistor DTR and the first transistor STR1 and the second transistor STR2 may each be a P-type MOSFET. In some other embodiments, one or more of the driving transistor DTR and the first transistor STR1 and the second transistor STR2 may be an N-type MOSFET, and the rest may be a P-type MOSFET.

[0111] Figure 5 is an equivalent circuit diagram of a pixel of a display device 1 according to another embodiment.

[0112] refer to Figure 5 The first electrode of the light emitting element LE may be connected to the first electrode of the fourth transistor STR4 and the second electrode of the sixth transistor STR6, and the second electrode of the light emitting element LE may be connected to the second power line ELVSL. The parasitic capacitor Cel may be formed between the first electrode and the second electrode of the light emitting element LE.

[0113] In addition, the first transistor STR1 and the third transistor STR3 may include a plurality of sub-transistors. Figure 5 In the embodiment, the first transistor STR1 may include sub-transistors ST1-1 and ST1-2, and the third transistor STR3 may include sub-transistors ST3-1 and ST3-2. Gate electrodes of the sub-transistors ST1-1 and ST1-2 of the first transistor STR1 are connected to the write scan line GWL and gate electrodes of the sub-transistors ST3-1 and ST3-2 of the third transistor STR3 are connected to the initialization scan line GIL, a gate electrode of the fourth transistor STR4 is connected to the control scan line GSL, and gate electrodes of the fifth transistor STR5 and the sixth transistor STR6 are connected to the light emitting line EL, but the embodiment is not limited thereto.

[0114] Each pixel PX (see Figure 1 ) includes a driving transistor DTR, a switching element and a capacitor CST. The switching element includes first to sixth transistors STR1, STR2, STR3, STR4, STR5 and STR6.

[0115] The driving transistor DTR includes a gate electrode, a first electrode, and a second electrode as described herein. The driving transistor DTR controls a drain-source current (Ids) (hereinafter referred to as "driving current") flowing between the first electrode and the second electrode of the driving transistor DTR based on a data voltage applied to the gate electrode of the driving transistor DTR.

[0116] The capacitor CST is formed between the second electrode of the driving transistor DTR and the first power line ELVDL. One electrode of the capacitor CST may be connected to the second electrode of the driving transistor DTR, and the other electrode may be connected to the first power line ELVDL.

[0117] When the first electrode of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5 and STR6 and the driving transistor DTR is a source electrode, the second electrode of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5 and STR6 and the driving transistor DTR may be a drain electrode. Alternatively, if the first electrode of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5 and STR6 and the driving transistor DTR is a drain electrode, the second electrode of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5 and STR6 and the driving transistor DTR may be a source electrode.

[0118] The active layer of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5 and STR6 and the driving transistor DTR may be formed of any one of polycrystalline silicon, amorphous silicon and an oxide semiconductor. In an example in which the semiconductor layer of each of the first to sixth transistors STR1, STR2, STR3, STR4, STR5 and STR6 and the driving transistor DTR is formed of polycrystalline silicon, the process for forming the semiconductor layer may be a low temperature polycrystalline silicon (LTPS) process.

[0119] In some embodiments, although in reference to Figure 5 In the described example, the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 and the driving transistor DTR are described as each being a P-type MOSFET (metal oxide semiconductor field effect transistor), but aspects of the present disclosure are not limited thereto. For example, aspects of the present disclosure support an implementation in which any one or all of the first to sixth transistors STR1, STR2, STR3, STR4, STR5, and STR6 and the driving transistor DTR can be formed as an N-type MOSFET.

[0120] In some embodiments, considering the characteristics of the driving transistor DTR and the characteristics of the light emitting element LE, etc., aspects of the present disclosure support setting a first power supply voltage of the first power line ELVDL, a second power supply voltage of the second power line ELVSL, and a third power supply voltage of the third power line VIL.

[0121] Figure 6 is an equivalent circuit diagram of a pixel of a display device 1 according to another embodiment.

[0122] according to Figure 6 The display device 1 (see Figure 1 ) includes Figure 4 and Figure 5The display device 1 (see Figure 1 ) aspects, and repeated descriptions of the same elements are omitted for the sake of brevity. Figure 6 The implementation method and Figure 5 The embodiment of is different in that the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5, and the sixth transistor STR6 are formed as P-type MOSFETs, and the first transistor STR1 and the third transistor STR3 are formed as N-type MOSFETs.

[0123] refer to Figure 6 , the active layer of each of the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 formed as a P-type MOSFET can be formed of polysilicon, and the active layer of each of the first transistor STR1 and the third transistor STR3 formed as an N-type MOSFET can be formed of an oxide semiconductor.

[0124] Figure 6 and Figure 5 The embodiment of is different in that the gate electrode of the second transistor STR2 and the gate electrode of the fourth transistor STR4 are connected to the write scan line GWL, and the gate electrode of the first transistor STR1 is connected to the control scan line GSL. Figure 6 In the example in , the first transistor STR1 and the third transistor STR3 are formed as N-type MOSFETs, so that a scan signal with a gate "high" voltage can be applied to the control scan line GSL and the initialization scan line GIL. In some aspects, since the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5, and the sixth transistor STR6 are formed as P-type MOSFETs, a scan signal with a gate "low" voltage can be applied to the write scan line GWL and the light emitting element LE.

[0125] It should be noted that the exemplary equivalent circuit diagram of the pixel PX according to the embodiment of the present disclosure described herein is not limited to the reference Figures 4 to 6 The equivalent circuit diagram of the pixel PX according to the embodiment of the present disclosure can be obtained by a person skilled in the art. Figures 4 to 6 In addition to or in addition to the embodiments shown in Figures 4 to 6 The present invention may be formed by other known or appropriate circuit structures other than the embodiments shown in the drawings.

[0126] Figure 7 is a cross-sectional view of a first display substrate of a display device 1 according to an embodiment. Figure 8 for Figure 7 Magnified view of area A. Fig. 9 To illustrate the setting Figure 8 A plan view of the metal aggregates on the second data capping layer.

[0127] exist Figure 7 , a cross section of a portion of the display area DPA and a cross section of a portion of the non-display area NDA are shown together. A cross section of the transistor region TRR and the capacitor region CPR of the pixel is shown in the cross section of the display area DPA, and a cross section of the pad area PDA is shown in the cross section of the non-display area NDA. Figure 7 The transistor region TRR shows where three transistors ( Figure 4 In the region where the driving transistor DTR is set, STR1, STR2 and DTR are located. Figure 7 In the figure, it is mainly shown Figure 2 The circuit layer CCL of the first display substrate 100 and the pixel defining layer PDL are shown in the stacked structure view, while the first display substrate 100 is omitted (see FIG. Figure 2 ) other characteristics. Figure 8 The pad area PDA (see FIG. Figure 7 ) in the wiring pad WPD (see Figure 7 ).

[0128] refer to Figure 2 and Figure 7 The circuit layer CCL includes a semiconductor layer 150, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate 110. The semiconductor layer 150 may include an oxide semiconductor. The plurality of conductive layers may include a bottom metal layer 120, a gate line GCL, a data conductive layer DCL, and a pixel electrode PXE. The plurality of insulating layers may include a buffer layer 161, a gate insulating layer 162, an interlayer insulating layer 163, a passivation layer 164, and a through-hole layer 165.

[0129] In some embodiments, the bottom metal layer 120 may be disposed on the first substrate 110. The bottom metal layer 120 may be a light blocking layer for protecting the semiconductor layer 150 from lower light or internal light. The bottom metal layer 120 may have a patterned shape. The bottom metal layer 120 may be disposed in the transistor region TRR. The semiconductor layer 150 may be disposed on the bottom metal layer 120, and the bottom metal layer 120 may overlap with the semiconductor layer 150 so that the bottom metal layer 120 covers the lower portion of the semiconductor layer 150. The bottom metal layer 120 may be disposed below the semiconductor layer 150 so that the bottom metal layer 120 covers at least the channel region of the semiconductor layer 150 or covers the entire semiconductor layer 150. The bottom metal layer 120 may be electrically connected to the source electrode SEL of the driving transistor DTR through the first contact hole CNT1, and the electrical connection may suppress the change in the voltage of the driving transistor DTR. The bottom metal layer 120 may be formed of a low-reflection material capable of reducing the reflection of light. The bottom metal layer 120 may be formed of, for example, a Ti / Cu double layer in which a titanium layer and a copper layer are stacked. However, the embodiments of the present disclosure are not limited thereto, and the bottom metal layer 120 may be formed of a Ti / Cu / Ti triple layer or a Cu single layer.

[0130] The buffer layer 161 may be disposed on the bottom metal layer 120. The buffer layer 161 may be disposed to cover the entirety of the bottom metal layer 120. The buffer layer 161 may be disposed to cover the entire surface of the first substrate 110 on which the bottom metal layer 120 is formed. The buffer layer 161 may include silicon nitride, silicon oxide, or silicon oxynitride. In some embodiments, the buffer layer 161 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In an embodiment, the buffer layer 161 may include SiN x / SiO x Double layer.

[0131] The semiconductor layer 150 may be disposed on the buffer layer 161. The semiconductor layer 150 is disposed in the transistor region TRR and may include a channel of the driving transistor DTR. The semiconductor layer 150 may include an oxide semiconductor, and the oxide semiconductor may include, for example, a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) and quaternary compounds (AB x C y D z ) In an embodiment, the semiconductor layer 150 may include indium gallium zinc oxide (IGZO).

[0132] The gate insulating layer 162 may be disposed on the buffer layer 161. The gate insulating layer 162 may be formed in the same pattern as a pattern of a gate line GCL to be described later herein. The gate insulating layer 162 disposed in the transistor region TRR may be disposed on the semiconductor layer 150, and the gate insulating layer 162 disposed in the capacitor region CPR may be disposed on the buffer layer 161. The sidewalls of the gate insulating layer 162 may be substantially aligned with the sidewalls of the gate conductive layer GCL described later hereinafter. For example, the sidewalls of the gate insulating layer 162 may be substantially aligned with the sidewalls of the gate electrode GEL and the gate metal layer 130, but are not limited thereto. The gate insulating layer 162 may include a silicon compound or a metal oxide. For example, the gate insulating layer 162 may include any one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide. In an embodiment, the gate insulating layer 162 may include SiO x However, the embodiments of the present disclosure are not limited thereto, and the gate insulating layer 162 may include SiO x / SiN x Double layer.

[0133] The gate conductive layer GCL may be disposed on the gate insulating layer 162. The gate conductive layer GCL may include a gate electrode GEL included in the transistor region TRR and a capacitor first electrode CEL1 (or a lower electrode) included in the capacitor region CPR. In some embodiments, the gate conductive layer GCL may include a scan line SCL described herein (see Figure 3 ) and the sensing signal line SSL (see Figure 3 ). In some embodiments, the gate conductive layer GCL may be disposed such that the gate conductive layer GCL does not overlap with the data conductive layer DCL of the pad area PDA, which will be described later herein.

[0134] The gate conductive layer GCL may be formed of a single layer or may be formed of a plurality of layers. In an embodiment, the gate conductive layer GCL may include a gate main metal layer 130a and a gate base layer 130b disposed below the gate main metal layer 130a. Both the gate main metal layer 130a and the gate base layer 130b may be formed of a conductive material. In some examples, the gate conductive layer GCL may be implemented without inserting an insulating layer between constituent layers of the gate conductive layer GCL that overlap in the thickness direction. The gate main metal layer 130a and the gate base layer 130b may be etched and patterned together by a single mask process (e.g., during the same mask process).

[0135] The gate base layer 130b is disposed below the gate main metal layer 130a. The gate base layer 130b provides an improvement in layer formation characteristics (such as, for example, adhesion of the gate main metal layer 130a). In addition, or alternatively, the gate base layer 130b can be used to prevent reactive materials from entering the gate main metal layer 130a from the gate insulating layer 162. In some embodiments, the gate base layer 130b can prevent or reduce the material (e.g., copper) constituting the gate main metal layer 130a from diffusing to the adjacent lower layer. The gate base layer 130b may include a material (such as, for example, titanium (Ti), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), nickel (Ni) or any appropriate combination thereof), but is not limited thereto.

[0136] In some aspects, the gate main metal layer 130a plays a major role in supporting the transmission signal and may be formed of a low resistance material. The gate main metal layer 130a may have a thickness greater than that of the gate base layer 130b and may be formed of a material having a low resistance compared to the gate base layer 130b. The gate main metal layer 130a may include a material (such as, for example, copper (Cu), molybdenum (Mo), aluminum (Al), silver (Ag), or any appropriate combination thereof), but is not limited thereto.

[0137] Although not shown, the gate metal layer 130 may further include a gate capping layer disposed on the gate main metal layer 130a. The gate capping layer may cover the gate main metal layer 130a on top of the gate main metal layer 130a and protect the gate main metal layer 130a. The gate capping layer may directly contact the gate main metal layer 130a, but is not limited thereto, and the gate capping layer may have a thickness less than that of the gate main metal layer 130a and may be formed of a material having a high resistance compared to the gate main metal layer 130a. The gate capping layer may be used to protect the gate main metal layer 130a from the influence of the layer disposed on the gate conductive layer GCL or from the influence of the etchant or other chemicals used during the manufacturing process of the display device 1. In addition, the gate capping layer may prevent the material (e.g., copper) forming the gate main metal layer 130a from diffusing toward the upper layer adjacent to the gate main metal layer 130a.

[0138] The interlayer insulating layer 163 may be disposed on the gate conductive layer GCL. The interlayer insulating layer 163 may be completely disposed on the gate conductive layer GCL, the semiconductor layer 150 exposed by the gate conductive layer GCL, and the buffer layer 161 exposed by the gate conductive layer GCL and the semiconductor layer 150. The interlayer insulating layer 163 may include an inorganic insulating material (such as, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, etc.). In an embodiment, the interlayer insulating layer 163 may include SiO x N y .

[0139] In some aspects, in the example drawings, for convenience of explanation, the case where the upper surface of the interlayer insulating layer 163 is flat in the display area DPA is explained, but aspects of the present disclosure are not limited thereto. For example, the interlayer insulating layer 163 formed of an inorganic material may have a surface shape reflecting a lower step. In this case, a relative comparison of the thickness of the interlayer insulating layer 163 of each portion can be performed by measuring the thickness from the same flat reference surface (e.g., the upper surface of the buffer layer 161) without a lower step structure.

[0140] The data conductive layer DCL may be disposed on the interlayer insulating layer 163. The data conductive layer DCL may include source and drain electrodes SEL and DEL included in the transistor region TRR, a capacitor second electrode CEL2 (or upper electrode) included in the capacitor region CPR, and a wiring pad WPD included in the pad region PDA.

[0141] The source electrode SEL and the drain electrode DEL may be connected to the semiconductor layer 150 through the second contact hole CNT2 penetrating the interlayer insulating layer 163. The source electrode SEL may also be connected to the bottom metal layer 120 through the first contact hole CNT1 penetrating the interlayer insulating layer 163 and the buffer layer 161. In addition, the data conductive layer DCL may include the data line DTL described herein (see Figure 3 ), reference voltage line RVL (see Figure 3 ) and the first power line ELVDL (see Figure 3 ).

[0142] refer to Figures 7 to 9 The data conductive layer DCL includes a data conductive metal layer 141 having a stacked structure, a first data capping layer 142 disposed on the data conductive metal layer 141 , a second data capping layer 143 disposed on the first data capping layer 142 , and a plurality of metal aggregates 145 disposed on the second data capping layer 143 .

[0143] The data conductive metal layer 141 may be formed of a single layer or a plurality of layers. In an implementation, the data conductive metal layer 141 may include a data main metal layer 141a and a data base layer 141b disposed under the data main metal layer 141a except for the data main metal layer 141a.

[0144] The data base layer 141b, the data main metal layer 141a, the first data capping layer 142, and the second data capping layer 143 may all be formed of conductive materials. In some embodiments, the data conductive layer DCL may be implemented so that the insulating layer is not inserted between the constituent layers of the data conductive layer DCL that overlap in the thickness direction. The data base layer 141b, the data main metal layer 141a, the first data capping layer 142, and the second data capping layer 143 may be etched and patterned together by a single mask process (e.g., during the same mask process). The process of forming the stacked structure of the data conductive layer DCL will be described later below. The term "data base layer" may be referred to as a base layer associated with forming a data line DTL, the term "data main metal layer" may refer to a metal layer associated with forming a data line DTL, the term "first data capping layer" may refer to a first capping layer formed on the data line DTL, and the term "second data capping layer" may refer to a second capping layer formed on the data line DTL.

[0145] Similar to the gate base layer 130b, the data base layer 141b may provide improvements in layer formation characteristics (such as, for example, adhesion) of the data main metal layer 141a. In some aspects, the data base layer 141b prevents reactive materials from entering the data main metal layer 141a from the interlayer insulating layer 163. The data base layer 141b may include one or more selected from titanium (Ti), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), and nickel (Ni), but is not limited thereto. In an embodiment, the data base layer 141b may be formed of titanium. The thickness of the data base layer 141b may be about 1000 Å. to about within the range.

[0146] The data main metal layer 141a plays a main role in supporting the transmission signal and may be formed of a low resistance material. The data main metal layer 141a may have a thickness thicker than the thickness of each of the data base layer 141b, the first data capping layer 142, and the second data capping layer 143, or the thickness of the data main metal layer 141a may be thicker than the total thickness of the data base layer 141b, the first data capping layer 142, and the second data capping layer 143. The data main metal layer 141a may be formed of a material having a lower resistance than the first data capping layer 142 directly disposed above the data main metal layer 141a and the data base layer 141b directly disposed below the data main metal layer 141a. The data main metal layer 141a may include one or more of the following materials selected from copper (Cu), aluminum (Al), silver (Ag), and molybdenum (Mo), but is not limited thereto. In an embodiment, the data main metal layer 141a may be formed of aluminum (Al).

[0147] The first data capping layer 142 covers and protects the data main metal layer 141a from above. When the second data capping layer 143 is exposed to an etchant or other chemicals used during a manufacturing process (e.g., a process of forming a pixel electrode PXE) after forming the data conductive layer DCL to be described later in this article and is etched, the first data capping layer 142 can be used to protect the data main metal layer 141a. In some aspects, the first data capping layer 142 can prevent the material (e.g., aluminum) constituting the data main metal layer 141a from diffusing toward the adjacent upper layer. The first data capping layer 142 can directly contact the data main metal layer 141a.

[0148] The first data capping layer 142 may be a single-layer film including titanium nitride (TiN). In some additional and / or alternative embodiments, the first data capping layer 142 may be a multi-layer film including titanium nitride (TiN) or the like.

[0149] The second data capping layer 143 may be disposed on the first data capping layer 142. The second data capping layer 143 may be used to protect the first data capping layer 142 from dry etching during a manufacturing process (e.g., a process of forming the third contact hole CNT3 and a process of forming the pad opening PDOP) after forming the data conductive layer DCL, which will be described later in this article. In some aspects, the second data capping layer 143 may prevent the thickness of the first data capping layer 142 from being reduced. For example, the second data capping layer 143 may prevent the thickness of the first data capping layer 142 from being reduced due to concerns that the first data capping layer 142 may be etched by dry etching.

[0150] The second data capping layer 143 may include a material that is not consumed by dry etching. In some embodiments, the second data capping layer 143 may be formed of any one or more of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO). In some embodiments, the second data capping layer 143 may be formed of a material selected from the group consisting of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO). For example, the second data capping layer 143 may be formed of a single layer selected from an IGZO layer, an ITO layer, and an IZO layer, but is not limited thereto. In another example, the second data capping layer 143 may be a multilayer formed of any combination of an IGZO layer, an ITO layer, and an IZO layer. In an embodiment, the second data capping layer 143 may be formed of an IZO single layer. In an embodiment, the second data capping layer 143 may be formed of an IGZO single layer.

[0151] A plurality of metal aggregates 145 may be disposed on the second data capping layer 143. Each metal aggregate 145 may be different in size and shape from each other. Additionally, or alternatively, two or more metal aggregates 145 may be identical in size and shape.

[0152] Each metal aggregate 145 may be formed of an inert metal. For example, the metal aggregate 145 may be formed of a material selected from the group consisting of gold (Au), silver (Ag), and platinum (Pt). In an embodiment, the metal aggregate 145 may be formed of a single metal (e.g., silver (Ag)). In one or more additional and / or alternative embodiments, the metal aggregate 145 may be formed of any appropriate combination of gold (Au), silver (Ag), and platinum (Pt).

[0153] The metal aggregate 145 has excellent bonding characteristics with the second data capping layer 143 and excellent bonding characteristics with other inert metals.

[0154] In an embodiment, the second data capping layer 143 is formed of a single layer of IGZO. In some embodiments, when a metal aggregate 145 formed of a single metal silver (Ag) is disposed on the second data capping layer 143, the metal aggregate 145 can be easily bonded to the second data capping layer 143 because the bonding characteristics between silver (Ag) and IGZO are excellent.

[0155] In an implementation, the data main metal layer 141a may include aluminum (Al), the first data capping layer 142 may include titanium nitride (TiN), the second data capping layer 143 may include IGZO, and the metal aggregation 145 may include silver (Ag).

[0156] In an example embodiment, by using titanium nitride (TiN) at the first data capping layer 142, the first data capping layer 142 does not form an oxide film, and the display device 1 can be formed without high pressing. In some aspects, when the metal aggregate 145 is formed on the second data capping layer 143, the provision of separate conductive balls at the second data capping layer 143 can be omitted. In addition, since silver (Ag) is a metal in the same group as gold (Au), and silver (Ag) and gold (Au) have good bonding characteristics with each other, silver (Ag) can be easily bonded to a material including gold (Au).

[0157] In an embodiment, the side surfaces (or sidewalls) of the data base layer 141b, the data main metal layer 141a, the first data capping layer 142, and the second data capping layer 143 may be aligned with each other. That is, the upper surface of the layer constituting the data conductive layer DCL and the lower surface of another layer constituting the data conductive layer DCL disposed on and in contact with the upper surface may be aligned without protruding from each other.

[0158] refer to Figure 8, the data main metal layer 141a, the data base layer 141b, the first data capping layer 142, and the second data capping layer 143 of the data conductive layer DCL may have different thicknesses. The respective thicknesses T2, T1, T3, and T4 of the layers 141b, 141a, 142, and 143 constituting the data conductive layer DCL may be defined as the distance from the lower surface to the upper surface of each of the respective layers 141b, 141a, 142, and 143.

[0159] In an embodiment, the thickness T1 of the data main metal layer 141a may be thicker than each of the thickness T2 of the data base layer 141b, the thickness T3 of the first data capping layer 142, and the thickness T4 of the second data capping layer 143. In an embodiment, the thickness T1 of the data main metal layer 141a may be thicker than the total thickness of the thickness T2 of the data base layer 141b, the thickness T3 of the first data capping layer 142, and the thickness T4 of the second data capping layer 143.

[0160] The data base layer 141b may be formed to have a thickness T2 and the first data capping layer 142 may be formed to have a thickness T3. The data base layer 141b and the first data capping layer 142 may be formed so that the data base layer 141b and the first data capping layer 142 directly contact the data main metal layer 141a at the bottom and the top of the data main metal layer 141a, respectively. The thickness T2 and the thickness T3 and the direct contact with the data main metal layer 141a support protecting the data main metal layer 141a.

[0161] In an embodiment, the data conductive layer DCL is a four-layer of Ti / Al / TiN / IGZO, wherein the data main metal layer 141a includes Al, the data base layer 141b includes Ti, the first data capping layer 142 includes TiN, and the second data capping layer 143 includes IGZO. In an example embodiment, the thickness T1 of the data main metal layer 141a may be to The thickness T2 of the data base layer 141b may be to The thickness T3 of the first data capping layer 142 may be to The thickness T4 of the second data capping layer 143 may be to

[0162] Return to reference Figure 7, the data conductive layer DCL may include a first region 140A, a second region 140B, and a third region 140C. The respective shapes and sizes of the first region 140A, the second region 140B, and the third region 140C may be based on the structure of the second data capping layer 143 disposed on the uppermost layer of the data conductive layer DCL and / or a layer in contact with the upper surface of the second data capping layer 143.

[0163] The second data capping layer 143 of the data conductive layer DCL may have different structures in the first region 140A, the second region 140B, and the third region 140C. In addition, or alternatively, the data conductive layer DCL may have a different layer contacting the upper surface of the second data capping layer 143 at each of the first region 140A, the second region 140B, and the third region 140C. A detailed description of the first region 140A, the second region 140B, and the third region 140C of the data conductive layer DCL will be described later herein.

[0164] The passivation layer 164 may be disposed on the data conductive layer DCL. The passivation layer 164 is used to cover and protect the data conductive layer DCL. The passivation layer 164 may include an inorganic insulating material (such as, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide (ZnO or ZnO 2 ) etc. or any combination thereof).

[0165] The passivation layer 164 may be formed entirely in the display area DPA. In some aspects, the passivation layer 164 may be formed such that the passivation layer 164 is not present in at least a portion of the non-display area NDA (eg, as in FIG. 1 ). Figure 7 For example, the passivation layer 164 may be disposed so that the passivation layer 164 does not exist on at least a portion of the third area 140C of the data conductive layer DCL or the wiring pad WPD of the pad area PDA included in the non-display area NDA.

[0166] The via layer 165 may be disposed on the passivation layer 164. The via layer 165 may cover the upper surface of the passivation layer 164 and expose the end surface of the passivation layer 164 disposed in the pad area PDA. In some aspects, the via layer 165 may cover a portion of the upper surface of the passivation layer 164 in the pad area PDA.

[0167] The through-hole layer 165 may include a pad opening PDOP exposing at least a portion of the passivation layer 164 and the third region 140C of the data conductive layer DCL of the pad area PDA. The through-hole layer 165 constituting the inner wall of the pad opening PDOP may expose the end surface of the passivation layer 164 disposed in the pad area PDA, but is not limited thereto. For example, the pad opening PDOP is formed by the passivation layer 164 and the through-hole layer 165 disposed in the pad area PDA, and the inner wall of the passivation layer 164 and the inner wall of the through-hole layer 165 constituting the pad opening PDOP may be aligned with each other. In some aspects, in the pad area PDA, the end surface of the passivation layer 164 may further protrude inwardly compared to the end surface of the through-hole layer 165. In some embodiments (not shown), the through-hole layer 165 may form the inner wall of the pad opening PDOP by covering the end surface of the passivation layer 164 disposed in the pad area PDA.

[0168] The via layer 165 may be formed of an organic insulating material such as, for example, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, polyphenylene sulfide resin, benzocyclobutene (BCB), or any combination thereof. The via layer 165 may further include a photosensitive material, but is not limited thereto. In an embodiment, the via layer 165 may be formed of a polyimide resin.

[0169] The pixel electrode PXE may be disposed on the through hole layer 165. Figure 2 Materials constituting the pixel electrode PXE are described. In an embodiment, the pixel electrode PXE may include three layers of ITO / Ag / ITO.

[0170] The pixel electrode PXE is disposed in the display area DPA and may be disposed so that the pixel electrode PXE is not included in the non-display area NDA. The pixel electrode PXE may overlap with the transistor region TRR and the capacitor region CPR of the display area DPA, but is not limited thereto. The pixel electrode PXE may be connected to the source electrode SEL of the driving transistor DTR through a third contact hole CNT3 penetrating the through-hole layer 165 and the passivation layer 164.

[0171] The pixel defining layer PDL may be disposed on the pixel electrode PXE. Figure 2 The materials described are the same. In an implementation, the pixel defining layer PDL may include polyimide.

[0172] The pixel defining layer PDL is disposed in the display area DPA and may be disposed so that the pixel defining layer PDL is not included in the non-display area NDA. The pixel defining layer PDL may be disposed so that the pixel defining layer PDL overlaps an edge portion of the pixel electrode PXE. The pixel defining layer PDL may also be disposed on the through hole layer 165 on which the pixel electrode PXE is not formed.

[0173] In the following description, the first region 140A, the second region 140B, and the third region 140C of the above-mentioned data conductive layer DCL will be described in detail.

[0174] The data conductive layer DCL may include a first region 140A overlapping the third contact hole CNT3, a second region 140B completely covered by the passivation layer 164, and a third region 140C exposed through the pad opening PDOP. The first region 140A and the second region 140B of the data conductive layer DCL may be disposed in the display area DPA, and the third region 140C of the data conductive layer DCL may be disposed in the non-display area NDA.

[0175] The first region 140A of the data conductive layer may be disposed in the transistor region TRR. The source electrode SEL of the driving transistor DTR may be formed in the first region 140A of the data conductive layer DCL disposed in the transistor region TRR. The second region 140B of the data conductive layer DCL may be disposed in the transistor region TRR and / or the capacitor region CPR of the display region DPA. The source electrode SEL and the drain electrode DEL of the driving transistor DTR or the second electrode CEL2 of the capacitor CST may be formed in the second region 140B of the data conductive layer DCL.

[0176] The first region 140A of the data conductive layer DCL may be connected to the pixel electrode PXE through the third contact hole CNT3. Specifically, for example, the passivation layer 164 and the pixel electrode PXE may be disposed on the upper surface of the second data capping layer 143 included in the first region 140A of the data conductive layer DCL. At least a portion of the upper surface of the second data capping layer 143 included in the first region 140A of the data conductive layer DCL overlapping the third contact hole CNT3 may contact the pixel electrode PXE, and the remaining portion of the upper surface of the second data capping layer 143 included in the first region 140A of the data conductive layer DCL may contact the passivation layer 164. The pixel electrode PXE may be electrically connected by filling the inner space of the third contact hole CNT3 with the pixel electrode PXE, so that the pixel electrode PXE contacts the upper surface of the second data capping layer 143 included in the first region 140A of the data conductive layer DCL overlapping the third contact hole CNT3.

[0177] The passivation layer 164 may be disposed on the upper surface of the second region 140B of the data conductive layer DCL. Specifically, the upper surface of the second data capping layer 143 included in the second region 140B of the data conductive layer DCL may contact the passivation layer 164. The passivation layer 164 disposed on the upper surface of the second data capping layer 143 included in the second region 140B of the data conductive layer DCL may be completely disposed on the upper surface of the second data capping layer 143 in the second region 140B of the data conductive layer DCL so that the passivation layer 164 completely covers the second region 140B of the data conductive layer DCL.

[0178] The third region 140C of the data conductive layer DCL may be disposed in the pad area PDA. The wiring pads WPD of the pad area PDA may be formed in the third region 140C of the data conductive layer DCL disposed in the pad area PDA.

[0179] A plurality of metal aggregates 145 may be disposed on an upper surface of the second data capping layer 143 included in the third region 140C of the data conductive layer DCL. A height hb of each of the metal aggregates 145 may be approximately to about In some examples, metal aggregates 145 may be equal in height or have different heights. The height of each metal aggregate 145 may be defined as the distance from the lower surface to the upper surface of the metal aggregate 145 .

[0180] At least a portion of the upper surface of the second data capping layer 143 on which the metal aggregation 145 is not disposed in the third region 140C of the data conductive layer DCL may be exposed. Accordingly, for example, the upper surface of the second data capping layer 143 and the plurality of metal aggregations 145 in the third region 140C of the data conductive layer DCL may be exposed through the pad opening PDOP.

[0181] Hereinafter, the manufacturing Figure 8 A method for forming a data conductive layer DCL of a display device.

[0182] Figures 10 to 12 For manufacturing Figure 7 A cross-sectional view of a process for forming a data conductive layer in a third region of a display device.

[0183] refer to Figure 8 and Fig.10 First, on the first substrate 110 (see Figure 2) is formed on the interlayer insulating layer 163 of the data conductive layer 141. The patterned data conductive layer DCL may be formed by a mask process. For example, a material layer for the data conductive metal layer 141, a material layer for the first data capping layer 142, and a material layer for the second data capping layer 143 are sequentially deposited on the entire surface of the interlayer insulating layer 163. Here, the material layer for the data conductive metal layer 141 may include a material layer for the data base layer 141b and a material layer for the data main metal layer 141a.

[0184] In an embodiment, when the data conductive layer DCL has a four-layer structure of Ti / Al / TiN / IGZO, a material layer for the data base layer 141b including titanium (Ti), a material layer for the data main metal layer 141a including aluminum (Al), a material layer for the first data capping layer 142 including titanium nitride (TiN), and a material layer for the second data capping layer 143 including IGZO can be formed by sputtering during physical vapor deposition PVD.

[0185] Next, refer to Fig.11 , depositing a metal material layer 145L on the second data capping layer 143. The metal material layer 145L may include an inert metal. The metal material layer 145L may include, for example, a material selected from the group consisting of gold (Au), silver (Ag), and platinum (Pt). In some embodiments, the metal material layer 145L may include, for example, one or more of gold (Au), silver (Ag), and platinum (Pt).

[0186] The metal material layer 145L may be deposited with a thickness T5 that is smaller than each of the thickness T2 of the data base layer 141b, the thickness T1 of the data main metal layer 141a, the thickness T3 of the first data capping layer 142, and the thickness T4 of the second data capping layer 143. The thickness T5 of the metal material layer 145L may be about to about

[0187] refer to Fig.12 , the metal aggregates 145 are formed by applying heat to the metal material layer 145L. For example, forming the metal aggregates 145 may include applying heat of a preset temperature to the metal material layer 145L.

[0188] Specifically, for example, when heat of a preset temperature is applied to the metal material layer 145L, the metal material included in the metal material layer 145L aggregates to generate the metal aggregate 145. In some embodiments, the preset temperature may be a relatively low temperature of about 100° C. to 250° C. However, aspects of the present disclosure are not limited thereto, and the preset temperature may include any appropriate temperature that supports the aggregation of the metal material according to the techniques described herein.

[0189] Fig.13 A schematic diagram illustrating bonding characteristics of a data conductive layer DCL according to an exemplary aspect of the present disclosure.

[0190] refer to Fig.13 , in reference Figures 10 to 12 The metal aggregate 145 formed on the second data capping layer 143 in the described data conductive layer DCL can be easily bonded with the metal 146 of the same group of metals. The height hb of the metal aggregate 145 can be reduced by thermal compression. In an embodiment, when the data conductive layer DCL is a four-layer Ti / Al / TiN / IGZO and the metal aggregate 145 including silver (Ag) is formed on IGZO, the metal 146 may be gold (Au). Gold (Au) is a metal in the same group as silver (Ag) and has excellent bonding properties, so that gold (Au) and silver (Ag) can be easily bonded to each other. In addition, since gold (Au) has excellent adhesion to IGZO, gold (Au) has excellent adhesion to the second data capping layer 143 on which the metal aggregate 145 including silver (Ag) is not provided.

[0191] Fig.14 is an electron micrograph of the surface of the data conductive layer DCL having the metal aggregates 145. Fig.15 is an electron micrograph of a cross section of the data conductive layer DCL having the metal aggregates 145.

[0192] refer to Fig.14 and Fig.15 , metal aggregates 145 are shown to be aggregated on the second data capping layer 143 in the data conductive layer DCL.

[0193] As described herein, improved pad area (PDA) can be achieved using techniques implemented with relatively low pressure and without the need for conductive balls (see Figure 7 ) bonding characteristics. According to aspects of the disclosure described herein, the technique includes treating a metal (e.g., metal material layer 145L (see Fig.11 ) is heat-treated to form a metal aggregation 145 on the data conductive layer DCL.

[0194] However, aspects of the present disclosure are not limited to the examples set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the claims (including functional equivalents thereof).

Claims

1. A display device, comprising: A substrate including a display area and a pad area; as well as a data conductive layer disposed in the pad region and on the substrate; The data conductive layer includes a data base layer, a data main metal layer arranged on the data base layer, a first data capping layer arranged on the data main metal layer, a second data capping layer arranged on the first data capping layer and a plurality of metal aggregates arranged on the second data capping layer.

2. The display device according to claim 1, wherein the plurality of metal aggregates are formed of an inert metal, The inert metal is formed of silver, gold or platinum. 3 . The display device according to claim 1 , wherein the second data capping layer is formed of a transparent conductive oxide.

4. The display device according to claim 3, wherein the second data capping layer is formed of indium gallium zinc oxide and has to Thickness.

5. The display device according to claim 1, wherein the first data capping layer is formed of titanium nitride and has to Thickness.

6. The display device according to claim 5, wherein the data main metal layer is formed of aluminum, And the data base layer is formed of titanium.

7. A display device according to claim 1, wherein the thickness of the data main metal layer is thicker than each of the thickness of the data base layer, the thickness of the first data capping layer and the thickness of the second data capping layer, or is thicker than the total thickness of the data base layer, the thickness of the first data capping layer and the thickness of the second data capping layer.

8. The display device according to claim 5, wherein the data main metal layer has to Thickness.

9. The display device according to claim 7, wherein the data base layer has to Thickness. 10 . The display device according to claim 1 , wherein the substrate is any one of a rigid substrate, a flexible substrate and an ultra-thin glass substrate.

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