Packaging substrate and packaging device

Abstract

The utility model discloses a packaging substrate and a packaging device, the packaging substrate comprises a first dielectric layer, a first lead wire layer and a through hole layer, the first lead wire layer is formed between the first dielectric layer and the through hole layer, the first dielectric layer is provided with a hole network array and a first conductive structure array matched with the hole network array, the rotating hole layer is in contact with each first conductive structure; the plurality of hole networks comprise a first type of hole network group and a second type of hole network group which are alternately distributed along a first preset direction, the first type of hole network group comprises a plurality of first type of conductive hole networks distributed along a second preset direction, and the second type of hole network group comprises a plurality of second type of conductive hole networks distributed along a second direction. The packaging substrate has high hole network density, and the packaging design requirement of a high-power chip can be met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a packaging substrate and a packaging device. Background Art

[0002] At present, the design of the plated through holes (PTH) of the package substrate generally adopts a staggered arrangement of the power hole network and the ground-to-air network. When the process requirements of the arrangement are known, the density of the PTH holes in the package substrate is not high, resulting in a large overall power impedance and weak overcurrent capacity, which is not enough to adapt to the packaging design requirements of the current high-power server chips.

[0003] In the relevant packaging design, the packaging substrate includes a build-up layer and a core layer. Build-up holes can be formed in the build-up layer, and core holes used for each layer of transmission lines can be formed in the core layer, so that the core holes and the corresponding build-up holes can form a hole network. The types of these hole networks can be power hole networks or ground hole networks. When the power hole network and the ground hole network are arranged in an interlaced manner, it is necessary to limit the spacing between the power hole network and the ground hole network to avoid the risk of short circuit in process manufacturing, but this also causes the hole network density on the packaging substrate to be relatively low, which is not conducive to the packaging design requirements of high-power chips. Utility Model Content

[0004] The purpose of the present application is to provide a packaging substrate and a packaging device to increase the hole network density of the packaging substrate, thereby ensuring the packaging design requirements of high-power chips.

[0005] In a first aspect, the present application provides a packaging substrate, comprising: a first dielectric layer, a via layer, and a second dielectric layer, wherein the via layer is formed between the first dielectric layer and the second dielectric layer, the first dielectric layer having a hole network array and a first conductive structure array matching the hole network array, a plurality of first conductive structures included in the first conductive structure array being correspondingly arranged in a plurality of hole networks included in the hole network array, the second dielectric layer having a via array and a second conductive structure array matching the via array, a plurality of second conductive structures included in the second conductive structure array being correspondingly arranged in a plurality of vias included in the via array, and the first conductive structure array being connected to the second conductive structure array through the via layer;

[0006] The plurality of hole networks include a first type hole network group and a second type hole network group alternately distributed along a first preset direction, the first type hole network group includes a plurality of first type conductive hole networks distributed along a second preset direction, and the second type hole network group includes a plurality of second type conductive hole networks distributed along a second direction;

[0007] The spacing between the first type of hole network group and the adjacent second type of hole network group is a first spacing, the spacing between two adjacent first type of conductive hole networks included in each first type of hole network group is a second spacing, and the spacing between two adjacent second type of conductive hole networks included in each second type of hole network group is a third spacing, and the second spacing and the third spacing are both smaller than the first spacing.

[0008] In the case of adopting the above technical solution, the first conductive structure array of the present application includes a plurality of first conductive structures correspondingly arranged in the plurality of hole networks included in the hole network array, and the plurality of hole networks include a first type hole network group and a second type hole network group alternately distributed along a first preset direction, the first type hole network group includes a plurality of first type conductive hole networks distributed along a second preset direction, and the second type hole network group includes a plurality of second type conductive hole networks distributed along a second direction. In this case, the spacing between the first type hole network group and the adjacent second type hole network group is the first spacing, the spacing between the adjacent two first type conductive hole networks included in each first type hole network group is the second spacing, and the spacing between the adjacent two second type conductive hole networks included in each second type hole network group is the third spacing. However, since the signals transmitted by the first conductive structures formed in the first type hole network group and the second type hole network group are different, the signals transmitted by the first conductive structures formed in each first type conductive hole network are the same, and the signals transmitted by the first conductive structures formed in each second type conductive hole network are the same, therefore, when the second spacing and the third spacing are both smaller than the first spacing, the distribution density of the first type hole network group and the second type hole network group in the first preset direction is relatively low, thereby avoiding the risk of short circuit in process manufacturing, improving the tolerance rate of production and use, and ensuring that the packaged device can be used normally. The distribution density of the first type of conductive hole network included in the first type hole network group in the second preset direction is relatively high, which can reduce the overall impedance of the packaged device and improve the current carrying capacity. Similarly, the distribution density of the second type of conductive hole network included in the second type hole network group in the second preset direction is relatively high, which can reduce the overall impedance of the packaged device and improve the current carrying capacity.

[0009] Moreover, the package substrate of the present application includes a via layer formed between the first dielectric layer and the second dielectric layer, and the first conductive structure array of the first dielectric layer is connected to the second conductive structure array of the second dielectric layer through the via layer. Therefore, when the die is packaged on the printed circuit board through the package substrate, regardless of whether the arrangement form of the die bump array and the hole network array is the same, the first conductive structure array of the first dielectric layer can be connected to the die bump array through the via layer and the second conductive structure array. It can be seen that the package substrate of the present application can achieve the decoupling of the arrangement form of the die bump array and the hole network array, solve the problem of mismatch between the arrangement form of the die bump array and the hole network array, and improve the application scope of the package substrate.

[0010] In a possible implementation, a plurality of first-type conductive hole networks included in different first-type hole network groups are aligned and formed in the first dielectric layer, and a plurality of second-type conductive hole networks included in different second-type hole networks are aligned and formed in the first dielectric layer.

[0011] In a possible implementation, a plurality of first-class conductive hole networks included in the first-class hole network group and a plurality of second-class conductive hole networks included in the adjacent second-class hole network group are staggered and formed in the first dielectric layer. In this case, the gap between two adjacent second-class conductive hole networks included in the adjacent second-class hole network group is utilized to provide more accommodation space for the adjacent first-class hole network group, thereby reducing the distance (i.e., the first distance) between the first-class hole network group and the adjacent second-class hole network group. In this way, the distribution density of the first-class hole network and the second-class hole network in the first preset direction can be increased, thereby reducing the overall impedance of the packaged device and improving the current carrying capacity.

[0012] In a possible implementation, for each first-type hole network group, the geometric centers of the core holes in each first-type conductive hole network are located on the same first straight line, and for each second-type hole network group, the geometric centers of the core holes in each second-type conductive hole network are located on the same second straight line, and the first straight line and the second straight line are different straight lines;

[0013] The geometric centers of the projections of the core holes in the corresponding first-type conductive hole networks included in different first-type hole network groups are located on the same third straight line, and the geometric centers of the projections of the core holes in the corresponding second-type conductive hole networks included in different second-type hole network groups are located on the same fourth straight line, and the third straight line and the fourth straight line are different straight lines. In this case, the multiple first-type conductive hole networks included in the first-type hole network group and the multiple second-type conductive hole networks included in the adjacent second-type hole network group are staggered and formed in the first dielectric layer.

[0014] In one possible implementation, the projection pattern of each hole network on a preset plane includes a core hole projection and a plurality of accumulated hole projections located circumferentially of the core hole projection, the plurality of accumulated hole projections include a target hole projection, and the target hole projection in each hole network group is located in the gap between two adjacent hole networks in adjacent hole network groups.

[0015] In the technical solution of the present application, considering that the distance between two adjacent hole networks included in each hole network group is relatively small, the gap between two adjacent hole networks is not easy to accommodate the hole network included in the adjacent hole network group of larger size. Therefore, the gap between the projection of the stacked holes with relatively small projection area in the hole network group and the adjacent hole networks in the adjacent hole network group can be limited. In this way, even if the distance between the projection of the target hole included in the hole network group and the adjacent hole networks included in the adjacent hole network group is too large, it will not cause the risk of short circuit in process manufacturing due to being too small. It can be seen that the present application can reduce the distribution density of the hole network in the second preset direction in this way to reduce the overall impedance of the packaged device, improve the current carrying capacity, and reduce the risk of short circuit in process manufacturing.

[0016] In a possible implementation, the plurality of stacked hole projections include a first pair of stacked hole projections and a second pair of stacked hole projections, the angle between the geometric center line of the first pair of stacked hole projections and the first preset direction is less than or equal to the first preset angle, and the angle between the geometric center line of the second pair of stacked hole projections and the second preset direction is less than or equal to the second preset angle. In this case, the first pair of stacked hole projections and the second pair of stacked hole projections are distributed around the core hole projection in a cross form.

[0017] In one possible implementation, the multiple stacked hole projections include a first pair of stacked hole projections and a second pair of stacked hole projections, the core hole projection has a first side and a second side, the first pair of stacked hole projections are located on the first side, the second pair of stacked hole projections are located on the second side, and the first side and the second side are distributed along a second preset direction.

[0018] In the technical solution of the present application, when the projections of the first pair of stacked holes and the second pair of stacked holes included in each type of hole network are distributed along the second preset direction, the space occupied by a single hole network in the second preset direction of the package substrate is relatively small, so that the distribution density of the hole network in the second preset direction is relatively high. Moreover, the two pairs of stacked hole projections included in the multiple hole networks included in each hole network group (the first hole network group or the second hole network group) are distributed along the first preset direction, but since there is no distance requirement between the same type of hole networks, therefore, compared with the scheme of alternating distribution of different types of hole networks in the related art, the distribution density of the hole network in the present application along the first preset direction is relatively high.

[0019] It can be seen that the present application can not only increase the hole density of the hole network in the first preset direction, but also increase the hole density of the hole network in the second preset direction by limiting the position and distribution direction of the two pairs of stacked hole projections included in the hole network relative to the core hole projection, thereby increasing the overall impedance of the packaging device, improving the current carrying capacity, and avoiding the risk of short circuit in process manufacturing.

[0020] In a possible implementation, each hole network includes a lower build-up layer hole, a core hole, and an upper build-up layer hole arranged in the thickness direction of the first lead layer along a direction close to the transfer layer, the aperture of the lower build-up layer hole and the aperture of the upper build-up layer hole are both smaller than the aperture of the core hole, and the projections of the lower build-up layer holes and the upper build-up layer holes included in each hole network on the same preset plane are located in the circumference of the core hole;

[0021] Each first conductive structure includes an upper build-up layer conductive contact portion, a lower build-up layer conductive contact portion and a core conductive contact portion, wherein the upper build-up layer conductive contact portion included in each first conductive structure is arranged in an upper build-up layer hole included in a corresponding hole network, the lower build-up layer conductive contact portion included in each first conductive structure is arranged in a lower build-up layer hole included in a corresponding hole network, and the core conductive contact portion included in each first conductive structure is arranged in a core hole included in a corresponding hole network;

[0022] The packaging substrate of the present application also includes a first lead layer and a second lead layer. The lower conductive contact portion included in the same first conductive structure is connected to the middle conductive contact portion through the first lead layer, the middle conductive contact portion included in the same first conductive structure is connected to the upper conductive contact portion through the second lead layer, and the via layer is connected to the upper conductive contact portion included in each first conductive structure through the via layer.

[0023] In one possible implementation, the packaging substrate of the present application also includes a hole pad array that matches the bare chip bump array, and the hole pad array includes multiple hole pads formed on the surface of the multiple holes included in the hole array that are away from the hole layer, and the hole array and the hole network array are staggered in their orthographic projections on the same preset plane.

[0024] In the technical solution of the present application, the first conductive structure provided in the hole network can be connected to the second conductive structure in the rotary hole through the rotary hole layer. The orthographic projections of the rotary hole array and the hole network array on the same preset plane are staggered, so the hole network array can be rearranged through the rotary hole array opened by the second dielectric layer. At the same time, since the plurality of hole pads included in the hole pad array are formed on the surface of the plurality of rotary holes included in the rotary hole array away from the rotary hole layer, and the hole pad array matches the bare chip bump array, the second conductive structure provided in the rotary hole can be connected to the bare chip bump through the hole pad. It can be seen that no matter how the hole network array is distributed, the first conductive structure array provided therein can be connected to the hole pad array through the rotary hole layer and the second conductive structure array, and the hole pad array can be in contact with the bare chip bump array. Therefore, the packaging substrate of the present application can provide a power signal to the bare chip at a lower impedance.

[0025] In a second aspect, the present application further provides a packaging device, comprising the packaging substrate described in the first aspect of the present application or any possible implementation method.

[0026] The beneficial effects brought about by the technical solution of the second aspect of the present application are the same as the beneficial effects of the first aspect or any possible implementation method, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0028] Figure 1 A schematic diagram of hole network distribution in a related art is shown;

[0029] Figure 2 A schematic diagram showing the structure of a PDN system according to an embodiment of the present application is shown;

[0030] Figure 3 Schematic diagram of an equivalent model of a PDN system shown;

[0031] Figure 4 A schematic diagram of a chip packaging principle is shown;

[0032] Figure 5 A schematic diagram showing the basic structure of a packaging substrate according to an embodiment of the present application is shown;

[0033] Figure 6 A schematic diagram showing the structure of the pore network of an embodiment of the present application is shown;

[0034] Figure 7 A schematic diagram of a hole network array according to an embodiment of the present application is shown;

[0035] Figure 8 A schematic diagram of the three-dimensional structure of the pore network of an embodiment of the present application is shown;

[0036] Fig. 9 A schematic diagram of the arrangement of the hole network in an embodiment of the present application is shown;

[0037] Fig.10 Another schematic diagram of a hole network array according to an embodiment of the present application is shown;

[0038] Fig.11 A schematic diagram of the staggered arrangement of the hole network in an embodiment of the present application is shown;

[0039] Fig. 12A A schematic diagram showing a distribution of the projection of the stacked holes on the hole network of an embodiment of the present application is shown;

[0040] Fig. 12B Another schematic diagram showing the distribution of the projection of the stacked holes on the hole network of the embodiment of the present application is shown;

[0041] Fig. 12CAnother schematic diagram showing the distribution of the projection of the stacked holes on the hole network of the embodiment of the present application is shown;

[0042] Fig.13 Another schematic diagram of the hole network array of the embodiment of the present application is shown;

[0043] Fig.14 A schematic structural diagram of a packaging device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0047] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0048] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0049] As the power consumption of large-size servers increases, chips face many power integrity challenges. How to design the core power module is becoming increasingly important for chip design, and the density design of the plated through holes (Plating Through Hole) of the package substrate is related to the power supply quality of the chip.

[0050] At present, the PTH of the packaging substrate is generally designed with an alternating arrangement of the power hole network and the ground hole network. When the process requirements of the arrangement are known, the PTH hole density in the packaging substrate is not high, resulting in a large overall power impedance and weak overcurrent capacity, which is insufficient to adapt to the current packaging design requirements of high-power server chips.

[0051] In the relevant packaging design, the packaging substrate includes a build-up layer and a core layer. The build-up layer holes can be formed in the build-up layer, and the core holes used for the transmission lines of each layer can be formed in the core layer, so that the core holes and the corresponding build-up layer holes can form a hole network. The types of these hole networks can be power hole networks or ground hole networks.

[0052] Figure 1 FIG. 2 shows a schematic diagram of the hole network distribution in a related art. Figure 1 As shown, the hole network array of the embodiment of the present application may include multiple power hole networks 101 and multiple ground hole networks 102 staggered and arranged in an array, and whether in the array row direction or the array column direction, the power hole network 101 and the ground hole network 102 are arranged in a staggered manner. In this case, it is necessary to limit the spacing between the power hole network 101 and the ground hole network 102 to avoid the risk of short circuit in process manufacturing, but this also causes the hole network density on the packaging substrate to be relatively low, which is not conducive to the packaging design requirements of high-power chips.

[0053] For example, from a top-down perspective of the packaging substrate, four ground hole networks 102 are arranged around a single power hole network 101, and each power hole network 101 and the four ground hole networks 102 around it need to retain a gap of at least 60 μm to ensure that the contact leads formed by the power hole network 101 and the ground hole network 102 will not short-circuit during the manufacturing process. However, this also results in the power hole network 101 and the ground hole network 102 occupying a relatively large space on the packaging substrate, resulting in a relatively low overall density of the hole network on the packaging substrate.

[0054] At present, we can take the control of the power distribution network (PDN) system impedance as the starting point and adopt the PDN system network design method to optimize the PDN system impedance. This method is called the target impedance design method. Its core idea is to optimize the PDN system impedance by using the linear constraint relationship between the current change, impedance, and voltage change.

[0055] Figure 2 FIG. 2 shows a schematic diagram of the structure of the PDN system in an embodiment of the present application. Figure 2 As shown, the PDN system 200 may include a power supply 201 and a capacitor 202 connected in series to the power supply 201. Since various factors of the PDN system 200 can be attributed to the influence on the impedance, the PDN system 200 can be equivalent to Figure 3 The equivalent model 300 of the PDN system is shown. Figure 3 As shown, the equivalent model 300 may include a constant voltage source 301 and an impedance 302 connected in series to the constant voltage source 301, and the voltage difference ΔV across the impedance 302 satisfies ΔV=Z*ΔI, the impedance 302 may represent the total impedance of the package substrate, and ΔI represents the maximum transient current change of the constant voltage source 301. When the current ΔI is constant, if the voltage difference ΔV across the impedance needs to be controlled within an allowable range, the impedance of the PDN system needs to be controlled, and the smaller the impedance, the better the performance of the PDN system.

[0056] For the packaging substrate, power supply impedance is an important factor affecting the chip power supply. Figure 4 FIG. 1 shows a schematic diagram of a chip packaging principle. Figure 4 As shown, in the embodiment of the present application, a voltage regulator module (VRM) 401 can provide a suitable power supply voltage for the bare die, which can be connected to the bare die 403 through a package substrate 402. The core layer (i.e., the core board) of the package substrate 402 is provided with a plurality of plated through holes PTH, and the current I output by the VRM401 can be transmitted to the bare die 403 through the plurality of plated through holes PTH, so that the VRM401 supplies power to the bare die 403.

[0057] like Figure 4As shown, when the current I output by VRM401 is equivalent to water flow, the core layer of the package substrate 402 can be equivalent to a filter screen perpendicular to the water flow surface, and the density of the plated through hole PTH can be equivalent to the hole density on the filter screen. Since the aperture size of the plated through hole PTH is consistent under the same process standard, that is, the hole size on the filter screen is consistent, therefore, under the same water flow intensity, the greater the hole density on the filter screen of the same size, the more water will pass through the filter screen in the same time. Similarly, the greater the density of the plated through hole PTH in the core layer of the package substrate 402 of the same size, the stronger the corresponding flow capacity and the better the power supply effect.

[0058] The present application provides a packaging substrate and a packaging device, which can be applicable to a multi-layer packaging substrate, such as a packaging substrate with six or more layers, and can increase the hole network density of the packaging substrate by arranging different hole networks in the hole network matrix, thereby ensuring the packaging design requirements of high-power chips. It should be understood that the number of layers of the packaging substrate in the embodiment of the present application can refer to the number of lead layers contained in the packaging substrate.

[0059] Figure 5 FIG. 1 shows a schematic diagram of the basic structure of the packaging substrate of an embodiment of the present application. Figure 5 As shown, the packaging substrate 500 provided in the embodiment of the present application includes: a first dielectric layer 501 and a via layer 502 , and the via layer 502 is formed above the first dielectric layer 501 .

[0060] The first dielectric layer of the embodiment of the present application has a hole network array and a first conductive structure array matching the hole network array, the hole network array may include multiple hole networks, and the first conductive structure array may include multiple first conductive structures. In this case, the multiple first conductive structures included in the first conductive structure array are correspondingly arranged in the multiple hole networks included in the hole network array, and the first conductive structure array is connected to the transfer layer 502. For example, the first conductive structure corresponds to the hole network one by one, and the first conductive structure can be arranged in the corresponding hole network.

[0061] Figure 6 FIG. 2 shows a schematic plan view of the pore network of an embodiment of the present application. Figure 6 As shown, the hole network 503 of the embodiment of the present application may include a core hole 5031 and a stacked hole 5032. The number of the stacked holes 5032 may be one or more. The core hole 5031 and the stacked holes 5032 are distributed along the thickness direction of the first dielectric layer 501. The core hole 5031 and the stacked holes 5032 may be distributed on the first dielectric layer 501 in a direction close to the transfer hole layer 502, and the core hole 5031 and the stacked holes 5032 may also be distributed on the first dielectric layer 501 in a direction away from the transfer hole layer 502.

[0062] Figure 7A schematic diagram of a hole network array according to an embodiment of the present application is shown. Figure 7 As shown, the multiple hole networks 503 of the embodiment of the present application can be divided according to the type of signal transmitted, and can include a first type of hole network group and a second type of hole network group. The number of the first type of hole network group and the second type of hole network group can be set according to actual conditions, and the first type of hole network group and the second type of hole network group can be alternately distributed along the first preset direction Y.

[0063] In practical applications, such as Figure 7 As shown, the first type of hole network group of the embodiment of the present application includes a plurality of first type conductive hole networks 503A distributed along the second preset direction X, and the second type of hole network group includes a plurality of second type conductive hole networks 503B distributed along the second preset direction X. When the first type of conductive hole network 503A is a power hole network, the second type of conductive hole network 503B is a ground hole network; when the first type of conductive hole network 503A is a ground hole network, the second type of conductive hole network 503B is a power hole network.

[0064] Exemplarily, for each first-type hole network group, the geometric center of the core hole projection in each first-type conductive hole network 503A is located on the same first straight line, and for each second-type hole network group, the geometric center of the core hole projection in each second-type conductive hole network 503B is located on the same second straight line. Since the first-type hole network group and the second-type hole network group can be alternately distributed along the first preset direction Y, the first straight line and the second straight line are different straight lines.

[0065] Correspondingly, such as Figure 7 As shown, the first conductive structures formed in the plurality of first-type conductive hole networks 503A may also be distributed along the second preset direction X, and the first conductive structures formed in the plurality of second-type conductive hole networks 503B may also be distributed along the second preset direction X. Here, the first preset direction Y and the second preset direction X of the embodiment of the present application may be different, for example, the first preset direction Y and the second preset direction X are perpendicular.

[0066] like Figure 7As shown, when the first type of hole network group and the second type of hole network group are alternately distributed along the first preset direction Y, since the signal types transmitted by the first conductive structure formed in the first type of hole network group and the second type of hole network group are different, the spacing between the first type of conductive hole network 503A included in the first type of hole network group and the second type of conductive hole network 503B included in the second type of hole network group is relatively large, so as to avoid the risk of short circuit in process manufacturing. Since the signal types transmitted by the multiple first type of conductive hole networks 503A included in each first type of hole network group are the same, and the signal types transmitted by the multiple second type of conductive hole networks 503B included in each second type of hole network group are the same, even if the spacing between two adjacent first type of conductive hole networks 503A is relatively small, the risk of short circuit in process manufacturing is relatively low. Similarly, even if the spacing between two adjacent second type of conductive hole networks 503B is relatively small, the risk of short circuit in process manufacturing is relatively low.

[0067] It can be seen that when the spacing between the first type of hole network group and the adjacent second type of hole network group is the first spacing d1, the spacing between the two adjacent first type of conductive hole networks included in each first type of hole network group is the second spacing d2, and the spacing between the two adjacent second type of conductive hole networks included in each second type of hole network group is the third spacing d3, d2<d1, d3<d1.

[0068] When d2<d1, d3<d1, the first conductive structure formed in the first type of hole network group and the second type of hole network group avoids the risk of short circuit in process manufacturing, improves the fault tolerance of production and use, and ensures that the packaged device can be used normally. The distribution density of the first type of conductive hole network 503A included in the first type of hole network group in the second preset direction X is relatively high. It can be seen that the packaging substrate 500 of the embodiment of the present application can compress the space occupied by the hole network in the second preset direction X, so that the hole network density in the second preset direction X increases, thereby reducing the overall impedance of the packaged device and improving the current flow capacity. Similarly, when the second type of hole network group includes multiple second type conductive hole networks 503B, the overall impedance of the packaged device can also be reduced and the current flow capacity can be improved.

[0069] like Figure 7 As shown, when the first preset direction Y and the second preset direction X are perpendicular, the first preset direction Y represents the column mode of the hole network array, and the second preset direction X represents the row direction of the hole network array. The package substrate of the embodiment of the present application can compress the space occupied by the hole network in the column direction and increase the density of the hole network in the row direction. Similarly, when the first preset direction and the second preset direction are perpendicular, the first preset direction represents the row mode of the hole network array, and the second preset direction represents the column direction of the hole network array. The package substrate of the embodiment of the present application can compress the space occupied by the hole network in the column direction and increase the density of the hole network in the column direction.

[0070] When the second spacing and the third spacing are both smaller than the first spacing, the distribution density of the first type of hole network group and the second type of hole network group in the first preset direction is relatively low, thereby avoiding the risk of short circuit, improving the tolerance of production and use, and ensuring that the packaged device can be used normally. The distribution density of the first type of conductive hole network included in the first type of hole network group in the second preset direction is relatively high, which can reduce the overall impedance of the packaged device and improve the current carrying capacity. Similarly, the distribution density of the second type of conductive hole network included in the second type of hole network group in the second preset direction is relatively high, which can reduce the overall impedance of the packaged device and improve the current carrying capacity.

[0071] In an alternative approach, Figure 5 and Figure 7 As shown, the package substrate 500 of the embodiment of the present application may also include a second dielectric layer 504, a via layer 502 is formed between the first dielectric layer 501 and the second dielectric layer 504, the second dielectric layer 504 has a via array and a second conductive structure array matching the via array, and the second conductive structure array includes a plurality of second conductive structures correspondingly arranged in the plurality of vias 504A included in the via array. In this case, the first conductive structure array is connected to the second conductive structure array through the via layer 502, so when the die is packaged on the printed circuit board through the package substrate 500, regardless of whether the arrangement form of the die bump array and the hole network array is the same, the first conductive structure array of the first dielectric layer 501 can be connected to the die bump array through the via layer 502 and the second conductive structure array as a medium, so the package substrate 500 of the embodiment of the present application can realize the decoupling of the arrangement form of the die bump array and the hole network array, solve the problem of mismatch between the arrangement form of the die bump array and the hole network array, and improve the application range of the package substrate.

[0072] It should be noted that the spacing between two pore networks in the embodiment of the present application may refer to the minimum distance between the two pore networks, which may be the distance between two core holes, or the distance between the core hole of one pore network and the stacked hole of the other pore network, or the distance between two stacked holes.

[0073] In an alternative approach, Figure 8 FIG. 2 shows a schematic diagram of the three-dimensional structure of the pore network of an embodiment of the present application. Figure 5 and 8 As shown, each hole network 503 may include lower accumulation holes 5032A, core holes 5031 and upper accumulation holes 5032B arranged along the thickness direction of the first dielectric layer 501 in the direction close to the transfer hole layer 502. The number of lower accumulation holes 5032A and the number of upper accumulation holes 5032B may be one or more. Figure 8 The number of lower build-up layer holes 5032A and the number of upper build-up layer holes 5032B shown may both be four.

[0074] like Figure 8 As shown, the aperture of the lower accumulation hole 5032A and the aperture of the upper accumulation hole 5032B in the embodiment of the present application are both smaller than the aperture of the core hole 5031 , and the projections of the lower accumulation hole 5032A and the upper accumulation hole 5032B included in each hole network 700 on the same preset plane are located circumferentially of the core hole 5031 .

[0075] For example, Figure 5 and Figure 8 As shown, when the first dielectric layer 501 includes a core layer 5011, a lower buildup layer 5012 and an upper buildup layer 5013, the core layer 5011 is located between the lower buildup layer 5012 and the upper buildup layer 5013. Here, the lower buildup layer 5012 and the upper buildup layer 5013 can be a single-layer structure or a multi-layer structure.

[0076] like Figure 8 As shown, the core hole 5031 can be opened on the core layer 5011, the lower accumulation layer 5012 opens a lower accumulation layer hole 5032A, the number of which can be one or more, the upper accumulation layer 5013 opens an upper accumulation layer hole 5032B, the number of which can be one or more, and the transfer hole layer 502 is located on the surface of the upper accumulation layer 5013 away from the core layer 5031.

[0077] In the formation of Figure 8 When forming the core hole 5031 as shown in FIG. 1 , a PTH process can be used to open a hole in the core layer 5011, and a conductive metal is electroplated in the opened hole to form the core hole 5031 as a plated through hole. Figure 8 When the lower build-up layer hole 5031A is formed as shown, a laser hole can be formed in the lower build-up layer 5012 by a laser drilling process to serve as the lower build-up layer hole 5031A; Figure 8 When the upper build-up layer hole 5031B is formed, a laser hole can be formed in the upper build-up layer 5013 using a laser drilling process to serve as the upper build-up layer hole 5031B.

[0078] Each first conductive structure includes an upper build-up layer conductive contact portion, a lower build-up layer conductive contact portion and a core conductive contact portion. The upper build-up layer conductive contact portion included in each first conductive structure is arranged in the upper build-up layer hole included in the corresponding hole network, the lower build-up layer conductive contact portion included in each first conductive structure is arranged in the lower build-up layer hole included in the corresponding hole network, and the core conductive contact portion included in each first conductive structure is arranged in the core hole included in the corresponding hole network.

[0079] like Figure 8As shown, considering that the projections of the lower buildup holes 5032A and the upper buildup holes 5032B included in each hole network 503 on the same preset plane are located in the circumference of the core hole 5031, the lower buildup conductive contact portion formed by the lower buildup hole 5032A may not be directly connected to the core conductive contact portion formed by the core hole 5031, and the lower buildup conductive contact portion formed by the upper buildup hole 5032B may not be directly connected to the core conductive contact portion formed by the core hole 5031. Therefore, as Figure 5 As shown, the packaging substrate 500 of the embodiment of the present application may also include a first lead layer L1 and a second lead layer L2, so that the lower conductive contact portion included in the same first conductive structure is connected to the middle conductive contact portion through the first lead layer L1, the middle conductive contact portion is connected to the upper conductive contact portion through the second lead layer L2, and the via layer 502 is connected to the upper conductive contact portion included in each first conductive structure.

[0080] In an alternative approach, Figure 5 As shown, the packaging substrate 500 of the embodiment of the present application may also include a hole pad array matching the bare chip bump array, the via layer 502 is arranged above the first dielectric layer 501, the second dielectric layer 504 is arranged on the surface of the via layer 502 away from the first dielectric layer 501, and the hole pad array is formed on the surface of the second dielectric layer 504 away from the via layer 502.

[0081] like Figure 5 As shown, the second dielectric layer has a rotary hole array, the rotary hole array and the hole network array are staggered in their orthographic projections on the same preset plane, the hole pad array includes a plurality of hole pads 505 formed on the surface of the plurality of rotary holes 504A included in the rotary hole array away from the rotary hole layer 502, and the rotary hole array and the hole network array are staggered in their orthographic projections on the same preset plane.

[0082] like Figure 5 As shown, the number of the hole-transfer layers 502 and the second dielectric layer 504 in the embodiment of the present application is multiple. When the second dielectric layer 504 is multi-layered, the multiple hole-transfer layers 502 are distributed in a direction away from the first dielectric layer 501, and a second dielectric layer 504 is arranged between two adjacent hole-transfer layers 502. Here, the projections of the hole-transfer arrays of different second dielectric layers 504 on the preset plane may be different.

[0083] like Figure 5As shown, since the via layer 502 is provided between the first dielectric layer 501 and the second dielectric layer 504, the second dielectric layer 504 has a via array, and the via array and the hole network array are staggered in their orthographic projections on the same preset plane, the hole network array can be rearranged through the via array provided in the second dielectric layer 504. At the same time, since the plurality of via pads 505 included in the via pad array are formed on the surface of the plurality of vias included in the via array away from the via layer, and the via pad array matches the die bump array, the second conductive structure provided in the via 504A can be connected to the die bumps through the via pads 505.

[0084] It can be seen that no matter what the distribution form of the hole network array is, the first conductive structure array provided therein can be connected to the hole pad array through the via layer and the second conductive structure array, and the hole pad array can be in contact with the bare chip bump array. Therefore, the packaging substrate of the present application can provide power signals to the bare chip at a lower impedance.

[0085] In an alternative approach, Fig. 9 The schematic diagram of the arrangement of the hole network in the embodiment of the present application is shown. Fig. 9 As shown, the first type of conductive hole networks 503A included in different first type hole network groups of the present application are aligned and formed as shown in FIG. Figure 5 In the first dielectric layer 501 shown, a plurality of second-type conductive hole networks 503B including different second-type hole networks are aligned and formed in the first dielectric layer 501 .

[0086] like Fig. 9 As shown, when the first preset direction Y is the column direction of the hole network array and the second preset direction X is the row direction of the hole network array, for the first type of conductive hole networks 503A in different rows, the geometric center connection line of the first type of conductive hole networks 503A in the same column is the same as the column direction. Similarly, for the second type of conductive hole networks 503B in different rows, the geometric center connection line of the second type of conductive hole networks 503B in the same column is the same as the column direction.

[0087] like Fig. 9 As shown, 35 hole networks can form a 5×7 hole network array, the odd-numbered row hole networks are the first type of hole network group, and the even-numbered row hole networks are the second type of hole network group. Since the hole networks in the same column included in the odd-numbered row hole network group and the even-numbered row hole network group are arranged in a symmetrical manner, the geometric center lines of the first type of conductive hole networks 503A in the same column included in each odd-numbered row hole network group are on the same straight line, and the geometric center lines of the second type of conductive hole networks 503B in the same column included in each even-numbered row hole network group are on the same straight line. In addition, the geometric centers of the first type of conductive hole networks 503A in the same column and the geometric centers of the second type of conductive hole networks 503B in the same column are on the same straight line.

[0088] For example, Fig. 9 As shown, the geometric center of the first column of the first type of conductive hole network 503A included in each odd-numbered hole network group is located on the first vertical line M1, and the geometric center of the first column of the second type of conductive hole network 503B included in each even-numbered hole network group is located on the first vertical line M1.

[0089] In an alternative approach, Fig.10 Another schematic diagram of the hole network array of the embodiment of the present application is shown. Fig.10 As shown, the first type of hole network group includes a plurality of first type conductive hole networks 503A and the adjacent second type of hole network group includes a plurality of second type conductive hole networks 503B staggered to form a plurality of conductive hole networks 503A. Figure 5 On the first dielectric layer 501 as shown.

[0090] For example, Fig.10 As shown, the geometric centers of the core holes projected in the corresponding first type conductive hole networks 503A included in different first type hole network groups are located on the same third straight line, and the geometric centers of the core holes projected in the corresponding second type conductive hole networks 503B included in different second type hole network groups are located on the same fourth straight line. When the plurality of first type conductive hole networks 503A included in the first type hole network group are misaligned with the plurality of second type conductive hole networks 503B included in the adjacent second type hole network group, the third straight line and the fourth straight line are different straight lines.

[0091] like Fig.10 As shown, when the multiple first-class conductive hole networks 503A included in the first-class hole network group are misaligned with the multiple second-class conductive hole networks 503B included in the adjacent second-class hole network group, the second-class conductive hole network 503B included in the second-class hole network group is located between the two adjacent first-class conductive hole networks 503A included in the adjacent first-class hole network group. In this case, the gap between the two adjacent second-class conductive hole networks 503B included in the adjacent second-class hole network group can be used to provide more accommodation space for the adjacent first-class hole network group, thereby reducing the distance between the first-class hole network group and the adjacent second-class hole network group (i.e., the first distance). In this way, not only the short-circuit risk of the first conductive structure formed in the first-class hole network group and the second-class hole network group in the process manufacturing is relatively low, but also the distribution density of the first-class hole network and the second-class hole network in the first preset direction can be increased, thereby reducing the overall impedance of the packaged device and improving the current capacity.

[0092] For example, for a unit area of ​​3000μm×4000μm, when a staggered method is used to form a power structure as a packaged device, the power hole network is arranged in the same row, and the ground hole network is arranged in the same row, and the stacked holes included in one row of hole networks can be inserted between two adjacent hole networks included in an adjacent row of hole networks. In this case, the hole network density in the column direction will be relatively high. For example, the number of hole networks in a unit area of ​​3000μm×4000μm can be 60, which is relatively low compared to the number of hole networks in a unit area of ​​3000μm×4000μm in the traditional solution (such as relatively Figure 7 35 as shown) and performs better in large-size and high-power server chips.

[0093] Fig.11 The schematic diagram of the staggered arrangement of the hole network in the embodiment of the present application is shown. Fig.11 As shown, 60 hole networks can form a 5×12 hole network array, the odd-numbered hole networks are the first-type hole network groups, and the geometric center lines of the first-type conductive hole networks 503A in the same column included in each odd-numbered hole network group are in the same straight line, and the geometric center lines of the second-type conductive hole networks 503B in the same column included in each even-numbered hole network group are in the same straight line. And the straight line where the geometric center of the first-type conductive hole network 503A in the same column is located is on a different straight line from the straight line where the geometric center of the second-type conductive hole network 503B in the same column is located.

[0094] For example, Fig.11 As shown, the geometric center of the first column of the first type of conductive hole network 503A included in each odd-numbered hole network group is on the first vertical line M1, and the geometric center of the first column of the second type of conductive hole network 503B included in each even-numbered hole network group is on the second vertical line M2.

[0095] In some optional ways, when the multiple first-type conductive hole networks included in the first-type hole network group of the embodiment of the present application are misaligned with the multiple second-type conductive hole networks included in the adjacent second-type hole network group, the projection pattern of each hole network on the preset plane includes a core hole projection and multiple layer hole projections located circumferentially of the core hole projection, the multiple layer hole projections include a target hole projection, and the target hole projection in each hole network group is located in the gap between the projection patterns of two adjacent hole networks in the adjacent hole network group on the preset plane. Here, each hole network group may include a first-type hole network group or a second-type hole network group.

[0096] When the projection of the target hole in each hole network group is located in the gap between the projection patterns of two adjacent hole networks in the adjacent hole network group on the preset plane, each hole network group can partially overlap with the space occupied by the adjacent hole network group in the first preset direction in the first preset direction. When the multiple first-class conductive hole networks included in different first-class hole network groups are aligned, the space occupied by each hole network group in the first preset direction is independent of the space occupied by the adjacent hole network group in the first preset direction. It can be seen that in the embodiment of the present application, when the multiple first-class conductive hole networks included in the first-class hole network group are misaligned with the multiple second-class conductive hole networks included in the adjacent second-class hole network group, the density of the hole network in the first preset direction is relatively high, which can further reduce the overall impedance of the packaged device and improve the current carrying capacity.

[0097] For example, Fig. 12A A schematic diagram showing the distribution of the projection of the stacked holes on the hole network of the embodiment of the present application is shown. Fig. 12A As shown, the multiple stacked hole projections of the embodiment of the present application include a first pair of stacked hole projections and a second pair of stacked hole projections, the angle α between the geometric center line N1 of the first pair of stacked hole projections and the first preset direction Y is less than or equal to the first preset angle, and the angle β between the geometric center line N2 of the second pair of stacked hole projections and the second preset direction is less than or equal to the second preset angle. In this case, the first pair of stacked hole projections and the second pair of stacked hole projections are distributed around the core hole projection in a cross form.

[0098] For example, Fig. 12B Another schematic diagram of the distribution of the projection of the stacked holes on the hole network of the embodiment of the present application is shown. Fig. 12B As shown, the multiple stacked hole projections of the embodiment of the present application include a first pair of stacked hole projections 1202A and a second pair of stacked hole projections 1202B. The core hole projection 1201 of the embodiment of the present application may have a first side and a second side, the first pair of stacked hole projections 1202A are located on the first side, and the second pair of stacked hole projections 1202B are located on the second side.

[0099] like Fig. 12B As shown, when the projections of the plurality of stacked holes belong to the projection pattern of the first type of conductive hole network on the preset plane, the first side and the second side are distributed along the first preset direction Y. Fig. 12C As shown, when the projections of the plurality of stacked holes belong to the projection pattern of the second type of conductive hole network on the preset plane, the first side and the second side are distributed along the second preset direction X.

[0100] Fig.13 Another schematic diagram of the hole network array of the embodiment of the present application is shown. Fig.13 As shown, the hole network array of the embodiment of the present application is arranged in a 6×8 array, and the hole network array has a total of 48 networks.

[0101] When the projection pattern of each first type conductive hole network and each second type conductive hole network on the preset plane is referenced Fig. 12B When the distribution density of the hole network in the first preset direction Y is relatively low, the distribution density of the hole network in the second preset direction X is relatively high; when the projection pattern reference of each first type conductive hole network and each second type conductive hole network on the preset plane Fig. 12C When the hole network is distributed in the first preset direction Y, the density is relatively high, and the hole network is distributed in the second preset direction X, the density is relatively high.

[0102] Moreover, the projections of the two pairs of accumulated holes included in the multiple hole networks included in each hole network group (the first hole network group or the second hole network group) are distributed along the first preset direction Y. Although the distribution density of the hole network in the first preset direction Y is relatively high, since there is no distance requirement between the hole networks of the same type, compared with the hole networks of different types (using Fig. 12C The pore network structure shown in the figure is alternately distributed, and the distribution density of the pore network in the embodiment of the present application along the first preset direction is relatively high.

[0103] It can be seen that the embodiment of the present application limits the position and distribution direction of the projections of the two pairs of stacked holes included in the hole network relative to the projection of the core hole, which can not only increase the hole density of the hole network in the second preset direction X, but also increase the hole density of the hole network in the second preset direction X, thereby increasing the overall impedance of the packaging device, improving the current flow capacity, and avoiding short circuits during the process manufacturing process.

[0104] The embodiment of the present application further provides a packaging device, which may include a packaging substrate. The packaging substrate may refer to the packaging substrate 500 of the embodiment of the present application, or various deformation structures based on the packaging substrate 500.

[0105] Fig.14 FIG. 1 shows a schematic diagram of the structure of a packaging device provided in an embodiment of the present application. Fig.14 As shown, the packaged device of the embodiment of the present application may include a package substrate 1401 and a bare chip 1402. The package substrate 1401 includes a first dielectric layer 1401A, a via layer 1401B, a second dielectric layer 1401C and a plurality of hole pads 1401D, the first dielectric layer has a plurality of hole networks H1, which can be arranged with reference to various related arrangements of the hole network in the foregoing text, and the second dielectric layer has a plurality of vias H2, which can be arranged with reference to various related arrangements of the vias in the foregoing text.

[0106] The first conductive structure can be arranged in the hole network 1411A, the first conductive structure can be connected to the printed circuit board 1403 through the solder ball a, the first conductive structure can be connected to the hole pad 1401D through the via layer 1401B and the second conductive structure, and the hole pad 1401D can be connected to the die 1402 through the die bump b. The beneficial effects of the packaged device of the embodiment of the present application can refer to the beneficial effects of the package substrate of the embodiment of the present application, which will not be described in detail here.

[0107] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0108] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A packaging substrate, characterized in that: include: A first dielectric layer, a via layer and a second dielectric layer, wherein the via layer is formed between the first dielectric layer and the second dielectric layer, the first dielectric layer has a hole network array and a first conductive structure array matching the hole network array, a plurality of first conductive structures included in the first conductive structure array are correspondingly arranged in a plurality of hole networks included in the hole network array, the second dielectric layer has a via array and a second conductive structure array matching the via array, a plurality of second conductive structures included in the second conductive structure array are correspondingly arranged in a plurality of vias included in the via array, and the first conductive structure array is connected to the second conductive structure array through the via layer; The plurality of pore networks include a first type of pore network group and a second type of pore network group alternately distributed along a first preset direction, the first type of pore network group includes a plurality of first type of conductive pore networks distributed along a second preset direction, and the second type of pore network group includes a plurality of second type of conductive pore networks distributed along a second direction; The spacing between the first type of hole network group and the adjacent second type of hole network group is a first spacing, the spacing between two adjacent first type of conductive hole networks included in each first type of hole network group is a second spacing, and the spacing between two adjacent second type of conductive hole networks included in each second type of hole network group is a third spacing, and the second spacing and the third spacing are both smaller than the first spacing.

2. The packaging substrate according to claim 1, characterized in that: A plurality of first-type conductive hole networks included in different first-type hole network groups are aligned and formed in the first dielectric layer, and a plurality of second-type conductive hole networks included in different second-type hole networks are aligned and formed in the first dielectric layer.

3. The packaging substrate according to claim 1, characterized in that: The plurality of first-type conductive hole networks included in the first-type hole network group and the plurality of second-type conductive hole networks included in the adjacent second-type hole network group are staggeredly formed in the first dielectric layer.

4. The packaging substrate according to claim 1, characterized in that: For each of the first-type pore network groups, the geometric centers of the core pore projections in each of the first-type conductive pore networks are located on the same first straight line, and for each of the second-type pore network groups, the geometric centers of the core pore projections in each of the second-type conductive pore networks are located on the same second straight line, and the first straight line and the second straight line are different straight lines; The geometric centers of the projections of the core holes in the first type of conductive hole networks included in different first type hole network groups are located on the same third straight line, and the geometric centers of the projections of the core holes in the second type of conductive hole networks included in different second type hole network groups are located on the same fourth straight line, and the third straight line and the fourth straight line are different straight lines.

5. The packaging substrate according to claim 1, characterized in that: The projection pattern of each hole network on the preset plane includes a core hole projection and a plurality of accumulated hole projections located in the circumference of the core hole projection, and the plurality of accumulated hole projections include a target hole projection; The projection of the target holes in each of the hole network groups is located in the gap between the projection patterns of two adjacent hole networks in adjacent hole network groups on a preset plane, and each of the hole network groups includes a first type of hole network group or a second type of hole network group.

6. The packaging substrate according to claim 5, characterized in that: The multiple stacked hole projections include a first pair of stacked hole projections and a second pair of stacked hole projections, wherein an angle between a line connecting geometric centers of the first pair of stacked hole projections and the first preset direction is less than or equal to the first preset angle, and an angle between a line connecting geometric centers of the second pair of stacked hole projections and the second preset direction is less than or equal to the second preset angle.

7. The packaging substrate according to claim 5, characterized in that: The multiple build-up hole projections include a first pair of build-up hole projections and a second pair of build-up hole projections, the core hole projection has a first side and a second side, the first pair of build-up hole projections are located on the first side, the second pair of build-up hole projections are located on the second side, and the first side and the second side are distributed along the first preset direction.

8. The packaging substrate according to any one of claims 1 to 7, characterized in that: Each of the hole networks includes lower accumulation holes, core holes and upper accumulation holes arranged in the thickness direction of the first dielectric layer along the direction close to the transfer hole layer, the apertures of the lower accumulation holes and the apertures of the upper accumulation holes are both smaller than the aperture of the core holes, and the projections of the lower accumulation holes and the upper accumulation holes included in each of the hole networks on the same preset plane are located in the circumference of the core hole; Each of the first conductive structures comprises an upper build-up layer conductive contact portion, a lower build-up layer conductive contact portion and a core conductive contact portion, wherein the upper build-up layer conductive contact portion of each of the first conductive structures is disposed in an upper build-up layer hole corresponding to the hole network, the lower build-up layer conductive contact portion of each of the first conductive structures is disposed in a lower build-up layer hole corresponding to the hole network, and the core conductive contact portion of each of the first conductive structures is disposed in a core hole corresponding to the hole network; The packaging substrate also includes a first lead layer and a second lead layer. The lower conductive contact portion included in the same first conductive structure is connected to the middle conductive contact portion through the first lead layer, and the middle conductive contact portion included in the same first conductive structure is connected to the upper conductive contact portion through the second lead layer. The via layer is connected to the upper conductive contact portions included in each of the first conductive structures.

9. The packaging substrate according to any one of claims 1 to 7, characterized in that: The packaging substrate also includes a hole pad array matching the bare chip bump array, the hole pad array includes a plurality of hole pads formed on a surface of the plurality of vias included in the via array away from the via layer, and the via array and the hole network array are staggered in their orthographic projection on the same preset plane.

10. A packaging device, characterized in that: It comprises a bare chip and a packaging substrate as claimed in any one of claims 1 to 9.

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