Numerical control power supply circuit and terminal equipment

Abstract

The embodiment of the utility model discloses a numerical control power supply circuit and terminal equipment. The numerical control power supply circuit comprises a main control module, a core output module, an integrated display output module and an auxiliary output module, the main control module is connected with each output module and the CPU; each output module is connected with the CPU; the main control module outputs corresponding driving signals according to the power supply requirement of the CPU to respectively control the core output module to output a core voltage with a corresponding voltage value, the integrated display output module to output an integrated display voltage with a corresponding voltage value and the auxiliary output module to output an auxiliary voltage with a corresponding voltage value; the main control module also carries out current and temperature detection on the core output module, the integrated display output module and the auxiliary output module, and controls the working state of each output module. One main control module can simultaneously control the three output modules to output corresponding power supply to the CPU, separate control is not needed, and the problem that three groups of basic voltages of an existing CPU need to be separately controlled by two power supply main control chips is solved.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, in particular to a digital control power supply circuit and terminal equipment. Background Art

[0002] The existing CPU (central processing unit) is powered by three basic voltages, namely VDDCR voltage (core voltage), VDDCR_SOC voltage (integrated display voltage) and VDD_MISC voltage (auxiliary voltage). At present, the power supply circuit of the CPU designed on the motherboard requires two power supply main control chips and their peripheral circuits to control, one of which controls the output of VDDCR voltage and VDDCR_SOC voltage, and the other controls the output of VDD_MISC voltage. Both power supply main control chips are analog control chips, and the corresponding peripheral circuit structure is complex, the BOM (bill of materials) uses a lot of materials, and the R&D and material costs are high; and the operating performance of the motherboard is poor. Utility Model Content

[0003] In view of the above technical problems, the embodiments of the present utility model provide a digital control power supply circuit and a terminal device to solve the problem that the three basic voltages of the existing CPU need to be controlled separately by two power supply main control chips.

[0004] The utility model provides a digital control power supply circuit for supplying power to a CPU, which includes a main control module, a core output module, an integrated display output module and an auxiliary output module; the main control module is connected to the core output module, the integrated display output module, the auxiliary output module and the CPU; the core output module, the integrated display output module and the auxiliary output module are all connected to the CPU;

[0005] The main control module outputs corresponding driving signals according to the power supply requirements of the CPU to respectively control the core output module to output the core voltage of the corresponding voltage value, the integrated display output module to output the integrated display voltage of the corresponding voltage value, and the auxiliary output module to output the auxiliary voltage of the corresponding voltage value;

[0006] The main control module also performs current and temperature detection on the core output module, the integrated display output module and the auxiliary output module to control the working state of each output module.

[0007] Optionally, in the digital control power supply circuit, the main control module includes a digital power chip, a first capacitor, a first resistor and an enabling unit;

[0008] The PWM7 pin, CS7 pin and TEMP2 pin of the digital power chip are all connected to the integrated display output module; the PWM1 pin, PWM2 pin, PWM3 pin, PWM4 pin, PWM5 pin, CS1 pin, CS2 pin, CS3 pin, CS4 pin, CS5 pin and TEMP1 pin of the digital power chip are all connected to the core output module; the EN1 pin, EN2 pin and EN3 pin of the digital power chip are all connected to the enable unit; the SVD pin, SVC pin and SVIO pin of the digital power chip are one-to-one connected to the SVD pin, SVC pin and SVT pin of the CPU; the PWM8 pin, TEMP3 pin and CS8 pin of the digital power chip are all connected to the auxiliary output module; the VINSEN pin of the digital power chip is connected to one end of the first resistor, the other end of the first resistor inputs the first voltage, the VDD33 pin of the digital power chip inputs the second voltage, and the VDD18 pin of the digital power chip is grounded through the first capacitor.

[0009] Optionally, in the digital control power supply circuit, the enabling unit includes a first switch tube, a second switch tube, a second resistor, a third resistor, a fourth resistor, a second capacitor and a third capacitor;

[0010] The base of the first switch tube is connected to one end of the fourth resistor and one end of the second capacitor, the other end of the fourth resistor is input with the third voltage, the collector of the first switch tube is connected to one end of the second resistor and the gate of the second switch tube, the other end of the second resistor is input with the fourth voltage, the other end of the second capacitor and the emitter of the first switch tube are both grounded; the drain of the second switch tube is connected to one end of the third resistor and one end of the third capacitor, and is also connected to the EN1 pin, EN2 pin and EN3 pin of the digital power chip; the other end of the third resistor is input with the fifth voltage, and the source of the second switch tube and the other end of the third capacitor are both grounded.

[0011] Optionally, in the digital control power supply circuit, the main control module further includes a fifth resistor, a sixth resistor, a fourth capacitor and a fifth capacitor;

[0012] One end of the fifth resistor inputs the second voltage, the other end of the fifth resistor is connected to one end of the fourth capacitor and the VDD33 pin of the digital power chip, the other end of the fourth capacitor is grounded, one end of the sixth resistor is connected to the VINSEN pin of the digital power chip and one end of the first resistor, the other end of the sixth resistor is grounded, and the fifth capacitor is connected in parallel with the sixth resistor.

[0013] Optionally, in the digital control power supply circuit, the core output module includes a first driver chip, a second driver chip, a third driver chip, a fourth driver chip, a fifth driver chip, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor;

[0014] The VDRV pin, EN pin and VDD pin of the first driver chip are all input with the second voltage; the PWM pin, CS pin and VTEMP / FLT pin of the first driver chip are connected one-to-one with the PWM1 pin, CS1 pin and TEMP1 pin of the digital power chip; the VIN pin of the first driver chip is input with the first voltage, the SW1 pin and SW11 pin of the first driver chip are connected with one end of the first inductor, the other end of the first inductor is connected with the core voltage pin of the CPU, and the BST pin of the first driver chip is connected with the PHASE pin of the first driver chip through the sixth capacitor;

[0015] The VDRV pin, EN pin and VDD pin of the second driver chip are all input with the second voltage; the PWM pin, CS pin and VTEMP / FLT pin of the second driver chip are connected one-to-one with the PWM2 pin, CS2 pin and TEMP1 pin of the digital power chip; the VIN pin of the second driver chip is input with the first voltage, the SW1 pin and SW11 pin of the second driver chip are connected with one end of the second inductor, the other end of the second inductor is connected with the core voltage pin of the CPU, and the BST pin of the second driver chip is connected with the PHASE pin of the second driver chip through the seventh capacitor;

[0016] The VDRV pin, EN pin and VDD pin of the third driver chip are all input with the second voltage; the PWM pin, CS pin and VTEMP / FLT pin of the third driver chip are connected one-to-one with the PWM3 pin, CS3 pin and TEMP1 pin of the digital power chip; the VIN pin of the third driver chip is input with the first voltage, the SW1 pin and SW11 pin of the third driver chip are connected with one end of the third inductor, the other end of the third inductor is connected with the core voltage pin of the CPU, and the BST pin of the third driver chip is connected with the PHASE pin of the third driver chip through the eighth capacitor;

[0017] The VDRV pin, EN pin and VDD pin of the fourth driver chip are all input with the second voltage; the PWM pin, CS pin and VTEMP / FLT pin of the fourth driver chip are connected one-to-one with the PWM4 pin, CS4 pin and TEMP1 pin of the digital power chip; the VIN pin of the fourth driver chip is input with the first voltage, the SW1 pin and SW11 pin of the fourth driver chip are connected with one end of the fourth inductor, the other end of the fourth inductor is connected with the core voltage pin of the CPU, and the BST pin of the fourth driver chip is connected with the PHASE pin of the fourth driver chip through the ninth capacitor;

[0018] The VDRV pin, EN pin and VDD pin of the fifth driver chip all input the second voltage; the PWM pin, CS pin, VTEMP / FLT pin of the fifth driver chip are connected one-to-one with the PWM5 pin, CS5 pin and TEMP1 pin of the digital power chip; the VIN pin of the fifth driver chip inputs the first voltage, the SW1 pin and SW11 pin of the fifth driver chip are connected to one end of the fifth inductor, the other end of the fifth inductor is connected to the core voltage pin of the CPU, and the BST pin of the fifth driver chip is connected to the PHASE pin of the fifth driver chip through the tenth capacitor.

[0019] Optionally, in the digital control power supply circuit, the core output module further includes an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor and a fifteenth capacitor;

[0020] One end of the eleventh capacitor is connected to the other end of the first inductor and the core voltage pin of the CPU, one end of the twelfth capacitor is connected to the other end of the second inductor and the core voltage pin of the CPU, one end of the thirteenth capacitor is connected to the other end of the third inductor and the core voltage pin of the CPU, one end of the fourteenth capacitor is connected to the other end of the fourth inductor and the core voltage pin of the CPU, and one end of the fifteenth capacitor is connected to the other end of the fifth inductor and the core voltage pin of the CPU; the other end of the eleventh capacitor, the other end of the twelfth capacitor, the other end of the thirteenth capacitor, the other end of the fourteenth capacitor, and the other end of the fifteenth capacitor are all grounded.

[0021] Optionally, in the digital control power supply circuit, the core output module further includes a sixteenth capacitor, a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-fourth capacitor and a twenty-fifth capacitor;

[0022] The sixteenth capacitor is connected between the VDD pin and the AGND pin of the first driver chip, the seventeenth capacitor is connected between the VIN pin and the ground of the first driver chip, the eighteenth capacitor is connected between the VDD pin and the AGND pin of the second driver chip, the nineteenth capacitor is connected between the VIN pin and the ground of the second driver chip, the twentieth capacitor is connected between the VDD pin and the AGND pin of the third driver chip, the twenty-first capacitor is connected between the VIN pin and the ground of the third driver chip, the twenty-second capacitor is connected between the VDD pin and the AGND pin of the fourth driver chip, the twenty-third capacitor is connected between the VIN pin and the ground of the fourth driver chip, the twenty-fourth capacitor is connected between the VDD pin and the AGND pin of the fifth driver chip, and the twenty-fifth capacitor is connected between the VIN pin and the ground of the fifth driver chip.

[0023] Optionally, in the digital control power supply circuit, the integrated display output module includes a sixth driver chip, a sixth inductor and a twenty-sixth capacitor:

[0024] The VDRV pin, EN pin and VDD pin of the sixth driver chip are all input with the second voltage; the PWM pin, CS pin and VTEMP / FLT pin of the sixth driver chip are connected one-to-one with the PWM7 pin, CS7 pin and TEMP2 pin of the digital power chip; the VIN pin of the sixth driver chip is input with the first voltage, the SW1 pin and SW11 pin of the sixth driver chip are both connected with one end of the sixth inductor, the other end of the sixth inductor is connected with the core voltage pin of the CPU, and the BST pin of the sixth driver chip is connected with the PHASE pin of the sixth driver chip through the twenty-sixth capacitor.

[0025] Optionally, in the digital control power supply circuit, the auxiliary output module includes a seventh driving chip, a seventh inductor and a thirtieth capacitor:

[0026] The VDRV pin, EN pin and VDD pin of the seventh driver chip all input the second voltage; the PWM pin, CS pin, VTEMP / FLT pin of the seventh driver chip are connected one-to-one with the PWM8 pin, CS8 pin and TEMP3 pin of the digital power chip; the VIN pin of the seventh driver chip inputs the first voltage, the SW1 pin and SW11 pin of the seventh driver chip are both connected to one end of the seventh inductor, the other end of the seventh inductor is connected to the auxiliary voltage pin of the CPU, and the BST pin of the seventh driver chip is connected to the PHASE pin of the seventh driver chip through the thirtieth capacitor.

[0027] The second aspect of the embodiment of the utility model provides a terminal device, including a mainboard, on which a CPU is provided, wherein the mainboard is also provided with the digital control power supply circuit, and the digital control power supply circuit is connected to the CPU;

[0028] The digital control power supply circuit outputs core voltage, integrated display voltage and auxiliary voltage of corresponding voltage values ​​to supply power to the CPU according to the power supply demand of the CPU; and also controls the working state according to the current and temperature.

[0029] In the technical solution provided by the embodiment of the utility model, a digital control power supply circuit is used to power the CPU, which includes a main control module, a core output module, an integrated display output module and an auxiliary output module; the main control module is connected to the core output module, the integrated display output module, the auxiliary output module and the CPU; the core output module, the integrated display output module and the auxiliary output module are all connected to the CPU; the main control module outputs corresponding drive signals according to the power supply requirements of the CPU to control the core output module to output the core voltage of the corresponding voltage value, the integrated display voltage of the corresponding voltage value, and the auxiliary voltage of the corresponding voltage value of the auxiliary output module; the main control module also performs current and temperature detection on the core output module, the integrated display output module and the auxiliary output module to control the working state of each output module. One main control module can simultaneously control the three output modules to output the corresponding power supply to the CPU without separate control, saving some electronic components and solving the problem that the three basic voltages of the existing CPU need to be separately controlled by two power supply main control chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural block diagram of the mainboard in the embodiment of the utility model.

[0031] Figure 2 1 is a circuit diagram of the CPU in the embodiment of the utility model.

[0032] Figure 3 1 is a circuit diagram of the main control module in the embodiment of the utility model.

[0033] Figure 4 This is a circuit diagram of a portion of the core output module in an embodiment of the utility model.

[0034] Figure 5 This is another circuit diagram of the core output module in the embodiment of the utility model.

[0035] Figure 6 It is a circuit diagram of the integrated display output module in the embodiment of the utility model.

[0036] Figure 7 4 is a circuit diagram of an auxiliary output module in an embodiment of the utility model.

[0037] Figure 8 Schematic diagram of the circuit layout of the mainboard in the embodiment of the utility model. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. The embodiments in the utility model and all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the utility model.

[0039] See also Figure 1 The terminal device provided by the embodiment of the utility model includes a mainboard, on which a numerical control power supply circuit 10 and a CPU 20 are provided. The numerical control power supply circuit 10 is connected to the CPU 20. The numerical control power supply circuit 10 outputs a core voltage, an integrated display voltage and an auxiliary voltage of corresponding voltage values ​​to power the CPU according to the power supply requirements of the CPU; and also controls the working state according to the current and temperature.

[0040] The circuit structure of the CPU 20 is as follows Figure 2 As shown, only the pin connections related to this embodiment are shown here, and other pins and their connection relationships are prior art and are not described in detail here. As long as the CPU supports the SVI3 protocol, it can be powered by the CNC power supply circuit 10, such as the CPU of the AM5 platform. It should be understood that Figure 2 In the figure, the core voltage pins (VDDCR_n, n is a positive integer, sorted from 1 to 203) include VDDCR_1, VDDCR_2, VDDCR_3, ..., VDDCR_202 and VDDCR_203. The integrated graphics voltage pins (VDDCR_SOC_m, m is a positive integer, sorted from 1 to 24) include VDDCR_SOC_1, VDDCR_SOC_2, VDDCR_SOC_3, ..., VDDCR_SOC_23 and VDDCR_SOC_24. The auxiliary voltage pins (VDD_MISC_x, x is a positive integer, sorted from 1 to 20) include VDD_MISC_1, VDD_MISC_2, VDD_MISC_3, ..., VDD_MISC_19 and VDD_MISC_20. Since the number of power supply pins is large but they are all arranged in sequence, the power supply pins arranged in sequence in the middle part are omitted from the illustration.

[0041] It should be understood that the mainboard is also provided with an existing power supply circuit, which has multiple different power supply terminals, providing corresponding first voltage 12V_IN, second voltage +3VS, third voltage 1.05V, fourth voltage 5V_SB, fifth voltage 3P3V_SYS, etc. The specific circuit structure of the power supply circuit is not described in detail here.

[0042] The digital control power supply circuit 10 includes a main control module 110, a core output module 120, an integrated display output module 130 and an auxiliary output module 140; the main control module 110 is connected to the core output module 120, the integrated display output module 130, the auxiliary output module 140 and the CPU 20; the core output module 120, the integrated display output module 130 and the auxiliary output module 140 are all connected to the CPU 20; the main control module 110 outputs corresponding drive signals according to the power supply requirements of the CPU to control the core output module 120 to output a core voltage VDDCR of a corresponding voltage value, the integrated display output module 130 to output an integrated display voltage VDDCR_SOC of a corresponding voltage value, and the auxiliary output module 140 to output an auxiliary voltage VDD_MISC of a corresponding voltage value; the main control module 110 also performs current and temperature detection on the core output module 120, the integrated display output module 130 and the auxiliary output module 140 to control the working states of the core output module 120, the integrated display output module 130 and the auxiliary output module 140. One main control module can simultaneously control the three output modules to output the corresponding power to the CPU without separate control, saving some electronic components.

[0043] Please also read Figure 3 The main control module 110 includes a digital power chip UP, a first capacitor C1, a first resistor R1 and an enabling unit 111; the PWM7 pin, CS7 pin and TEMP2 pin of the digital power chip UP are all connected to the integrated display output module 130; the PWM1 pin, PWM2 pin, PWM3 pin, PWM4 pin, PWM5 pin, CS1 pin, CS2 pin, CS3 pin, CS4 pin, CS5 pin and TEMP1 pin of the digital power chip UP are all connected to the core output module 120; the EN1 pin, EN2 pin and EN3 pin of the digital power chip UP are all connected to the enabling unit 111; the SVD pin, SVC pin and SVIO pin of the digital power chip UP are connected to the CPU The SVD pin, SVC pin, and SVT pin of 20 are connected one-to-one; the PWM8 pin, TEMP3 pin, and CS8 pin of the digital power chip UP are all connected to the auxiliary output module 140; the VINSEN pin of the digital power chip UP is connected to one end of the first resistor R1, and the other end of the first resistor R1 inputs the first voltage 12V_IN, the VDD33 pin of the digital power chip UP inputs the second voltage +3VS, and the VDD18 pin of the digital power chip UP is grounded through the first capacitor C1.

[0044] The enabling unit 111 includes a first switch tube Q1 (NPN transistor), a second switch tube Q2 (NMOS), a second resistor R2, a third resistor R3, a fourth resistor R4, a second capacitor C2 and a third capacitor C3; a base B of the first switch tube Q1 is connected to one end of the fourth resistor R4 and one end of the second capacitor C2, and the other end of the fourth resistor R4 is input with a third voltage of 1.05V, a collector C of the first switch tube Q1 is connected to one end of the second resistor R2 and a gate G of the second switch tube Q2, and the other end of the second resistor R2 is input with a fourth voltage of 5V_SB, and the other end of the second capacitor C2 and the emitter E of the first switch tube Q1 are both grounded; a drain D of the second switch tube Q2 is connected to one end of the third resistor R3 and one end of the third capacitor C3, and is also connected to the EN1 pin, the EN2 pin and the EN3 pin of the digital power chip UP; the other end of the third resistor R3 is input with a fifth voltage of 3P3V_SYS, and the source S of the second switch tube Q2 and the other end of the third capacitor C3 are both grounded.

[0045] Among them, the model of the digital power chip UP is preferably MP2825, which supports the SVID (Serial Voltage Identification) power management protocol of AMD CPU, and transmits SVID signals (including data signal SVD, clock signal SVC and warning signal SVTO) between the CPU. The output voltage values ​​of the core voltage VDDCR, the integrated display voltage VDDCR_SOC and the auxiliary voltage VDD_MISC are controlled by the dynamic voltage regulation of the SVID signal. Under different working conditions, the CPU will autonomously send corresponding SVID request information to the digital power chip UP according to its own working voltage requirements. The digital power chip UP reads the SVID data of the SVID request information, and then converts it internally through the digital power chip UP, and outputs the corresponding drive signal for PWM control and regulation.

[0046] When the mainboard is connected to the power supply, when the power switch of the mainboard is not turned on, the third voltage 1.05V is not powered on, and the fourth voltage 5V_SB is powered on. The base B of the first switch tube Q1 is pulled up by R4 to 0V to a low level, the collector C and the emitter E of the first switch tube Q1 are not conducting, the gate G of the second switch tube Q2 is pulled up by R2 to a high level of the fourth voltage 5V_SB, and the drain D and the source S of the second switch tube Q2 are conducting and pulled to the ground; the first enable signal EN1, the second enable signal EN2 and the third enable signal EN3 are all low levels, and the digital power chip UP does not work at this time.

[0047] When the power switch of the mainboard is turned on, all voltages are powered, the third voltage 1.05V is powered on normally, and the fourth voltage 5V_SB and the fifth voltage 3P3V_SYS remain powered on. The base B of the first switch tube Q1 is pulled up to a high level of 1.05V by R4, the collector C and emitter E of the first switch tube Q1 are turned on and pulled to the ground, and the gate G of the second switch tube Q2 is pulled down to a low level, the drain D and the source S of the second switch tube Q2 are not conducting, and the three enable signals (EN1, EN2 and EN3) are pulled up to a high level of 3.3V by R3, and the digital power chip UP starts working.

[0048] At this time, the voltage detection signal VINSEN is generated on the 49th pin (i.e., the VINSEN pin) of the digital power chip UP, the second voltage +3VS is input to the 50th pin (i.e., the VDD33 pin), the three enable pins (i.e., the EN1 pin, the EN2 pin, and the EN3 pin used to turn on the control voltage signal) and all other input signals are normal, everything is ready, and the digital power chip UP starts working.

[0049] The PWM1 to PWM5 pins of the digital power chip UP correspond to outputting the first drive signal PWM1 to the fifth drive signal PWM5 to the core output module 120, respectively, to implement PWM pulse width modulation control. The digital power chip UP also receives the current signal fed back by the core output module 120, the integrated display output module 130 and the auxiliary output module 140, thereby adjusting the duty cycle of the corresponding drive signal PWMB to adjust the voltage of each output circuit until the required voltage value is reached; it also receives the temperature signal fed back by each output circuit, and outputs the corresponding drive signal PWM to control whether the corresponding output circuit is working.

[0050] R4 and C2, R3 and C3 form RC delay units respectively, which are used to set the power-on time of the enable pin of the digital power chip UP to achieve the purpose of timing control. R2 is a pull-up isolation resistor.

[0051] Most of the important power supply parameters are stored in the internal registers of the digital power supply chip UP (including PHASE_NUM power phase number, ICCMAX maximum current value, Frequency switching frequency, OCP overcurrent protection value, OVP overvoltage protection value, UVP undervoltage protection value, OTP overtemperature protection value, etc.). In specific implementation, the SDA and SCL pins of the digital power supply chip UP can be connected through the Tool provided by the manufacturer, and the internal register parameters of the chip can be read and adjusted through the I2C signal (SDA, SCL).

[0052] The peripheral circuit structure of the digital power chip UP is simple, the number of components used is small, and when adjusting the power parameters, the digital parameters of the chip internal registers can be directly modified without replacing the hardware components on the board. The R&D project design and power parameter debugging are simpler and more accurate, and the power performance is more efficient and stable.

[0053] Preferably, the main control module 110 also includes a fifth resistor R5, a sixth resistor R6, a fourth capacitor C4 and a fifth capacitor C5; one end of the fifth resistor R5 inputs the second voltage +3VS, the other end of the fifth resistor R5 is connected to one end of the fourth capacitor C4 and the VDD33 pin of the digital power chip UP, the other end of the fourth capacitor C4 is grounded, one end of the sixth resistor R6 is connected to the VINSEN pin of the digital power chip UP and one end of the first resistor R1, the other end of the sixth resistor R6 is grounded, and the fifth capacitor C5 is connected in parallel with the sixth resistor R6.

[0054] Among them, R5 is used to prevent sudden high voltage from burning out the VDD33 pin, C4 is used to filter the input second voltage +3VS, C5 is used to filter the voltage detection signal VINSEN, and the voltage division value of R1 and R6 is used to set the size of the voltage detection signal VINSEN.

[0055] Please also read Figure 4 and Figure 5 The core output module 120 includes a first driver chip U1, a second driver chip U2, a third driver chip U3, a fourth driver chip U4, a fifth driver chip U5, a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9 and a tenth capacitor C10; the VDRV pin, the EN pin and the VDD pin of the first driver chip U1 are all input with the second voltage +3VS; the AGND pin (including the AGND1 pin and the AGND2 pin) and the PGND pin (including the PGN The first driver chip U1 has a PWM pin, a CS pin, and a VTEMP / FLT pin connected to the PWM1 pin, the CS1 pin, and the TEMP1 pin of the digital power chip UP in a one-to-one manner; the first driver chip U1 has a VIN pin (including the VIN1 pin to the VIN4 pin) inputting a first voltage 12V_IN; the first driver chip U1 has a SW1 pin and a SW11 pin connected to one end of the first inductor L1; the other end of the first inductor L1 is connected to the core voltage pin of the CPU; the BST pin of the first driver chip U1 is connected to the PHASE pin of the first driver chip U1 through the sixth capacitor C6.

[0056] The VDRV pin, EN pin and VDD pin of the second driver chip U2 are all input with the second voltage +3VS; the AGND pin (including the AGND1 pin and the AGND2 pin) and the PGND pin (including the PGND1 pin to the PGND12 pin) of the second driver chip U2 are all grounded; the PWM pin, the CS pin, and the VTEMP / FLT pin of the second driver chip U2 are connected one-to-one with the PWM2 pin, the CS2 pin, and the TEMP1 pin of the digital power chip UP; the VIN pin (including the VIN1 pin to the VIN4 pin) of the second driver chip U2 is input with the first voltage 12V_IN, the SW1 pin and the SW11 pin of the second driver chip U2 are connected to one end of the second inductor L2, the other end of the second inductor L2 is connected to the core voltage pin of the CPU, and the BST pin of the second driver chip U2 is connected to the PHASE pin of the second driver chip U2 through the seventh capacitor C7.

[0057] The VDRV pin, EN pin and VDD pin of the third driver chip U3 are all input with the second voltage +3VS; the AGND pin (including the AGND1 pin and the AGND2 pin) and the PGND pin (including the PGND1 pin to the PGND12 pin) of the third driver chip U3 are all grounded; the PWM pin, the CS pin, and the VTEMP / FLT pin of the third driver chip U3 are connected one-to-one with the PWM3 pin, the CS3 pin, and the TEMP1 pin of the digital power chip UP; the VIN pin (including the VIN1 pin to the VIN4 pin) of the third driver chip U3 is input with the first voltage 12V_IN, the SW1 pin and the SW11 pin of the third driver chip U3 are connected to one end of the third inductor L3, the other end of the third inductor L3 is connected to the core voltage pin of the CPU, and the BST pin of the third driver chip U3 is connected to the PHASE pin of the third driver chip U3 through the eighth capacitor C8.

[0058] The VDRV pin, EN pin and VDD pin of the fourth driver chip U4 are all input with the second voltage +3VS; the AGND pin (including the AGND1 pin and the AGND2 pin) and the PGND pin (including the PGND1 pin to the PGND12 pin) of the fourth driver chip U4 are all grounded; the PWM pin, the CS pin, and the VTEMP / FLT pin of the fourth driver chip U4 are connected one-to-one with the PWM4 pin, the CS4 pin, and the TEMP1 pin of the digital power chip UP; the VIN pin (including the VIN1 pin to the VIN4 pin) of the fourth driver chip U4 is input with the first voltage 12V_IN, the SW1 pin and the SW11 pin of the fourth driver chip U4 are connected to one end of the fourth inductor L4, the other end of the fourth inductor L4 is connected to the core voltage pin of the CPU, and the BST pin of the fourth driver chip U4 is connected to the PHASE pin of the fourth driver chip U4 through the ninth capacitor C9.

[0059] The VDRV pin, EN pin and VDD pin of the fifth driver chip U5 are all input with the second voltage +3VS; the AGND pin (including the AGND1 pin and the AGND2 pin) and the PGND pin (including the PGND1 pin to the PGND12 pin) of the fifth driver chip U5 are all grounded; the PWM pin, the CS pin, and the VTEMP / FLT pin of the fifth driver chip U5 are connected one-to-one with the PWM5 pin, the CS5 pin, and the TEMP1 pin of the digital power chip UP; the VIN pin (including the VIN1 pin to the VIN4 pin) of the fifth driver chip U5 is input with the first voltage 12V_IN, the SW1 pin and the SW11 pin of the fifth driver chip U5 are connected to one end of the fifth inductor L5, the other end of the fifth inductor L5 is connected to the core voltage pin of the CPU, and the BST pin of the fifth driver chip U5 is connected to the PHASE pin of the fifth driver chip U5 through the tenth capacitor C10.

[0060] Among them, the models of the first driver chip U1 to the fifth driver chip U5 are preferably MP87661-A DrMOS (Driver and MOSFET) driver chips, and the working principles of each driver chip are the same. Here, the first driver chip U1 is taken as an example. The first drive signal PWM1 output by the digital power chip UP controls the PWM pulse width modulation of the first driver chip U1. After the upper and lower bridge MOS tubes inside the first driver chip U1 are switched, the first SW switch signal is output from the SW1 pin and the SW11 pin, and then converted into the core voltage VDDCR after energy storage by the first inductor L1 to provide core power supply for the CPU. The CS pin of the first driver chip U1 feeds back the first current signal CS1 to the digital power chip UP to detect the current output by the first driver chip U1, thereby adjusting the duty cycle of the first drive signal PWM1, and the output core voltage VDDCR can be adjusted. The VTEMP / FLT pin of the first driver chip U1 feeds back the first temperature signal VTEMP1 to the digital power chip UP to detect the operating temperature of the first driver chip U1. When the temperature is greater than the set threshold, the digital power chip UP outputs the corresponding first drive signal PWM1 (such as a low level) to control the first driver chip U1 to stop working.

[0061] Preferably, the core output module 120 also includes an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14 and a fifteenth capacitor C15; one end of the eleventh capacitor C11 is connected to the other end of the first inductor L1 and the core voltage pin of the CPU, one end of the twelfth capacitor C12 is connected to the other end of the second inductor L2 and the core voltage pin of the CPU, one end of the thirteenth capacitor C13 is connected to the other end of the third inductor L3 and the core voltage pin of the CPU, one end of the fourteenth capacitor C14 is connected to the other end of the fourth inductor L4 and the core voltage pin of the CPU, and one end of the fifteenth capacitor C15 is connected to the other end of the fifth inductor L5 and the core voltage pin of the CPU; the other end of the eleventh capacitor C11, the other end of the twelfth capacitor C12, the other end of the thirteenth capacitor C13, the other end of the fourteenth capacitor C14 and the other end of the fifteenth capacitor C15 are all grounded.

[0062] The SW switch signals output by the SW1 and SW11 pins of each driver chip are stored in the connected inductor and then filtered by the corresponding capacitor before being output, providing a more stable power supply to the CPU.

[0063] Preferably, the core output module 120 further includes a sixteenth capacitor C16, a seventeenth capacitor C17, an eighteenth capacitor C18, a nineteenth capacitor C19, a twentieth capacitor C20, a twenty-first capacitor C21, a twenty-second capacitor C22, a twenty-third capacitor C23, a twenty-fourth capacitor C24 and a twenty-fifth capacitor C25; the sixteenth capacitor C16 is connected between the VDD pin and the AGND pin of the first driver chip U1, the seventeenth capacitor C17 is connected between the VIN pin and the ground of the first driver chip U1, the eighteenth capacitor C18 is connected between the VDD pin and the AGND pin of the second driver chip U2, and the nineteenth capacitor C24 is connected between the VDD pin and the AGND pin of the second driver chip U2. C19 is connected between the VIN pin of the second driver chip U2 and the ground, the twentieth capacitor C20 is connected between the VDD pin and the AGND pin of the third driver chip U3, the twenty-first capacitor C21 is connected between the VIN pin of the third driver chip U3 and the ground, the twenty-second capacitor C22 is connected between the VDD pin and the AGND pin of the fourth driver chip U4, the twenty-third capacitor C23 is connected between the VIN pin of the fourth driver chip U4 and the ground, the twenty-fourth capacitor C24 is connected between the VDD pin and the AGND pin of the fifth driver chip U5, and the twenty-fifth capacitor C25 is connected between the VIN pin of the fifth driver chip U5 and the ground.

[0064] The sixteenth capacitor C16 to the twenty-fifth capacitor C25 are respectively used to filter the voltages on the connected pins to make the power supply of the corresponding driver chip more stable.

[0065] Please also read Figure 6The integrated display output module 130 includes a sixth driver chip U6, a sixth inductor L6 and a twenty-sixth capacitor C26: the VDRV pin, the EN pin and the VDD pin of the sixth driver chip U6 are all input with the second voltage +3VS; the AGND pin (including the AGND1 pin and the AGND2 pin) and the PGND pin (including the PGND1 pin to the PGND12 pin) of the sixth driver chip U6 are all grounded; the PWM pin, the CS pin, and the VTEMP / FLT pin of the sixth driver chip U6 are one-to-one connected with the PWM7 pin, the CS7 pin, and the TEMP2 pin of the digital power chip UP; the VIN pin (including the VIN1 pin to the VIN4 pin) of the sixth driver chip U6 is input with the first voltage 12V_IN, the SW1 pin and the SW11 pin of the sixth driver chip U6 are both connected to one end of the sixth inductor L6, the other end of the sixth inductor L6 is connected to the core voltage pin of the CPU, and the BST pin of the sixth driver chip U6 is connected to the PHASE pin of the sixth driver chip U6 through the twenty-sixth capacitor C26.

[0066] The model of the sixth driver chip U6 is preferably a DrMOS driver chip of MP87661-A. The sixth drive signal PWMA output by the digital power chip UP controls the PWM pulse width modulation of the sixth driver chip U6. After the upper and lower bridge MOS tubes inside the sixth driver chip U6 are switched, the sixth SW switch signal is output from the SW1 pin and the SW11 pin, and then after the sixth inductor L6 stores energy, the integrated display voltage VDDCR_SOC is output to provide integrated display power supply to the CPU. The CS pin of the sixth driver chip U6 feeds back the sixth current signal CSA to the digital power chip UP to detect the current output by the sixth driver chip U6, thereby adjusting the duty cycle of the sixth drive signal PWMA, and the output integrated display voltage VDDCR_SOC can be adjusted. The VTEMP / FLT pin of the sixth driver chip U6 feeds back the sixth temperature signal VTEMP2 to the digital power chip UP to detect the operating temperature of the sixth driver chip U6. When the temperature is greater than the set threshold, the digital power chip UP outputs the corresponding sixth drive signal PWMA to control the sixth driver chip U6 to stop working.

[0067] Preferably, the integrated display output module 130 also includes a twenty-seventh capacitor C27, a twenty-eighth capacitor C28 and a twenty-ninth capacitor C29; one end of the twenty-seventh capacitor C27 is connected to the other end of the sixth inductor L6 and the core voltage pin of the CPU, the other end of the twenty-seventh capacitor C27 is grounded, the twenty-eighth capacitor C28 is connected between the VDD pin and the AGND pin of the sixth driver chip U6, and the twenty-ninth capacitor C29 is connected between the VIN pin of the sixth driver chip U6 and ground.

[0068] The 27th capacitor C27 is used to filter the output integrated display voltage VDDCR_SOC to provide a more stable integrated display power supply to the CPU. The 28th capacitor C28 is used to filter the input second voltage +3VS, and the 29th capacitor C29 is used to filter the input first voltage 12V_IN to make the power supply of the sixth driver chip U6 more stable.

[0069] Please also read Figure 7 The auxiliary output module 140 includes a seventh driver chip U7, a seventh inductor L7 and a thirtieth capacitor C30: the VDRV pin, the EN pin and the VDD pin of the seventh driver chip U7 are all input with the second voltage +3VS; the AGND pin (including the AGND1 pin and the AGND2 pin) and the PGND pin (including the PGND1 pin to the PGND12 pin) of the seventh driver chip U7 are all grounded; the PWM pin, the CS pin, the VTEMP / FLT pin of the seventh driver chip U7 are one-to-one connected with the PWM8 pin, the CS8 pin and the TEMP3 pin of the digital power chip UP; the VIN pin (including the VIN1 pin to the VIN4 pin) of the seventh driver chip U7 is input with the first voltage 12V_IN, the SW1 pin and the SW11 pin of the seventh driver chip U7 are both connected to one end of the seventh inductor L7, the other end of the seventh inductor L7 is connected to the auxiliary voltage pin of the CPU, and the BST pin of the seventh driver chip U7 is connected to the PHASE pin of the seventh driver chip U7 through the thirtieth capacitor C30.

[0070] The model of the seventh driver chip U7 is preferably a DrMOS driver chip of MP87661-A. The sixth seventh drive signal PWMB output by the digital power chip UP controls the PWM pulse width modulation of the seventh driver chip U7. After the upper and lower bridge MOS tubes inside the seventh driver chip U7 are switched, the seventh SW switch signal is output from the SW1 pin and the SW11 pin, and then the auxiliary voltage VDD_MISC is output after energy storage by the seventh inductor L7 to provide auxiliary power supply to the CPU. The CS pin of the seventh driver chip U7 feeds back the seventh current signal CSB to the digital power chip UP to detect the current output by the seventh driver chip U7, thereby adjusting the duty cycle of the seventh drive signal PWMB, and the size of the output auxiliary voltage VDD_MISC can be adjusted. The VTEMP / FLT pin of the seventh driver chip U7 feeds back the seventh temperature signal VTEMP3 to the digital power chip UP to detect the operating temperature of the seventh driver chip U7. When the temperature is greater than the set threshold, the digital power chip UP outputs the corresponding seventh drive signal PWMB to control the seventh driver chip U7 to stop working.

[0071] Preferably, the integrated display output module 130 also includes a thirty-first capacitor C31, a thirty-second capacitor C32 and a thirty-third capacitor C33; one end of the thirty-first capacitor C31 is connected to the other end of the seventh inductor L7 and the auxiliary voltage pin of the CPU, the other end of the thirty-first capacitor C31 is grounded, the thirty-second capacitor C32 is connected between the VDD pin and the AGND pin of the seventh driver chip U7, and the thirty-third capacitor C33 is connected between the VIN pin of the seventh driver chip U7 and ground.

[0072] The thirty-first capacitor C31 is used to filter the output auxiliary voltage VDD_MISC to provide a more stable auxiliary power supply to the CPU. The thirty-second capacitor C32 is used to filter the input second voltage +3VS, and the thirty-third capacitor C33 is used to filter the input first voltage 12V_IN to make the power supply of the seventh driver chip U7 more stable.

[0073] Figure 8 Only the positions of some important components related to the present embodiment on the main board are shown, such as the main control module 110 and the core output module 120 are arranged adjacent to each other, the integrated display output module 130 is arranged on the right side of the CPU, and the auxiliary output module 140 is arranged on the left side of the CPU. This is only an example and can be laid out according to requirements during specific implementation.

[0074] In summary, the numerical control power supply circuit and terminal equipment provided by the utility model replace the existing two power main control chips with a single fully digital digital power chip with a DrMOS solution to simultaneously control the power supply voltage output of three CPUs. The digitalization of the power supply parameters of the digital power chip is more convenient for Debug. The peripheral circuit structure of the chip is simple, the circuit integration is high, the working efficiency is high, the mainboard operating performance is greatly improved, the number of parts required is small, the layout wiring is convenient, the BOM material is small, and the R&D and material costs are low.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A numerical control power supply circuit for supplying power to a CPU, characterized in that: It includes a main control module, a core output module, an integrated display output module and an auxiliary output module; the main control module is connected to the core output module, the integrated display output module, the auxiliary output module and the CPU; the core output module, the integrated display output module and the auxiliary output module are all connected to the CPU; The main control module outputs corresponding driving signals according to the power supply requirements of the CPU to respectively control the core output module to output the core voltage of the corresponding voltage value, the integrated display output module to output the integrated display voltage of the corresponding voltage value, and the auxiliary output module to output the auxiliary voltage of the corresponding voltage value; The main control module also performs current and temperature detection on the core output module, the integrated display output module and the auxiliary output module to control the working state of each output module.

2. The numerical control power supply circuit according to claim 1, characterized in that: The main control module includes a digital power chip, a first capacitor, a first resistor and an enabling unit; The PWM7 pin, CS7 pin and TEMP2 pin of the digital power chip are all connected to the integrated display output module; The PWM1 pin, PWM2 pin, PWM3 pin, PWM4 pin, PWM5 pin, CS1 pin, CS2 pin, CS3 pin, CS4 pin, CS5 pin and TEMP1 pin of the digital power chip are all connected to the core output module; The EN1, EN2 and EN3 pins of the digital power chip are all connected to the enable unit; The SVD pin, SVC pin, and SVIO pin of the digital power chip are connected one-to-one with the SVD pin, SVC pin, and SVT pin of the CPU; The PWM8 pin, TEMP3 pin and CS8 pin of the digital power chip are all connected to the auxiliary output module; The VINSEN pin of the digital power chip is connected to one end of the first resistor, the other end of the first resistor inputs the first voltage, the VDD33 pin of the digital power chip inputs the second voltage, and the VDD18 pin of the digital power chip is grounded through the first capacitor.

3. The numerical control power supply circuit according to claim 2, characterized in that: The enabling unit includes a first switch tube, a second switch tube, a second resistor, a third resistor, a fourth resistor, a second capacitor and a third capacitor; The base of the first switch tube is connected to one end of the fourth resistor and one end of the second capacitor, the other end of the fourth resistor is input with the third voltage, the collector of the first switch tube is connected to one end of the second resistor and the gate of the second switch tube, the other end of the second resistor is input with the fourth voltage, the other end of the second capacitor and the emitter of the first switch tube are both grounded; the drain of the second switch tube is connected to one end of the third resistor and one end of the third capacitor, and is also connected to the EN1 pin, EN2 pin and EN3 pin of the digital power chip; the other end of the third resistor is input with the fifth voltage, and the source of the second switch tube and the other end of the third capacitor are both grounded.

4. The numerical control power supply circuit according to claim 2, characterized in that: The main control module also includes a fifth resistor, a sixth resistor, a fourth capacitor and a fifth capacitor; One end of the fifth resistor inputs the second voltage, the other end of the fifth resistor is connected to one end of the fourth capacitor and the VDD33 pin of the digital power chip, the other end of the fourth capacitor is grounded, one end of the sixth resistor is connected to the VINSEN pin of the digital power chip and one end of the first resistor, the other end of the sixth resistor is grounded, and the fifth capacitor is connected in parallel with the sixth resistor.

5. The numerical control power supply circuit according to claim 2 or 3, characterized in that: The core output module includes a first driver chip, a second driver chip, a third driver chip, a fourth driver chip, a fifth driver chip, a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a tenth capacitor; The VDRV pin, EN pin and VDD pin of the first driver chip are all input with the second voltage; the PWM pin, CS pin and VTEMP / FLT pin of the first driver chip are connected one-to-one with the PWM1 pin, CS1 pin and TEMP1 pin of the digital power chip; the VIN pin of the first driver chip is input with the first voltage, the SW1 pin and SW11 pin of the first driver chip are connected with one end of the first inductor, the other end of the first inductor is connected with the core voltage pin of the CPU, and the BST pin of the first driver chip is connected with the PHASE pin of the first driver chip through the sixth capacitor; The VDRV pin, the EN pin and the VDD pin of the second driver chip are all input with a second voltage; The PWM pin, CS pin, and VTEMP / FLT pin of the second driver chip are connected one-to-one with the PWM2 pin, CS2 pin, and TEMP1 pin of the digital power chip; The VIN pin of the second driver chip inputs the first voltage, the SW1 pin and the SW11 pin of the second driver chip are connected to one end of the second inductor, the other end of the second inductor is connected to the core voltage pin of the CPU, and the BST pin of the second driver chip is connected to the PHASE pin of the second driver chip through the seventh capacitor; The VDRV pin, EN pin and VDD pin of the third driver chip are all input with the second voltage; the PWM pin, CS pin and VTEMP / FLT pin of the third driver chip are connected one-to-one with the PWM3 pin, CS3 pin and TEMP1 pin of the digital power chip; the VIN pin of the third driver chip is input with the first voltage, the SW1 pin and SW11 pin of the third driver chip are connected with one end of the third inductor, the other end of the third inductor is connected with the core voltage pin of the CPU, and the BST pin of the third driver chip is connected with the PHASE pin of the third driver chip through the eighth capacitor; The VDRV pin, the EN pin and the VDD pin of the fourth driver chip are all input with a second voltage; The PWM pin, CS pin, and VTEMP / FLT pin of the fourth driver chip are connected one-to-one with the PWM4 pin, CS4 pin, and TEMP1 pin of the digital power chip; the VIN pin of the fourth driver chip inputs the first voltage, the SW1 pin and the SW11 pin of the fourth driver chip are connected to one end of the fourth inductor, the other end of the fourth inductor is connected to the core voltage pin of the CPU, and the BST pin of the fourth driver chip is connected to the PHASE pin of the fourth driver chip through the ninth capacitor; The VDRV pin, the EN pin and the VDD pin of the fifth driver chip are all input with a second voltage; The PWM pin, CS pin, and VTEMP / FLT pin of the fifth driver chip are connected one-to-one with the PWM5 pin, CS5 pin, and TEMP1 pin of the digital power chip; The VIN pin of the fifth driver chip inputs the first voltage, the SW1 pin and SW11 pin of the fifth driver chip are connected to one end of the fifth inductor, the other end of the fifth inductor is connected to the core voltage pin of the CPU, and the BST pin of the fifth driver chip is connected to the PHASE pin of the fifth driver chip through the tenth capacitor.

6. The numerical control power supply circuit according to claim 5, characterized in that: The core output module further includes an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor and a fifteenth capacitor; One end of the eleventh capacitor is connected to the other end of the first inductor and the core voltage pin of the CPU, one end of the twelfth capacitor is connected to the other end of the second inductor and the core voltage pin of the CPU, one end of the thirteenth capacitor is connected to the other end of the third inductor and the core voltage pin of the CPU, one end of the fourteenth capacitor is connected to the other end of the fourth inductor and the core voltage pin of the CPU, and one end of the fifteenth capacitor is connected to the other end of the fifth inductor and the core voltage pin of the CPU; the other end of the eleventh capacitor, the other end of the twelfth capacitor, the other end of the thirteenth capacitor, the other end of the fourteenth capacitor, and the other end of the fifteenth capacitor are all grounded.

7. The numerical control power supply circuit according to claim 5, characterized in that: The core output module also includes a sixteenth capacitor, a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a twenty-third capacitor, a twenty-fourth capacitor and a twenty-fifth capacitor; The sixteenth capacitor is connected between the VDD pin and the AGND pin of the first driver chip, the seventeenth capacitor is connected between the VIN pin and the ground of the first driver chip, the eighteenth capacitor is connected between the VDD pin and the AGND pin of the second driver chip, the nineteenth capacitor is connected between the VIN pin and the ground of the second driver chip, the twentieth capacitor is connected between the VDD pin and the AGND pin of the third driver chip, the twenty-first capacitor is connected between the VIN pin and the ground of the third driver chip, the twenty-second capacitor is connected between the VDD pin and the AGND pin of the fourth driver chip, the twenty-third capacitor is connected between the VIN pin and the ground of the fourth driver chip, the twenty-fourth capacitor is connected between the VDD pin and the AGND pin of the fifth driver chip, and the twenty-fifth capacitor is connected between the VIN pin and the ground of the fifth driver chip.

8. The numerical control power supply circuit according to claim 5, characterized in that: The integrated display output module includes a sixth driver chip, a sixth inductor and a twenty-sixth capacitor: The VDRV pin, EN pin and VDD pin of the sixth driver chip are all input with the second voltage; the PWM pin, CS pin and VTEMP / FLT pin of the sixth driver chip are connected one-to-one with the PWM7 pin, CS7 pin and TEMP2 pin of the digital power chip; the VIN pin of the sixth driver chip is input with the first voltage, the SW1 pin and SW11 pin of the sixth driver chip are both connected with one end of the sixth inductor, the other end of the sixth inductor is connected with the core voltage pin of the CPU, and the BST pin of the sixth driver chip is connected with the PHASE pin of the sixth driver chip through the twenty-sixth capacitor.

9. The numerical control power supply circuit according to claim 5, characterized in that: The auxiliary output module includes a seventh driving chip, a seventh inductor and a thirtieth capacitor: The VDRV pin, EN pin and VDD pin of the seventh driver chip all input the second voltage; the PWM pin, CS pin, VTEMP / FLT pin of the seventh driver chip are connected one-to-one with the PWM8 pin, CS8 pin and TEMP3 pin of the digital power chip; the VIN pin of the seventh driver chip inputs the first voltage, the SW1 pin and SW11 pin of the seventh driver chip are both connected to one end of the seventh inductor, the other end of the seventh inductor is connected to the auxiliary voltage pin of the CPU, and the BST pin of the seventh driver chip is connected to the PHASE pin of the seventh driver chip through the thirtieth capacitor.

10. A terminal device, comprising a mainboard, wherein the mainboard is provided with a CPU, wherein: The mainboard is also provided with a numerical control power supply circuit as claimed in any one of claims 1 to 9, and the numerical control power supply circuit is connected to the CPU; The digital control power supply circuit outputs core voltage, integrated display voltage and auxiliary voltage of corresponding voltage values ​​to supply power to the CPU according to the power supply demand of the CPU; and also controls the working state according to the current and temperature.

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