Array substrate, display panel and display device

Abstract

The utility model discloses an array substrate, a display panel and a display device, and aims to solve the problem of abnormal display caused by non-uniform common voltage distribution of a large-size display panel in the prior art. The array substrate comprises a substrate body, a common electrode layer located on one side of the substrate body, a plurality of common connecting lines extending in the first direction and a plurality of first connecting parts. The common electrode layer comprises a plurality of common electrode rows which extend in the first direction and are arranged in the second direction, and a plurality of common electrode columns which extend in the second direction and are arranged in the first direction; the common electrode row comprises a plurality of common electrode blocks which are sequentially arranged along the first direction; the common electrode column comprises a plurality of common electrode blocks which are sequentially arranged in the second direction; in at least part of the common electrode columns, any two adjacent common electrode blocks are electrically connected through the first connecting parts.

Description

Technical Field

[0001] The utility model relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] Large-screen display products are widely used in practical applications. In large-size products, the IC signal transmission process will be greatly affected by the impedance load (RC loading). The impedance difference between the near and far ends of the IC is different. According to the formula R=ρL / S, ρ is the resistivity of the material, L is the wire length of the resistor, and S is the cross-sectional area of ​​the wire of the resistor. The larger the L, the larger the R, that is, the farther away from the IC end, the greater the impedance. In large-size products, due to the large-size display products, the signals near the IC end and far away from the IC end are affected by the difference in the size of RC loading, and the Vcom signal will have uneven brightness distribution in the display area, resulting in abnormal display. Utility Model Content

[0003] The utility model provides an array substrate, a display panel and a display device, so as to improve the display abnormality problem caused by uneven common voltage distribution in the large-size display panel of the prior art.

[0004] The embodiment of the utility model provides an array substrate, comprising: a substrate, a common electrode layer located on one side of the substrate, a plurality of common connection lines extending along a first direction, and a plurality of first connection parts;

[0005] The common electrode layer includes: a plurality of common electrode rows extending along the first direction and arranged along the second direction, and a plurality of common electrode columns extending along the second direction and arranged along the first direction; the common electrode rows include: a plurality of common electrode blocks arranged in sequence along the first direction; the common electrode columns include: a plurality of common electrode blocks arranged in sequence along the second direction;

[0006] The plurality of common electrode blocks in the same common electrode row are electrically connected via the common connection line; and in at least part of the common electrode columns, any two adjacent common electrode blocks are electrically connected via the first connection portion.

[0007] In a possible implementation manner, the array substrate further includes: a plurality of gate lines extending along the first direction; the common connection lines are made of the same layer and material as the gate lines;

[0008] In the same common electrode row, a plurality of common electrode blocks are in direct contact and electrically connected to the common connection line.

[0009] In a possible implementation manner, the first connection portion includes: a first sub-connection portion extending along the second direction, a second sub-connection portion connected to one end of the first sub-connection portion, and a third sub-connection portion connected to the other end of the first sub-connection portion; an orthographic projection of the first sub-connection portion on the substrate intersects with an orthographic projection of the gate line on the substrate;

[0010] The common connection line comprises: a connection line main portion extending along the first direction, and a connection line extension portion extending from the connection line main portion along a side away from the gate line;

[0011] The orthographic projection of the second sub-connection portion on the substrate covers the orthographic projection of the connection line extension portion on the substrate, and the common electrode block on one side of the gate line is electrically connected to the second sub-connection portion through the connection line extension portion.

[0012] In a possible implementation, the array substrate further includes: a transfer portion; the transfer portion is an orthographic projection of the substrate, covering the orthographic projection of the third sub-connection portion on the substrate, and the common electrode block on the other side of the gate line is electrically connected to the third sub-connection portion through the transfer portion.

[0013] In a possible implementation manner, an orthographic projection pattern of the transition portion on the substrate is the same as an orthographic projection pattern of the connecting line extension portion on the substrate.

[0014] In a possible implementation manner, the array substrate further includes: a first via hole and a second via hole;

[0015] The common electrode block on one side of the gate line is electrically connected to the second sub-connection portion through the connecting line extension portion and the first via hole; the common electrode block on the other side of the gate line is electrically connected to the third sub-connection portion through the transition portion and the second via hole;

[0016] In the area where the same common electrode column is located, centers of all the first via holes and centers of all the second via holes are located on the same straight line.

[0017] In a possible implementation manner, a size of an orthographic projection of the first via hole on the substrate is the same as a size of an orthographic projection of the second via hole on the substrate.

[0018] In a possible implementation, the width of the first sub-connection portion in the first direction is smaller than the width of the second sub-connection portion in the first direction; the width of the first connection portion in the first direction is smaller than the width of the third sub-connection portion in the first direction.

[0019] In a possible implementation manner, a plurality of first connection portions connecting the common electrode blocks in the same common electrode column are located in the same column direction.

[0020] In a possible implementation manner, the array substrate includes: a plurality of first common electrode columns and a plurality of second common electrode columns; two adjacent first common electrode columns are spaced apart from each other by two second common electrode columns;

[0021] In the first common electrode column and the second common electrode column, the first connection portion is only located within the orthographic projection of the first common electrode column on the substrate.

[0022] In a possible implementation, the array substrate further includes: a pixel electrode layer located on a side of the common connection line away from the substrate; the pixel electrode layer includes: a plurality of pixel electrodes distributed in an array;

[0023] The first connecting portion and the pixel electrode are formed in the same layer and made of the same material.

[0024] In a possible implementation, the pixel electrode layer includes: a first pixel electrode column, a second pixel electrode column, and a third pixel electrode column extending along the second direction; the area where the first pixel electrode column is located emits blue light, the area where the second pixel electrode column is located emits red light, and the area where the third pixel electrode column is located emits green light;

[0025] The orthographic projections of the first connecting portions on the substrate are all located within the orthographic projections of the first pixel electrode columns on the substrate.

[0026] In a possible implementation, the first pixel electrode column includes a plurality of first pixel electrodes distributed along the second direction, the second pixel electrode column includes a plurality of second pixel electrodes distributed along the second direction, and the third pixel electrode column includes a plurality of third pixel electrodes distributed along the second direction;

[0027] The first pixel electrode has a recessed portion; a portion of the first connecting portion has an orthographic projection on the substrate that overlaps with an orthographic projection of the recessed portion on the substrate; and a pattern of the second pixel electrode is the same as a pattern of the third pixel electrode.

[0028] In a possible implementation, the array substrate includes a display area and a peripheral area located outside the display area; the plurality of common electrodes are located in the display area;

[0029] The array substrate further comprises: a first connecting wire located in the peripheral area and extending along the second direction and electrically connected to the common connecting wire, and a common wire located in the peripheral area and surrounding the display area and located at a different layer from the first connecting wire; the common connecting wire is electrically connected to the common wire through the first connecting wire;

[0030] The first connecting line is electrically connected to the common line at a first position point; the first position point is located in the center area between the orthographic projections of two adjacent gate lines on the substrate in the orthographic projection of the substrate.

[0031] The embodiment of the utility model further provides a display panel, comprising the array substrate provided in the embodiment of the utility model.

[0032] The embodiment of the present invention further provides a display device, comprising the display panel provided by the embodiment of the present invention.

[0033] The beneficial effects of the embodiments of the utility model are as follows: In the embodiments of the utility model, the common electrode layer includes a plurality of common electrode blocks distributed in an array, the common electrode blocks of the common electrode rows are connected as a whole through a common connecting line, and the common electrode blocks of the common electrode columns are connected as a whole through a first connecting portion, so that the entire common electrode layer can be formed into a mesh structure that is connected in the horizontal and vertical directions, so that the voltage of the common electrode layer can be more evenly distributed in the display area of ​​the entire display panel, thereby improving the screen abnormal display problem caused by uneven distribution of common voltage due to impedance differences at different positions. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of an array substrate provided by an embodiment of the utility model;

[0035] Figure 2 for Figure 1 A local enlarged schematic diagram in FIG.

[0036] Figure 3 for Figure 1 A schematic cross-sectional view at the dotted line e1;

[0037] Figure 4A A schematic diagram of a single film layer of a common electrode layer provided in an embodiment of the utility model;

[0038] Figure 4B A schematic diagram of a single film layer where the gate line is located provided in an embodiment of the utility model;

[0039] Figure 4C A schematic diagram of a single film layer where a data line is provided in an embodiment of the utility model;

[0040] Figure 4DA schematic diagram of a single film layer of a pixel electrode layer provided in an embodiment of the utility model;

[0041] Figure 4E for Figure 4D A local enlarged schematic diagram of the . DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0044] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0045] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0046] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0047] See also Figure 1-Figure 3 , Figure 4A-4E As shown, Figure 2 for Figure 1 A local enlarged schematic diagram of Figure 3 for Figure 1 Schematic diagram of the cross section at the dotted line e1, Figure 4A A schematic diagram of a single film layer of a common electrode layer provided in an embodiment of the utility model, Figure 4B A schematic diagram of a single film layer where the gate line is provided in an embodiment of the utility model, Figure 4C A schematic diagram of a single film layer where the data line is provided in an embodiment of the utility model. Figure 4D A schematic diagram of a single film layer of a pixel electrode layer provided in an embodiment of the utility model, Figure 4E for Figure 4D In the partially enlarged schematic diagram, an embodiment of the utility model provides an array substrate, comprising: a substrate 10, a common electrode layer located on one side of the substrate 10, a plurality of common connection lines 2 extending along a first direction X, and a plurality of first connection portions 3; the common electrode layer comprises: a plurality of common electrode rows 110 extending along the first direction X and arranged along a second direction Y, and a plurality of common electrode columns 120 extending along the second direction Y and arranged along the first direction X; the common electrode row 110 comprises: a plurality of common electrode blocks 1 arranged in sequence along the first direction X; the common electrode column 120 comprises: a plurality of common electrode blocks 1 arranged in sequence along the second direction Y; a plurality of common electrode blocks 1 of the same common electrode row 110 are electrically connected through a common connection line 2; and in at least part of the common electrode columns 120, any two adjacent common electrode blocks 1 are electrically connected through the first connection portion 3.

[0048] In an embodiment of the utility model, the common electrode layer includes a plurality of common electrode blocks 1 distributed in an array, the common electrode blocks of the common electrode row 110 are connected as a whole through a common connecting line 2, and the common electrode blocks 1 of the common electrode column 120 are connected as a whole through a first connecting portion 3, so that the entire common electrode layer can be formed into a mesh structure that is connected in the horizontal and vertical directions, so that the voltage of the common electrode layer can be more evenly distributed in the display area of ​​the entire display panel, thereby improving the screen abnormal display problem caused by uneven distribution of common voltage due to impedance differences at different positions.

[0049] In one possible implementation, combining Figure 1-Figure 3 , Figure 4A-4E As shown, the array substrate further includes: a plurality of gate lines 4 extending along the first direction X; a common connection line 2 and the gate line 4 are made of the same layer and the same material; and a plurality of common electrode blocks 1 are directly in contact and electrically connected with the common connection line 2 in the same common electrode row 110. In the embodiment of the utility model, the common connection line 2 and the gate line 4 are in the same layer, and the common connection line 2 can be formed at the same time as the gate line 4 is formed, so that while realizing the electrical connection of a row of common electrode blocks 1, the manufacturing process of the display panel can also be simplified.

[0050] In a specific implementation, a common electrode layer may be formed first, and then gate lines 4 and common connecting lines 2 on the same layer as gate lines 4 may be formed, wherein there may be no insulating layer between the common electrode layer and the layer where gate lines 4 are located, and there is a gap between the common electrode blocks 1 and the gate lines 4 to achieve mutual insulation between the common electrode blocks 1 and the gate lines 4, and the common connecting lines 2 may be formed above the common electrode rows 110 and directly overlapped with each common electrode block 1 in the common electrode rows 110, so as to electrically connect all common electrode blocks 1 in the common electrode rows 110 as a whole through the common connecting lines 2.

[0051] In one possible implementation, combining Figure 4E As shown, the first connection part 3 includes: a first sub-connection part 31 extending along the second direction Y, a second sub-connection part 32 connected to one end of the first sub-connection part 31, and a third sub-connection part 33 connected to the other end of the first sub-connection part 31; Figure 2 and Figure 4E As shown, the orthographic projection of the first sub-connection portion 31 on the substrate 10 intersects with the orthographic projection of the gate line 4 on the substrate 10;

[0052] See also Figure 4B As shown, the common connection line 2 includes: a connection line main part 21 extending along the first direction X, and a connection line extension part 22 extending from the connection line main part 21 along a side away from the gate line 4; optionally, a part of the gate line connection part 21 and a protrusion connected to the gate line connection part 21 and protruding outwardly toward the side away from the gate line 4 can be used as the connection line extension part 22; combined Figure 2 , Figure 4B and Figure 4E As shown, the positive projection of the second sub-connection portion 32 on the substrate 10 covers the positive projection of the connection line extension portion 22 on the substrate 10, and the common electrode block 1 on one side of the gate line 4 (for example, Figure 2 The common electrode block 1) below the middle gate line 2 is electrically connected to the second sub-connection portion 32 via the connection line extension portion 22 .

[0053] In the embodiment of the utility model, the common connection line 2 includes: a connection line main part 21 and a connection line extension part 22. The common electrode block 1 on one side of the gate line 4 is electrically connected to the second sub-connection part 32 through the connection line extension part 22, which can reduce the resistance when the common electrode block is connected to the second sub-connection part 32. Since a first connection line 6 is arranged at this position (the line width of the first connection line 6 is substantially the same as the line width of the gate line 4, for example, the line width is 8 μm), and the size of the first via K1 is substantially 4.5 μm, due to process precision conditions, it is necessary to ensure that the line width of the first connection line 6 at the position of the first via K1 is sufficient (greater than 5 μm) to avoid the problem of abnormal display caused by a part of the first via K1 being hit on the first connection line 6 and a part being hit on the common electrode block.

[0054] In one possible implementation, combining Figure 2 As shown, the orthographic projection of the second sub-connection portion 32 on the substrate 10 can overlap with the orthographic projection of the connection line extension portion 22 on the substrate 10; in a possible embodiment, the orthographic projection pattern of the second sub-connection portion 32 on the substrate 10 can be the same shape and size as the orthographic projection pattern of the connection line extension portion 22 on the substrate 10, and the two overlap with each other.

[0055] In one possible implementation, see Figure 4B As shown, the array substrate further includes: a transfer portion 23; Figure 2 As shown, the positive projection of the transition portion 23 on the substrate 10 covers the positive projection of the third sub-connection portion 33 on the substrate 10, and the common electrode block 1 on the other side of the gate line 4 (for example, Figure 2 The common electrode block 1) above the middle gate line 2 is electrically connected to the third sub-connection portion 33 through the adapter 23. In the embodiment of the utility model, the array substrate further includes the adapter 23, and the common electrode block on the other side of the gate line 4 is electrically connected to the third sub-connection portion 33 through the adapter 23, which can reduce the resistance when the common electrode block is connected to the third connection portion 33.

[0056] In one possible implementation, see Figure 4B As shown, the transition portion 23 and the gate line 4 are made of the same layer and material, and the transition portion 23 and the connecting line extension portion 22 are respectively located on different sides of the same gate line 4 to electrically connect two common electrode blocks 1 on different sides of the gate line 4 .

[0057] In one possible implementation, see Figure 4B As shown, the orthographic projection pattern of the transition portion 23 on the substrate 10 is the same as the orthographic projection pattern of the connecting line extension portion 22 on the substrate 10. For example, the orthographic projection patterns of both on the substrate 10 are rectangular, for example, both are square.

[0058] In one possible implementation, combining Figure 1-Figure 3 As shown, the array substrate further includes: a first via hole K1, and a second via hole K2; the common electrode block 1 on one side of the gate line 4 is electrically connected to the second sub-connection portion 32 through the first via hole K1 via the connection line extension portion 22; the common electrode block 1 on the other side of the gate line 4 is electrically connected to the third sub-connection portion 33 through the adapter portion 23 via the second via hole K2; in the area where the same common electrode column 120 is located, the centers of all the first via holes K1 and the centers of all the second via holes K2 are located in the same straight line. That is, in the area where the same common electrode column 120 is located, the centers of all the via holes connecting the first connection portion 3 and the common electrode block 1 are located in the same straight line, realizing the mutual electrical connection of the common electrode blocks 1 in one common electrode column.

[0059] In one possible implementation, combining Figure 1-Figure 3 As shown, the size of the orthographic projection of the first via K1 on the substrate 10 is the same as the size of the orthographic projection of the second via K2 on the substrate 10. In one possible embodiment, the shape of the orthographic projection of the first via K1 on the substrate 10 is a rectangle, the shape of the orthographic projection of the second via K2 on the substrate 10 is a rectangle, the length of the rectangular first via K1 in the first direction X is the same as the length of the rectangular second via K2 in the first direction X, and the length of the rectangular first via K1 in the second direction Y is the same as the length of the rectangular second via K2 in the second direction Y. In another possible embodiment, the shape of the orthographic projection of the first via K1 on the substrate 10 is a circle, the shape of the orthographic projection of the second via K2 on the substrate 10 is a circle, and the diameter of the circular first via K1 is the same as the diameter of the circular second via K2.

[0060] In one possible implementation, see Figure 4E As shown, the width d1 of the first sub-connection portion 31 in the first direction X is smaller than the width d2 of the second sub-connection portion 32 in the first direction X; the width d1 of the first connection portion 31 in the first direction X is smaller than the width d3 of the third sub-connection portion 33 in the first direction X. In the embodiment of the utility model, compared with the second sub-connection portion 32 or the third sub-connection portion 33, the width of the first sub-connection portion 31 in the first direction X is smaller, which can reduce the overlapping area of ​​the first connection portion 3 and the gate line 4, thereby reducing the coupling effect between the common voltage signal and the gate line scanning signal, and reducing the adverse effect of the first connection portion 3 on the gate line scanning signal.

[0061] In one possible implementation, combining Figure 4A and Figure 4D As shown, a plurality of first connection portions 3 connecting the common electrode blocks 1 in the same common electrode column 120 are located in the same column direction, that is, the first connection portions 3 in the area where the same common electrode column 120 is located are all located in the same column direction.

[0062] In one possible implementation, combining Figure 4A and Figure 4D As shown, the array substrate includes: a plurality of first common electrode columns 121, and a plurality of second common electrode columns 122; two second common electrode columns 122 are spaced between two adjacent first common electrode columns 121; in the first common electrode columns 121 and the second common electrode columns 122, the orthographic projection of the first connection portion 3 on the substrate 10 is only located within the orthographic projection of the first common electrode column 121 on the substrate 10. That is, every two common electrode columns 120 are spaced apart, the common electrode blocks 1 in one common electrode column 120 are electrically connected together through the first connection portion 3, and the first connection portion is provided between adjacent sub-pixels in the same column.

[0063] In one possible implementation, combining Figure 4D As shown, the array substrate further includes: a pixel electrode layer located on the side of the common connection line 2 away from the substrate 10; the pixel electrode layer includes: a plurality of pixel electrodes 5 distributed in an array; and the first connection portion 3 is made of the same layer and material as the pixel electrode 5. In this way, the first connection portion 3 is formed while the pixel electrode 5 is formed, thereby improving the uneven distribution of the common voltage signal and simplifying the manufacturing process of the display panel.

[0064] In one possible implementation, combining Figure 4DAs shown, the pixel electrode layer includes: a first pixel electrode column 501, a second pixel electrode column 502, and a third pixel electrode column 503 extending along the second direction Y; the area where the first pixel electrode column 501 is located emits blue light, the area where the second pixel electrode column 502 is located emits red light, and the area where the third pixel electrode column 503 is located emits green light; the orthographic projection of the first connecting portion 3 on the substrate 10 is located within the orthographic projection of the first pixel electrode column 501 on the substrate 10. Due to the resistance of the common electrode, the common voltage will drift and cannot be restored in time, causing the red sub-pixel and the blue sub-pixel to be darker. Since the light transmittance brightness of different color resistors is different, and the light transmittance brightness of the red color resistor is the smallest, the sub-pixel placed with the via (the first via K1 and / or the second via K2) will reduce a part of the aperture ratio. If the via is set in the red sub-pixel, the aperture ratio of the red sub-pixel will be reduced, making the brightness of the red sub-pixel even lower. Therefore, placing the via (the first via K1 and / or the second via K2) and the related first connecting portion 3 in the blue sub-pixel can improve the problem of brightness difference of different sub-color pixels caused by common voltage offset, thereby reducing the brightness difference of different color sub-pixels.

[0065] In one possible implementation, combining Figure 4A and Figure 4D As shown, the orthographic projection of the first common electrode column 121 on the substrate 1 overlaps with the orthographic projection of the first pixel electrode column 501 on the substrate 1; the orthographic projection of one second common electrode column 122 on the substrate 1 overlaps with the orthographic projection of the second pixel electrode column 502 on the substrate 1; and the orthographic projection of another second common electrode column 122 on the substrate 1 overlaps with the orthographic projection of the third pixel electrode column 503 on the substrate 1.

[0066] In one possible implementation, combining Figure 4D and Figure 4E As shown, the first pixel electrode column 501 includes a plurality of first pixel electrodes 51 distributed along the second direction Y, the second pixel electrode column 502 includes a plurality of second pixel electrodes 52 distributed along the second direction Y, and the third pixel electrode column 503 includes a plurality of third pixel electrodes 53 distributed along the second direction Y; the first pixel electrode 51 has a recessed portion 50; the orthographic projection of a portion of the first connecting portion 3 on the substrate 10 overlaps with the orthographic projection of the recessed portion 50 on the substrate 10. In the embodiment of the utility model, for the pixel electrode column where the first connecting portion 3 is provided, each first pixel electrode 51 is provided with a recessed portion 50 at a position corresponding to the first connecting portion 3, so that the first connecting portion 3 is provided at this position to realize the electrical connection of adjacent common electrode blocks 1.

[0067] In one possible implementation, combining Figure 4D and Figure 4EAs shown, the pattern of the second pixel electrode 52 and the third pixel electrode 53 may not be provided with the recessed portion 50, and the pattern of the second pixel electrode 52 may be the same as the pattern of the third pixel electrode 53. Due to the provision of the recessed portion 50, the pattern of the first pixel electrode 51 may be different from that of the second pixel electrode 52 and the third pixel electrode 53.

[0068] In a possible implementation, as shown in FIG4E , the pixel electrode 5 includes: a first slit group F1 arranged along the second direction Y, and a second slit group F2; the first slit group F1 includes: a plurality of first slits; the second slit group F2 includes: a plurality of second slits; the extension direction of the first slits is different from the extension direction of the second slits. In a possible implementation, as shown in FIG4E , the slit extension directions at the corresponding positions of two adjacent pixel electrodes 5 in the first direction X are the same, that is, for example, Figure 4E In the embodiment, in two adjacent pixel electrodes 5 in the first direction X, the first slits of the two first slit groups F1 extend in the same direction, and the second slits of the two second slit groups F2 extend in the same direction.

[0069] In one possible implementation, combining Figure 1 As shown, the array substrate includes a display area AA, and a peripheral area BB located outside the display area AA; a plurality of common electrodes 1 are located in the display area AA; the array substrate further includes: a first connection wiring 6 located in the peripheral area BB and extending along the second direction Y and electrically connected to the common connection line 2, and a common wiring 7 located in the peripheral area BB and surrounding the display area AA and located at a different layer from the first connection wiring 6; the first connection wiring 6 can be in the same layer and the same material as the common connection wiring 2, and the common connection wiring 2 is electrically connected to the common wiring 7 through the first connection wiring 6;

[0070] The first connecting wire 6 is electrically connected to the common wire 7 at a first position point O; the orthographic projection of the first position point O on the substrate 10 is located in the central area between the orthographic projections of two adjacent gate lines 4 on the substrate 10. In this way, the connection between the first connecting wire 6 and the common wire 7 can be facilitated to avoid interference with the gate lines 4.

[0071] In one possible implementation, combining Figure 4C As shown, the array substrate further includes a plurality of data lines 8 extending along the second direction Y; the common wiring 7 can be in the same layer and material as the data line 8; in a possible implementation manner, the common wiring 7 can be in the same layer and material as the data line 8; Figure 4C As shown, the common wiring 7 also has a hollow portion 70; Figure 4BAs shown, the array substrate further includes a second connection line 60 electrically connected to the first connection line 6 and extending along the first direction X, and the common connection line 2 is electrically connected to the common line 7 through the second connection line 60; wherein the width of the second connection line 60 in the second direction Y is greater than the width of the first connection line 6 in the first direction X, that is, the line width of the second connection line 60 is greater than the line width of the first connection line 6; specifically, the second connection line 60 can be electrically connected to the common line 7 through the transfer pattern of the common electrode layer, specifically, combined with Figure 1 As shown, the second connecting line 60 can be electrically connected to the transfer pattern of the common electrode layer through the first group of holes Z1, and the common line 7 can be electrically connected to the transfer pattern of the common electrode layer through the second group of holes Z2, so that the electrical connection between the second connecting line 60 and the common line 7 is achieved; wherein, since the second connecting line 60 and the gate line 4 are on the same layer, the common line 7 and the data line 8 are on the same layer, and the data line 8 is located between the layer where the gate line 4 is located and the common electrode layer, therefore, the hollow portion 70 provided in the common line 7 can facilitate the conduction between the second connecting line 60 located at the lower layer and the transfer pattern of the common electrode layer at the top layer.

[0072] In a possible implementation, combining 1, Figure 4A and Figure 4D As shown, the common electrode blocks 1 correspond to the pixel electrodes 5 one by one, and in the area formed by the intersection of the gate lines 4 and the data lines 8, there is a common electrode block 1 and a pixel electrode 5 distributed.

[0073] Based on the same utility model concept, an embodiment of the utility model further provides a display panel, including the array substrate provided by the embodiment of the utility model.

[0074] The display panel provided by the embodiment of the utility model can be a large-size display panel. For a small-size display panel, the common wiring mainly consists of two parts, one is distributed in a circle near the display area AA, and the other is distributed in a circle near the gate drive circuit GOA. Due to the small size of the display panel, the difference between the common signal near the IC end and far away from the IC end is small, which has little effect on the display effect. However, in large-size display products, according to the formula R=ρL / S, where ρ is the resistivity of the material, L is the wire length of the resistor, and S is the wire cross-sectional area of ​​the resistor, the larger L is, the larger R is, that is, the farther away from the IC end, the greater the impedance, and the common wiring resistance causes the common voltage to drift. The common offset cannot be restored in time, which will cause abnormal display. Through the embodiment of the utility model, the adjacent common electrode blocks in the common electrode column are electrically connected through the first connecting part, which reduces the impedance difference caused by the distance, and makes the common voltage distribution more uniform.

[0075] Based on the same utility model concept, the embodiment of the utility model further provides a display device, including the display panel provided by the embodiment of the utility model. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be repeated.

[0076] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0077] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An array substrate, characterized in that: include: A substrate, a common electrode layer located on one side of the substrate, a plurality of common connection lines extending along a first direction, and a plurality of first connection portions; The common electrode layer includes: a plurality of common electrode rows extending along the first direction and arranged along the second direction, and a plurality of common electrode columns extending along the second direction and arranged along the first direction; the common electrode rows include: a plurality of common electrode blocks arranged in sequence along the first direction; the common electrode columns include: a plurality of common electrode blocks arranged in sequence along the second direction; The plurality of common electrode blocks in the same common electrode row are electrically connected via the common connection line; and in at least part of the common electrode columns, any two adjacent common electrode blocks are electrically connected via the first connection portion.

2. The array substrate according to claim 1, characterized in that: The array substrate further comprises: a plurality of gate lines extending along the first direction; the common connection lines are made of the same layer and material as the gate lines; In the same common electrode row, a plurality of common electrode blocks are in direct contact and electrically connected to the common connection line.

3. The array substrate according to claim 2, characterized in that: The first connection portion includes: a first sub-connection portion extending along the second direction, a second sub-connection portion connected to one end of the first sub-connection portion, and a third sub-connection portion connected to the other end of the first sub-connection portion; an orthographic projection of the first sub-connection portion on the substrate intersects with an orthographic projection of the gate line on the substrate; The common connection line comprises: a connection line main portion extending along the first direction, and a connection line extension portion extending from the connection line main portion along a side away from the gate line; The orthographic projection of the second sub-connection portion on the substrate covers the orthographic projection of the connection line extension portion on the substrate, and the common electrode block on one side of the gate line is electrically connected to the second sub-connection portion through the connection line extension portion.

4. The array substrate according to claim 3, characterized in that: The array substrate further includes: a transition portion; the transition portion has an orthographic projection on the substrate covering the orthographic projection of the third sub-connection portion on the substrate, and the common electrode block on the other side of the gate line is electrically connected to the third sub-connection portion through the transition portion.

5. The array substrate according to claim 4, characterized in that: The orthographic projection pattern of the transition portion on the substrate is the same as the orthographic projection pattern of the connecting line extension portion on the substrate.

6. The array substrate according to claim 4, characterized in that: The array substrate further includes: a first via hole and a second via hole; The common electrode block on one side of the gate line is electrically connected to the second sub-connection portion through the connecting line extension portion and the first via hole; the common electrode block on the other side of the gate line is electrically connected to the third sub-connection portion through the transition portion and the second via hole; In the area where the same common electrode column is located, centers of all the first via holes and centers of all the second via holes are located on the same straight line.

7. The array substrate according to claim 6, characterized in that: The size of the first via hole projected on the substrate is the same as the size of the second via hole projected on the substrate.

8. The array substrate according to claim 3, characterized in that: The width of the first sub-connection portion in the first direction is smaller than the width of the second sub-connection portion in the first direction; the width of the first connection portion in the first direction is smaller than the width of the third sub-connection portion in the first direction.

9. The array substrate according to claim 1, wherein: A plurality of first connection portions connecting the common electrode blocks in the same common electrode column are located in the same column direction.

10. The array substrate according to claim 9, characterized in that: The array substrate comprises: a plurality of first common electrode columns and a plurality of second common electrode columns; two adjacent first common electrode columns are spaced apart from each other by two second common electrode columns; In the first common electrode column and the second common electrode column, the first connection portion is only located within the orthographic projection of the first common electrode column on the substrate.

11. The array substrate according to any one of claims 1 to 10, characterized in that: The array substrate further comprises: a pixel electrode layer located on a side of the common connection line away from the substrate; the pixel electrode layer comprises: a plurality of pixel electrodes distributed in an array; The first connecting portion and the pixel electrode are formed in the same layer and made of the same material.

12. The array substrate according to claim 11, characterized in that: The pixel electrode layer comprises: a first pixel electrode column, a second pixel electrode column, and a third pixel electrode column extending along the second direction; the area where the first pixel electrode column is located emits blue light, the area where the second pixel electrode column is located emits red light, and the area where the third pixel electrode column is located emits green light; The orthographic projections of the first connecting portions on the substrate are all located within the orthographic projections of the first pixel electrode columns on the substrate.

13. The array substrate according to claim 12, wherein: The first pixel electrode column includes a plurality of first pixel electrodes distributed along the second direction, the second pixel electrode column includes a plurality of second pixel electrodes distributed along the second direction, and the third pixel electrode column includes a plurality of third pixel electrodes distributed along the second direction; The first pixel electrode has a recessed portion; a portion of the first connecting portion has an orthographic projection on the substrate that overlaps with an orthographic projection of the recessed portion on the substrate; and a pattern of the second pixel electrode is the same as a pattern of the third pixel electrode.

14. The array substrate according to any one of claims 2 to 8, characterized in that: The array substrate comprises a display area and a peripheral area located outside the display area; a plurality of common electrodes are located in the display area; The array substrate further comprises: a first connecting wire located in the peripheral area and extending along the second direction and electrically connected to the common connecting wire, and a common wire located in the peripheral area and surrounding the display area and located at a different layer from the first connecting wire; the common connecting wire is electrically connected to the common wire through the first connecting wire; The first connecting line is electrically connected to the common line at a first position point; the first position point is located in the center area between the orthographic projections of two adjacent gate lines on the substrate in the orthographic projection of the substrate.

15. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 14.

16. A display device, characterized in that: Comprising the display panel as claimed in claim 15.

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