Memory

Abstract

The utility model discloses a memory, and the memory comprises a memory array which comprises a plurality of memory unit pairs arranged in an array, and a plurality of word lines and a plurality of bit lines which are connected with the memory unit pairs; the peripheral circuit is connected with the storage array and generates a bit line adjusting voltage and a bit line operating voltage according to an operation instruction, and the bit line adjusting voltage is smaller than the bit line operating voltage; in the plurality of bit lines, the bit line regulating voltage is applied to an addressing bit line connected with a selected memory cell in the memory cell pair, and the bit line operating voltage is applied to a pairing bit line connected with a non-selected memory cell in the memory cell pair; wherein the bit line adjusting voltage is greater than zero. According to the memory disclosed by the invention, the data in the memory unit can be accurately read, and a multifunctional high-precision read operation function is realized.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a memory. Background Art

[0002] Non-volatile memory devices with a split floating gate structure have occupied an increasingly important position in the memory field with their performance advantages such as low cost, low power consumption, high reliability and fast access speed, and are widely used in the consumer electronics field.

[0003] When applying a corresponding voltage to a selected memory cell of a non-volatile memory to implement a read operation, different bit line voltages need to be applied to the bit line and the paired bit line connected to the selected memory cell in the non-volatile memory. However, due to inaccurate bias voltage, the read value of the memory cell often causes deviation and error. Therefore, how to improve the bit line bias voltage has always been a very important issue that requires continuous research.

[0004] new content

[0005] The present application provides a memory that can improve the problem of reading current accuracy and significantly improve data reading precision.

[0006] The present application provides a memory, the memory comprising:

[0007] A memory array, the memory array comprising a plurality of memory cell pairs arranged in an array, and a plurality of word lines and a plurality of bit lines connecting the memory cell pairs; and

[0008] A peripheral circuit is connected to the memory array and generates a bit line adjustment voltage and a bit line operation voltage according to an operation instruction, wherein the bit line adjustment voltage is less than the bit line operation voltage; and the bit line adjustment voltage is applied to an addressing bit line connected to a selected memory cell in the memory cell pair among the plurality of bit lines, and the bit line operation voltage is applied to a pairing bit line connected to a non-selected memory cell in the memory cell pair; wherein the bit line adjustment voltage is greater than zero.

[0009] In some embodiments, the peripheral circuit includes: a voltage generating module, which is connected to the multiple bit lines and sets the bit line operating voltage according to a selected voltage level corresponding to the operation instruction, and sets the bit line adjustment voltage according to the selected voltage level, and wherein the operation instruction includes one of a read operation, a programming verification operation, and an erase verification operation.

[0010] In some embodiments, the voltage generating module provides multiple voltage levels, and the selected voltage level is selected from one of the multiple voltage levels corresponding to each of the operating instructions, and the voltage difference between the bit line operating voltage and the corresponding bit line adjustment voltage under different selected voltage levels is maintained in a preset window.

[0011] In some embodiments, the voltage generating module comprises:

[0012] A clamping voltage selector, wherein an input end of the clamping voltage selector receives the operation instruction and selects the selected voltage level;

[0013] a first clamping voltage generator connected to the clamping voltage selector and generating a first clamping voltage as the bit line adjustment voltage according to the selected voltage level; and

[0014] The second clamping voltage generator is connected to the clamping voltage selector and generates a second clamping voltage as the bit line operating voltage according to the selected voltage level.

[0015] In some embodiments, the peripheral circuit further includes: an instruction decoder connected to the clamp voltage selector, receiving the operation instruction, and outputting a mode flag to the clamp voltage selector.

[0016] In some embodiments, the voltage generating module further includes: a multiplexer, the multiplexer receiving the first clamping voltage and the second clamping voltage, and selectively outputting one of the first clamping voltage and the second clamping voltage to a bit line clamper.

[0017] In some embodiments, each two adjacent pairs of memory cells in the same row in the memory array share one bit line, and the plurality of bit lines further include a first special bit line located on a side of the addressing bit line away from the pairing bit line, and a second special bit line located on a side of the pairing bit line away from the addressing bit line, wherein the voltage generating module further outputs the first clamping voltage and the second clamping voltage to the at least one first special bit line and the at least one second special bit line, respectively.

[0018] In some embodiments, the plurality of bit lines in the storage array form a bit line group with every m bit lines, where m is a positive integer multiple of 3, and the plurality of bit lines further include a first special bit line located in a target bit line group of the addressing bit line and located on a side of the addressing bit line away from the pairing bit line, or a second special bit line located in the target bit line group and located on a side of the pairing bit line away from the addressing bit line, wherein the voltage generating module further outputs the first clamping voltage and the second clamping voltage to the at least one first special bit line and the at least one second special bit line, respectively.

[0019] In some embodiments, the peripheral circuit further includes:

[0020] a reference current generator, configured to generate a reference current; and

[0021] A sense amplifier is connected to the reference current generator and to one of the paired bit line and the address bit line, and receives and compares the reference current and the read current generated in the paired bit line and the address bit line, thereby outputting a signal representing the storage value of the selected memory cell.

[0022] In some embodiments, the reference current generator outputs a reference current corresponding to the change of the operating instruction according to the change of the operating instruction.

[0023] Through the memory disclosed in the present application, since the current distribution curve of the memory cell can be returned to the predetermined ideal position, the data of the memory cell can be accurately read out by comparing the magnitude relationship between the read current and the reference current by the current comparator. Furthermore, the voltages of the addressing bit lines and the matching bit lines of multiple voltage levels can be designed according to the test results and mode requirements of the memory cell, corresponding to multiple read operation modes, so as to realize a multi-functional high-precision read operation function. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic block diagram of internal functional modules of a memory provided for some embodiments of the present application;

[0026] Figure 2 A partial circuit diagram of a memory array provided for some embodiments of the present application;

[0027] Figure 3An equivalent circuit diagram of a memory cell pair provided for some embodiments of the present application;

[0028] Figure 4 A schematic cross-sectional structure diagram of a storage unit pair provided in some embodiments of the present application;

[0029] Figure 5(a) and 5(b) Another structural schematic diagram and an equivalent circuit diagram of a storage unit pair in a memory provided in some embodiments of the present application are respectively provided;

[0030] Figure 6 A preset read current reference distribution diagram of a memory cell under different background modes provided by some embodiments of the present application;

[0031] Figure 7 A schematic diagram of the coupling effect of a word line on a floating gate in a memory cell provided in some embodiments of the present application;

[0032] Figure 8 A reference distribution diagram of read current of a memory cell provided in some embodiments of the present application in different background modes due to coupling of a word line to a floating gate;

[0033] Fig. 9 A schematic diagram of pressurization of a storage unit for a read operation provided in some embodiments of the present application;

[0034] Fig.10 A read current reference distribution variation diagram of a memory cell provided for some embodiments of the present application;

[0035] Fig.11 A schematic block diagram of internal functional modules of a memory provided for some embodiments of the present application;

[0036] Fig.12 A schematic diagram of the connection relationship between a clamp voltage generator and a bit line clamp provided in some embodiments of the present application;

[0037] FIG. 13( a ) is a schematic diagram of a read operation voltage of a common bit line memory array provided in some embodiments of the present application;

[0038] FIG. 13( b ) is a schematic diagram of read operation voltages of a non-shared bit line memory array provided in some embodiments of the present application; and

[0039] Fig.14 A read operation flow chart is provided for some embodiments of the present application.

[0040] The reference numerals are as follows:

[0041] 100, 200 memory;

[0042] 10 memory array; 101 memory cell pair; 102 memory cell; 103 word line gate; 104 split gate structure;

[0043] 105 floating gate; 106 control gate; 107 semiconductor layer; 1081 first source and drain region; 1082 second source and drain region;

[0044] 109 channel area;

[0045] 20, 30 peripheral circuit;

[0046] 212 word line driver; 211 word line voltage generator; 222 control gate driver; 221 control gate voltage generator; 240 row decoder; Cg0 The first control gate line: Cg1 a second control signal;

[0047] 251 bit line driver; 272 bit line clamp; 271 clamp voltage generator; 250 column decoder;

[0048] 262 sensitive amplifier current comparator; 261 reference current generator; 280 data latch; 290 input / output interface; 271a first clamp voltage generator; 271b second clamp voltage generator; 273 clamp voltage selector; 274 instruction decoder DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of this application.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0053] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", and both include the following combinations of A, B and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0054] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0055] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] As used herein, "about," "substantially," or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0058] Please refer to Figure 1 As shown, Figure 1 A block diagram of a memory provided according to some embodiments of the present application. The memory 100 mainly includes a memory array 10 and a peripheral circuit 20 connected to and controlling the memory array 10 .

[0059] Please refer to Figure 2 As shown, Figure 2 The circuit diagram is an example of a memory array 10 provided as a memory according to some embodiments of the present application. It can be understood that the memory array illustrated here is only an example, and the present application can be applied to memory arrays of various forms. Figure 2 The memory array 10 shown includes a plurality of memory cell pairs 101 arranged in an array, and the plurality of memory cell pairs 101 arranged in an array are arranged in multiple rows and columns, and each row of memory cell pairs 111 includes at least two memory cell pairs 101 arranged along a row direction X, and each column of memory cell pairs 121 includes at least two memory cell pairs 101 arranged along a column direction (i.e., a second direction Y). Figure 2 Only four rows and five columns of memory cell pairs 101 are shown. In fact, the number of rows and columns of memory cell pairs 101 included in the memory depends on its storage capacity. It should be noted that the row direction and column direction can be in any direction. For example, a row or column of memory cell pairs can also be arranged in a diagonal direction. For example, a row of memory cell pairs 111 does not necessarily have to be arranged in a straight line, but can also be arranged in a zigzag pattern alternating up and down. The specific situation of the rows and columns depends on the actual process layout. Please refer to Figure 3 and Figure 4 As shown, Figure 3 A circuit diagram of a memory cell pair 101 provided for some embodiments of the present application, Figure 4 A schematic cross-sectional structure diagram of a storage unit pair 101 provided for some embodiments of the present application.

[0060] like Figure 4 As shown, the memory 100 includes a semiconductor layer 107, and the semiconductor layer 107 can be of a first doping type. Each memory cell pair 101 includes a first source and drain region 1081, a second source and drain region 1082, and a channel region 109 located in the semiconductor layer 107. The channel region 109 is located between the first source and drain region 1081 and the second source and drain region 1082. The first source and drain region 1081 and the second source and drain region 1082 can be of a second doping type, which is different from the first doping type. For example, the first doping type can be a P-type, and the second doping type can be an N-type. It can be understood that the first doping type can be an N-type, and the second doping type can be a P-type.

[0061] like Figure 3 and Figure 4 As shown, each memory cell pair 101 is a split-gate floating-gate device structure. Each memory cell pair 101 includes two memory cells 102 connected in series and a word line gate 103 located between the two memory cells 102. The two memory cells 102 connected in series share one word line gate 103. The word line gate 103 is located on one side of the channel region 109 and an insulating layer (not shown in the figure) is provided between the word line gate 103 and the semiconductor layer 107.

[0062] Each memory cell pair 101 further includes two spaced-apart split gate structures 104 located on one side of the channel region 109. The word line gate 103 is located between the two split gate structures 104. An insulating layer (not shown) is disposed between the word line gate 103 and the split gate structure 104. The orthographic projections of the split gate structure 104 and the word line gate 103 on the semiconductor layer 107 overlap with the orthographic projection of the channel region 109 on the semiconductor layer 107.

[0063] Each split gate structure 104 includes a floating gate 105 and a control gate 106. The control gate 106 is located on a side of the floating gate 105 away from the semiconductor layer 107 along the first direction X. An insulating layer (not shown in the figure) is disposed between the floating gate 105 and the semiconductor layer 107. An insulating layer (not shown in the figure) is also disposed between the control gate 106 and the floating gate 105. Figure 4 As shown, Figure 4 The cross-sectional structure diagram of two spaced-apart split-gate structures 104 is shown. Figure 4 In order to conveniently describe each split-gate structure, the two split-gate structures 104 are collectively labeled, and the individual labels are a first split-gate structure 1041 and a second split-gate structure 1042, and the first split-gate structure 1041 includes a first floating gate 1051 and a first control gate 1061, and the second split-gate structure 1042 includes a second floating gate 1052 and a second control gate 1062. The first floating gate 1051 and the second floating gate 1052 constitute two storage bits, the first storage bit is the first floating gate 1051, and the second storage bit is the second floating gate 1052. It should be noted here that, for the convenience of description, the collective label 104 represents the split-gate structure, and the individual labels 1041 and 1042 also represent the split-gate structure, but the collective label 104 represents that the two structures are both split-gate structures, and the individual labels 1041 and 1042 further represent each split-gate structure. The same arrangement is also applied to reference numerals 105 and 1051 / 1052, and reference numerals 106 and 1061 / 1062. For the convenience of description, the two reference numerals will be used interchangeably.

[0064] The material of the control gate 106 and the word line gate 103 includes metal. The material of the floating gate 105 includes polysilicon. The material of the insulating layer between the word line gate 103 and the semiconductor layer 107, the insulating layer between the control gate 106 and the floating gate 105, the insulating layer between the floating gate 105 and the semiconductor layer 107, and the insulating layer between the word line gate 103 and the split gate structure 104 may include silicon oxide.

[0065] Due to the above structural design of the memory cell pair 101, each memory cell pair 101 can store two bits of data. When the data stored in each memory cell 102 is "0", the floating gate 105 of the memory cell 102 has more electrons, so that the memory cell 102 is in a programmed state. At this time, the memory cell 102 has a first threshold voltage. When the data stored in each memory cell 102 is "1", no electrons are stored in the floating gate 105 of the memory cell 102, so that the memory cell 102 is in an unprogrammed state. At this time, the memory cell 102 has a second threshold voltage. The first threshold voltage is greater than the second threshold voltage. For example, the first threshold voltage may be greater than or equal to 2V and less than or equal to 3V. The second threshold voltage may be less than 0V.

[0066] Back to Figure 2 ,like Figure 2 As shown, the memory 100 further includes a plurality of word lines WL arranged along the column direction (ie, the second direction Y). , i is an integer greater than or equal to 0. For example, a plurality of word lines WL Including word lines WL arranged in sequence <0> , WL <1> , WL <2> and WL <3> .like Figure 2 and Figure 3 As shown, the word line gate 103 of each memory cell pair 101 in each row of memory cell pairs 111 is connected to a word line WL connect.

[0067] like Figure 2 As shown, the memory 100 further includes two control gate lines connected to each row of memory cell pairs 111. The two control gate lines include a first control gate line Cg0 and the second control gate line Cg1 For example, a plurality of first control gate lines Cg0 The first control gate lines Cg0 are arranged in sequence along the column direction (ie, the second direction Y). <0> , the first control gate line Cg0 <1> , the first control gate line Cg0 <2> and the first control gate line Cg0 <3> ; Multiple second control gate lines Cg1 The second control gate lines Cg1 are arranged in sequence along the column direction (ie, the second direction Y). <0> , the second control gate line Cg1 <1> , the second control gate line Cg1 <2> and the second control gate line Cg1 <3> A first control gate line Cg0 and a second control gate line Cg1 Adjacently arranged, and a word line WL Set on a first control gate line Cg0 and a second control gate line Cg1 Between. Figure 2 and Figure 3 As shown, the first control gate line Cg0 and the second control gate line Cg1 are respectively connected to the control gates 106 of the two memory cells 102 of each memory cell pair 101 in each row of memory cell pairs 111. Figure 3 and Figure 4 As shown, the first storage bit (first floating gate 1051) corresponds to the first control gate 1061, and the first control gate 1061 is connected to the first control gate line Cg0. The second storage bit (second floating gate 1052) corresponds to the second control gate 1062, and the second control gate 1062 is connected to the second control gate line Cg1. connect.

[0068] The memory 100 also includes a plurality of bit lines. Figure 4 The first source-drain region 1081 and the second source-drain region 1082 of each memory cell pair 101 shown in the figure can be connected to two adjacent bit lines through bit line contacts (not shown).

[0069] In some embodiments, two adjacent memory cell pairs 101 in a row of memory cell pairs 111 share a bit line. In this way, the number of bit lines can be reduced, and there is more space for arranging memory cell pairs 101, so as to increase the storage capacity of the memory 100. Specifically, Figure 2 and Figure 3 As shown, the plurality of bit lines include a plurality of first bit lines BLDj and a plurality of second bit lines BLUj alternately arranged along a row direction (i.e., a first direction X), where j is a natural number. For example, the plurality of first bit lines BLDj include first bit lines BLD0 to BLU2, and the plurality of second bit lines BLUj include second bit lines BLU0 to BLD1. Two adjacent memory cell pairs 101 of a row of memory cell pairs 111 are located in two adjacent columns. In the adjacent two memory cell pairs 101 of a row of memory cell pairs 111, as shown in FIG. Figure 3 and Figure 4 As shown, the first source-drain region 1081 and the second source-drain region 1082 of one memory cell pair 101 are connected to the first bit line BLDj and the second bit line BLUj respectively through the bit line contacts, and the first source-drain region 1081 and the second source-drain region 1082 of another memory cell pair 101 are connected to the second bit line BLUj and the first bit line BLD(j+1) respectively through the bit line contacts. Figure 3 and Figure 4 As shown, a first source-drain region 1081 of a memory cell pair 101 is connected to a first bit line BLDj, and a second source-drain region 1082 of a memory cell pair 101 is connected to a second bit line BLUj.

[0070] In other embodiments, two adjacent memory cell pairs 101 in a row of memory cell pairs 111 may not share a bit line. For example, in two adjacent memory cell pairs 101 in a row of memory cell pairs 111, any one of the two bit lines connected to one memory cell pair 101 is different from any one of the two bit lines connected to another memory cell pair 101. That is, although not shown in the figure, it can be understood that in this embodiment, two bit lines are set between every two adjacent memory cell pairs, each connected to an adjacent memory cell pair, so that the two bit lines connected to any one memory cell pair are not connected to the adjacent memory cell pairs in the same row. In this way, when any one of the adjacent two memory cell pairs 101 in a row of memory cell pairs 111 is operated through a non-shared bit line, the operation is simpler.

[0071] It should be noted that although the bit line labels are divided into two groups, BLD and BLU, they may not be divided into two groups depending on different operation configurations. For example, in the following description, BL0, BL1, . . . BLn will be directly used for description.

[0072] Back to Figure 1 ,like Figure 1 As shown, the peripheral circuit 20 is connected to the memory array 10, and the peripheral circuit 20 generally includes at least a row decoder 240, a word line voltage generator 211, a word line driver 212, a column decoder 250, a bit line driver 251, a clamp voltage generator 271, a bit line clamp 272, a reference current generator 261, and a sensitive amplifier current comparator 262. Figures 2 to 4 The memory with the memory cell pair 101 in the example also includes a control gate voltage generator 221 and a control gate driver 222. In addition, the peripheral circuit 20 also includes a logic controller (not shown) not shown in the figure, and the logic controller is used to control the actions of the above-mentioned devices according to the operation instructions received by the memory, which is further explained below.

[0073] The row decoder 240 receives a row address signal from a bus (not shown) and decodes the row address signal to select an address word line. and the second control gate line Cg1 The logic controller (not shown) also controls the word line voltage generator 211 to output a word line driving voltage, and controls the gate voltage generator 221 to output a control line driving voltage.

[0074] The word line driver 212 is connected to a plurality of word lines WL , the word line voltage generator 211 and the row decoder 240. The word line driver 212 receives the row address selection signal and the word line driving voltage, and outputs the word line driving voltage to the plurality of word lines WL according to the row address selection signal. , to select at least one word line WL At least one row of memory cell pairs 111 is connected.

[0075] The control gate driver 222 and the plurality of first control gate lines Cg0 and a plurality of second control gate lines Cg1 , the control gate voltage generator 221 and the row decoder 240. The control gate driver 222 receives the row address selection signal and the control line drive voltage, and outputs the control line drive voltage to the selected first control gate line Cg0 according to the row address selection signal. and the selected second control gate line Cg1 , to select at least one first control gate line Cg0 A row of memory cells connected thereto, and / or at least one second control gate line Cg1 A row of connected storage cells.

[0076] The bit line driver 251, the bit line clamp 272, the clamp voltage generator 271 and the column decoder 250 belong to the column driving circuit. The clamp voltage generator 271 and the column decoder 250 are connected to the logic controller.

[0077] The column decoder 250 receives the column address signal and decodes the column address signal to select the addressed bit line. The clamp voltage generator 271 generates the clamp voltage required for each selected bit line. The bit line clamp 272 is connected to the clamp voltage generator 271, receives the clamp voltage and outputs the set clamp voltage to the selected bit line.

[0078] The bit line driver 251 is connected to a plurality of bit lines, the bit line clamp 272, and the column decoder 250. The bit line driver 251 receives a bit line voltage and a column address selection signal, and outputs a set clamped bit line voltage to a selected bit line according to the column address selection signal, so as to operate at least one column of memory cell pairs 121 connected to the selected bit line.

[0079] The peripheral circuit 20 further includes a sensitive amplifier current comparator 262, a reference current generator 261, a data latch (not shown), etc. The sensitive amplifier current comparator 262 is connected to the reference current generator 261 and a plurality of bit lines and is connected to the data latch 223. The sensitive amplifier current comparator 262 is used to compare the read current with the reference current generated by the reference current generator 261 after receiving the read current, determine the data stored in the selected storage unit, and then store the data in the data latch, and output it to the data line together with the data read from other bit lines for output.

[0080] Based on the structural design of the peripheral circuit 20 of the above memory, the operation on the memory may include an erase operation, a read operation and a program operation. The following further illustrates the data read operation.

[0081] like Figure 3 and Figure 4 As shown, this memory with a memory cell pair is a non-volatile flash memory device that uses a split gate structure and a polysilicon floating gate layer as a memory cell. It has an increasingly important position in the memory field due to its low cost, low power consumption, high reliability, and fast access speed, and is widely used in the consumer electronics field. This structure will be used as an example for explanation below, but it should be understood that it is not limited to this structure.

[0082] The structural diagram and equivalent circuit diagram of the memory cell pair in the memory disclosed in some embodiments of the present application can also be shown in Figure 5 (a) and Figure 5 (b). A memory cell pair has two control gates (Control Gate) CG0 and CG1, and uses a polysilicon floating gate (FG: Floating Gate) as a memory cell, which can store two bits of data; there is a word line (word line) WL responsible for selecting the cell. The two ends of the memory cell pair are connected to two bit lines (Bit Line) BL0 and BL1. It can be understood that here the memory unit formed by the two split gate structures is called a memory cell pair, but in some places, there are also cases where the memory unit containing two split gate structures is simply called a memory cell.

[0083] The memory cell reads data through a current comparator. When reading data, a read voltage Vcgrv is applied to the control gate CG0 (Control Gate) to be read, a high voltage Vpass is applied to the other control gate CG1, a gate voltage Vwl is applied to WL, a Vbl voltage is applied to BL0, and BL1 is connected to VSS, generating a read current of the memory cell between the two BLs. Depending on the different background data (Background Pattern) stored in the two control gates CG0 and CG1 of the memory cell pair, the impedance of the memory cell in the bit line BL path will be different, so that the final read current passing through the bit line BL is different. By comparing the read current with the read reference current, the data stored in the read control gate CG0 can be read.

[0084] The read operation includes data reading (Read), erase verification (Erase Verify, EV), program verification (Program Verify, PV) and other modes, and each mode corresponds to a different reference current. Figure 6 The reading current distribution and reference current under different background data and different modes of the memory cell (or memory cell pair) are displayed. The so-called reading reference current here can be one of the reading operation reference current Rd Iref, the programming verification operation reference current PV Iref, and the erasing verification operation reference current EV Iref. Figure 6 As shown, the two numbers in each normal distribution curve representing the stored value are the data stored in the storage cells connected to the control gates CG1 and CG0 in a storage cell pair. When the background data is 00 or 10, the read current normal distribution curve is on the left side of the read reference current, and the data read out of CG0 is 0; when the background data is 01 or 11, the read current normal distribution curve is on the right side of the read reference current (Rd Iref, PV Iref, EV Iref), and the data read out of CG0 is 1.

[0085] In the aforementioned embodiment, unlike the traditional floating gate FLASH (flash memory), the memory cell pair disclosed in the embodiment of the present application uses a split gate structure, and its word line WL is located between the two control gates CG1 and CG0. According to further research of the present application, Figure 7 As shown, due to the split gate structure, there are capacitors Cwl, Ccg, and Cox between the word line WL end and the floating gates on the left and right sides, so that the floating gate voltage Vfg of a storage cell is no longer only composed of the control gate voltage Vcg, the substrate voltage Vsub and the charge in the floating gate, but also includes the contribution of the coupling effect of the word line voltage Vwl on the floating gate FG.

[0086] Assume that the current charge stored in the floating gate is Q, apply Vcg0 voltage to the control gate CG0, apply Vwl voltage to the word line WL end, the substrate voltage is Vsub, Ccg is the equivalent capacitance value between the control gate and the floating gate FG, Cox is the equivalent capacitance value between the control gate and the substrate end, and Cwl is the equivalent capacitance value between the word line WL port and the floating gate FG. Assume that a read operation is performed on CG0. At this time, Vcg0 = Vcgrv = 0V. Since Vbl0 = 0V on the CG0 side, Vsub on the CG0 side can be approximately 0V. At this time, the floating gate voltage Vfg is mainly composed of the word line WL voltage and the charge in the floating gate, specifically:

[0087] Vfg=Vwl*Cr+Q / Ctotal;

[0088] Wherein, Ctotal is the total capacitance value, Ctotal=Ccg+Cox+Cwl;

[0089] Cr is the coupling ratio, Cr = Cwl / Ctotal;

[0090] In addition, according to further research of the present application, the coupling ratio of the word line WL to the floating gate FG is about 15% or more. The Vwl voltage on the word line WL is about 3-4V, and the coupling voltage Vcouple of Vwl to CG0 is about 0.4-0.6V.

[0091] When performing a read operation, for the memory cell where CG0 is located, the coupling voltage on its floating gate FG further increases the conductive channel at its substrate, making it easier for electrons to flow through the substrate, which is equivalent to reducing the resistance between the bit line BL1 and the bit line BL0, and increasing the current (Icell) between the bit line BL1 and the bit line BL0 under the same background data (Background Pattern), that is, the read current. From the current distribution curve of the memory cell, due to the coupling effect of the word line WL on the floating gate FG, the overall current distribution curve moves rightward from the ideal black curve to the actual gray curve, as shown in Figure 1. Figure 8 shown.

[0092] Due to the deviation of the overall read current curve, the read current distribution no longer corresponds to the reference current (Rd Iref, PV Iref, EV Iref), and using the original reference current benchmark to determine the data stored in the memory cell may no longer be reliable.

[0093] Therefore, the present application further proposes a read operation scheme suitable for a storage unit according to some embodiments of the present application, which can improve the problem of increased read current caused by the coupling effect of the word line WL on the floating gate FG in the aforementioned embodiments, and further significantly improve data reading accuracy.

[0094] Specifically, Fig. 9 As shown, in this embodiment, the effect of the word line WL on the floating gate FG can be offset, and the reading accuracy is improved. Corresponding to a specific memory cell, when reading data, a read voltage Vcgrv is applied to the control gate CG0 (Control Gate) to be read, a high voltage Vpass is applied to the other control gate CG1, and a gate voltage Vwl is applied to the word line WL. In the direction of the bit line BL, a Vbl0 voltage greater than 0 is applied to the addressing bit line BL0, and a larger Vbl1 voltage is applied to the matching bit line BL1, and Vbl1 is greater than Vbl0, so that a read current of the memory cell is generated between the two bit lines BL. According to the different background patterns of the memory cells corresponding to the two control gates CG0 and CG1 of the memory cell pair, the impedance of the memory cell in the path between the two bit lines BL0-BL1 will be different, so that the final read current passing through the bit line BL is different. By comparing the magnitude of the read current with the read reference current, the data stored in CG0 is obtained.

[0095] Through such a configuration, the voltage at the addressing bit line BL0 is increased from 0 to Vbl0, and the voltage V0 at the CG0 substrate is raised, that is, the bit line adjustment voltage Vbl0 of the addressing bit line BL0 is made greater than zero. Although the coupling effect of the word line WL on the floating gate FG on the CG0 side still exists, the voltage difference between the substrate and the floating gate FG is significantly reduced. Reasonable adjustment of the Vbl0 voltage (bit line adjustment voltage Vbl0) can make the voltage difference between the substrate and the floating gate FG close to 0, offsetting the effect of the coupling effect of the word line WL on the floating gate FG on the CG0 side. Further, the voltage of the paired word line Vbl1 is also increased, so that the voltage difference between the paired bit line Vbl1 and the addressing bit line Vbl0 remains unchanged, or is maintained within a preset window, and the current of the conductive channel will be able to return to a normal level. Therefore, here, making the bit line adjustment voltage Vbl0 of the addressing bit line greater than zero means providing a bit line adjustment voltage with a voltage that can offset the effect of the coupling effect of the word line WL on the floating gate FG on the CG0 side.

[0096] Table 1 shows an example of bias voltages for each port. It should be understood that these data are at least for illustration only and do not represent limitations on the technology presented in this application.

[0097] Port Name Pressurization range Word Line WL Vwl=3-4V Control gate CG0 Vcgrv=0V Control gate CG1 Vpass=5-6V Address bit line BL0 Vbl0=0-0.6V Pairing bit line BL1 Vbl1=0.6-1.2V

[0098] Table 1

[0099] like Fig.10 As shown, from the current distribution curve of the memory cell, the read operation scheme in this embodiment is equivalent to moving the overall current distribution curve from the black dotted line to the left to the gray dotted line to the ideal distribution position. In this way, the data of the memory cell can be accurately read out after comparing the magnitude relationship between the read current and the reference current (Rd Iref, PVIref, EV Iref) through the current comparator.

[0100] In some embodiments, the step of generating a bit line adjustment voltage and a bit line operation voltage according to an operation instruction includes: setting the bit line operation voltage according to a selected voltage level corresponding to the operation instruction, and setting the bit line adjustment voltage according to the selected voltage level, and wherein the operation instruction includes one of a read operation, a program verification operation, and an erase verification operation.

[0101] Specifically, taking the reading of 1 bit of data as an example, the voltage ranges on the word line WL, the bit line BL and the control gate CG are shown in Table 1. Among them, Vbl0 and Vbl1 can be designed with multiple voltage levels according to the test results and mode requirements of the storage unit, corresponding to multiple read operation modes, so as to achieve multi-functional high-precision read operation functions. For example, Vbl0 and Vbl1 can be different levels such as 0.2V and 0.8V, or 0.3V and 0.9V, but the voltage difference between the two voltages remains in the same relative relationship.

[0102] In order to achieve the above operations, Fig.11 As shown, Fig.11 A specific chip module block diagram of a memory according to some embodiments of the present application is disclosed. Fig.11 As shown in FIG. 1 , the memory 20 mainly includes a memory array 10 and a peripheral circuit 30. The memory array 10 and the peripheral circuit 30 are Figure 1 The memory array 10 shown is the same, and the memory array includes a plurality of memory cell pairs arranged in an array, and a plurality of word lines and a plurality of bit lines connecting the memory cell pairs, and the description thereof will not be repeated.

[0103] The peripheral circuit 30 is generally similar to Figure 1 The peripheral circuit 20 shown is similar, and also includes a row decoder 240, a word line voltage generator 211, a word line driver 212, a column decoder 250, a bit line driver 251, a clamp voltage generator 271, a bit line clamp 272, a reference current generator 261, a sensitive amplifier current comparator 262, a data latch 280, and an input / output interface (I / O) 290. However, the peripheral circuit 20 shown in FIG. 1 is similar to the peripheral circuit 20 shown in FIG. 1 and is similar to the peripheral circuit 20 shown in FIG. Figure 1 The peripheral circuit 20 in the illustrated embodiment differs in that Figure 1 The clamping voltage generator 271 in the illustrated embodiment is replaced by a first clamping voltage generator 271a and a second clamping voltage generator 271b, and further includes a clamping voltage selector 273 and a command decoder 274. Herein, the first clamping voltage generator 271a, the second clamping voltage generator 271b, the clamping voltage selector 273, and the command decoder 274 are collectively referred to as a voltage generating module 270.

[0104] pass Fig.11 The peripheral circuit 30 shown is connected to the memory array 10, and will generate a bit line adjustment voltage Vbl0 and a bit line operation voltage Vbl1 respectively through the first clamping voltage generator 271a and the second clamping voltage generator 271b according to the operation instruction, and the bit line adjustment voltage Vbl0 is less than the bit line operation voltage Vbl1; then, through the bit line clamp 272, the bit line adjustment voltage Vbl0 is applied to the addressing bit line BL0 connected to the selected memory cell in the memory cell pair among the multiple bit lines, and the bit line operation voltage Vbl1 is applied to the matching bit line BL1 connected to the non-selected memory cell in the memory cell pair; wherein, the bit line adjustment voltage Vbl0 is greater than zero.

[0105] In some embodiments, Fig.11 As shown, the voltage generating module 270 is connected to the plurality of bit lines BL0-BLn, and sets the bit line operating voltage Vbl1 according to a selected voltage level corresponding to the operation instruction, and sets the bit line regulating voltage Vbl0 according to the selected voltage level, wherein the operation instruction includes one of a read operation, a program verification operation, and an erase verification operation.

[0106] In some embodiments, the voltage generating module provides multiple voltage levels, and the selected voltage level is selected from one of the multiple voltage levels corresponding to the operation instruction, and the voltage difference between the bit line operation voltage Vbl1 and the corresponding bit line adjustment voltage Vbl0 under different selected voltage levels is maintained within a window.

[0107] Specifically, the voltage level can be, for example, Vbl0=0.1V, Vbl1=0.7V; Vbl0=0.2V, Vbl1=0.8V; Vbl0=0.3V, Vbl1=0.9V... etc., and the voltage difference between the two voltages is kept fixed. It is also possible to set Vbl0 and Vbl1 to 0.2V and 0.75V, or 0.2V and 0.85V, and keep the voltage difference between the two voltages within a preset window, that is, a window of <0.55V, 0.65V>. That is, no matter how the bit line operation voltage Vbl1 and the corresponding bit line adjustment voltage Vbl0 are adjusted, the voltage difference between the two at any voltage level is maintained within a certain range, and this certain range can be a fixed difference or within a preset window. It can be understood that the preset window means that the voltage difference value can have a certain fluctuation, but the read / program verification / erase verification operation of the corresponding storage unit can be correctly completed. When the voltage difference is within the preset window, the reading accuracy is high. If it is less than the minimum value of the preset window, it may cause the corresponding storage unit to fail to read or read errors. Although 0.6V is used as an example in this solution, in actual situations, it can be adjusted according to the state of the storage unit, for example, the voltage difference is within the window of <0.5V, 0.7V>.

[0108] The aforementioned setting of the bit line operating voltage according to a selected voltage level corresponding to the operating instruction may mean that the selected voltage level is a different voltage level under different operating instructions, for example, different voltage levels are given in response to a read operation instruction, a program verification operation instruction, and an erase verification operation instruction, and then different bit line operating voltages Vbl1 and the bit line adjustment voltage Vbl0 are given, and these instructions all belong to a read action.

[0109] The aforementioned selected voltage level is selected from one of the multiple voltage levels corresponding to the operation instruction, and may refer to multiple voltage levels under the same operation instruction. For example, the same read operation instruction is used, but different read voltages are given. Specifically, in the case of multi-level storage of a bit, different bit line read voltage combinations including word line voltages may be given according to different levels of reading, and the bit line operation voltage Vbl1 may be a variation of 0.6V, 0.9V, and 1.2V. Alternatively, even in single-level storage, if a bit is to be read in multiple ways for accurate reading, different voltage levels may be selected one by one for reading, for example, the bit line operation voltage Vbl1 may be a variation of 0.6V, 0.9V, 0.7V, and 0.8V, and so on.

[0110] In some embodiments, the item set according to a selected voltage level corresponding to the operation instruction may also be the reference current.

[0111] Specifically, Fig.11 As shown, the reference current generator 261 receives a signal from the instruction decoder 274 (described later) and changes the reference current to be provided to the sensitive amplifier current comparator 262. For example, according to the read operation instruction, the program verification operation instruction, and the erase verification operation instruction, the read operation reference current Rd Iref, the program verification operation reference current PV Iref, and the erase verification operation reference current EV Iref are respectively provided. It can be understood that this reference current can also correspond to different current levels under the same instruction. That is, the same program verification instruction is provided, but different reference currents are provided.

[0112] In order to achieve some of the functions described above, in some embodiments, Fig.11 As shown, the voltage generating module also includes:

[0113] A clamp voltage selector 273, wherein an input end of the clamp voltage selector 273 receives the operation instruction and selects the selected voltage level;

[0114] The first clamping voltage generator 271a is connected to the clamping voltage selector 273, and generates a first clamping voltage Vbl0 as the bit line adjustment voltage according to the selected voltage level.

[0115] The second clamping voltage generator 271b is connected to the clamping voltage selector 273, and generates a second clamping voltage serving as the bit line operating voltage Vbl1 according to the selected voltage level.

[0116] Specifically, Fig.11 As shown, the voltage generating module 270 is designed with a clamping voltage selector 273 and two bit line clamping voltage generators 271a / 271b in the direction of the bit line BL. The clamping voltage selector 273 controls the two clamping voltage generators 271a / 271b to generate the read voltage of the corresponding mode according to different read operation modes (data read (Read), erase verification (Erase Verify, EV), program verification (Program Verify, PV)), etc.

[0117] Through the two clamping voltage generators 271a / 271b, a bit line adjustment voltage Vbl0 greater than zero can be generated for application to the addressing bit line BL0 of the selected memory cell, and a bit line operation voltage Vbl1 can be generated for application to the paired bit line BL1 of the selected memory cell, that is, the bit line BL1 connected to the non-selected memory cell in the memory cell pair.

[0118] In some embodiments, the voltage generating module 270 further includes an instruction decoder 274 connected to the clamping voltage selector 273, receiving the operation instruction, and outputting a mode flag M to the clamping voltage selector 273. The mode flag M may also be sent to the reference current generator 261.

[0119] Specifically, in the direction of the bit line BL, the clamp voltage selector 273 reads the read operation mode flag M and controls the first clamp voltage generator 271a and the second clamp voltage generator 271b to generate clamp voltages Vbl0 and Vbl1 of the corresponding mode gear. After the column decoder 250 decodes the address information, Vbl0 and Vbl1 are applied to the two bit lines BL0 and BL1 of the selected cell.

[0120] In addition, in the direction of the word line WL, the word line voltage generator 211 generates a word line voltage Vwl, and the control gate voltage generator 221 generates a conduction voltage Vpass and a read voltage Vcg of the two control gates CG1 and CG0, and the Vwl, Vpass and Vcg are applied to the selected memory cell through decoding control by the row decoder 240. The read current flows from the matching bit line BL1 to the address bit line BL0, and is compared with the reference current by the sensitive amplifier current comparator 262 to obtain the value stored in the selected memory cell, and is temporarily stored by the data latch 280, and then sent out through the input / output interface (I / O) port 290.

[0121] That is, according to some embodiments of the present application, the peripheral circuit 30 also includes: a reference current generator 261 for generating a reference current; and a sensitive amplifier current comparator 262, wherein the sensitive amplifier current comparator 262 is connected to the reference current generator 261 and to one of the pairing bit line BL1 and the addressing bit line BL0, and receives and compares the reference current Iref and the read current Ird generated in the pairing bit line BL1 and the addressing bit line BL0, and outputs a signal representing the storage value of the selected storage unit; and wherein the reference current generator 261 outputs a reference current corresponding to the change of the operation instruction according to the change of the operation instruction.

[0122] Through the above configuration, using a clamp voltage selector 273 to control two bit line clamp voltage generators 271a / 271b can be applied to various situations to realize the operation described in this application. In addition, the read mode flag M can select the number of bits according to the design mode requirements, such as one bit or two bits. In addition, various parameters can also be designed to refine the Vbl1 and Vbl0 gear selection for the necessary read operation instructions READ, program verification operation instructions PV, and erase verification operation instructions EV, and then the subsequent parameters are confirmed according to the chip requirements and storage unit characteristics.

[0123] Further Fig.12 As shown, in some embodiments, the voltage generating module 270 further includes:

[0124] The multiplexer 275 receives the first clamping voltage and the second clamping voltage from the first clamping voltage generator 271 a and the second clamping voltage generator 271 b respectively, and selectively outputs one of the first clamping voltage and the second clamping voltage.

[0125] Through the configuration of the multiplexer 275, one of the first clamping voltage and the second clamping voltage, which respectively represent the bit line adjustment voltage Vbl0 and the bit line operation voltage Vbl1, can be selectively applied to the selected bit line.

[0126] The above has described the peripheral circuit structure and operation scheme of the memory according to some embodiments of the present application. The following will further describe the application of the aforementioned structure and operation scheme to different memory arrays.

[0127] As shown in Figure 13(a), according to some embodiments of the present application, each two adjacent memory cell pairs located in the same row WL(0:3) in the memory array 10 share a bit line BLn / BLn-1 / BLn-2 / BL8 / BL7 / BL6 / BL5 / BL4 / BL3 / BL2 / BL1 / BL0, and the multiple bit lines also include a first special bit line BL3 / BL2 / BL1 / BL0 located on a side of the addressing bit line BL4 away from the pairing bit line BL5, and a second special bit line BL6 / BL7 / BL8 / BLn-2 / BLn-1 / BLn located on a side of the pairing bit line BL5 away from the addressing bit line BL4, and the voltage generating module 270 further outputs the first clamping voltage 0.2V and the second clamping voltage 0.8V to the at least one first special bit line BL3 / BL2 / BL1 / BL0 and the at least one second special bit line BL6 / BL7 / BL8 / BLn-2 / BLn-1 / BLn, respectively.

[0128] As shown in FIG. 13( b ), according to some embodiments of the present application, the plurality of bit lines BL0, BL1, BL2, BL3, BL4, and BL5 in the memory array 10 are each m bit lines as a bit line group, where m is a positive multiple of 3, and the plurality of bit lines will also include a first special bit line located in a target bit line group (e.g., BL0-BL2) of the addressing bit line and located on a side of the addressing bit line away from the pairing bit line, or a second special bit line located in the target bit line group (BL0-BL2) and located on a side of the pairing bit line away from the addressing bit line. For example, when the selected memory cell CG1 is to be addressed, <1> When reading / BL2, the plurality of bit lines will further include a first special bit line located in a target bit line group (BL0-BL2) of the address bit line BL2 and located on a side of the address bit line BL2 away from the matching bit line BL1, or a second special bit line BL0 located in the target bit line group (BL0-BL2) and located on a side of the matching bit line BL1 away from the address bit line BL2. In this embodiment, only the second special bit line BL0 exists, and the first special bit line does not exist, so the voltage generating module 270 will also output the second clamping voltage 0.8V to the at least one second special bit line BL0.

[0129] It can be understood that in the memory array example of FIG. 13( b ), when the selected memory cell CG0 is to be <1> When / BL1 is read, the plurality of bit lines will also include a first special bit line BL2 located in a target bit line group (BL0-BL2) of the address bit line BL1 and located on a side of the address bit line BL1 away from the matching bit line BL0. In this embodiment, only the first special bit line BL2 exists, and the second special bit line does not exist. Therefore, the voltage generating module 270 will also output the first clamping voltage 0.2V to the at least one first special bit line BL2.

[0130] Fig.13a 13b are only some example memory arrays with shared bit lines; it is understood that, except Fig.13a and Fig.13b In addition to the memory array shown, the memory array may also be, as described above, two bit lines are set between every two adjacent memory cell pairs, each connected to the adjacent memory cell pairs, so that the two bit lines connected to any memory cell pair are not connected to the memory cell pairs adjacent to the same row. Since the connection structure of this memory array is easy to understand, no additional diagram is provided, and only the text is described as above. In this example where two bit lines are set between every two adjacent memory cell pairs and each connected to the adjacent memory cell pairs, the operation method is to provide the first clamping voltage and the second clamping voltage generated by two clamping voltage generators for the two bit lines on the left and right sides of the memory cell to be read.

[0131] To further explain, the first special bit line and the second special bit line shown here are used to suppress interference, and thus apply the same voltage as the adjacent address bit line or matching bit line to avoid interference between the bit lines due to the voltage difference between the bit lines.

[0132] In brief, FIG. 13(a) and FIG. 13(b) above illustrate two read operation voltage setting schemes for two common memory arrays. For the memory array, we only read the value of one cell at a time. For the memory array sharing the bit line BL, the memory cell to be read is used as the dividing line, and the left and right side bit lines respectively take the first clamping voltage and the second clamping voltage generated by the two clamping voltage generators.

[0133] For a storage array without a shared BL, a scheme in which three bit lines BL form a group is given as an example. For the bit line group where the storage cell to be read is located, the same voltage is applied to two adjacent bit lines as needed, and a clamping voltage generated by another bit line clamper is applied to the other bit line.

[0134] As for a memory array in which two bit lines are provided between two adjacent memory cell pairs not shown and each is connected to the adjacent memory cell pairs, the first clamping voltage and the second clamping voltage generated by two clamping voltage generators are respectively provided to the left and right two bit lines of the memory cell to be read.

[0135] Through the aforementioned memory, since the current distribution curve of the memory cell can be returned to the predetermined ideal position, the data of the memory cell can be accurately read out by comparing the magnitude relationship between the read current and the reference current by the current comparator. Furthermore, the voltages of the addressing bit lines and the matching bit lines of multiple voltage levels can be designed according to the test results and mode requirements of the memory cell, corresponding to multiple read operation modes, so as to realize a multifunctional high-precision read operation function.

[0136] In view of the aforementioned operation scheme and memory structure, the following takes the reading application as an example to further illustrate an operation flow example of implementing some embodiments of the present application based on the technical main axis of the present application. Fig.14 As shown, the reading process includes the following steps S1 to S6:

[0137] Step S1: When entering a read operation (e.g., a read instruction is sent) or entering a verification operation, a relative read mode flag (READ / EV / PV) is generated, and the row / column address source code is sent to the row / column address decoder for decoding; the read mode flag is sent to the clamp voltage selector, and the read mode flag or the reference voltage flag is sent to the reference current generator and other voltage generators, so that the reference current generator and other voltage generators can generate reference currents Iref, Vwl, Vread, Vpass, etc.;

[0138] Step S2: the clamp voltage selector determines the read operation mode according to the read mode flag bit (READ / EV / PV);

[0139] Step S3: generating a first clamping voltage Vbl0 and a second clamping voltage Vbl1;

[0140] Step S4: performing current comparison, that is, comparing the read current in the selected bit line with the reference current sent by the reference current generator under decoding by the row and column decoders;

[0141] Step S5: Send the read data to the data latch (DAT_latch);

[0142] Step S6: Output data from the input / output interface (I / O).

[0143] In the process of the steps S1 to S4, various operation details and structural details described above may be included. Specifically, in combination with various operation details and structural details described above, the memory corresponding to the aforementioned memory structure and function may be summarized as follows.

[0144] That is, in some embodiments, the memory includes:

[0145] A memory array, the memory array comprising a plurality of memory cell pairs arranged in an array, and a plurality of word lines and a plurality of bit lines connecting the memory cell pairs; and

[0146] A peripheral circuit is connected to the memory array and generates a bit line adjustment voltage and a bit line operation voltage according to an operation instruction, wherein the bit line adjustment voltage is less than the bit line operation voltage; and the bit line adjustment voltage is applied to an addressing bit line connected to a selected memory cell in the memory cell pair among the plurality of bit lines, and the bit line operation voltage is applied to a pairing bit line connected to a non-selected memory cell in the memory cell pair; wherein the bit line adjustment voltage is greater than zero.

[0147] As mentioned above, making the bit line adjustment voltage Vbl0 of the addressing bit line greater than zero here means providing a bit line adjustment voltage whose voltage can offset the effect of the coupling effect of the word line WL on the floating gate FG on the CG0 side. By such a setting, the coupling effect can be offset, leading to an improvement in the accuracy of numerical reading.

[0148] In some embodiments, applied in steps S2 to S3, the voltage generating module sets the bit line operating voltage according to a selected voltage level corresponding to the operating instruction, and sets the bit line adjustment voltage according to the selected voltage level, and wherein the operating instruction includes one of a read operation, a program verification operation, and an erase verification operation.

[0149] In some embodiments, in step S3, the selected voltage level is selected from one of a plurality of voltage levels corresponding to each of the operation instructions, and the voltage difference between the bit line operation voltage and the corresponding bit line adjustment voltage under different selected voltage levels is maintained in a preset window.

[0150] Specifically, as mentioned above, the voltage difference between Vbl0 and Vbl1 is maintained constant or within a window range. These can be understood by referring to the above description, so they will not be repeated here.

[0151] In some embodiments, in step S2, the instruction decoder 274 receives the operation instruction and outputs a mode flag M according to the operation instruction to specify the selected voltage level.

[0152] In some embodiments, in step S3, the clamp voltage selector 273 specifies the selected voltage level according to the operation instruction; and according to the voltage level, two clamp voltages are generated as the bit line adjustment voltage and the bit line operation voltage respectively through the first clamp voltage generator 271a and the second clamp voltage generator 271b.

[0153] In some embodiments, in step S3 , the multiplexer 275 selectively applies the two clamping voltages to the corresponding bit lines.

[0154] In some embodiments, in step S3, the voltage generating module applies the bit line regulating voltage to at least one first special bit line; and applies the bit line operating voltage to at least one second special bit line;

[0155] Wherein, each two adjacent pairs of storage cells in the same row share a bit line, the first special bit line is located on a side of the addressing bit line away from the pairing bit line, and the second special bit line is located on a side of the pairing bit line away from the addressing bit line.

[0156] In some embodiments, in step S3, the voltage generating module applies the bit line regulating voltage to at least one first special bit line; or applies the bit line operating voltage to at least one second special bit line;

[0157] Among them, the multiple bit lines are composed of m bit lines each as a bit line group, m is a positive integer multiple of 3, the first special bit line is located in a target bit line group including the addressing bit line and is located on a side of the addressing bit line away from the pairing bit line, and the second special bit line is located in the target bit line group and is located on a side of the pairing bit line away from the addressing bit line.

[0158] Specifically, these technical details are as described above corresponding to FIG. 13( a ) and FIG. 13( b ), and thus will not be repeated here. You can understand them by referring to the above description.

[0159] In some embodiments, in step S4, the memory generates a read current between the pairing bit line and the addressing bit line, compares it with a reference current, and outputs a signal representing the storage value of the selected memory cell; and wherein, for different operation instructions, the reference current varies according to the differences of each operation instruction, and the bit line operation voltage and the bit line adjustment voltage are set according to the same selected voltage level.

[0160] Specifically, as mentioned above, the reference current is changed according to whether the operation instruction is a read operation instruction READ, a program verification operation instruction PV, or an erase verification operation instruction EV, and the voltage levels of Vbl1 and Vbl0 can be the same or change accordingly. This can be set through the flag bit, which has been specifically described above and will not be repeated here.

[0161] Through the memory described above, since the current distribution curve of the memory cell can be returned to the predetermined ideal position, the data of the memory cell can be accurately read out by comparing the magnitude relationship between the read current and the reference current by the current comparator. Furthermore, the voltages of the addressing bit lines and the matching bit lines of multiple voltage levels can be designed according to the test results and mode requirements of the memory cell, corresponding to multiple read operation modes, so as to realize a multifunctional high-precision read operation function.

[0162] The embodiments of the present application may also be applied to a storage system, which may include one or more memories described in the above embodiments, and a memory controller for controlling the memory, wherein the memory controller is coupled to the memory and configured to control the memory.

[0163] It should be noted that the storage system here includes the aforementioned memory controller and the aforementioned memory, and the storage system can be integrated into various types of storage devices, for example, included in the same package (for example, Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is to say, the storage system can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0164] The above is a detailed introduction to a memory provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A memory, characterized in that: The memory comprises: A memory array, the memory array comprising a plurality of memory cell pairs arranged in an array, and a plurality of word lines and a plurality of bit lines connecting the memory cell pairs; and A peripheral circuit is connected to the memory array and generates a bit line adjustment voltage and a bit line operation voltage according to an operation instruction, wherein the bit line adjustment voltage is less than the bit line operation voltage; and the bit line adjustment voltage is applied to an addressing bit line connected to a selected memory cell in the memory cell pair among the plurality of bit lines, and the bit line operation voltage is applied to a pairing bit line connected to a non-selected memory cell in the memory cell pair; wherein the bit line adjustment voltage is greater than zero.

2. The memory according to claim 1, characterized in that: The peripheral circuit comprises: A voltage generating module, wherein the voltage generating module is connected to the plurality of bit lines and sets the bit line operating voltage according to a selected voltage level corresponding to the operating instruction and sets the bit line regulating voltage according to the selected voltage level, wherein the operating instruction includes one of a read operation, a program verification operation, and an erase verification operation.

3. The memory according to claim 2, characterized in that: The voltage generating module provides multiple voltage levels, and the selected voltage level is selected from one of the multiple voltage levels corresponding to each of the operation instructions, and the voltage difference between the bit line operating voltage and the corresponding bit line regulating voltage under different selected voltage levels is maintained in a preset window.

4. The memory according to claim 2, characterized in that: The voltage generating module comprises: A clamping voltage selector, wherein an input end of the clamping voltage selector receives the operation instruction and selects the selected voltage level; a first clamping voltage generator connected to the clamping voltage selector and generating a first clamping voltage as the bit line adjustment voltage according to the selected voltage level; and The second clamping voltage generator is connected to the clamping voltage selector and generates a second clamping voltage as the bit line operating voltage according to the selected voltage level.

5. The memory according to claim 4, characterized in that: The peripheral circuit also includes: The instruction decoder is connected to the clamp voltage selector, receives the operation instruction, and outputs a mode flag to the clamp voltage selector.

6. The memory according to claim 4, characterized in that: The voltage generating module further includes: a multiplexer, wherein the multiplexer receives the first clamping voltage and the second clamping voltage and selectively outputs one of the first clamping voltage and the second clamping voltage to a bit line clamper.

7. The memory according to claim 4, characterized in that: Each two adjacent pairs of storage cells in the same row in the storage array share one bit line, and the plurality of bit lines further include a first special bit line located on a side of the addressing bit line away from the pairing bit line, and a second special bit line located on a side of the pairing bit line away from the addressing bit line, wherein the voltage generating module further outputs the first clamping voltage and the second clamping voltage to the at least one first special bit line and the at least one second special bit line, respectively.

8. The memory according to claim 4, characterized in that: The multiple bit lines in the storage array form a bit line group with every m bit lines, where m is a positive integer multiple of 3, and the multiple bit lines also include a first special bit line located in a target bit line group of the addressing bit line and located on a side of the addressing bit line away from the matching bit line, or a second special bit line located in the target bit line group and located on a side of the matching bit line away from the addressing bit line, wherein the voltage generating module further outputs the first clamping voltage and the second clamping voltage to the at least one first special bit line and the at least one second special bit line, respectively.

9. The memory according to claim 2, characterized in that: The peripheral circuit also includes: a reference current generator, configured to generate a reference current; and A sense amplifier is connected to the reference current generator and to one of the paired bit line and the address bit line, and receives and compares the reference current and the read current generated in the paired bit line and the address bit line, thereby outputting a signal representing the storage value of the selected memory cell.

10. The memory according to claim 9, characterized in that: The reference current generator outputs a reference current corresponding to the change of the operation command according to the change of the operation command.

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