Audio and video processing module
By designing detection circuits and selection circuits in the audio and video processing module, the rapid switching of audio and video data when a fault occurs is achieved, and the problem of slow response speed of audio and video modules in the prior art is solved, thereby improving the data continuity and reliability.
Patent Information
- Application Number
- CN202421805804.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-29
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2034-07-29
AI Technical Summary
The existing audio and video processing modules cannot switch signal channels in time when a fault is detected, resulting in the continuity and reliability of audio and video data.
An audio and video processing module is designed, including a processing module and a channel selection module. Through the coordinated work of the detection circuit and the selection circuit, the signal channel can be quickly identified and switched, ensuring the continuity and reliability of audio and video data.
Through hardware circuit detection and signal channels, the system response speed is significantly improved, the continuity and reliability of audio and video data is ensured, and the omission of key evidence and inaccuracy of accident investigation are avoided.
Smart Images
Figure CN222827296U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of audio and video, and in particular to an audio and video processing module. Background Art
[0002] In the field of aviation safety, the importance of audio and video modules as the core source of evidence for flight accident investigations is self-evident. It accurately records audio and video data during flight, covering key information such as crew communications, system status, and passenger reactions, providing valuable basis for accident analysis, prevention strategy formulation, and safety management system optimization. However, during the aircraft data collection and storage process, the failure or unstable state of the audio and video module will directly hinder the transmission of the signal to the storage device. If it is not handled in time, it will lead to the loss of monitoring information and the omission of key evidence, which will seriously affect the accuracy of accident investigations and safety assessments, and even cause irreparable losses. Therefore, it is extremely important to ensure the high reliability and stability of the audio and video modules.
[0003] The patent name that has been made public is a Chinese utility model patent with the publication number CN112770083A, which is "Dual-machine hot standby redundant audio and video system". This patent uses software to monitor the heartbeat signals of two audio and video processing boards to ensure that normal boards are in working condition. However, this design has slow response speed and efficiency, which is not conducive to maintaining smoothness and stability of the audio and video module during continuous shooting. Utility Model Content
[0004] The purpose of the present application is to provide an audio and video processing module, which solves the technical problem that the existing audio and video processing module cannot switch the signal channel in time when a fault is detected.
[0005] In order to solve the above technical problems, the solution adopted by this application is as follows:
[0006] The utility model provides an audio and video processing module, comprising a processing module and a channel selection module, wherein the processing module is connected to the selection module; the characteristic is that: the processing module comprises a primary processing module and a secondary processing module; the channel selection module comprises a detection circuit and a selection circuit; the output end of the primary processing module is connected to the input end of the detection circuit, the output end of the detection circuit is connected to the input end of the selection circuit, and the output end of the selection circuit is connected to the input end of the secondary processing module;
[0007] The detection circuit includes a differential amplifier circuit and a comparison circuit; the input end of the differential amplifier circuit serves as the input end of the detection circuit; the output end of the differential amplifier circuit is connected to the input end of the comparison circuit; the output end of the comparison circuit serves as the output end of the detection circuit;
[0008] The differential amplifier circuit comprises an operational amplifier, an input end of the operational amplifier serves as an input end of the differential amplifier circuit, and an output end of the operational amplifier serves as an output end of the differential amplifier circuit;
[0009] The comparison circuit comprises a first comparator, a second comparator and a third comparator, wherein the positive input terminal of the first comparator is connected to the negative input terminal of the second comparator and the input terminal is set here as the input terminal of the comparison circuit; the output terminals of the first comparator and the second comparator are connected and the output terminal is set here as the output terminal of the comparison circuit; the input terminal of the third comparator is connected to the input terminal of the operational amplifier; and the output terminal of the third comparator is used as the output terminal of the comparison circuit;
[0010] The selection circuit includes an XOR gate, a first AND gate, and a NOT gate. An input end of the XOR gate is connected to an input end of the first AND gate, and an output end of the XOR gate, two input ends of the first AND gate, and an input end of the NOT gate are connected; one input end and two input ends of the XOR gate are both input ends of the selection circuit; the output end of the first AND gate and the output end of the NOT gate are both output ends of the selection circuit.
[0011] In some embodiments, the primary processing module includes a low-pass filter amplifier and a high-pass filter amplifier, the input end of the low-pass filter amplifier serves as the input end of the primary processing module, the output end of the low-pass filter amplifier is connected to the input end of the high-pass filter amplifier, and the output end of the high-pass filter amplifier serves as the output end of the primary processing module.
[0012] In some embodiments, the comparison circuit further includes a voltage follower, the input end of the operational amplifier is connected to the input end of the third comparator through the voltage follower, and the voltage follower plays an isolation role in signal transmission.
[0013] In some embodiments, the secondary processing module includes a main control chip, and an output end of the main control chip serves as an output end of the secondary processing module.
[0014] In some embodiments, the main control chip is FPGA.
[0015] In some embodiments, the secondary processing module further includes an analog-to-digital converter, the output end of the analog-to-digital converter is connected to the input end of the main control chip, and the input end of the analog-to-digital converter serves as the input end of the secondary processing module.
[0016] In some embodiments, an alarm module is further included, and an input end of the alarm module is connected to an output end of the selection circuit.
[0017] In some embodiments, the selection circuit also includes a second AND gate and a third AND gate, an input end of the second AND gate is connected to the output end of the NOT gate, two input ends of the second AND gate, two input ends of the third AND gate, and two input ends of the XOR gate are connected; one input end of the third AND gate is connected to the output end of the XOR gate; the output end of the second AND gate and the output end of the third AND gate are respectively connected to the input end of the alarm module.
[0018] The technical solution of the present application has at least the following advantages and beneficial effects:
[0019] 1. The utility model integrates a detection circuit and a selection circuit, which work together to achieve rapid identification and switching of audio and video module failures. The design uses hardware circuits to detect failures and select signal channels, which significantly improves the response speed of the system and ensures the continuity and reliability of audio and video data;
[0020] 2. The utility model adopts connecting two groups of audio and video acquisition devices of the same type as redundancy protection, which can effectively locate and isolate faulty cameras and optimize energy consumption management. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 This is the detection circuit diagram of the utility model;
[0022] Figure 2 It is the selection circuit diagram of the utility model;
[0023] Figure 3 This is the circuit diagram of the primary processing module of the utility model. DETAILED DESCRIPTION
[0024] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0025] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in the subsequent figures. If the terms "center", "upper", "lower", "inner", "outer", etc. indicate an orientation or position relationship based on the orientation or position relationship shown in the figure, or the orientation or position relationship in which the product of the application is usually placed when in use, it is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. It should also be noted that unless otherwise clearly specified and limited, if the terms "set", "install", and "connect" appear, they should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a connection between the two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0026] Example 1
[0027] Please refer to Figure 1-Figure 3 The utility model provides an audio and video processing module, including a processing module and a channel selection module, the processing module is connected to the selection module; the processing module includes a primary processing module and a secondary processing module; the channel selection module includes a detection circuit and a selection circuit; the input end of the primary processing module is connected to the audio and video data acquisition device, the output end of the primary processing module is connected to the input end of the detection circuit, the output end of the detection circuit is connected to the input end of the selection circuit, and the output end of the selection circuit is connected to the input end of the secondary processing module;
[0028] It should be noted that the primary processing module is a preprocessing module, whose main purpose is to filter and amplify the signals transmitted by the audio and video data acquisition device to facilitate subsequent signal processing; the function of the secondary processing module is to further sample, quantize and encode the transmitted signals.
[0029] It should be noted that, in the present invention, each group of audio and video processing modules includes at least two primary processing modules.
[0030] It should be noted that the secondary processing module includes a main control chip, and the output end of the main control chip serves as the output end of the secondary processing module; it should be noted that the main control chip is an FPGA.
[0031] In some embodiments, the secondary processing module also includes an analog-to-digital converter, the output end of the analog-to-digital converter is connected to the input end of the main control chip, and the input end of the analog-to-digital converter serves as the input end of the secondary processing module; the coordinated use of the analog-to-digital converter and the main control chip can perform secondary processing on the signal, thereby enhancing the quality of the signal.
[0032] It should be noted that the detection circuit detects whether the primary processing module is in a normal working state. If the primary processing module is in an abnormal working state, the detection circuit sends a control signal to the selection circuit, so that the selection circuit selects a normal channel.
[0033] Furthermore, the primary processing module includes a low-pass filter amplifier and a high-pass filter amplifier, the input end of the low-pass filter amplifier serves as the input end of the primary processing module, the output end of the low-pass filter amplifier is connected to the input end of the high-pass filter amplifier, and the output end of the high-pass filter amplifier serves as the output end of the primary processing module.
[0034] Further, the first-level processing module circuit includes operational amplifiers U1 and U2, capacitors C1 and C2, and resistors R1, R2, R3, R4, R5, and R6;
[0035] The low-pass filter amplifier includes an operational amplifier U1, a capacitor C1, and resistors R1, R2, and R3; the high-pass filter amplifier includes an operational amplifier U2, a capacitor C2, and resistors R4, R5, and R6;
[0036] Specifically, the end of resistor R11 is set as the F_IN input end, the other end of resistor R1, one end of capacitor C1, and the positive input end of operational amplifier U1 are connected, and pin 5 of operational amplifier U1 is connected to a power supply; the negative input end of operational amplifier U1, one end of resistor R2, and one end of resistor R3 are connected; the other end of resistor R2 is grounded, the other end of resistor R3, the output end of operational amplifier U1, and one end of capacitor C2 are connected, the other end of capacitor C2, one end of resistor R6, and the positive input end of operational amplifier U2 are connected; the negative input end of operational amplifier U2, one end of resistor R5, and one end of resistor R4 are connected, the other end of resistor R5 is grounded, the other end of resistor R4 is connected to the output end of operational amplifier U2, and the F_OUT output end is set here; pin 5 of operational amplifier U2 is connected to a power supply, the other end of capacitor C1, pin 2 of operational amplifier U1, the other end of resistor R6, and pin 2 of operational amplifier U2 are connected and grounded.
[0037] It should be noted that the F_IN input terminal is connected to an audio and video data acquisition device; the audio and video data acquisition device is a prior art and will not be described in detail here.
[0038] The detection circuit includes a differential processing circuit and a comparison circuit; the input end of the differential amplifier circuit serves as the input end of the detection circuit; the output end of the differential amplifier circuit is connected to the input end of the comparison circuit; the output end of the comparison circuit serves as the output end of the detection circuit;
[0039] The differential processing circuit includes an operational amplifier, an input end of the operational amplifier serves as an input end of the differential processing circuit, and an output end of the operational amplifier serves as an output end of the differential processing circuit;
[0040] The comparison circuit includes a first comparator, a second comparator, and a third comparator. The positive input terminal of the first comparator is connected to the negative input terminal of the second comparator, and the input terminal is set here as the input terminal of the comparison circuit; the output terminals of the first comparator and the second comparator are connected, and the output terminal is set here as the output terminal of the comparison circuit; the input terminal of the third comparator is connected to the input terminal of the operational amplifier; and the output terminal of the third comparator is used as the output terminal of the comparison circuit;
[0041] The comparison circuit also includes a voltage follower, and the input end of the operational amplifier is connected to the input end of the third comparator through the voltage follower.
[0042] Further, the detection circuit includes operational amplifiers U3 and U6, a first comparator U4, a second comparator U5, a third comparator U7, a capacitor C3, diodes D1 and D2, resistors R7, R8, R9, R10, R11, R12, R13, R14 and R15, and a potentiometer PR1;
[0043] Wherein, the differential amplifier circuit includes an operational amplifier U3, resistors R7, R8, and R9; the comparison circuit includes an operational amplifier U6, a first comparator U4, a second comparator U5, a third comparator U7, a capacitor C3, diodes D1 and D2, resistors R10, R11, R12, R13, R14, and R15, and a potentiometer PR1;
[0044] It should be noted that in the comparison circuit, the voltage follower includes an operational amplifier U6 and a resistor R14; the voltage follower plays an isolation role in signal transmission;
[0045] Specifically, one end of the resistor R7 is set as the T_IN1 input terminal; the other end of the resistor R7, the negative input terminal of the operational amplifier U3, and one end of the resistor R9 are connected, and the other end of the resistor R9, the output terminal of the operational amplifier U3, the positive input terminal of the operational amplifier U4, and the negative input terminal of the operational amplifier U5 are connected; Pin 5 of the operational amplifier U3 is grounded, and Pin 2 is connected to the power supply, one end of the resistor R8 is set as the T_IN2 input terminal, and the output terminal of the resistor R8, the positive input terminal of the operational amplifier U3, and the positive input terminal of the operational amplifier U6 are connected; the negative input terminal of the operational amplifier U6 is connected to one end of the resistor R14, and the other end of the resistor R14, the output terminal of the operational amplifier U6, and one end of the resistor R15 are connected; Pin 2 of the operational amplifier U6 is connected to the power supply, and Pin 5 is grounded, the other end of the resistor R15, one end of the capacitor C3, and the positive input terminal of the operational amplifier U7 are connected, and the other end of the capacitor C3 is grounded; the operational amplifier Pin 2 of U7 is connected to the power supply, and pin 5 is grounded. The negative input terminal of the operational amplifier U7 is connected to the middle pin of the potentiometer PR,1, one end of the potentiometer PR1 is connected to the power supply, and the other end is grounded; the output terminal of the operational amplifier U7 is set to the T_OUT2 output terminal, pin 4 of the operational amplifier U4 is connected to the power supply, and pin 5 is grounded, the negative input terminal of the operational amplifier U4, one end of the resistor R10, and one end of the resistor R11 are connected, the other end of the resistor R10 is connected to the power supply, and the other end of the resistor R11 is grounded; the output terminal of the operational amplifier U4 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the cathode of the diode D2, and is set as the T_OUT1 output terminal here; pin 2 of the operational amplifier U5 is connected to the power supply, and pin 5 is grounded, the positive input terminal of the operational amplifier U5, one end of the resistor R13, and one end of the resistor R12 are connected, the other end of the resistor R12 is grounded, and the other end of the resistor R13 is connected to the power supply.
[0046] It should be noted that the output terminals of the two primary processing modules are connected to the input terminals T_IN1 and T_IN2 respectively.
[0047] In this embodiment, an alarm module is also included, and the input end of the alarm module is connected to the output end of the selection circuit; the alarm module is a prior art and will not be described in detail here.
[0048] The selection circuit includes an XOR gate, a first AND gate, and a NOT gate. An input terminal of the XOR gate is connected to an input terminal of the first AND gate, and an output terminal of the XOR gate, a second input terminal of the first AND gate, and an input terminal of the NOT gate are connected. An input terminal and a second input terminal of the XOR gate are both input terminals of the selection circuit. An output terminal of the first AND gate and an output terminal of the NOT gate are both output terminals of the selection circuit.
[0049] The selection circuit also includes a second AND gate and a third AND gate, an input end of the second AND gate is connected to the output end of the NOT gate, two input ends of the second AND gate, two input ends of the third AND gate, and two input ends of the XOR gate are connected; one input end of the third AND gate is connected to the output end of the XOR gate; the output end of the second AND gate and the output end of the third AND gate are respectively connected to the input end of the alarm module.
[0050] Further, the selection circuit includes a first AND gate U10, a second AND gate U11, a third AND gate U12, a NOT gate U9, and an XOR gate U8;
[0051] Specifically, pin 1 of the XOR gate U8 is connected to the A input terminal of the first AND gate U10, and the CON_IN1 input terminal is set here; pin 2 of the XOR gate U8, the B input terminal of the second AND gate U11, and the B input terminal of the third AND gate U12 are connected, and the CON_IN2 input terminal is set here; the output terminal of the XOR gate U8, the B input terminal of the first AND gate U10, the input terminal of the NOT gate U11, and the A input terminal of the third AND gate U12 are connected; the output terminal of the NOT gate U9 is connected to the A input terminal of the second AND gate U11, and the CON_OUT2 output terminal is set here; the output terminal of the first AND gate U10 is set to the CON_OUT1 output terminal, the output terminal of the second AND gate U11 is set to the CON_OUT3 output terminal, and the output terminal of the third AND gate U12 is set to the CON_OUT4 output terminal.
[0052] It should be noted that the CON_IN1 input terminal is connected to the T_OUT1 output terminal in the detection circuit, and the CON_IN2 input terminal is connected to the T_OUT2 output terminal in the detection circuit;
[0053] It should be noted that, in this embodiment, a MOS tube is used as a switch for channel switching, the first MOS tube is used to control the switch of one channel, and the second MOS tube is used to control the switch of the second channel; the output end of CON_OUT2 is connected to the first MOS tube, and the output end of CON_OUT1 is connected to the second MOS tube;
[0054] MOS tubes used as channel switches belong to the existing technology and will not be described in detail here.
[0055] It should be noted that the CON_OUT1 output terminal, the CON_OUT3 output terminal, and the CON_OUT4 output terminal are all connected to the alarm module.
[0056] To facilitate understanding of the selection circuit, the input and output truth table of the selection circuit is shown in Table 1 (in the table, "1" represents a high level and "0" represents a low level).
[0057] Table 1 Input and output truth table of the selection circuit
[0058]
[0059] As can be seen from Table 1, when both the CON_IN1 input terminal and the CON_IN2 input terminal receive a low level, it indicates that the two primary processing modules are in normal working state. At this time, the CON_OUT2 output terminal outputs a signal to the first MOS tube, opening a channel, and no alarm occurs at this time;
[0060] When the CON_IN1 input terminal receives a low level and the CON_IN2 input terminal receives a high level, it indicates that both primary processing modules are in abnormal working state. At this time, the CON_OUT4 output terminal outputs a signal to the alarm module.
[0061] When the CON_IN1 input terminal receives a high level and the CON_IN2 input terminal receives a low level, the primary processing module connected to the first channel is in an abnormal state, and the primary processing module connected to the second channel is normal. At this time, the CON_OUT1 output terminal outputs signals to the second MOS tube and the alarm module respectively, the second channel is turned on, and the alarm module locates the abnormality of the first channel;
[0062] When both the CON_IN1 input terminal and the CON_IN2 input terminal receive a high level, the primary processing module connected to the first channel is in a normal state, and the primary processing module connected to the second channel is abnormal. At this time, the CON_OUT2 output terminal outputs a signal to the first MOS tube, and the first channel is turned on; the CON_OUT3 output terminal outputs a signal to the alarm module, and the alarm module locates the abnormality of the second channel.
[0063] For ease of understanding, the workflow of the present invention is described by taking video processing as an example:
[0064] The video acquisition device transmits the collected data to two primary processing modules for filtering and amplification processing;
[0065] The primary processing module connected to the first channel and the primary processing module connected to the second channel transmit the processed signals to the two input terminals of the differential amplifier circuit for differential amplification processing, and the primary processing module connected to the second channel transmits the signals to the third comparator U7 for comparison;
[0066] If the differentially amplified signal does not exceed the threshold range, and the third comparator U7 compares that the signal output by the primary processing module connected to the second channel does not exceed the threshold, it means that both primary processing modules are normal, and at this time, the output terminal T_OUT1 outputs a low level, and the output terminal T_OUT2 outputs a low level;
[0067] If the signal after differential amplification exceeds the threshold range, and the third comparator U7 compares that the signal output by the primary processing module connected to the second channel does not exceed the threshold, it means that the primary processing module connected to the first channel is faulty and the primary processing module connected to the second channel is normal. At this time, the output terminal T_OUT1 outputs a high level and the output terminal T_OUT2 outputs a low level.
[0068] If the signal after differential amplification exceeds the threshold range, and the third comparator U7 compares that the signal output by the primary processing module connected to the second channel exceeds the threshold, it means that the primary processing module connected to the second channel is faulty and the primary processing module connected to the first channel is normal. At this time, the output terminal T_OUT1 outputs a high level and the output terminal T_OUT2 outputs a high level.
[0069] If the differentially amplified signal does not exceed the threshold range, but the third comparator U7 compares that the signal output by the primary processing module connected to the second channel exceeds the threshold, it means that both primary processing modules are faulty. At this time, the output terminal T_OUT1 outputs a low level and the output terminal T_OUT2 outputs a high level.
[0070] The judgment result is transmitted from the comparison circuit to the selection circuit, and the selection circuit performs channel selection and alarm positioning according to the received signal.
[0071] It should be noted that the audio processing method is the same as the video processing method.
[0072] It should be noted that in the present invention, after the video analog signal and the audio analog signal pass through different primary processing modules respectively, the processed audio and video signals will be transmitted to the same secondary processing module. In addition to further processing the two signals, the secondary processing module will also perform signal synchronization processing on them to ensure audio and video synchronization.
[0073] So far, various embodiments of the present invention have been described in detail. In order to avoid obscuring the concept of the present invention, some details known in the art are not described. Based on the above description, those skilled in the art can fully understand how to implement the technical solution of the present invention, and the scope of the present invention is defined by the attached claims.
Claims
1. An audio and video processing module, comprising a processing module and a channel selection module, wherein the processing module is connected to the selection module; characterized in that: The processing module includes a primary processing module and a secondary processing module; the channel selection module includes a detection circuit and a selection circuit; the output end of the primary processing module is connected to the input end of the detection circuit, the output end of the detection circuit is connected to the input end of the selection circuit, and the output end of the selection circuit is connected to the input end of the secondary processing module; The detection circuit includes a differential amplifier circuit and a comparison circuit; the input end of the differential amplifier circuit serves as the input end of the detection circuit; the output end of the differential amplifier circuit is connected to the input end of the comparison circuit; the output end of the comparison circuit serves as the output end of the detection circuit; The differential amplifier circuit comprises an operational amplifier, an input end of the operational amplifier serves as an input end of the differential amplifier circuit, and an output end of the operational amplifier serves as an output end of the differential amplifier circuit; The comparison circuit comprises a first comparator, a second comparator and a third comparator, wherein the positive input terminal of the first comparator is connected to the negative input terminal of the second comparator and the input terminal is set here as the input terminal of the comparison circuit; the output terminals of the first comparator and the second comparator are connected and the output terminal is set here as the output terminal of the comparison circuit; the input terminal of the third comparator is connected to the input terminal of the operational amplifier; and the output terminal of the third comparator is used as the output terminal of the comparison circuit; The selection circuit includes an XOR gate, a first AND gate, and a NOT gate. An input end of the XOR gate is connected to an input end of the first AND gate, and an output end of the XOR gate, two input ends of the first AND gate, and an input end of the NOT gate are connected; one input end and two input ends of the XOR gate are both input ends of the selection circuit; the output end of the first AND gate and the output end of the NOT gate are both output ends of the selection circuit.
2. The audio and video processing module according to claim 1, characterized in that: The primary processing module includes a low-pass filter amplifier and a high-pass filter amplifier. The input end of the low-pass filter amplifier serves as the input end of the primary processing module, the output end of the low-pass filter amplifier is connected to the input end of the high-pass filter amplifier, and the output end of the high-pass filter amplifier serves as the output end of the primary processing module.
3. The audio and video processing module according to claim 1, characterized in that: The comparison circuit further includes a voltage follower, through which the input end of the operational amplifier is connected to the input end of the third comparator, and the voltage follower plays an isolation role in signal transmission.
4. The audio and video processing module according to claim 1, characterized in that: The secondary processing module includes a main control chip, and the output end of the main control chip serves as the output end of the secondary processing module.
5. The audio and video processing module according to claim 4, characterized in that: The main control chip is FPGA.
6. The audio and video processing module according to claim 4, characterized in that: The secondary processing module further includes an analog-to-digital converter, the output end of the analog-to-digital converter is connected to the input end of the main control chip, and the input end of the analog-to-digital converter serves as the input end of the secondary processing module.
7. The audio and video processing module according to claim 1, characterized in that: It also includes an alarm module, the input end of the alarm module is connected to the output end of the selection circuit.
8. The audio and video processing module according to claim 7, characterized in that: The selection circuit also includes a second AND gate and a third AND gate, an input end of the second AND gate is connected to the output end of the NOT gate, two input ends of the second AND gate, two input ends of the third AND gate, and two input ends of the XOR gate are connected; an input end of the third AND gate is connected to the output end of the XOR gate; the output end of the second AND gate and the output end of the third AND gate are respectively connected to the input end of the alarm module.