Anti-static integrated circuit module
By setting up multiple series diodes in the integrated circuit module, the problem of weak current resistance during reverse breakdown is solved, and stronger ESD protection and current resistance are achieved, and power equipment is protected.
Patent Information
- Application Number
- CN202421700557.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-18
- Publication Date
- 2025-05-02
- Estimated Expiration
- 2034-07-18
AI Technical Summary
In the existing ESD protection measures, the diode has weak current resistance during reverse breakdown and is prone to burning, resulting in failure and performance of power systems and electronic equipment.
An anti-static integrated circuit module is designed to improve ESD protection and enhance the current resistance of the diode by setting multiple diodes in series on the P++ semiconductor substrate.
It effectively improves the ESD protection capability of the circuit, enhances the current resistance of the diode, protects the power equipment, and reduces the failure rate and performance losses.
Smart Images
Figure CN222827582U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to an anti-static integrated circuit module. Background Art
[0002] Electrostatic discharge (ESD) refers to the charge transfer phenomenon that occurs when objects with different electric potentials are close to or in contact with each other. During the electrostatic discharge process, the discharge time is short and a large transient voltage or current will be generated, which may cause damage or even burning of electronic devices. Therefore, the ESD protection of electronic devices has an extremely important impact on their reliability performance.
[0003] At present, a commonly used ESD protection measure is to use the reverse breakdown characteristics of the diode. When the ESD phenomenon occurs, the diode reversely breaks down, and its working impedance can be reduced to an extremely low conduction value, thereby allowing large currents to pass through, while clamping the voltage to a predetermined level, thereby protecting electronic devices. However, when reverse breakdown occurs, the current resistance of the diode is very weak. In the power system, when the current passing through the diode exceeds its tolerance, it will cause the diode to burn out, thereby causing a failure in the power system; in electronic equipment, when the diode is subjected to excessive current, it will cause damage to the equipment and cause safety hazards. At the same time, excessive current will also reduce the performance of the equipment and shorten its service life. Utility Model Content
[0004] In view of the deficiencies of the above-mentioned related prior arts, the present application provides an anti-static integrated circuit module, which improves the ESD protection capability while improving the current resistance capability, protects the power equipment, and has strong practicality.
[0005] In order to achieve the above purpose, the utility model adopts the following technologies:
[0006] An anti-static integrated circuit module comprises: a P++ semiconductor substrate, a first diode, a second diode and a third diode.
[0007] An N-epitaxial layer is provided on the top surface of the P++ semiconductor substrate, and a plurality of first P++ isolation wells are provided in the N-epitaxial layer along the length direction thereof, and the lower end of the first P++ isolation well is located in the P++ semiconductor substrate; the first diode includes a first N+ region provided in the N-epitaxial layer and located between two first P++ isolation wells; there are a plurality of second diodes, all provided on one side of the first diode, and connected in series with each other, including a first P+ region provided in the N-epitaxial layer and located between the two first P++ isolation wells, and second N+ regions are provided on both sides of the first P+ region, and two second N+ regions of the first second diode are connected in series with each other. + region is connected to the first P+ region of the next second diode through a wire, and the two second N+ regions of the last second diode are connected to a first P++ isolation well through a wire; the third diode is arranged between the first diode and the second diode, including a second P+ region arranged in the N-epitaxial layer and located between the two first P++ isolation wells, and third N+ regions are respectively arranged on both sides of the second P+ region; the first N+ region is connected to the first P+ region through a wire, and the first P+ region of the previous second diode is connected to the two third N+ regions through a wire, and one of the third N+ regions is provided with a VDD port.
[0008] Furthermore, it also includes a fourth diode located between the first diode and the second diode, the fourth diode includes a second P++ isolation well arranged between the two first P++ isolation wells, a third P+ region with one end located in the P++ semiconductor substrate is provided in the second P++ isolation well, a fourth N+ region is provided at the other end of the third P+ region, and the first P+ region closest to the third diode is also connected to the fourth N+ region through a wire.
[0009] Furthermore, a first diode and a third diode are provided on the side of the second diode farthest from the first diode, the first P+ region of the third diode is connected to the first N+ region of the second diode through a wire, and the two second N+ regions of the third diode are connected to the VDD port through a wire.
[0010] Furthermore, the first N+ region is provided with an IO port.
[0011] Furthermore, the number of the second diodes is 8 to 9.
[0012] Furthermore, a GND terminal is provided at the bottom of the P++ semiconductor substrate.
[0013] The beneficial effects of the utility model are:
[0014] By setting up multiple diodes in series, the ESD protection capability of the circuit is improved, and the current resistance of the diode is made stronger, thereby protecting the power equipment. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present invention.
[0016] Figure 1 This is a cross-sectional view of the overall structure of an embodiment of the present application.
[0017] Figure 2 Schematic diagram of the circuit structure of an embodiment of the present application.
[0018] Figure 3 An overall structural cross-sectional view of an additional fourth diode is provided for the embodiment of the present application.
[0019] Figure 4 This is a schematic diagram of the circuit structure after adding a fourth diode in the embodiment of the present application.
[0020] Figure 5 A cross-sectional view of the overall structure of an embodiment of the present application is provided with a plurality of first diodes and a second diode.
[0021] Figure 6 A schematic diagram of a circuit structure in which a plurality of first diodes and a plurality of second diodes are provided in an embodiment of the present application. DETAILED DESCRIPTION
[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the utility model clearer, the implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings, but the embodiments described in the utility model are only part of the embodiments of the utility model, rather than all the embodiments.
[0023] like Figure 1 to Figure 6 As shown, this example provides an anti-static integrated circuit module, including: a P++ semiconductor substrate 1, a first diode 2, a second diode 3, and a third diode 4.
[0024] An N-epitaxial layer 11 is provided on the top surface of the P++ semiconductor substrate 1, and a plurality of first P++ isolation wells 12 are provided in the N-epitaxial layer 11 along its length direction, and the lower end of the first P++ isolation well 12 is located in the P++ semiconductor substrate 1; the first diode 2 includes a first N+ region 21 provided in the N-epitaxial layer 11 and located between two first P++ isolation wells 12; there are a plurality of second diodes 3, all provided on one side of the first diode 2, and connected in series with each other, including a first P+ region 31 provided in the N-epitaxial layer 11 and located between the two first P++ isolation wells 12, and second N+ regions 32 are provided on both sides of the first P+ region 31, and the two second N+ regions 32 of the first second diode 3 are connected to the second second diode 3 of the latter. The first P+ region 31 is connected by a wire, and the two second N+ regions 32 of the last second diode 3 are connected to a first P++ isolation well 12 by a wire, so that multiple second diodes 3 are connected in series; the third diode 4 is arranged between the first diode 2 and the second diode 3, including a second P+ region 41 arranged in the N-epitaxial layer 11 and located between the two first P++ isolation wells 12, and third N+ regions 42 are respectively arranged on both sides of the second P+ region 41; the first N+ region 21 is connected to the first P+ region 41 by a wire, and the first P+ region 31 of the previous second diode 3 is connected to the two third N+ regions 42 by a wire, and one of the third N+ regions 42 is provided with a VDD port to provide a positive voltage for the circuit.
[0025] Specifically, in order to enhance the ESD protection effect of the circuit, a fourth diode 5 is further arranged between the first diode 2 and the second diode 3. The fourth diode 5 includes a second P++ isolation well 51 arranged between the two first P++ isolation wells 12. The second P++ isolation well 51 is provided with a third P+ region 52 with one end located in the P++ semiconductor substrate 1, and the other end of the third P+ region 52 is provided with a fourth N+ region 53. The first P+ region 31 closest to the third diode 4 is also connected to the fourth N+ region 53 through a wire, so that the fourth diode 5 and the second diode 3 are also connected in series.
[0026] Specifically, a first diode 2 and a third diode 4 are further provided on the side of the second diode 3 which is farthest from the first diode 2. The first P+ region 41 of the third diode 4 is connected to the first N+ region 31 of the second diode 3 through a wire, and the two second N+ regions 42 of the third diode 4 are connected to the VDD port through a wire. The first diode 2 and the third diode 4 are a group, and multiple groups of first diodes 2 and third diodes 4 can be added to form a multi-channel input structure to achieve multi-path protection of the circuit.
[0027] Specifically, the first N+ region 21 is provided with an IO port. If only one first diode 2 is provided, the entire module has only one IO port, forming a single-channel input structure. At this time, the circuit can be protected. If multiple first diodes 2 and third diodes 4 are provided, the entire module is also provided with multiple IO ports, forming a multi-channel input structure. Multi-channel protection of the circuit can be achieved using one protection core, which saves circuit area compared to using multiple modules to perform single-channel protection respectively.
[0028] Specifically, each diode has a forward conduction voltage drop V when it is forward-conducting. fb , its forward conduction voltage drop is usually 0.6V-0.7V, the number of second diodes 3 can be 8-9, then the forward diode voltage drops of multiple second diodes 3 will be superimposed, that is: V FB =V fb1 + V fb2 + V fb3 +…+V fbn ; Thereby, the clamping voltage can be maintained at a safe level and large current can be allowed to pass, thereby protecting the circuit.
[0029] Specifically, a GND terminal is provided at the bottom of the P++ semiconductor substrate 1 to achieve grounding.
[0030] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. An anti-static integrated circuit module, characterized in that: include: A P++ semiconductor substrate (1), a top surface of which is provided with an N-epitaxial layer (11), a plurality of first P++ isolation wells (12) are provided in the N-epitaxial layer (11) along its length direction, and the lower ends of the first P++ isolation wells (12) are located in the P++ semiconductor substrate (1); A first diode (2) comprising a first N+ region (21) provided in an N-epitaxial layer (11) and located between two first P++ isolation wells (12); There are a plurality of second diodes (3), all arranged on one side of the first diode (2) and connected in series, comprising a first P+ region (31) arranged in the N-epitaxial layer (11) and located between two first P++ isolation wells (12), second N+ regions (32) are also arranged on both sides of the first P+ region (31), the two second N+ regions (32) of the first second diode (3) are connected to the first P+ region (31) of the next second diode (3) through a wire, and the two second N+ regions (32) of the last second diode (3) are connected to a first P++ isolation well (12) through a wire; A third diode (4) is provided between the first diode (2) and the second diode (3), comprising a second P+ region (41) provided in the N-epitaxial layer (11) and located between two first P++ isolation wells (12), and third N+ regions (42) are provided on both sides of the second P+ region (41); The first N+ region (21) and the first P+ region (41) are connected via a wire, and the first P+ region (31) of the previous second diode (3) and two third N+ regions (42) are connected via wires, wherein one of the third N+ regions (42) is provided with a VDD port.
2. The anti-static integrated circuit module according to claim 1, characterized in that: The invention also comprises a fourth diode (5) located between the first diode (2) and the second diode (3); the fourth diode (5) comprises a second P++ isolation well (51) located between the two first P++ isolation wells (12); a third P+ region (52) having one end located in the P++ semiconductor substrate (1) is provided in the second P++ isolation well (51); a fourth N+ region (53) is provided at the other end of the third P+ region (52); and the first P+ region (31) closest to the third diode (4) is also connected to the fourth N+ region (53) via a wire.
3. The anti-static integrated circuit module according to claim 1, characterized in that: The first diode (2) and a third diode (4) are also provided on one side of the second diode (3) which is farthest from the first diode (2); the first P+ region (41) of the third diode (4) is connected to the first N+ region (31) of the second diode (3) via a wire, and the two second N+ regions (42) of the third diode (4) are connected to the VDD port via a wire.
4. The anti-static integrated circuit module according to claim 3, characterized in that: The first N+ region (21) is provided with an IO port.
5. The anti-static integrated circuit module according to claim 1, characterized in that: The number of the second diodes (3) is 8 to 9.
6. The anti-static integrated circuit module according to claim 1, characterized in that: A GND terminal is provided at the bottom of the P++ semiconductor substrate (1).