Laminated cell and photovoltaic module

Abstract

The utility model is suitable for the technical field of solar power generation, and provides a laminated cell and a photovoltaic assembly, the laminated cell comprises a TOPCon cell structure as a bottom cell and a perovskite cell structure as a top cell, a boron doping layer of the TOPCon cell structure is arranged on the front surface of a silicon substrate; the at least one layer of front passivation contact structure is laminated on the boron doped layer, and the front passivation contact structure comprises a first silicon oxide layer and a first doped layer; the at least one layer of back surface passivation contact structure is laminated on the back surface of the silicon substrate, the back surface passivation contact structure comprises a second silicon dioxide layer and a second doping layer, and the back surface metal electrode is connected with the second doping layer; the perovskite cell structure comprises an electron transport layer, a light absorption layer, a hole transport layer and a front metal electrode which are sequentially arranged on the outermost first doping layer, and can be well compatible with an existing mainstream TOPCon cell production line, so that the preparation cost of the laminated cell is reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of solar power generation, and in particular relates to a laminated battery and a photovoltaic component. Background Art

[0002] Perovskite solar cells are solar cells that use perovskite-type organic metal halide semiconductors as light-absorbing materials. Existing perovskite / crystalline silicon stacked cells use HJT (Hetero-junction with Intrinsic Thin-film) cells as bottom cells. The HJT cells include ITO / nc-Si(n+) / a-Si(i) / c-Si / a-Si(i) / a-Si(p+) / TCO / Ag as bottom cells. Figure 1 However, due to the high cost of HJT cells, this will also result in high costs for perovskite stacked cells with HJT cells as the bottom cells.

[0003] In order to reduce the battery cost, a double-sided passivation contact structure can also be used as a perovskite stacked battery with a bottom battery. The double-sided passivation contact structure includes poly(p+) / poly(n+) / SiOx / c-Si / SiOx / poly(p+) / Cr / Ag, such as Figure 2 However, the double-sided passivation contact structure is not compatible with the current TOPCon battery structure production line, resulting in high bottom battery preparation costs. Utility Model Content

[0004] The embodiment of the utility model provides a laminated battery, aiming to solve the problem that the existing laminated battery has high preparation cost and is not compatible with the mainstream TOPCon battery production line.

[0005] The embodiment of the utility model is implemented as follows: a stacked battery, including a TOPCon battery structure as a bottom battery and a perovskite battery structure as a top battery;

[0006] The TOPCon cell structure includes a silicon substrate, a boron-doped layer, at least one front passivation contact structure, at least one back passivation contact structure and a back metal electrode;

[0007] The boron doped layer is arranged on the front side of the silicon substrate;

[0008] At least one front passivation contact structure stack is disposed on the boron doped layer, the front passivation contact structure comprising a first silicon oxide layer and a first doped layer sequentially disposed in a direction away from the silicon substrate;

[0009] At least one back passivation contact structure is stacked on the back of the silicon substrate, the back passivation contact structure includes a second silicon oxide layer and a second doped layer sequentially arranged in a direction away from the silicon substrate, and a back metal electrode is connected to the second doped layer;

[0010] The perovskite cell structure includes an electron transport layer, a light absorption layer, a hole transport layer and a front metal electrode which are sequentially arranged on the outermost first doping layer.

[0011] Furthermore, the silicon substrate includes any one of a P-type silicon wafer and an N-type silicon wafer.

[0012] Further, a boron doped layer is arranged in a local area of ​​the front surface.

[0013] Furthermore, the width of the boron doped layer is 20 micrometers to 2000 micrometers.

[0014] Furthermore, at least two boron-doped layers are arranged on the front side, and the distance between two adjacent boron-doped layers is 100 micrometers to 5000 micrometers.

[0015] Furthermore, the edge of the front passivation contact structure is directly opposite to or staggered from the edge of the boron doped layer.

[0016] Furthermore, the width of the boron doped layer is smaller than the width of the front passivation contact structure.

[0017] Furthermore, the first doping layer and the second doping layer have the same polarity.

[0018] Furthermore, the stacked cell further comprises a back passivation film, which is arranged on a side of the second doped layer away from the second silicon oxide layer, and the back metal electrode passes through the back passivation film and is connected to the second doped layer.

[0019] Further, the back surface passivation film includes at least one of silicon nitride, aluminum oxide, silicon oxynitride and silicon oxide.

[0020] Furthermore, the front side and / or the back side of the silicon substrate is a polished surface or a velvet surface.

[0021] Furthermore, a TCO layer is disposed on a side of the hole transport layer away from the light absorbing layer.

[0022] Furthermore, an anti-reflection layer is disposed on a side of the TCO layer away from the hole transport layer.

[0023] Furthermore, a first interface passivation layer is provided between the electron transport layer and the light absorbing layer.

[0024] Furthermore, a second interface passivation layer is provided between the light absorbing layer and the hole transport layer.

[0025] In a second aspect, the present application also provides a photovoltaic module, comprising the laminated cell as described above.

[0026] The beneficial effect of the present application is that the stacked battery of the present application includes a TOPCon battery structure as a bottom battery and a perovskite battery structure as a top battery, wherein the TOPCon battery structure includes a silicon substrate, a boron-doped layer, at least one front passivation contact structure, at least one back passivation contact structure and a back metal electrode; the boron-doped layer is arranged on the front side of the silicon substrate; at least one front passivation contact structure stack is arranged on the boron-doped layer, and the front passivation contact structure includes a first silicon oxide layer and a first doped layer arranged in sequence along a direction from the silicon substrate to away from the silicon substrate; at least one back passivation contact structure stack is arranged on the back side of the silicon substrate, and the back passivation contact structure includes a first silicon oxide layer and a first doped layer arranged in sequence along a direction from the silicon substrate to away from the silicon substrate; A second silicon oxide layer and a second doped layer are sequentially arranged on the silicon substrate in a direction away from the silicon substrate, and the back metal electrode is connected to the second doped layer; the perovskite battery structure includes an electron transport layer, a light absorption layer, a hole transport layer and a front metal electrode sequentially arranged on the outermost first doped layer, which is well compatible with the existing mainstream TOPCon battery production line, thereby reducing the preparation cost of the stacked battery; in addition, during the preparation process, the front passivation contact structure can be directly prepared on the boron doped layer, reducing the process steps and reducing the preparation cost, and the front passivation contact structure and the back passivation contact structure can be prepared and formed at the same time without setting a mask, simplifying the preparation process and improving the preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of an existing HJT battery-based stacked battery;

[0028] Figure 2 It is a schematic diagram of the structure of an existing laminated battery based on a double-sided passivated contact structure;

[0029] Figure 3 It is a structural schematic diagram of an embodiment of a stacked battery provided by the present application;

[0030] Figure 4 It is a structural schematic diagram of a partial arrangement of a front passivation contact structure of an embodiment of a laminated battery provided by the present application;

[0031] Figure 5 This is a schematic structural diagram of a local arrangement of a boron-doped layer in an embodiment of a stacked battery provided by the present application;

[0032] Figure 6 It is a structural schematic diagram of the preparation process of an embodiment of the stacked battery provided in the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, in which the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the utility model, and cannot be understood as limiting the utility model. In addition, it should be understood that the specific embodiments described herein are only used to explain the utility model and are not used to limit the utility model.

[0034] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present invention.

[0035] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present utility model, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0036] In the description of the present utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0037] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0038] The disclosure below provides many different embodiments or examples for realizing different structures of the utility model. In order to simplify the disclosure of the utility model, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the utility model. In addition, the utility model can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the utility model provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0039] The stacked battery of the present application includes a TOPCon battery structure as a bottom battery and a perovskite battery structure as a top battery, wherein the TOPCon battery structure includes a silicon substrate, a boron-doped layer, at least one front passivation contact structure, at least one back passivation contact structure and a back metal electrode; the boron-doped layer is arranged on the front side of the silicon substrate; at least one front passivation contact structure stack is arranged on the boron-doped layer, and the front passivation contact structure includes a first silicon oxide layer and a first doped layer arranged in sequence along a direction from the silicon substrate to away from the silicon substrate; at least one back passivation contact structure stack is arranged on the back side of the silicon substrate, and the back passivation contact structure includes a first silicon oxide layer and a first doped layer arranged in sequence along a direction from the silicon substrate to away from the silicon substrate A second silicon oxide layer and a second doped layer are sequentially arranged in the direction away from the silicon substrate, and the back metal electrode is connected to the second doped layer; the perovskite battery structure includes an electron transport layer, a light absorption layer, a hole transport layer and a front metal electrode sequentially arranged on the outermost first doped layer, which is well compatible with the existing mainstream TOPCon battery production line, thereby reducing the preparation cost of the stacked battery; in addition, during the preparation process, the front passivation contact structure can be directly prepared on the boron doped layer, which reduces the process steps and reduces the preparation cost, and the front passivation contact structure and the back passivation contact structure can be prepared and formed at the same time without setting a mask, thereby simplifying the preparation process and improving the preparation efficiency.

[0040] Embodiment 1

[0041] like Figures 3 to 6As shown, one embodiment of the present application provides a stacked cell, including a TOPCon cell structure 100 as a bottom cell and a perovskite cell structure 200 as a top cell;

[0042] The TOPCon cell structure 100 includes a silicon substrate 110, a boron doped layer 120, at least one front passivation contact structure 130, at least one back passivation contact structure 140 and a back metal electrode 150;

[0043] The boron doped layer 120 is disposed on the front surface of the silicon substrate 110;

[0044] At least one front passivation contact structure 130 is stacked on the boron doped layer 120, and the front passivation contact structure 130 includes a first silicon oxide layer 131 and a first doping layer 132 sequentially arranged in a direction from the silicon substrate 110 to away from the silicon substrate 110;

[0045] At least one back passivation contact structure 140 is stacked on the back of the silicon substrate 110, and the back passivation contact structure 140 includes a second silicon oxide layer 141 and a second doping layer 142 sequentially arranged in a direction away from the silicon substrate 110, and a back metal electrode 150 is connected to the second doping layer 142;

[0046] The perovskite cell structure 200 includes an electron transport layer 210 , a light absorption layer 220 , a hole transport layer 230 and a front metal electrode 240 which are sequentially arranged on the outermost first doping layer 132 .

[0047] During implementation, the silicon substrate 110 can be an N-type silicon wafer or a P-type silicon wafer, wherein the N-type silicon wafer is obtained by adding a pentavalent element (such as phosphorus) to intrinsic semiconductor silicon, and the P-type silicon wafer is obtained by adding a trivalent element (such as boron, gallium or indium) to intrinsic semiconductor silicon, which will not be elaborated herein.

[0048] The silicon substrate 110 has a front side and a back side. Generally, the front side of the silicon substrate 110 is considered to be the light-receiving side of the solar cell. Similarly, the back side of the silicon substrate 110 is considered to be the backlight side of the solar cell.

[0049] A boron-doped layer 120 is disposed on the front side of the silicon substrate 110 . The boron-doped layer 120 is generated by diffusing boron on the silicon substrate 110 . That is, the boron-doped layer 120 refers to a thin layer doped with boron atoms formed by doping the front side of the silicon substrate 110 with boron elements.

[0050] After the boron diffusion process is performed on the silicon substrate 110, a boron-doped layer 120 and a BSG (Back Surface Field Silicon Wafer) layer may be generated on the front side of the silicon substrate 110, or a boron-doped layer 120 and a PSG (Phosphorus-doped Silicon Wafer) layer may be generated on the front side of the silicon substrate 110. Before performing subsequent processes, it is necessary to remove the BSG or PSG on the front side and retain the boron-doped layer 120.

[0051] In some embodiments, the BSG or PSG on the front side can be removed by etching, for example, the silicon substrate 110 after boron diffusion is placed in an etching solution to remove the BSG or PSG on the front side. The etching solution can be an aqueous solution of H2SO4 (sulfuric acid) plus HF (hydrogen fluoride) or a solution that can etch BSG or PSG, without limitation.

[0052] In some possible embodiments, in order to prevent the etching solution from causing damage to the back side and / or side of the silicon substrate 110, the back side and / or side of the silicon substrate 110 after boron diffusion can be first covered with a layer of water film, and then the silicon substrate 110 covered with the water film is placed in the etching solution to remove the BSG or PSG on the front side, so that only the boron doped layer 120 is retained on the front side of the silicon substrate 110.

[0053] In some possible embodiments, after the silicon substrate 110 is subjected to a boron diffusion process, a boron-doped layer 120 plus a layer of BSG or PSG may be generated on the front side of the silicon substrate 110, and a boron-doped layer 120 plus a layer of BSG or PSG may be generated on the back side of the silicon substrate 110. Before performing subsequent processes, it is necessary to remove the BSG or PSG on the front side, the BSG or PSG on the back side, and the boron-doped layer 120 on the back side, that is, only the boron-doped layer 120 on the front side is retained.

[0054] At least one layer of front passivation contact structure 130 is further disposed on the boron doped layer 120 . The front passivation contact structures 130 are stacked layer by layer on the boron doped layer 120 in a stacked manner.

[0055] The front passivation contact structure 130 is a passivation contact structure arranged on the front of the battery, including a first silicon oxide layer 131 and a first doping layer 132, wherein the first silicon oxide layer 131 refers to a tunneling oxide layer (SiO2), and the first doping layer 132 refers to a doped polysilicon layer (n-poly). The doped polysilicon layer and the silicon substrate 110 generate an anti-blocking layer at the contact surface, forming a potential barrier to holes, blocking minority holes from reaching the interface of silicon oxide / silicon substrate 110. On the other hand, the tunneling oxide layer can achieve selective permeation of carriers, because the potential barrier height caused by the tunneling oxide layer for electron tunneling is 3.1eV, while the potential barrier height for holes is 4.5eV. Due to the tunneling barrier height caused by the tunneling oxide layer, few or almost no holes can pass through the barrier to reach the other side of the tunneling oxide layer. Even if they can pass through, there is a potential barrier in the doped polysilicon layer to block the holes from reaching the interface of the metal semiconductor contact for recombination, which greatly improves the conversion efficiency of the battery.

[0056] During implementation, the first silicon oxide layer 131 and the first doping layer 132 may be prepared by PECVD (plasma enhanced chemical vapor deposition) or LPCVD (Low Pressure Chemical Vapor Deposition), without limitation.

[0057] Optionally, the passivation contact structure may have only one layer, that is, a first silicon oxide layer 131 and a first doping layer 132 are disposed on the boron doped layer 120, such as Figure 3 shown.

[0058] Optionally, the passivation contact structure may be provided with multiple layers, such as 2 layers, 3 layers, 4 layers or other number of layers, without limitation. Exemplarily, taking the passivation contact structure including 2 layers as an example, that is, a first silicon oxide layer 131, a first doping layer 132, a first silicon oxide layer 131 and a first doping layer 132 are sequentially provided on the boron-doped layer 120, that is, a boron-doped layer 120 / SiOx / n-poly / SiOx / n-poly structure; Optionally, taking the passivation contact structure including 3 layers as an example, that is, a first silicon oxide layer 131, a first doping layer 132, a first silicon oxide layer 131, a first doping layer 132, a first silicon oxide layer 131 and a first doping layer 132 are sequentially provided on the boron-doped layer 120, that is, a boron-doped layer 120 / SiOx / n-poly / SiOx / n-poly / SiOx / n-poly structure, which is not described in detail.

[0059] At least one back passivation contact structure 140 is disposed on the back side of the silicon substrate 110. The at least one back passivation contact structure 140 is disposed on the back side of the silicon substrate 110 in a stacked manner, wherein the back passivation contact structure 140 includes a second silicon oxide layer 141 and a second doping layer 142 sequentially disposed in a direction away from the silicon substrate 110, and the back metal electrode 150 is connected to the second doping layer 142. In implementation, the back passivation contact structure 140 can refer to the above-mentioned front passivation contact structure 130, and no further description is given.

[0060] Optionally, the front passivation contact structure 130 and the back passivation contact structure 140 have the same polarity, that is, the first doping layer 132 and the second doping layer 142 have the same polarity. The front passivation contact structure 130 and the back passivation contact structure 140 can be prepared step by step or simultaneously to reduce the preparation process flow.

[0061] A back metal electrode 150 is disposed on the back passivation contact structure 140, and the back metal electrode 150 can be connected to the second doped layer 142 of any layer of the back passivation contact structure 140. Exemplarily, taking the case where a layer of back passivation contact structure 140 is disposed on the back of the silicon substrate 110, the back metal electrode 150 is directly connected to the second doped layer 142. When multiple layers of back passivation contact structures 140 are disposed on the back of the silicon substrate 110, for example, two layers of back passivation contact structures 140, the back metal electrode 150 can be connected to the second doped layer 142 of the second layer (a layer away from the silicon substrate 110) of the back passivation contact structure 140, or the back metal electrode 150 can pass through the second layer of the back passivation contact structure 140 and then connect to the second doped layer 142 of the first layer (a layer closest to the silicon substrate 110) of the back passivation contact structure 140, without limitation.

[0062] A perovskite cell structure 200 is arranged on the basis of the front passivation contact structure 130 , including an electron transport layer 210 , a light absorption layer 220 , a hole transport layer 230 and a front metal electrode 240 arranged in sequence from the silicon substrate 110 to a direction away from the silicon substrate 110 .

[0063] The electron transport layer 210 (ETL) is mainly responsible for transporting electrons and inhibiting electron backflow. The electron transport layer 210 is composed of two layers of materials: dense TiO2 (titanium dioxide) and mesoporous TiO2. Among them, dense TiO2 is used to prevent direct contact between the substrate (here is the TOPCon battery structure 100) and the perovskite to avoid the transmission of holes to the substrate; mesoporous TiO2 provides a framework and support for the growth of perovskite, forming a porous TiO2 / perovskite mixed layer for transporting electrons. In the preparation process, the ETL material is first coated on the substrate, and then subjected to high-temperature treatment to form a good electron transmission channel.

[0064] The light absorbing layer 220 refers to the perovskite light absorbing layer 220, which is mainly responsible for absorbing sunlight and converting it into charge carriers. Perovskite materials usually use materials such as organic lead halides or all-inorganic lead halides, and a typical representative is lead iodide methylamine (CH3NH3Pbl3). These materials can absorb sunlight, generate photoelectrons, and realize photoelectric conversion.

[0065] The hole transport layer 230 (HTL) is mainly responsible for extracting and transporting photogenerated holes and inhibiting hole backflow. Commonly used HTL materials include Spiro-OMeTAD (Chinese name: 2,2',7,7'-tetra-N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene) and the like. In the preparation process, the HTL material is first coated on the electron transport layer 210 (ETL), and then heat-treated or photo-treated to form a good hole transport channel for extracting and transporting photogenerated holes.

[0066] The front metal electrode 240 is mainly responsible for transferring charges and connecting to an external circuit. It is made by evaporating a layer of gold, silver or aluminum on the outside of the hole transport layer 230. For example, the metal material is deposited on the HTL by vacuum evaporation or sputtering to form a transparent and conductive electrode film. It is then heat-treated or light-treated to optimize the electrode performance and improve the photoelectric conversion efficiency of the battery.

[0067] The stacked cell of the present application includes a TOPCon cell structure 100 as a bottom cell and a perovskite cell structure 200 as a top cell, wherein the TOPCon cell structure 100 includes a silicon substrate 110, a boron-doped layer 120, at least one front passivation contact structure 130, at least one back passivation contact structure 140 and a back metal electrode 150; the boron-doped layer 120 is arranged on the front side of the silicon substrate 110; at least one front passivation contact structure 130 is stacked on the boron-doped layer 120, and the front passivation contact structure 130 includes a first silicon oxide layer 131 and a first doping layer 132 sequentially arranged in a direction from the silicon substrate 110 to away from the silicon substrate 110; at least one back passivation contact structure 140 is stacked on the back side of the silicon substrate 110, and the back passivation contact structure 140 includes a first silicon oxide layer 131 and a first doping layer 132 sequentially arranged in a direction from the silicon substrate 110 to away from the silicon substrate 110; A second silicon oxide layer 141 and a second doped layer 142 are sequentially arranged from the silicon substrate 110 to a direction away from the silicon substrate 110, and a back metal electrode 150 is connected to the second doped layer 142; the perovskite battery structure 200 includes an electron transport layer 210, a light absorption layer 220, a hole transport layer 230 and a front metal electrode 240 sequentially arranged on the outermost first doped layer 132, and can be well compatible with the existing mainstream TOPCon battery production line, thereby reducing the preparation cost of the stacked battery; in addition, during the preparation process, the front passivation contact structure 130 can be directly prepared on the boron doped layer 120, which reduces the process steps and reduces the preparation cost, and the front passivation contact structure 130 and the back passivation contact structure 140 can be prepared and formed at the same time without setting a mask, thereby simplifying the preparation process and improving the preparation efficiency.

[0068] In some optional embodiments, the boron doped layer 120 is disposed in a local region of the front surface.

[0069] In implementation, the boron doped layer 120 may be full surface or regional contact, that is, the boron doped layer 120 may be disposed on the entire front surface of the silicon substrate 110, such as Figure 3 As shown, it can also be set in a partial area of ​​the front side of the silicon substrate 110, such as Figure 5 The width of the boron doped layer 120 is 20 microns to 2000 microns, for example, the width of the boron doped layer 120 is 40 microns, 50 microns, 200 microns, 700 microns or 1500 microns, etc., without limitation, and the boron doped layer 120 is disposed below the front passivation contact structure 130. Through such a configuration, the surface recombination of the non-contact area can be effectively reduced, and the battery efficiency can be improved.

[0070] In some optional embodiments, when the boron-doped layer 120 is arranged in a local area of ​​the front side, at least two boron-doped layers 120 may be arranged, and the distance between two adjacent boron-doped layers 120 is 100 microns-5000 microns. For example, the distance between two adjacent boron-doped layers 120 is 200 microns, 700 microns, 900 microns, 3000 microns or 3500 microns, etc., without limitation.

[0071] In some optional embodiments, the edge of the front passivation contact structure 130 is opposite to or staggered with the edge of the boron doped layer 120, wherein one side edge of the front passivation contact structure 130 may be opposite to or staggered with one side edge of the boron doped layer 120, and similarly, the other side edge of the front passivation contact structure 130 may be opposite to or staggered with the other side edge of the boron doped layer 120. Exemplarily, when each edge of the front passivation contact structure 130 is opposite to the edge of the boron doped layer 120, the shape and size of the front passivation contact structure 130 and the boron doped layer 120 are the same.

[0072] In other embodiments, when any edge of the front passivation contact structure 130 is misaligned with the edge of the boron doped layer 120, it indicates that the front passivation contact structure 130 and the boron doped layer 120 are not completely the same. For example, the front passivation contact structure 130 may be disposed in a local area of ​​the boron doped layer 120, that is, the front passivation contact structure 130 is smaller than the boron doped layer 120, such as Figure 4 As shown, through the above arrangement, contact recombination can be effectively reduced.

[0073] In some possible embodiments, the width of the boron-doped layer 120 is smaller than that of the front passivation contact structure 130 . Through the above configuration, the width of the boron-doped layer 120 is smaller, thereby reducing contact recombination.

[0074] In some optional embodiments, the stacked battery provided in the present application further includes a back passivation film 160 , which is disposed on a side of the second doping layer 142 away from the second silicon oxide layer 141 , and the back metal electrode 150 passes through the back passivation film 160 and is connected to the second doping layer 142 .

[0075] The back passivation film 160 is a passivation film, which is used to improve the photoelectric conversion efficiency and stability of the solar cell, reduce surface damage and oxidation reaction of the solar cell, and extend the service life of the solar cell.

[0076] In some possible embodiments, the passivation film includes at least one of silicon nitride, aluminum oxide, silicon oxynitride and silicon oxide, etc., without limitation. Preferably, the back passivation film 160 may be made of aluminum oxide to ensure light absorption rate.

[0077] Optionally, the back passivation film 160 may be provided with an opening, and the back metal electrode 150 passes through the opening of the back passivation film 160 and is connected to the second doping layer 142. In other possible embodiments, the back passivation film 160 is not provided with an opening, and the back passivation film 160 is burned through by molten metal slurry and connected to the second doping layer 142, and the metal slurry is cooled and solidified to form the back metal electrode 150.

[0078] In some optional embodiments, the stacked battery provided in the present application also includes a front passivation film 170, which is arranged on the side of the first doping layer 132 away from the first silicon oxide layer 131. The battery preparation method and function of the front passivation film 170 can refer to the above-mentioned back passivation film 160 and will not be elaborated.

[0079] In some optional embodiments, the front and / or back of the silicon substrate 110 is a polished surface or a velvet surface. Generally, before the silicon substrate 110 is subjected to the boron diffusion process, the silicon substrate 110 may be polished or velvet-treated. Among them, the polishing process of the silicon substrate 110 may be performed by mechanical polishing, chemical mechanical polishing, electrochemical polishing, photocatalytic assisted chemical mechanical polishing, etc., in order to enhance the polishing effect, improve the surface roughness of the silicon substrate 110, and increase the material removal rate. The velvet treatment refers to the use of a specific process (such as a chemical wet process) to process the front and / or back of the silicon substrate 110 to form a pyramid-shaped velvet surface on the front and / or back. The light trapping principle of the velvet surface is used. When light is incident on a certain angle of the inclined surface, the light will be reflected to another angle of the inclined surface, forming secondary or multiple absorption, thereby increasing the absorption rate, reducing the reflectivity of light, and increasing the short-circuit current, thereby improving the photoelectric conversion efficiency.

[0080] In some optional embodiments, a TCO layer (not shown) is disposed on the side of the hole transport layer 230 away from the light absorbing layer 220 , that is, a TCO layer is disposed between the hole transport layer 230 and the front metal electrode 240 .

[0081] The TCO (Transparent conducting oxide) layer is a transparent conductive oxide film uniformly plated on the hole transport layer 230 by physical or chemical plating methods, and plays a role in collecting current.

[0082] During implementation, the TCO layer mainly includes oxides of In (indium), Sn (tin), Zn (zinc) and Cd (cadmium) and their composite multi-oxide thin film materials. For example, the TCO layer can be made of IZO (indium zinc oxide), ITO (tin-doped indium oxide), IWO (tungsten-doped indium oxide) or IZrO (zirconium-doped indium oxide), etc., without limitation.

[0083] In some optional embodiments, an anti-reflection layer (not shown) is disposed on one side of the TCO layer away from the hole transport layer 230. In implementation, the anti-reflection layer is an anti-reflection film disposed on the TCO layer. The anti-reflection film is also called an anti-reflection film, which is used to reduce or eliminate reflected light, thereby increasing the amount of light transmitted, and further improving the conversion efficiency of the battery.

[0084] Optionally, the anti-reflection layer may be made of LiFx (lithium fluoride) or MgFx (magnesium fluoride) or other film layers that reduce light reflection and increase light transmittance. For example, the anti-reflection layer may also be composed of at least one layer of a silicon nitride layer, a silicon oxynitride layer and a silicon oxide layer, without limitation.

[0085] In some optional embodiments, a first interface passivation layer (not shown) is provided between the electron transport layer 210 and the light absorbing layer 220. Optionally, a second interface passivation layer (not shown) is provided between the light absorbing layer 220 and the hole transport layer 230. In implementation, the first interface passivation layer and the second interface passivation layer are both a layer of passivation coating, and the passivation coating includes titanium dioxide (TiO2), aluminum oxide (Al2O3) and ferric oxide (Fe2O3), etc., without limitation. This layer of passivation coating can reduce the reflectivity and surface roughness of the battery and improve the photoelectric conversion efficiency of the battery.

[0086] Embodiment 2

[0087] In some optional embodiments, the present application provides a photovoltaic module, comprising the stacked cell as described above.

[0088] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the structure and implementation principle of the photovoltaic assembly described above can refer to the corresponding structure and implementation principle in the aforementioned embodiment 1, and will not be repeated here.

[0089] The stacked cell of the present application includes a TOPCon cell structure 100 as a bottom cell and a perovskite cell structure 200 as a top cell, wherein the TOPCon cell structure 100 includes a silicon substrate 110, a boron-doped layer 120, at least one front passivation contact structure 130, at least one back passivation contact structure 140 and a back metal electrode 150; the boron-doped layer 120 is arranged on the front side of the silicon substrate 110; at least one front passivation contact structure 130 is stacked on the boron-doped layer 120, and the front passivation contact structure 130 includes a first silicon oxide layer 131 and a first doping layer 132 sequentially arranged in a direction from the silicon substrate 110 to away from the silicon substrate 110; at least one back passivation contact structure 140 is stacked on the back side of the silicon substrate 110, and the back passivation contact structure 140 includes a first silicon oxide layer 131 and a first doping layer 132 sequentially arranged in a direction from the silicon substrate 110 to away from the silicon substrate 110; A second silicon oxide layer 141 and a second doped layer 142 are sequentially arranged from the silicon substrate 110 to a direction away from the silicon substrate 110, and a back metal electrode 150 is connected to the second doped layer 142; the perovskite battery structure 200 includes an electron transport layer 210, a light absorption layer 220, a hole transport layer 230 and a front metal electrode 240 sequentially arranged on the outermost first doped layer 132, and can be well compatible with the existing mainstream TOPCon battery production line, thereby reducing the preparation cost of the stacked battery; in addition, during the preparation process, the front passivation contact structure 130 can be directly prepared on the boron doped layer 120, which reduces the process steps and reduces the preparation cost, and the front passivation contact structure 130 and the back passivation contact structure 140 can be prepared and formed at the same time without setting a mask, thereby simplifying the preparation process and improving the preparation efficiency.

[0090] Optionally, taking a front passivation contact structure 130 and a back passivation contact structure 140 as an example, Figure 6 As shown, the preparation process of the laminated battery provided in this application includes the following steps:

[0091] ①. Clean the silicon substrate 110 first, and then perform texturing or polishing on the silicon substrate 110; ②. Perform boron diffusion on the texturing or polishing silicon substrate 110 to generate a boron-doped layer 120 and BSG on both the front and back sides of the silicon substrate 110; ③. Remove the back side boron-doped layer 120 and the front and back side BSG; ④. Then perform a front and back high-temperature n-poly process using PECVD or LPCVD to form a back side SiOx / n-poly passivation contact, and form a tunnel junction passivation contact with a full surface n-poly / SiOx / boron-doped layer 120 on the front side.

[0092] During implementation, when performing the high-temperature n-poly process on the front side, the front passivation contact structure 130 can be directly prepared on the boron-doped layer 120, without the need to use a mask, thereby reducing the process flow and controlling costs. In addition, the front n-poly process and the back n-poly process can be performed simultaneously or separately. Preferably, the front n-poly process and the back n-poly process can be performed simultaneously, that is, the front passivation contact structure 130 and the back passivation contact structure 140 can be prepared in one step, further simplifying the preparation process.

[0093] After the n-poly process, ⑤, remove the BSG on the front and back sides and then perform RCA cleaning.

[0094] When implemented, the RCA cleaning method mainly includes two steps:

[0095] SC1 cleaning: This is an alkaline solution, the main purpose of which is to remove particles, metals and organic matter. Through the strong oxidizing effect of hydrogen peroxide and the alkaline corrosion effect of ammonium hydroxide, particles and organic pollutants on the surface of silicon wafers can be effectively removed.

[0096] SC2 cleaning: This is an acidic solution, the main function of which is to remove metal ions. The metal impurities on the surface of the wafer can be removed through the oxidation of hydrogen peroxide and the acid corrosion of hydrochloric acid.

[0097] In addition, the RCA cleaning method also includes several other cleaning solutions, such as a mixture of H2SO4+H2O2 (sulfuric acid plus hydrogen peroxide) for removing metals and organic matter, and diluted hydrofluoric acid for removing oxide films on the surface of silicon wafers. The order and conditions of using these cleaning solutions are selected according to specific cleaning requirements and material properties, and are not limited.

[0098] In order to improve the effect of RCA cleaning, it can also be combined with megasonic cleaning technology. Megasonic cleaning uses high-frequency sound waves in liquid media to generate tiny cavitation bubbles. When these bubbles burst, local shock waves are generated, thereby effectively removing pollutants on the surface of silicon wafers. The above combined method can ensure the cleanliness of silicon wafers.

[0099] After RCA cleaning, ⑥, a back passivation film 160 is deposited, and a grid line (back metal electrode 150) is screen-printed to obtain a TOPCon battery structure 100, ⑦, and then a perovskite battery is prepared, ⑧, and a front metal electrode 240 is printed to obtain a laminated battery structure as shown in FIG. Figure 3 shown.

[0100] It should be noted that the perovskite cell and the printed front metal electrode 240 can be prepared by the above-mentioned cell preparation method, or by a solvent thermal method, a spin coating method or a vapor deposition method, etc., which will not be described in detail.

[0101] In some possible embodiments, light injection and laser enhanced contact processing can be performed after screen printing and grid line sintering. After the light injection, laser irradiation is used while applying a reverse bias current to optimize the paste contact.

[0102] In some possible embodiments, taking the local setting of the boron-doped layer 120 as an example, the preparation process of the stacked battery provided in the present application includes the following steps:

[0103] The silicon substrate 110 is cleaned. The silicon substrate 110 adopts a P-type silicon wafer, and then the silicon substrate 110 is textured or polished. Boron is diffused on the silicon substrate 110 after the texture or polishing process to generate a boron-doped layer 120 and BSG on both the front and back sides of the silicon substrate 110; the back boron-doped layer 120 and the front and back BSG are removed; then a high-temperature n-poly process is performed on the front and back sides, and a local n-poly / SiOx / boron-doped layer 120 tunneling junction passivation contact is formed on the front side by patterning the front n-poly / SiOx / boron-doped layer 120, that is, a local n-poly / SiOx / boron-doped layer 120 tunneling junction passivation contact is formed below the front metal electrode 240 where it is necessary to set up, and a back n-poly passivation contact is formed at the same time, and the BSG is removed and then RCA cleaning is performed;

[0104] The RCA cleaning process and principle refer to the above-mentioned embodiment and will not be described in detail.

[0105] After RCA cleaning, a passivation film is deposited on the back side, and the grid line (back metal electrode 150) is screen printed to obtain a TOPCon cell structure 100. Then, a perovskite cell is prepared and a front metal electrode 240 is printed. The obtained stacked cell structure is as follows: Figure 4 or Figure 5 shown.

[0106] In some possible embodiments, light injection and laser enhanced contact processing can be performed after screen printing and grid line sintering.

[0107] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the structure and implementation principle of the laminated battery described above can refer to the corresponding structure and implementation principle in the aforementioned embodiments 1 and 2, and will not be repeated here.

[0108] The stacked cell of the present application includes a TOPCon cell structure 100 as a bottom cell and a perovskite cell structure 200 as a top cell, wherein the TOPCon cell structure 100 includes a silicon substrate 110, a boron-doped layer 120, at least one front passivation contact structure 130, at least one back passivation contact structure 140 and a back metal electrode 150; the boron-doped layer 120 is arranged on the front side of the silicon substrate 110; at least one front passivation contact structure 130 is stacked on the boron-doped layer 120, and the front passivation contact structure 130 includes a first silicon oxide layer 131 and a first doping layer 132 sequentially arranged in a direction from the silicon substrate 110 to away from the silicon substrate 110; at least one back passivation contact structure 140 is stacked on the back side of the silicon substrate 110, and the back passivation contact structure 140 includes a first silicon oxide layer 131 and a first doping layer 132 sequentially arranged in a direction from the silicon substrate 110 to away from the silicon substrate 110; A second silicon oxide layer 141 and a second doped layer 142 are sequentially arranged from the silicon substrate 110 to a direction away from the silicon substrate 110, and a back metal electrode 150 is connected to the second doped layer 142; the perovskite battery structure 200 includes an electron transport layer 210, a light absorption layer 220, a hole transport layer 230 and a front metal electrode 240 sequentially arranged on the outermost first doped layer 132, and can be well compatible with the existing mainstream TOPCon battery production line, thereby reducing the preparation cost of the stacked battery; in addition, during the preparation process, the front passivation contact structure 130 can be directly prepared on the boron doped layer 120, which reduces the process steps and reduces the preparation cost, and the front passivation contact structure 130 and the back passivation contact structure 140 can be prepared and formed at the same time without setting a mask, thereby simplifying the preparation process and improving the preparation efficiency.

[0109] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A laminated battery, characterized in that: Including a TOPCon cell structure as a bottom cell and a perovskite cell structure as a top cell; The TOPCon cell structure comprises a silicon substrate, a boron doped layer, at least one front passivation contact structure, at least one back passivation contact structure and a back metal electrode; The boron doped layer is arranged on the front side of the silicon substrate; At least one layer of the front passivation contact structure is stacked on the boron doped layer, and the front passivation contact structure includes a first silicon oxide layer and a first doped layer sequentially arranged in a direction away from the silicon substrate; At least one layer of the back passivation contact structure is stacked on the back side of the silicon substrate, the back passivation contact structure comprises a second silicon oxide layer and a second doped layer sequentially arranged in a direction away from the silicon substrate, and the back metal electrode is connected to the second doped layer; The perovskite cell structure includes an electron transport layer, a light absorption layer, a hole transport layer and a front metal electrode which are sequentially arranged on the outermost first doping layer.

2. The stacked battery according to claim 1, characterized in that: The silicon substrate includes any one of a P-type silicon wafer and an N-type silicon wafer.

3. The stacked battery according to claim 1, characterized in that: The boron doped layer is disposed in a local area of ​​the front surface.

4. The stacked battery according to claim 3, characterized in that: The width of the boron doped layer is 20 micrometers to 2000 micrometers.

5. The laminated battery according to claim 3 or 4, characterized in that: At least two boron-doped layers are disposed on the front surface, and the distance between two adjacent boron-doped layers is 100 micrometers to 5000 micrometers.

6. The laminated battery according to claim 1 or 2, characterized in that: The edge of the front passivation contact structure is directly opposite to or staggered from the edge of the boron doping layer.

7. The stacked battery according to claim 6, characterized in that: The width of the boron doped layer is smaller than the width of the front passivation contact structure.

8. The laminated battery according to claim 1, characterized in that: The first doping layer and the second doping layer have the same polarity.

9. The laminated battery according to claim 1, characterized in that: The stacked battery further includes a back passivation film, which is disposed on a side of the second doped layer away from the second silicon oxide layer, and the back metal electrode passes through the back passivation film and is connected to the second doped layer.

10. The laminated battery according to claim 9, characterized in that: The back passivation film includes at least one of silicon nitride, aluminum oxide, silicon oxynitride and silicon oxide.

11. The stacked battery according to claim 1, characterized in that: The front side and / or the back side of the silicon substrate is a polished surface or a velvet surface.

12. The stacked battery according to claim 1, characterized in that: A TCO layer is disposed on a side of the hole transport layer away from the light absorbing layer.

13. The stacked battery according to claim 12, characterized in that: An anti-reflection layer is disposed on a side of the TCO layer away from the hole transport layer.

14. The stacked battery according to claim 1, characterized in that: A first interface passivation layer is disposed between the electron transport layer and the light absorbing layer.

15. The laminated battery according to claim 1 or 14, characterized in that: A second interface passivation layer is disposed between the light absorbing layer and the hole transport layer.

16. A photovoltaic module, characterized in that: Comprising the stacked battery according to any one of claims 1 to 15.

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