Boundary scanning test equipment

Abstract

The utility model discloses boundary scan test equipment, which comprises a boundary scan chain, a first FPGA chip, a second FPGA chip and a USB interface chip, and is characterized in that the USB interface chip is electrically connected with the first FPGA chip through the boundary scan chain and is used for sending a first test signal to the first FPGA chip through the boundary scan chain; the first FPGA chip is electrically connected with the second FPGA chip; the USB interface chip is electrically connected with the second FPGA chip through the boundary scan chain and used for reading a first state signal sent by the second FPGA chip through the boundary scan chain, and the first state signal corresponds to the first test signal; and the combination of the first state signal and the first test signal is used for indicating that the circuit connection state between the first FPGA chip and the second FPGA chip is a closed circuit, a short circuit or an open circuit.

Description

Technical Field

[0001] The present application relates to the field of scan testing technology, and in particular to a boundary scan testing device. Background Art

[0002] With the gradual expansion of the domestic server and chip markets, server stability and reliability have become key indicators for evaluating server quality. As key server components, the motherboard, memory, and hard disks have a crucial impact on server stability and reliability. Consequently, performance testing of these components has become a core technology in server production.

[0003] Currently, the testing technology for chips on circuits has transitioned from conventional testing methods such as flying probe testing and online testing to a testing method called boundary scan.

[0004] Boundary scan technology is widely used for testing large-scale, highly integrated chip-level circuits and plays a crucial role in the automated testing of high-density, multi-layer server motherboards and peripheral devices such as high-speed memory modules and solid-state drives. However, due to a lack of relevant testing technology in China for server testing and high-density digital chip testing, there has been a lack of boundary scan testing equipment capable of detecting the connection status between FPGA chips, identifying faults in these connections, and adapting it for teaching and practical applications.

[0005] With respect to the technical problem in the above-mentioned prior art that there is currently a lack of a boundary scan test device that can detect the connection status between FPGA chips, identify connection failures between FPGA chips, and be used for teaching and practice, no effective solution has been proposed yet. Utility Model Content

[0006] The utility model provides a boundary scan test device to at least solve the technical problem in the prior art that there is currently a lack of a boundary scan test device that can detect the connection status between FPGA chips, identify connection faults between FPGA chips, and be used for teaching and practice.

[0007] According to one aspect of the present application, a boundary scan test device is provided, including: a boundary scan chain, a first FPGA chip, a second FPGA chip and a USB interface chip, wherein the USB interface chip is electrically connected to the first FPGA chip through the boundary scan chain, and is used to send a first test signal to the first FPGA chip through the boundary scan chain; the first FPGA chip and the second FPGA chip are electrically connected; and the USB interface chip is electrically connected to the second FPGA chip through the boundary scan chain, and is used to read a first status signal sent by the second FPGA chip through the boundary scan chain, wherein the first status signal corresponds to the first test signal, and the combination of the first status signal and the first test signal is used to indicate that the circuit connection status between the first FPGA chip and the second FPGA chip is open, short circuit or open circuit.

[0008] Optionally, it also includes: an ARM processor, wherein the USB interface chip is electrically connected to the ARM processor through a boundary scan chain, and is used to send a second test signal to the ARM processor through the boundary scan chain; the ARM processor is electrically connected to the first FPGA chip; and the USB interface chip is also used to read a second status signal from the first FPGA chip, wherein the second status signal corresponds to the second test signal, and the combination of the second status signal and the second test signal is used to indicate that the circuit connection status between the ARM processor and the first FPGA chip is open, short circuit or open circuit.

[0009] Optionally, it also includes: a circuit network component, wherein the circuit network component is connected to the first FPGA chip and the second FPGA chip respectively.

[0010] Optionally, the circuit network component includes: a resistor network, a capacitor network, a resistor-capacitor hybrid network and / or a differential network.

[0011] Optionally, it also includes: a first digital display tube connected to the first FPGA chip.

[0012] Optionally, it also includes: a second digital display tube connected to the second FPGA chip.

[0013] Optionally, it further includes: a power supply component connected to the first FPGA chip, the second FPGA chip, the first digital display tube, the second digital display tube and the ARM processor respectively.

[0014] Optionally, the power supply component includes: a power supply and a voltage conversion module connected to the power supply, wherein the voltage conversion module is used to convert the voltage of the power supply into a voltage suitable for the first FPGA chip, the second FPGA chip, the first digital display tube, the second digital display tube and the ARM processor.

[0015] Optionally, the voltage conversion module is a DC-DC converter.

[0016] Optionally, it further includes: a USB interface, wherein the USB interface chip is connected to the terminal device via the USB interface.

[0017] The present application provides a boundary scan test device. The boundary scan test device includes a boundary scan chain, a first FPGA chip, a second FPGA chip, and a USB interface chip. The USB interface chip is connected to the first FPGA chip via the boundary scan chain. The first FPGA chip is connected to the second FPGA chip. The USB interface chip is electrically connected to the second FPGA chip via the boundary scan chain. Thus, after receiving a signal generation instruction, the USB interface chip sends a first test signal to the first FPGA chip via the boundary scan chain. Then, the first FPGA chip sends the first test signal to the second FPGA chip. Thus, the USB interface chip can read the first status signal sent by the second FPGA chip via the boundary scan chain, and finally send the first status signal and the first test signal to the terminal device. The combination of the first status signal and the first test signal is used to indicate whether the circuit connection status between the first FPGA chip and the second FPGA chip is open, short circuit, or open circuit.

[0018] Therefore, in the technical solution disclosed in the present application, the first FPGA chip and the second FPGA chip are set as test objects in the boundary scan test equipment. And after the first test signal sent by the USB interface chip passes through the first FPGA chip and the second FPGA chip, the combination of the generated first state signal and the first test signal can indicate whether there is a fault between the first FPGA chip and the second FPGA chip (that is, there is a path, a short circuit or an open circuit between the first FPGA chip and the second FPGA chip), thereby being able to monitor the circuit connection state between the first FPGA chip and the second FPGA chip. In addition, the operator can simulate the electrical connection state (that is, the path connection state, the short circuit connection state and the open circuit connection state) of the first FPGA chip and the second FPGA chip by manually adjusting the connection state of each component on the circuit network component, which is convenient for the operator to use in teaching and practice.

[0019] This solves the technical problem in the prior art of the lack of a boundary scan test device that can detect the connection status between FPGA chips, identify connection faults between FPGA chips, and be used for teaching and practice.

[0020] Based on the detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings below, those skilled in the art will become more aware of the above and other purposes, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Hereinafter, some specific embodiments of the present application will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0022] Figure 1 1 is a schematic diagram of the overall structure of a boundary scan test device according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of a boundary scan chain according to an embodiment of the present application;

[0024] Figure 3A is a schematic diagram of a resistor network according to an embodiment of the present application;

[0025] Figure 3B is a schematic diagram of a capacitor network according to an embodiment of the present application;

[0026] Figure 3C is a schematic diagram of a resistor-capacitor hybrid network according to an embodiment of the present application; and

[0027] Figure 3D Schematic diagram of a differential network according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] In order to help those skilled in the art better understand the present invention, the following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first," "second," and the like in the specification and claims of the present invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present invention described herein. In addition, the terms "including" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatuses.

[0031] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0032] Figure 1 1 is a schematic diagram of the overall structure of a boundary scan test device according to an embodiment of the present application; Figure 2 FIG is a schematic diagram of a boundary scan chain 10 according to an embodiment of the present application. Figure 1 and Figure 2 As shown, the present application provides a boundary scan test device, including: a boundary scan chain 10, a first FPGA chip 210, a second FPGA chip 220 and a USB interface chip 310, wherein the USB interface chip 310 is electrically connected to the first FPGA chip 210 through the boundary scan chain 10, and is used to send a first test signal to the first FPGA chip 210 through the boundary scan chain 10; the first FPGA chip 210 and the second FPGA chip 220 are electrically connected; and the USB interface chip 310 is electrically connected to the second FPGA chip 220 through the boundary scan chain 10, and is used to read a first state signal sent by the second FPGA chip 220 through the boundary scan chain 10, wherein the first state signal corresponds to the first test signal, and the combination of the first state signal and the first test signal is used to indicate that the circuit connection state between the first FPGA chip 210 and the second FPGA chip 220 is open, short circuit or open circuit.

[0033] As described in the background technology, the current testing technology for chips on circuits has transitioned from conventional testing methods such as flying probe testing and in-circuit testing to a test method called boundary scan. Boundary scan technology is widely used for large-scale, highly integrated chip-level circuit testing and plays an important role in the automated testing of high-density multi-layer server motherboards and peripheral high-speed memory sticks, solid-state drives, and other devices. However, due to the lack of relevant testing technology in the field of server testing and high-density digital chip testing in China, there has been no boundary scan test equipment that can detect the connection status between FPGA chips, identify connection faults between FPGA chips, and be used for teaching and practical applications.

[0034] In view of this, the present application provides a boundary scan test device, which includes a boundary scan chain 10 , a first FPGA chip 210 , a second FPGA chip 220 , and a USB interface chip 310 .

[0035] The USB interface chip 310 is electrically connected to the first FPGA chip 210 via the boundary scan chain 10. The first FPGA chip 210 is electrically connected to the second FPGA chip 220. The USB interface chip 310 is electrically connected to the second FPGA chip 220 via the boundary scan chain 10.

[0036] Thus, after receiving the signal generation instruction sent by the terminal device through the USB interface 320, the USB interface chip 310 generates a first test signal and sends the first test signal to the first FPGA chip 210 through the boundary scan chain 10. The first test signal is a bit digital signal.

[0037] Then, the first FPGA chip 210 sends the first test signal to the second FPGA chip 220, and the second FPGA chip 220 generates a corresponding first state signal. The first state signal corresponds to the first test signal, and the first state signal can be one of a plurality of different modes.

[0038] Furthermore, the USB interface chip 310 reads the first status signal through the boundary scan chain 10 and sends the first test signal and the first status signal to the terminal device. Thus, an operator can determine the circuit connection status between the first FPGA chip 210 and the second FPGA chip 220 through the terminal device based on the first status signal and the first test signal.

[0039] Furthermore, by combining the first state signal and the first test signal and performing vector analysis, the circuit connection state between the first FPGA chip 210 and the second FPGA chip 220 can be obtained. The circuit connection state between the first FPGA chip 210 and the second FPGA chip 220 is a connection, a short circuit, or an open circuit.

[0040] For example, the first test signal output by the first FPGA chip 210 is combined with the first state signal output by the second FPGA chip 220, and vector analysis is performed. If the first state signal and the first test signal exhibit the characteristics of a digital logic "AND signal," it can be determined that the circuit connection between the first FPGA chip 210 and the second FPGA chip 220 is a short circuit.

[0041] For another example, the first test signal output by the first FPGA chip 210 is combined with the first state signal output by the second FPGA chip 220, and vector analysis is performed. If the first state signal and the first test signal exhibit characteristics of a digital logic "OR signal," it can be determined that the circuit connection between the first FPGA chip 210 and the second FPGA chip 220 is open.

[0042] For another example, the first test signal output by the first FPGA chip 210 is combined with the first state signal output by the second FPGA chip 220, and vector analysis is performed. If the first state signal exhibits the same digital logic characteristics as the first test signal, the circuit connection between the first FPGA chip 210 and the second FPGA chip 220 can be determined to be a path.

[0043] Therefore, in the technical solution disclosed in this application, the first FPGA chip 210 and the second FPGA chip 220 are set as test objects in the boundary scan test equipment. And after the first test signal sent by the USB interface chip 310 passes through the first FPGA chip 210 and the second FPGA chip 220, the combination of the generated first state signal and the first test signal can indicate whether there is a fault between the first FPGA chip 210 and the second FPGA chip 220 (that is, whether there is a path, a short circuit, or an open circuit between the first FPGA chip 210 and the second FPGA chip 220). Therefore, in the above situation, the operator can simulate the electrical connection state (that is, the path connection state, the short circuit connection state, and the open circuit connection state) of the first FPGA chip 210 and the second FPGA chip 220 by manually adjusting the connection state of each component on the circuit network component, thereby facilitating the operator's use in teaching and practice.

[0044] This solves the technical problem in the prior art of the lack of a boundary scan test device that can detect the connection status between FPGA chips, identify connection faults between FPGA chips, and be used for teaching and practice.

[0045] Preferably, the first FPGA chip 210 and the second FPGA chip 220 are Anlu Technology EF2L45LG144, which supports LVDS interface and CMOS level interface. The USB interface chip 310 is Nanjing Qinheng high-speed interface chip CH347.

[0046] Furthermore, those skilled in the art should understand that in this embodiment, the first FPGA chip 210 receives the first test signal and the second FPGA chip 220 outputs the first state signal, but the actual situation is not limited to this. For example, the second FPGA chip 220 may receive the first test signal and the first FPGA chip 210 may output the first state signal.

[0047] Optionally, it also includes: an ARM processor 40, wherein the USB interface chip 310 is electrically connected to the ARM processor 40 through the boundary scan chain 10, and is used to send a second test signal to the ARM processor 40 through the boundary scan chain 10; the ARM processor 40 is electrically connected to the first FPGA chip 210; and the USB interface chip 310 is also used to read a second status signal from the first FPGA chip 210, wherein the second status signal corresponds to the second test signal, and the combination of the second status signal and the second test signal is used to indicate that the circuit connection status between the ARM processor 40 and the first FPGA chip 210 is open, short circuit or open circuit.

[0048] Specifically, refer to Figure 1 and Figure 2 As shown, the boundary scan test device further includes an ARM processor 40. The USB interface chip 310 is electrically connected to the ARM processor 40 via the boundary scan chain 10. The pins of the ARM processor 40 and the first FPGA chip 210 are directly connected.

[0049] Thus, after receiving the signal generation instruction sent by the terminal device, the USB interface chip 310 sends the second test signal to the ARM processor 40. After receiving the second test signal, the ARM processor 40 sends the second test signal to the first FPGA chip 210, so that the first FPGA chip 210 can generate a second status signal. The second status signal corresponds to the second test signal, and the combination of the second status signal and the second test signal is used to indicate whether the circuit connection state between the ARM processor 40 and the first FPGA chip 210 is open, short, or open.

[0050] The USB interface chip 310 then reads the second status signal through the boundary scan chain 10 and sends the second status signal to the terminal device. Thus, an operator can use the terminal device to perform vector analysis on the combination of the second status signal and the second test signal to determine the circuit connection status between the ARM processor 40 and the first FPGA chip 210.

[0051] Therefore, it can be seen from the above that the boundary scan test device disclosed in this application can not only test the circuit connection status between the first FPGA chip 210 and the second FPGA chip 220, but also test the circuit connection status between the ARM processor 40 and the first FPGA chip 210. Therefore, the boundary scan test device can also be used to teach or practice the connection fault between the ARM processor 40 and the first FPGA chip 210.

[0052] Preferably, the ARM processor 40 uses the TI single-chip microcomputer TM4C129 of the ARM model.

[0053] Furthermore, it is worth noting that the ARM processor 40 and the first FPGA chip 210 are directly connected, and no network component 50 is provided between the ARM processor 40 and the first FPGA chip 210. Therefore, the detection of the circuit connection status between the ARM processor 40 and the first FPGA chip 210 and the detection of the circuit connection status between the first FPGA chip 210 and the first FPGA chip 220 described above can reflect different circuit detection application scenarios.

[0054] In addition, reference Figure 2 As shown, the boundary scan chain 10 is actually a bus composed of TDI, TMS, TCK and TDO. Among them, the first FPGA chip 210, the second FPGA chip 220, the ARM processor 40 and the USB interface chip 310 are all provided with the above-mentioned TDI, TMS, TCK and TDO. TDI can send test signals, instructions or configuration information to the object under test (for example, the first FPGA chip 210, the second FPGA chip 220 and the ARM processor 40). TDO can obtain the test results, status information or output data of the object under test. TCK is used for synchronous transmission of display data. TMS is used to select different test or operation modes.

[0055] And among them, reference Figure 2As described above, the USB interface chip 310 outputs the first test signal through the set TDO and inputs it to the first FPGA chip 210 through the set TDI. The first FPGA chip 210 outputs the first test signal through the set TDO and inputs the first test signal to the second FPGA chip 220 through the set TDI. The second FPGA chip 220 generates a first status signal and outputs the first status signal through the set TDO. Thus, the USB interface chip 310 reads the first status signal through the set TDI.

[0056] Similarly, reference Figure 2 As shown, the USB interface chip 310 outputs the second test signal through the set TDO and inputs it to the ARM processor 40 through the set TDI. The ARM processor 40 outputs the second test signal through the set TDO and inputs the second test signal to the first FPGA chip 210 through the set TDI. The first FPGA chip 210 generates a second status signal and outputs the second status signal through the set TDO. The USB interface chip 310 thus reads the second status signal through the set TDI.

[0057] Optionally, the system further includes a circuit network component 50, wherein the circuit network component 50 is respectively connected to the first FPGA chip 210 and the second FPGA chip 220. Further optionally, the circuit network component 50 includes a resistor network 510, a capacitor network 520, a resistor-capacitor hybrid network 530, and / or a differential network 540.

[0058] Specifically, refer to Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D As shown, a circuit network component 50 is further provided between the first FPGA chip 210 and the second FPGA chip 220 .

[0059] Furthermore, the circuit network component 50 may include, for example, a resistor network 510, a capacitor network 520, a resistor-capacitor hybrid network 530, and / or a differential network 540. Thus, by adjusting the resistor network 510, the capacitor network 520, the resistor-capacitor hybrid network 530, and / or the differential network 540 in the circuit network component 50, the circuit connection state between the first FPGA chip 210 and the second FPGA chip 220 may be changed.

[0060] For example, if the circuit network assembly 50 includes a resistor network 510, the operator can adjust the resistance value of the resistor network 510 to 0, thereby causing a short circuit between the first FPGA chip 210 and the second FPGA chip 220. The operator can then use the boundary scan test equipment to demonstrate to students the testing process and test results when a short circuit occurs between the first FPGA chip 210 and the second FPGA chip 220.

[0061] Preferably, the resistor network 510 is a hybrid topology consisting of multiple resistors connected in series and in parallel. The capacitor network 520 is a hybrid topology consisting of multiple capacitors connected in series and in parallel. The resistor-capacitor hybrid network 530 is a hybrid topology consisting of resistors and capacitors connected in series and in parallel. The differential network 540 is a hybrid interface mode in which the input and output are combined in a series capacitor configuration.

[0062] Optionally, the system further includes: a first digital display tube 610 connected to the first FPGA chip 210 . Further optionally, the system further includes: a second digital display tube 620 connected to the second FPGA chip 220 .

[0063] Specifically, refer to Figure 1 As shown, the first FPGA chip 210 is further connected to a first digital display tube 610, and the second FPGA chip 220 is further connected to a second digital display tube 620. The operator can determine whether the first FPGA chip 210 is operating normally based on the first digital display tube 610, and can also determine whether the second FPGA chip 220 is operating normally based on the second digital display tube 620. For example, if the first digital display tube 610 displays a number normally, it indicates that the first FPGA chip 210 is operating normally; otherwise, the first FPGA chip 210 is not operating normally. If the second digital display tube 620 displays a number normally, it indicates that the second FPGA chip 220 is operating normally; otherwise, the second FPGA chip 220 is not operating normally.

[0064] In addition, the operator can also determine the test result of the first FPGA chip 210 through the first digital display tube 610 and the test result of the second FPGA chip 220 through the second digital display tube 620. That is, the operator can determine whether the circuit connection between the first FPGA chip 210 and the second FPGA chip 220 is open, short, or disconnected based on the numbers displayed on the first and second digital display tubes 610, 620. Furthermore, the first and second digital display tubes 610, 620 display two hexadecimal digits of data information.

[0065] Therefore, by setting a first digital display tube 610 connected to the first FPGA chip 210 and a second digital display tube 620 connected to the second FPGA chip 220 in the boundary scan test equipment, the technical effect of facilitating the operator to determine whether the first FPGA chip 210 and the second FPGA chip 220 are in a normal working state and to determine the circuit connection status between the first FPGA chip 210 and the second FPGA chip 220 is achieved.

[0066] Preferably, the first digital display tube 610 and the second digital display tube 620 adopt a 2-digit 7-segment type, with a diode voltage drop of 2V and a current of 5mA.

[0067] Optionally, the system further includes a power supply assembly 70 connected to the first FPGA chip 210, the second FPGA chip 220, the first digital display tube 610, the second digital display tube 620, and the ARM processor 40, respectively. Further optionally, the power supply assembly 70 includes a power supply 710 and a voltage conversion module 720 connected to the power supply 710, wherein the voltage conversion module 720 is configured to convert the voltage of the power supply 710 into a voltage suitable for the first FPGA chip 210, the second FPGA chip 220, the first digital display tube 610, the second digital display tube 620, and the ARM processor 40. Further optionally, the voltage conversion module 720 is a DC-DC converter.

[0068] Specifically, refer to Figure 1 As shown, the boundary scan test device is further provided with a power supply component 70. The power supply component 70 is respectively connected to the first FPGA chip 210, the second FPGA chip 220, the first digital display tube 610, the second digital display tube 620, and the ARM processor 40, thereby providing power to the first FPGA chip 210, the second FPGA chip 220, the first digital display tube 610, the second digital display tube 620, and the ARM processor 40.

[0069] The power supply assembly 70 includes a power supply 710 and a voltage conversion module 720 connected to the power supply 710. The voltage conversion module 720 can convert the voltage of the power supply 710 into a voltage suitable for use by the first FPGA chip 210, the second FPGA chip 220, the first digital display tube 610, the second digital display tube 620, and the ARM processor 40.

[0070] In addition, it is worth noting that the voltage conversion module in the present application can be, for example, a DC-DC converter. With a 5V input, the output XL1509 chip provides a 3.3V-2A operating current.

[0071] Thus, by setting a power supply component 70 including a power supply 710 and a voltage conversion module 720 in the boundary scan test equipment, and connecting the power supply component 70 to the first FPGA chip 210, the second FPGA chip 220, the first digital display tube 610, the second digital display tube 620 and the ARM processor 40 respectively, the technical effect of being able to supply power to the first FPGA chip 210, the second FPGA chip 220, the first digital display tube 610, the second digital display tube 620 and the ARM processor 40, and ensuring the normal operation of the first FPGA chip 210, the second FPGA chip 220, the first digital display tube 610, the second digital display tube 620 and the ARM processor 40 is achieved.

[0072] Optionally, the device further includes a USB interface 320, wherein the USB interface chip 310 is connected to a terminal device via the USB interface 320. Thus, an operator can use the peripheral terminal device and send a signal generation instruction to the USB interface chip 310 via the USB interface 320; and can also read the test results via the USB interface 320.

[0073] To sum up, this application can complete the testing of the ARM processor, the first FPGA chip and the second FPGA chip in accordance with the IEEE1149 standard, thereby being able to identify faults artificially set by the operator, thereby achieving the purpose of teaching and experimentation.

[0074] Unless otherwise specifically stated, the relative arrangement of the parts and steps, the numerical expressions and the numerical values ​​set forth in these embodiments do not limit the scope of the present invention. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship. The techniques, methods and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as part of the authorization specification. In all examples shown and discussed here, any specific values ​​should be interpreted as being merely exemplary and not as limitations. Therefore, other examples of the exemplary embodiments may have different values. It should be noted that similar numbers and letters represent similar items in the following figures, and therefore, once an item is defined in one figure, it does not need to be further discussed in subsequent figures.

[0075] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0076] In the description of the present invention, it needs to be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0077] The above description is merely a preferred embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A boundary scan test device, characterized in that: include: A boundary scan chain (10), a first FPGA chip (210), a second FPGA chip (220) and a USB interface chip (310), wherein The USB interface chip (310) is electrically connected to the first FPGA chip (210) via the boundary scan chain (10), and is used to send a first test signal to the first FPGA chip (210) via the boundary scan chain (10); The first FPGA chip (210) and the second FPGA chip (220) are electrically connected; The USB interface chip (310) is electrically connected to the second FPGA chip (220) via the boundary scan chain (10), and is used to read a first state signal sent by the second FPGA chip (220) via the boundary scan chain (10), wherein the first state signal corresponds to the first test signal, and a combination of the first state signal and the first test signal is used to indicate whether the circuit connection state between the first FPGA chip (210) and the second FPGA chip (220) is open, short or open.

2. The boundary scan test device according to claim 1, characterized in that: Also includes: ARM processor (40), wherein The USB interface chip (310) is electrically connected to the ARM processor (40) via the boundary scan chain (10), and is used to send a second test signal to the ARM processor (40) via the boundary scan chain (10); The ARM processor (40) is electrically connected to the first FPGA chip (210); and The USB interface chip (310) is also used to read a second status signal from the first FPGA chip (210), wherein the second status signal corresponds to the second test signal, and the combination of the second status signal and the second test signal is used to indicate whether the circuit connection state between the ARM processor (40) and the first FPGA chip (210) is open, short or open.

3. The boundary scan test device according to claim 2, characterized in that: Also includes: A circuit network component (50), wherein The circuit network component (50) is connected to the first FPGA chip (210) and the second FPGA chip (220) respectively.

4. The boundary scan test device according to claim 3, characterized in that: The circuit network component (50) includes: a resistor network (510), a capacitor network (520), a resistor-capacitor hybrid network (530) and / or a differential network (540).

5. The boundary scan test device according to claim 4, characterized in that: Also includes: A first digital display tube (610) connected to the first FPGA chip (210).

6. The boundary scan test device according to claim 5, characterized in that: Also includes: A second digital display tube (620) connected to the second FPGA chip (220).

7. The boundary scan test device according to claim 6, characterized in that: Also includes: A power supply component (70) connected to the first FPGA chip (210), the second FPGA chip (220), the first digital display tube (610), the second digital display tube (620), and the ARM processor (40) respectively.

8. The boundary scan test device according to claim 7, characterized in that: The power supply component (70) comprises: a power supply (710) and a voltage conversion module (720) connected to the power supply (710), wherein The voltage conversion module (720) is used to convert the voltage of the power supply (710) into a voltage suitable for the first FPGA chip (210), the second FPGA chip (220), the first digital display tube (610), the second digital display tube (620) and the ARM processor (40).

9. The boundary scan test device according to claim 8, characterized in that: The voltage conversion module (720) is a DC-DC converter.

10. The boundary scan test device according to claim 1, characterized in that: Also includes: USB interface (320), wherein The USB interface chip (310) is connected to the terminal device via the USB interface (320).

Images