Multi-network-port expansion circuit and industrial control system
By designing multi-network expansion circuits, increasing the number of external network ports of industrial control systems, the problem of limited communication rate caused by the limited number of network ports in the prior art is solved, and more efficient network communication and stronger processing performance are achieved.
Patent Information
- Application Number
- CN202421894655.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-06
- Publication Date
- 2025-05-09
- Estimated Expiration
- 2034-08-06
AI Technical Summary
The number of external network ports of existing industrial control systems is limited, resulting in limited communication rates between the upper computer cloud and the lower computer equipment, thereby reducing the operating efficiency of the entire industrial system.
A multi-network expansion circuit is designed, including a CPU, a first network chip, a second network chip and an Ethernet switching chip. By setting up the two PCIE interfaces of the CPU, each connected to a network chip, and at least two Ethernet network ports are expanded through the Ethernet switching chip, so that the industrial control system includes at least three external network ports.
By increasing the number of external network ports of the industrial control system, the efficiency of network communication between the upper and lower computer equipment through the industrial control system is improved, and the flexibility and processing performance of the industrial control system are improved.
Smart Images
Figure CN222852290U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of network communication, in particular to a multi-network port expansion circuit and an industrial control system. Background Art
[0002] With the vigorous development of the energy industry and the continuous upgrading of the energy industry field environment, the complexity of industrial sites has increased, which makes data interaction and control between various industrial equipment in industrial scenarios particularly important.
[0003] In actual industrial environments, industrial control systems usually perform comprehensive control over the host cloud and the lower-level devices, and implement data interaction between the host cloud and the lower-level devices. However, faced with the current situation of a large number of industrial field devices and complex interrelationships, as well as the problem that the number of external network ports of currently commonly used industrial control systems is limited (at most two), the communication rate between the host cloud and the lower-level devices is limited, resulting in low operating efficiency of the entire industrial system.
[0004] In summary, how to improve the efficiency of network communication between the upper computer cloud and the lower computer equipment through the industrial control system is a technical problem that needs to be urgently solved in the field of network communication technology. Utility Model Content
[0005] The main purpose of the utility model is to propose a multi-network port expansion circuit and an industrial control system, aiming to improve the efficiency of network communication between the upper computer cloud and the lower computer equipment through the industrial control system.
[0006] To achieve the above-mentioned purpose, the utility model proposes a multi-network port expansion circuit, which includes: a CPU, a first network chip, a second network chip and an Ethernet switch chip;
[0007] The CPU includes a first PCIE interface and a second PCIE interface, the CPU is connected to the first network chip through the first PCIE interface, and is connected to the second network chip through the second PCIE interface;
[0008] The first network chip is connected to the first Ethernet network port via an MDI interface;
[0009] The second network chip is connected to the Ethernet switch chip via an MDI interface, and the Ethernet switch chip is connected to a corresponding number of second Ethernet network ports via at least two MDI interfaces.
[0010] In one embodiment, the multi-network port expansion circuit further includes a first PHY chip, and the Ethernet switch chip includes at least one first RGMII interface;
[0011] The first RGMII interface is connected to a single first PHY chip, and when there are multiple first RGMII interfaces, the first PHY chips connected to the first RGMII interfaces are different;
[0012] The first PHY chip is connected to a single second Ethernet network port through an MDI interface, and when there are multiple first RGMII interfaces, the second Ethernet network ports connected to the first PHY chips are different.
[0013] In one embodiment, the Ethernet switch chip is integrated with at least three PHY modules;
[0014] The second network chip is connected to the first PHY module of the Ethernet switch chip through an MDI interface, wherein the first PHY module is any one of the multiple PHY modules.
[0015] In one embodiment, the multiple second PHY modules of the Ethernet switching chip are respectively connected to a single second Ethernet port, and the second Ethernet ports to which the multiple second PHY modules are respectively connected are different, wherein the second PHY module is a PHY module among the multiple PHY modules except the first PHY module.
[0016] In one implementation, both the first network chip and the second network chip have MAC functions and PHY functions.
[0017] In one embodiment, the first Ethernet network port is a Gigabit Ethernet network port.
[0018] In one implementation, the second Ethernet network port is a 100M Ethernet network port.
[0019] In one embodiment, the multi-network port expansion circuit further includes a second PHY chip, and the CPU further includes two second RGMII interfaces;
[0020] Each of the second RGMII interfaces is respectively connected to a single second PHY chip, and the second PHY chips connected to each of the second RGMII interfaces are different;
[0021] Each of the second PHY chips is respectively connected to a single EtherCAT network port, and the EtherCAT network ports to which each of the second PHY chips is connected are different.
[0022] In one embodiment, the multi-network port expansion circuit further includes a serial management interface;
[0023] The CPU is connected to the Ethernet switch chip, the first PHY chip and the second PHY chip through the serial management interface to manage the Ethernet switch chip, the first PHY chip and the second PHY chip;
[0024] The first PHY chip is a PHY chip connected to at least one first RGMII interface of the Ethernet switch chip, and the second PHY chip is a PHY chip connected to each second RGMII interface of the CPU.
[0025] The utility model provides a multi-network port expansion circuit, which includes a CPU, a first network chip, a second network chip and an Ethernet switching chip, wherein the CPU includes a first PCIE interface and a second PCIE interface, the CPU is connected to the first network chip through the first PCIE interface, and is connected to the second network chip through the second PCIE interface, the first network chip is connected to the first Ethernet network port through an MDI interface, the second network chip is connected to the Ethernet switching chip through the MDI interface, and the Ethernet switching chip is connected to a corresponding number of second Ethernet network ports through at least two MDI interfaces.
[0026] In this way, compared with the traditional industrial control system that connects to at most two network ports, the multi-network port expansion circuit provided by the utility model connects a network chip to each of the two PCIE interfaces of the CPU, wherein the first PCIE interface is connected to the first network chip, and the first network chip is connected to the first Ethernet network port through the MDI interface, the second PCIE interface is connected to the second network chip, and the MDI interface of the second network chip is connected to the Ethernet switching chip, and the Ethernet switching chip is connected to the corresponding number of second Ethernet network ports through at least two MDI interfaces, that is, the number of network ports expanded through the first network chip is one, and the number of network ports expanded through the second network chip and the Ethernet switching chip is at least two, thereby realizing that the industrial control system contains at least 3 external network ports, thereby improving the efficiency of network communication between the upper computer cloud and the lower computer equipment through the industrial control system. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.
[0028] Figure 1A schematic diagram of the structure of a first embodiment of a multi-network port expansion circuit provided by the utility model;
[0029] Figure 2 A schematic diagram of the structure of a second embodiment of a multi-network port expansion circuit provided by the utility model;
[0030] Figure 3 A schematic diagram of the structure of a third embodiment of a multi-network port expansion circuit provided by the utility model;
[0031] Figure 4 This is a structural schematic diagram of a fourth embodiment of the multi-network port expansion circuit provided by the utility model.
[0032] Description of Figure Numbers:
[0033] 10. CPU; 101. first PCIE interface; 102. second PCIE interface; 103. second RGMII interface; 20. first network chip; 30. second network chip; 40. Ethernet switch chip; 401. first RGMII interface; 402. PHY module of Ethernet switch chip; 402-1. first PHY module; 402-2. second PHY module; 50. first PHY chip; 60. second PHY chip; A. first Ethernet network port; B. second Ethernet network port; C. EtherCAT network port.
[0034] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0035] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0036] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components in a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.
[0037] In addition, if there are descriptions of "first", "second", etc. in the embodiments of the utility model, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited to "first" and "second" can explicitly or implicitly include at least one of the features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel schemes. Taking "Scheme 1 and / or Scheme 2" as an example, it includes scheme 1, or scheme 2, or schemes that are satisfied by both scheme 1 and scheme 2. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the utility model. It should be noted that the "connection" mentioned in the embodiments of the present application refers to a communication connection.
[0038] The utility model provides a multi-network port expansion circuit.
[0039] See also Figure 1 In the first embodiment of the utility model, the multi-network port expansion circuit includes: a CPU 10, a first network chip 20, a second network chip 30 and an Ethernet switch chip 40;
[0040] The CPU 10 includes a first PCIE interface 101 and a second PCIE interface 102. The CPU 10 is connected to the first network chip 20 through the first PCIE interface 101, and is connected to the second network chip 30 through the second PCIE interface 102.
[0041] The first network chip 20 is connected to the first Ethernet network port A via an MDI interface;
[0042] The second network chip 30 is connected to the Ethernet switch chip 40 via an MDI interface, and the Ethernet switch chip 40 is connected to a corresponding number of second Ethernet network ports B via at least two MDI interfaces.
[0043] In this embodiment, the multi-network port expansion circuit proposed in the utility model constitutes an improved industrial control system, and the multi-network port expansion circuit includes a CPU 10 (Central Processing Unit, central processing unit), two network chips and an Ethernet switching chip 40, wherein the network chip refers to an Ethernet controller chip, and the two network chips are respectively referred to as a first network chip 20 and a second network chip 30 for distinction. The CPU 10 includes two PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) interfaces, respectively referred to as a first PCIE interface 101 and a second PCIE interface 102 for distinction. Specifically, since the network chip is compatible with the function of connecting to the PCIE interface, the CPU 10 is connected to the first network chip 20 through the first PCIE interface 101, and is connected to the second network chip 30 through the second PCIE interface 102. The network chip is also compatible with the Ethernet physical interface. The first network chip 20 is connected to an Ethernet port (hereinafter referred to as the first Ethernet port for distinction) through an MDI (Medium Dependent Interface) interface, and the second network chip 30 is connected to the Ethernet switching chip 40 through the MDI interface. The Ethernet switching chip 40 integrates multiple PHY (Physical Layer) modules, and the PHY module has a PHY function. The Ethernet switching chip 40 can be connected to a corresponding number of Ethernet ports (hereinafter referred to as the second Ethernet port for distinction) through at least two MDI interfaces.
[0044] It should be noted that, at present, for a CPU 10 with only two PCIE interfaces, since the PCIE interface cannot be directly connected to the Ethernet port, the conversion from the PCIE interface to the Ethernet physical interface is usually implemented through an intermediate device, so that the Ethernet port is connected through the Ethernet physical interface, that is, at most two Ethernet ports are connected, so there is a problem of low scalability, resulting in weak flexibility and low processing performance of the industrial control system. However, the utility model is connected to the first network chip 20 through the first PCIE interface 101, so that the first network chip 20 is connected to an Ethernet port through the MDI interface, and is connected to the second network chip 30 through the second PCIE interface 102, so that the second network chip 30 is connected to the Ethernet switching chip 40 through the MDI interface, so that the Ethernet switching chip 40 is connected to at least two Ethernet ports through at least two MDI interfaces, thereby ensuring that the CPU 10 can expand at least 3 Ethernet ports, thereby improving the flexibility and processing performance of the industrial control system.
[0045] In a feasible implementation manner, the CPU 10 includes a PCIE 3.0X2 interface, and the PCIE 3.0X2 interface is expanded into two PCIE 3.0X1 interfaces, that is, the first PCIE interface 101 is a PCIE 3.0 interface, and the second PCIE interface 102 is also a PCIE 3.0 interface.
[0046] In this way, compared with the traditional industrial control system that connects at most two network ports, the multi-network port expansion circuit provided by the utility model is connected to a network chip by setting two PCIE interfaces of the CPU10, wherein the first PCIE interface 101 is connected to the first network chip 20, and the first network chip 20 is connected to the first Ethernet network port A through the MDI interface, the second PCIE interface 102 is connected to the second network chip 30, and the MDI interface of the second network chip 30 is connected to the Ethernet switching chip 40, and the Ethernet switching chip 40 is connected to the corresponding number of second Ethernet network ports B through at least two MDI interfaces, that is, the number of network ports expanded by the first network chip 20 is one, and the number of network ports expanded by the second network chip 30 and the Ethernet switching chip 40 is at least two, thereby realizing that the industrial control system contains at least 3 external network ports, thereby improving the efficiency of network communication between the upper computer cloud and the lower computer equipment through the industrial control system.
[0047] Further, refer to Figure 2 In the second embodiment of the utility model, the multi-network port expansion circuit further includes a first PHY chip 50, and the Ethernet switch chip 40 includes at least one first RGMII interface 401;
[0048] The first RGMII interface 401 is connected to a single first PHY chip 50, and when there are multiple first RGMII interfaces 401, the first PHY chips 50 connected to the first RGMII interfaces 401 are different;
[0049] The first PHY chip 50 is connected to a single second Ethernet network port B through an MDI interface, and when there are multiple first RGMII interfaces 401 , the second Ethernet network ports B connected to the first PHY chips 50 are different.
[0050] In this embodiment, the multi-network port expansion circuit also includes a PHY chip (hereinafter referred to as the first PHY chip for distinction), and the Ethernet switching chip 40 includes at least one RGMII (Reduced Gigabit Media Independent Interface) interface (hereinafter referred to as the first RGMII interface for distinction). When the number of first RGMII interfaces 401 on the Ethernet switching chip 40 is single, the first RGMII interface 401 is connected to a first PHY chip 50, and the first PHY chip 50 is connected to a second Ethernet port B through an MDI interface, so that the number of Ethernet ports expanded by the Ethernet switching chip increases by one; when the number of first RGMII interfaces 401 on the Ethernet switching chip is multiple, each first RGMII interface 401 is respectively connected to a single first PHY chip 50, and the first RGMII interfaces 401 are respectively connected to different first PHY chips 50, that is, each first RGMII interface 401 is only connected to one first PHY chip 50, and each first PHY chip 50 is also only connected to one first RGMII interface 401. And each first PHY chip 50 is connected to a single second Ethernet port B through an MDI interface, and the second Ethernet ports B connected to each first PHY chip 50 are different, that is, each first PHY chip 50 is connected to only one second Ethernet port B through one MDI interface, and each second Ethernet port B is connected to only one first PHY chip 50. In this way, the number of Ethernet ports expanded by the Ethernet switch chip 40 increases by multiple.
[0051] In one feasible implementation, the model of the Ethernet switch chip 40 is YT9215, and the Ethernet switch chip 40 integrates a 5-port 1000M PHY module and supports 1 or 2 groups of RGMII interfaces. When the Ethernet switch chip 40 supports 1 group of RGMII interfaces, one Ethernet network port is connected through 1 group of RGMII interfaces. When the Ethernet switch chip 40 supports 2 groups of RGMII interfaces, two Ethernet network ports are connected through two groups of RGMII interfaces. In addition, a transformer is usually set between the PHY chip and the Ethernet network port for adjusting the voltage. Specifically, when the number of the first RGMII interface 401 on the Ethernet switch chip 40 is single, the first RGMII interface 401 is connected to a single first PHY chip 50, and the first PHY chip 50 is connected to a single transformer through an MDI interface, and is connected to the second Ethernet network port B through the transformer. The same applies to the case where the number of the first RGMII interface 401 on the Ethernet switch chip 40 is multiple.
[0052] It should be understood that each first PHY chip 50 mentioned in the above content refers to a plurality of identical PHY chips, each transformer refers to a plurality of identical transformers, and each Ethernet network port refers to a plurality of identical Ethernet network ports.
[0053] In this embodiment, the Ethernet switch chip 40 is integrated with at least three PHY modules 402;
[0054] The second network chip 30 is connected to the first PHY module 402 - 1 of the Ethernet switch chip 40 via an MDI interface, wherein the first PHY module 402 - 1 is any one of the multiple PHY modules 402 .
[0055] It should be noted that the Ethernet switch chip 40 integrates at least three PHY modules 402 , wherein the PHY module 402 is connected to the network port via an MDI interface.
[0056] In this embodiment, the second network chip 30 is connected to the PHY module 402 (hereinafter referred to as the first PHY module for distinction) of the Ethernet switch chip 40 through the MDI interface, wherein the first PHY module 402-1 is any PHY module 402 among the multiple PHY modules 402 of the Ethernet switch chip 40.
[0057] In this embodiment, the multiple second PHY modules 402-2 of the Ethernet switching chip 40 are respectively connected to a single second Ethernet network port B, and the second Ethernet network ports B to which the multiple second PHY modules 402-2 are respectively connected are different, wherein the second PHY module 402-2 is a PHY module 402 among the multiple PHY modules 402 except the first PHY module 402-1.
[0058] It should be noted that the PHY modules other than the first PHY module 402-1 among the multiple PHY modules 402 integrated in the Ethernet switch chip are referred to as second PHY modules 402-2 for distinction. Each second PHY module 402-2 is connected to a single second Ethernet network port B through an MDI interface, and the second Ethernet network port B connected to each second PHY module 402-2 is different.
[0059] In this embodiment, both the first network chip 20 and the second network chip 30 have MAC function and PHY function.
[0060] It should be noted that the network chips connected to the two PCIE interfaces of the CPU 10 both have MAC function and PHY function. In a feasible implementation manner, the model of the first network chip 20 and the second network chip 30 is YT6801.
[0061] In this embodiment, the first Ethernet network port A is a Gigabit Ethernet network port.
[0062] It should be noted that the first Ethernet port A to which the first network chip 20 is connected through the MDI interface is a Gigabit Ethernet port.
[0063] In this embodiment, the second Ethernet network port B is a 100M Ethernet network port.
[0064] It should be noted that each second Ethernet network port B connected to the second network chip 30 through the Ethernet switch chip 40 is a 100M Ethernet network port. In this way, it is ensured that each Ethernet network port expanded on the CPU can meet the communication between devices with different transmission rate requirements.
[0065] Thus, the embodiment of the present application utilizes an Ethernet switch chip 40 that integrates five PHY modules 402 and at least one RGMII interface to expand at least five Ethernet ports, thereby increasing the communication rate between the upper computer cloud and the lower computer device through the industrial control system. And by setting a first network chip 20 connected to a PCIE interface on the CPU 10 to directly connect to the Gigabit Ethernet port, the Gigabit transmission rate requirement of the device to be communicated can be met, thereby further improving the performance of the industrial control system.
[0066] Further, in the third embodiment of the present utility model, referring to Figure 3 , the multi-network port expansion circuit further includes a second PHY chip 60, and the CPU 10 further includes two second RGMII interfaces 103;
[0067] Each of the second RGMII interfaces 103 is respectively connected to a single second PHY chip 60, and the second PHY chips 60 to which each of the second RGMII interfaces 103 is respectively connected are different;
[0068] Each of the second PHY chips 60 is connected to a single EtherCAT network port C, and each of the second PHY chips 60 is connected to a different EtherCAT network port C.
[0069] In this embodiment, the multi-network port expansion circuit also includes a second PHY chip 60, and the CPU 10 also includes two RGMII interfaces (hereinafter referred to as second RGMII interfaces for distinction), namely GMAC (Gigabit Media Access Control) interfaces. Among them, each second RGMII interface 103 is respectively connected to a single second PHY chip 60, and each second RGMII interface 103 is respectively connected to a different second PHY chip 60. Each second PHY chip 60 is respectively connected to a single EtherCAT network port C, and each second PHY chip 60 is respectively connected to a different EtherCAT network port C, that is, one second PHY chip 60 is only connected to one EtherCAT network port C, and one EtherCAT network port C is also only connected to one second PHY chip 60.
[0070] In a feasible implementation, the model of CPU 10 is RK3568. And, a transformer is usually set between the PHY chip and the EtherCAT network port C for adjusting the voltage. Specifically, each second RGMII interface 103 is connected to a single second PHY chip 60, and each second RGMII interface 103 is connected to a different second PHY chip 60. Each second PHY chip 60 is connected to a single transformer through an MDI interface, and each second PHY chip 60 is connected to a different transformer. Then, each transformer is connected to a single EtherCAT network port C, and each transformer is connected to a different EtherCAT network port C.
[0071] It should be understood that the second PHY chips 60 mentioned in the above content refer to multiple identical PHY chips, the transformers refer to multiple identical transformers, and the EtherCAT network ports C refer to multiple identical EtherCAT network ports C.
[0072] It should be noted that traditional industrial control systems cannot achieve the integration of EtherCAT and Ethernet network communication functions, but the multi-network port expansion circuit proposed in the utility model can connect the corresponding number of EtherCATs through the two RGMII interfaces of CPU10, and expand at least 5 Ethernet network ports through the two PCIE interfaces of the CPU, thereby realizing the integration of EtherCAT and Ethernet network communication functions, thereby improving the processing performance of the industrial control system and the communication efficiency between the upper computer cloud and the lower computer equipment.
[0073] Further, refer to Figure 4 , in a fourth embodiment of the present utility model, the multi-network port expansion circuit further includes a serial management interface;
[0074] The CPU 10 is connected to the Ethernet switch chip 40, the first PHY chip 50 and the second PHY chip 60 through the serial management interface to manage the Ethernet switch chip 40, the first PHY chip 50 and the second PHY chip 60;
[0075] The first PHY chip 50 is a PHY chip connected to at least one first RGMII interface 401 of the Ethernet switch chip 40 , and the second PHY chip 60 is a PHY chip connected to each second RGMII interface 103 of the CPU 10 .
[0076] It should be noted that the serial management interface includes an MDIO (Management Data Input / Output) interface and an MDC (Management Data Clock) interface.
[0077] In this embodiment, the CPU 10 is connected to the Ethernet switch chip 40, the first PHY chip 50 and the second PHY chip 60 through a serial management interface to manage the Ethernet switch chip 40, the first PHY chip 50 and the second PHY chip 60. Specifically, the CPU 10 implements the register configuration of the Ethernet switch chip 40, the first PHY chip 50 and the second PHY chip 60 through the serial management interface.
[0078] In one feasible implementation, CPU10 uses three groups of MDIO and MDC interfaces, namely serial management interface-1, serial management interface-2 and serial management interface-3, wherein serial management interface-1 is connected to each first PHY chip 50, serial management interface-2 is connected to the Ethernet switching chip 40, and serial management interface-3 is connected to each second PHY chip 60.
[0079] In this way, the embodiment of the present application realizes unified management of each PHY chip and the Ethernet switch chip 40.
[0080] The utility model also proposes an industrial control system, which includes a multi-network port expansion circuit. The specific structure of the multi-network port expansion circuit refers to the above-mentioned embodiment. Since the industrial control system adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here one by one.
[0081] The above description is only an exemplary embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the technical concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.
Claims
1. A multi-network port expansion circuit, characterized in that: The multi-network port expansion circuit includes: a CPU, a first network chip, a second network chip and an Ethernet switch chip; The CPU includes a first PCIE interface and a second PCIE interface, the CPU is connected to the first network chip through the first PCIE interface, and is connected to the second network chip through the second PCIE interface; The first network chip is connected to the first Ethernet network port via an MDI interface; The second network chip is connected to the Ethernet switch chip via an MDI interface, and the Ethernet switch chip is connected to a corresponding number of second Ethernet network ports via at least two MDI interfaces.
2. The multi-network port expansion circuit according to claim 1, characterized in that: The multi-network port expansion circuit also includes a first PHY chip, and the Ethernet switch chip includes at least one first RGMII interface; The first RGMII interface is connected to a single first PHY chip, and when there are multiple first RGMII interfaces, the first PHY chips connected to the first RGMII interfaces are different; The first PHY chip is connected to a single second Ethernet network port through an MDI interface, and when there are multiple first RGMII interfaces, the second Ethernet network ports connected to the first PHY chips are different.
3. The multi-network port expansion circuit according to claim 1, characterized in that: The Ethernet switch chip is integrated with at least three PHY modules; The second network chip is connected to the first PHY module of the Ethernet switch chip through an MDI interface, wherein the first PHY module is any one of the multiple PHY modules.
4. The multi-network port expansion circuit according to claim 3, characterized in that: The multiple second PHY modules of the Ethernet switching chip are respectively connected to a single second Ethernet port, and the second Ethernet ports to which the multiple second PHY modules are respectively connected are different, wherein the second PHY module is a PHY module among the multiple PHY modules except the first PHY module.
5. The multi-network port expansion circuit according to claim 1, characterized in that: The first network chip and the second network chip both have MAC function and PHY function.
6. The multi-network port expansion circuit according to claim 1, characterized in that: The first Ethernet network port is a Gigabit Ethernet network port.
7. The multi-network port expansion circuit according to any one of claims 1 to 2, characterized in that: The second Ethernet network port is a 100M Ethernet network port.
8. The multi-network port expansion circuit according to claim 1, characterized in that: The multi-network port expansion circuit also includes a second PHY chip, and the CPU also includes two second RGMII interfaces; Each of the second RGMII interfaces is respectively connected to a single second PHY chip, and the second PHY chips connected to each of the second RGMII interfaces are different; Each of the second PHY chips is respectively connected to a single EtherCAT network port, and the EtherCAT network ports to which each of the second PHY chips is connected are different.
9. The multi-network port expansion circuit according to claim 1, characterized in that: The multi-network port expansion circuit also includes a serial management interface; The CPU is connected to the Ethernet switch chip, the first PHY chip and the second PHY chip through the serial management interface to manage the Ethernet switch chip, the first PHY chip and the second PHY chip; The first PHY chip is a PHY chip connected to at least one first RGMII interface of the Ethernet switch chip, and the second PHY chip is a PHY chip connected to each second RGMII interface of the CPU.
10. An industrial control system, characterized in that: The industrial control system includes the multi-network port expansion circuit as described in any one of claims 1 to 9.