Display device

Abstract

The present disclosure relates to a display device including a display panel including pixels and a circuit board electrically connected to the display panel, in which the circuit board includes: a base film having a first region overlapping at least a portion of a connector and a second region overlapping at least a portion of the connector; the second area is separated from the connector; and a unit signal line disposed on the base film, the unit signal line being electrically connected to the connector, and the unit signal line having a first characteristic impedance in the first region and a second characteristic impedance in the second region, the second characteristic impedance being smaller than the first characteristic impedance.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly to a display device including a circuit board. Background Art

[0002] With the development of information technology, the importance of display devices as a connecting medium between users and information has become increasingly prominent. For example, the use of display devices such as liquid crystal display (LCD) devices, organic light emitting diode (OLED) display devices, plasma display panels (PDP), and quantum dot display devices is increasing.

[0003] The display device includes a display panel and a circuit board, wherein the circuit board is electrically connected to the display panel and provides various signals and voltages for driving the display panel. Utility Model Content

[0004] The embodiment provides a display device having high-speed signal transmission performance.

[0005] A display device according to an embodiment includes: a display panel including pixels; and a circuit board electrically connected to the display panel, wherein the circuit board includes: a base film having a first area and a second area, the first area overlapping at least a portion of a connector, and the second area being spaced apart from the connector; and a unit signal line disposed on the base film, the unit signal line being electrically connected to the connector, and the unit signal line having a first characteristic impedance in the first area and a second characteristic impedance in the second area, the second characteristic impedance being smaller than the first characteristic impedance.

[0006] A display device according to an embodiment includes: a display panel including pixels; and a circuit board electrically connected to the display panel, wherein the circuit board includes: a base film; a first component and a second component, which are arranged on the base film, and the first component and the second component are spaced apart from each other along a first direction; a first signal line, which is arranged on the base film, and the first signal line extends in a second direction intersecting the first direction, wherein the first signal line includes a first portion arranged between the first component and the second component; and a second signal line, which is arranged on the base film, and the second signal line extends in the second direction, wherein the second signal line includes a second portion arranged between the first component and the second component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Illustrative embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0008] Figure 1 is a plan view showing a display device according to an embodiment.

[0009] Figure 2 It is shown Figure 1 A circuit diagram of one of the pixels included in a display device.

[0010] Figure 3 According to the embodiment Figure 1 An enlarged plan view of area A.

[0011] Figure 4 According to the embodiment Figure 3 An enlarged plan view of area B in FIG.

[0012] Figure 5 It is along Figure 3 A cross-sectional view taken along line II'.

[0013] Figure 6 According to the embodiment Figure 3 An enlarged plan view of area B in FIG.

[0014] Figure 7 According to the embodiment Figure 1 An enlarged plan view of area A.

[0015] Figure 8 According to the embodiment Figure 1 An enlarged plan view of area A.

[0016] Fig. 9 It is along Figure 8 A cross-sectional view taken along line II-II'.

[0017] Fig.10 is a plan view showing a display device according to an embodiment.

[0018] Fig.11 is a plan view showing a display device according to an embodiment. DETAILED DESCRIPTION

[0019] The present invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are shown. However, the present invention can be implemented in many different forms and need not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be exhaustive and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout the specification and the accompanying drawings, the same reference numerals may refer to the same elements.

[0020] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2. A third direction DR3 may be a normal direction of the plane. That is, the third direction DR3 may be perpendicular to both the first direction DR1 and the second direction DR2 and may be in a thickness direction of the display device DD.

[0021] Figure 1 is a plan view showing a display device according to an embodiment.

[0022] Reference Figure 1 , the display device DD according to the embodiment may include a display panel DP, a flexible circuit film FPC, a data driver DIC, and a circuit board PCB.

[0023] The display panel DP may include a display area DA and a peripheral area NDA. The display area DA may be an area that generates light or displays an image by adjusting transmittance of light provided from an external light source.

[0024] A plurality of pixels PX may be arranged in the display area DA. Each of the pixels PX may emit light. When each of the pixels PX emits light, the display area DA may display an image.

[0025] The plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 crossing the first direction DR1. A third direction DR3 may be perpendicular to a plane defined by the first direction DR1 and the second direction DR2.

[0026] Lines connected to the plurality of pixels PX may also be provided in the display area DA. For example, the lines may include data signal lines, gate signal lines, power lines, and the like.

[0027] The peripheral area NDA may be located near the display area DA. For example, the peripheral area NDA may surround at least a portion of the display area DA. The peripheral area NDA may be an area where an image is not displayed. However, the present invention is not necessarily limited thereto, and an image may be displayed in at least a portion of the peripheral area NDA.

[0028] A gate driver for generating a gate signal and / or a light emitting driver for generating a light emitting control signal may be disposed in the peripheral area NDA. The gate driver and the light emitting driver may be formed together during a process of forming a plurality of pixels PX. The gate signal and the light emitting control signal may be applied to the plurality of pixels PX.

[0029] The peripheral area NDA may include a pad area PA. The pad area PA may be spaced apart from one side of the display area DA in the first direction DR1. The pad area PA may have a rectangular shape extending in the second direction DR2. The length of the pad area PA in the first direction DR1 may be shorter than the length of the display area DA in the first direction DR1. A pad electrode may be disposed in the pad area PA. The pad electrode may be electrically connected to the plurality of pixels PX. In addition, the pad electrode may be electrically connected to the circuit board PCB.

[0030] The flexible circuit film FPC may be disposed on one side of the display panel DP. For example, the flexible circuit film FPC may be spaced apart from one side of the display area DA along the first direction DR1. Specifically, each of the flexible circuit films FPC may overlap a portion of the pad area PA. One end of each of the flexible circuit films FPC may be electrically connected to a pad electrode disposed in the pad area PA.

[0031] In addition, the other side of each of the flexible circuit films FPC opposite to the side facing the display panel DP may be connected to the circuit board PCB. That is, the flexible circuit film FPC may electrically connect the display panel DP and the circuit board PCB. In an embodiment, each of the flexible circuit films FPC may be a flexible film. However, the present invention is not necessarily limited thereto.

[0032] In an embodiment, a plurality of data drivers DIC may be respectively disposed on a plurality of flexible circuit films FPC. The display device DD may have a chip on film (COF) structure. However, the present invention is not necessarily limited thereto.

[0033] The circuit board PCB may be connected to the other end of each of the flexible circuit films FPC. In an embodiment, the timing controller TIC may be disposed on the circuit board PCB. The timing controller TIC may generate image data and control signals based on an image signal input from the outside, and the data driver DIC may convert the image data applied from the timing controller TIC into a data voltage and transmit the data voltage to a plurality of pixels PX.

[0034] For example, the signal output from the timing controller TIC may be transmitted to the display panel DP through the flexible circuit film FPC. Specifically, the signal output from the timing controller TIC may be transmitted to the plurality of pixels PX through the pad electrodes of the display panel DP via the flexible circuit film FPC.

[0035] In addition, the connector CNT may be provided on the circuit board PCB. The connector CNT may include a conductive material. The connector CNT may electrically connect the circuit board PCB and an external device. For example, the external device may be combined with the connector CNT so that the circuit board PCB and the external device may be electrically connected. The external device may generate a driving signal, a driving voltage, etc. to display an image in the display area DA. The driving signal, driving voltage, etc. generated from the external device may be transmitted to a plurality of pixels PX through the circuit board PCB, the timing controller TIC, the flexible circuit film FPC, and the data driver DIC. In an embodiment, the circuit board PCB may be a printed circuit board.

[0036] exist Figure 1In FIG. 1 , the display device DD is shown to include three flexible circuit films FPC and three data drivers DIC, but the number of the flexible circuit films FPC and the data drivers DIC is not necessarily limited thereto. Figure 1 In the embodiment, the flexible circuit film FPC and the circuit board PCB are shown as being arranged on the bottom side of the display panel DP, but the present invention is not necessarily limited thereto. For example, the flexible circuit film FPC and the circuit board PCB may also be arranged on the top side, left side and / or right side of the display panel DP.

[0037] Figure 2 It is shown Figure 1 A circuit diagram of one of the pixels included in a display device.

[0038] Reference Figure 2 , also refer to Figure 1 , each of a plurality of pixels PX included in the display device DD according to the embodiment may include first, second and third transistors T1, T2 and T3, a storage capacitor CST and a light emitting diode LED.

[0039] The first transistor T1 may include a source electrode, a drain electrode, and a gate electrode. The first transistor T1 may adjust a current flowing from the driving voltage line ELVDL to the common voltage line ELVSL via the light emitting diode LED according to a voltage difference between the gate electrode and the source electrode, and the driving voltage line ELVDL supplies a driving voltage to the light emitting diode LED.

[0040] For example, the first transistor T1 may be a driving transistor for driving a light emitting diode LED. A gate electrode of the first transistor T1 may be connected to a first node N1. A source electrode of the first transistor T1 may be connected to a first electrode of the light emitting diode LED. A drain electrode of the first transistor T1 may be connected to a driving voltage line ELVDL to which a driving voltage is applied.

[0041] The second transistor T2 may include a source electrode, a drain electrode, and a gate electrode. The second transistor T2 may be turned on by a gate signal of a gate signal line GSL, and connects the data signal line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the gate signal line GSL. The source electrode of the second transistor T2 may be connected to the first node N1. The drain electrode of the second transistor T2 may be connected to the data signal line DTL.

[0042] The third transistor T3 may include a source electrode, a drain electrode, and a gate electrode. The third transistor T3 may be turned on by a sensing signal of the sensing signal line SSL, and connects the initialization voltage line VIL to one end of the light emitting diode LED. The gate electrode of the third transistor T3 may be connected to the sensing signal line SSL. The source electrode of the third transistor T3 may be connected to the second node N2. The drain electrode of the third transistor T3 may be connected to the initialization voltage line VIL to which the initialization voltage is applied.

[0043] However, the source electrode and the drain electrode of each of the first transistor T1, the second transistor T2, and the third transistor T3 are not necessarily limited thereto, and vice versa. In addition, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be formed as a thin film transistor.

[0044] The storage capacitor CST may include a first electrode and a second electrode. The first electrode of the storage capacitor CST may be connected to the first node N1. The second electrode of the storage capacitor CST may be connected to the second node N2. The storage capacitor CST may store a difference voltage between a gate voltage and a source voltage of the first transistor T1.

[0045] The light emitting diode LED can emit light according to the current supplied by the first transistor T1. The light emitting diode LED can be an organic light emitting diode including a first electrode (e.g., an anode electrode), an organic light emitting layer, and a second electrode (e.g., a cathode electrode). However, the embodiments of the utility model are not necessarily limited thereto, and the light emitting diode LED can be an inorganic light emitting diode including an inorganic light emitting layer or a quantum dot light emitting diode including a quantum dot light emitting layer, etc. In addition, the light emitting diode LED can be a micro LED. The first electrode of the light emitting diode LED can be connected to the source electrode of the first transistor T1, and the second electrode of the light emitting diode LED can be connected to a common voltage line ELVSL, and a common voltage lower than the driving voltage is applied to the common voltage line ELVSL.

[0046] exist Figure 2 In the description, a case has been described in which each of the pixels PX includes three transistors T1, T2 and T3, one storage capacitor CST and one light emitting diode LED, but the number of transistors included in each of the pixels PX, the number of storage capacitors included in each of the pixels PX, and the number of light emitting diodes included in each of the pixels PX are not necessarily limited thereto.

[0047] Figure 3 According to the embodiment Figure 1 An enlarged plan view of area A. Figure 4 According to the embodiment Figure 3 An enlarged plan view of area B in FIG. Figure 5 It is along Figure 3 Here, for the convenience of description, Figure 3 and Figure 4 The connector CNT is omitted (see Figure 1 ).

[0048] Reference Figure 1 , Figure 3 , Figure 4 and Figure 5 The circuit board PCB may include a base film BSF, first, second and third conductive layers MTL1, MTL2 and MTL3, first, second and third insulating layers IL1, IL2 and IL3, and unit signal lines SL1, SL2, . . . and SLn.

[0049] The base film BSF may support components of the circuit board PCB. In an embodiment, the base film BSF may include an insulating material such as an inorganic insulating material and / or an organic insulating material. These insulating materials may be used alone or in combination with each other.

[0050] like Figure 3 As shown in , the base film BSF may have a first area A1 and a second area A2. The first area A1 may be an area in which at least a portion of the connector CNT is set. For example, the first area A1 may be an area overlapping with at least a portion of the connector CNT in a plan view. For example, the first area A1 may be an area corresponding to the connector CNT. The second area A2 may be adjacent to the first area A1. For example, the second area may surround at least a portion of the first area A1. The second area A2 may be an area in which the connector CNT is not set. For example, in a plan view, the second area A2 may be adjacent to the first area A1 and may be spaced apart from the connector CNT.

[0051] The first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3 and the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 may be disposed on the base film BSF. For example, the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3 and the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 may be disposed in both the first area A1 and the second area A2 of the base film BSF.

[0052] In an embodiment, the first conductive layer MTL1 may be disposed on the base film BSF, the first insulating layer IL1 may be disposed on the first conductive layer MTL1, the second conductive layer MTL2 may be disposed on the first insulating layer IL1, the second insulating layer IL2 may be disposed on the second conductive layer MTL2, the third conductive layer MTL3 may be disposed on the second insulating layer IL2, and the third insulating layer IL3 may be disposed on the third conductive layer MTL3.

[0053] In an embodiment, each of the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3 may be used as one of a signal layer, a power layer, and a ground layer. For example, when one of the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3 is used as a signal layer, the conductive layer may include a pattern for transmitting a signal. In addition, when one of the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3 is used as a power layer, the conductive layer supplies power to various lines and diodes included in the circuit board PCB. In addition, when one of the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3 is used as a ground layer, the conductive layer may supply a ground voltage. Meanwhile, the number of conductive layers MTL included in the circuit board PCB and the number of insulating layers IL included in the circuit board PCB are not necessarily limited thereto.

[0054] The unit signal lines SL1, SL2, ..., and SLn may be disposed on the third insulating layer IL3. In an embodiment, the timing controller TIC may be connected to the unit signal lines SL1, SL2, ..., and SLn. In addition, the connector CNT may be connected to the unit signal lines SL1, SL2, ..., and SLn. For example, an external device may be electrically connected to the timing controller TIC through the connector CNT and the unit signal lines SL1, SL2, ..., and SLn. At the same time, Figure 3 The planar structures (eg, bending directions) of the unit signal lines SL1 , SL2 , . . . , and SLn shown in FIG. 1 are merely examples, and the present invention is not necessarily limited thereto.

[0055] In a plan view, the unit signal lines SL1, SL2, ..., and SLn may extend beyond a boundary between the first area A1 and the second area A2. For example, each of the unit signal lines SL1, SL2, ..., and SLn may be divided into a portion located in the first area A1 and a portion located in the second area A2. For example, in a plan view, each of the unit signal lines SL1, SL2, ..., and SLn may overlap with the connector CNT in the first area A1 and be spaced apart from the connector CNT in the second area A2.

[0056] Each of the unit signal lines SL1, SL2, ... and SLn may include a first signal line SL11, SL21, ... and SLn1 and a second signal line SL12, SL22, ... and SLn2. For example, each of the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 may be divided into a portion located in the first area A1 and a portion located in the second area A2. In other words, in a plan view, each of the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 may overlap with the connector CNT in the first area A1, or may be spaced apart from the connector CNT in the second area A2.

[0057] The first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 can form a differential pair. Therefore, even if noise changes the alternating current transmitted to the first signal lines SL11, SL21, ... and SLn1, the second signal lines SL12, SL22, ... and SLn2 can also change to compensate for the change in the alternating current transmitted to the first signal lines SL11, SL21, ... and SLn1. Conversely, even if noise changes the alternating current transmitted to the second signal lines SL12, SL22, ... and SLn2, the first signal lines SL11, SL21, ... and SLn1 can also change to compensate for the change in the alternating current transmitted to the second signal lines SL12, SL22, ... and SLn2. Therefore, the quality of the signal transmitted by the unit signal lines SL1, SL2, ... and SLn can be improved.

[0058] Next, through Figure 4 , the structure of each of the first signal lines SL11, SL21, . . . and SLn1 and the second signal lines SL12, SL22, . . . and SLn2 close to the boundary between the first area A1 and the second area A2 will be described in more detail. For convenience, Figure 4 Only the first signal line SL11 and the second signal line SL12 from among the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 are shown. The other signal lines SL1, SL2, ... and SLn may be connected to Figure 4 The first signal line SL11 and the second signal line SL12 shown in FIG. 1 have substantially the same structure.

[0059] The first signal lines SL11, SL21, ..., and SLn1 may include a first portion P1 located in the first area A1 and a second portion P2 located in the second area A2. For example, the first portion P1 may refer to a portion of the first signal lines SL11, SL21, ..., and SLn1 located in the first area A1 close to a boundary between the first area A1 and the second area A2, and the second portion P2 may refer to a portion of the first signal lines SL11, SL21, ..., and SLn1 located in the second area A2 close to a boundary between the first area A1 and the second area A2. For example, the first portion P1 and the second portion P2 are separated only by the boundary between the first area A1 and the second area A2, and do not mean a structural disconnection.

[0060] In an embodiment, the first portion P1 may have a first line width W1, and the second portion P2 may have a second line width W2. The second line width W2 may be greater than the first line width W1. In other words, the line widths of the first signal lines SL11, SL21, ..., and SLn1 in the first area A1 may be less than the line widths of the first signal lines SL11, SL21, ..., and SLn1 in the second area A2. For example, the line widths of the first signal lines SL11, SL21, ..., and SLn1 may be changed when they cross the boundary between the first area A1 and the second area A2.

[0061] The second signal lines SL12, SL22, ... and SLn2 may include a third portion P3 located in the first area A1 and a fourth portion P4 located in the second area A2. For example, the third portion P3 may refer to a portion of the second signal lines SL12, SL22, ... and SLn2 located in the first area A1 close to the boundary between the first area A1 and the second area A2, and the fourth portion P4 may refer to a portion of the second signal lines SL12, SL22, ... and SLn2 located in the second area A2 close to the boundary between the first area A1 and the second area A2. For example, the third portion P3 and the fourth portion P4 are separated only by the boundary between the first area A1 and the second area A2, and do not mean a structural disconnection.

[0062] In an embodiment, the third portion P3 may have a third line width W3, and the fourth portion P4 may have a fourth line width W4. The fourth line width W4 may be greater than the third line width W3. In other words, the line widths of the second signal lines SL12, SL22, ..., and SLn2 in the first area A1 may be less than the line widths of the second signal lines SL12, SL22, ..., and SLn2 in the second area A2. For example, the line widths of the second signal lines SL12, SL22, ..., and SLn2 may be changed when they cross the boundary between the first area A1 and the second area A2.

[0063] In an embodiment, the first separation distance D1 between the first portion P1 and the third portion P3 may be greater than the second separation distance D2 between the second portion P2 and the fourth portion P4. In other words, the gaps between the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2 in the first area A1 may be greater than the gaps between the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2 in the second area A2. For example, the distances between the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2 may be changed when they cross the boundary between the first area A1 and the second area A2.

[0064] Although in the case where the first line width W1 of the first portion P1 is smaller than the second line width W2 of the second portion P2, the third line width W3 of the third portion P3 is smaller than the fourth line width W4 of the fourth portion P4, and Figure 4 It is shown in FIG. 1 that the first separation distance D1 is greater than the second separation distance D2 , but the present invention is not limited thereto.

[0065] In some embodiments, the first line width W1 of the first portion P1 and the second line width W2 of the second portion P2 may be the same, the third line width W3 of the third portion P3 and the fourth line width W4 of the fourth portion P4 may be the same, and the first separation distance D1 may be greater than the second separation distance D2.

[0066] In some embodiments, the first separation distance D1 and the second separation distance D2 may be the same, the first line width W1 of the first portion P1 may be smaller than the second line width W2 of the second portion P2, and the third line width W3 of the third portion P3 may be smaller than the fourth line width W4 of the fourth portion P4.

[0067] In an embodiment, the first parasitic capacitance between the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 in the first area A1 may be smaller than the second parasitic capacitance between the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 in the second area A2.

[0068] For example, when the first line width W1 of the first part P1 is smaller than the second line width W2 of the second part P2, and the third line width W3 of the third part P3 is smaller than the fourth line width W4 of the fourth part P4, since the first separation distance D1 is greater than the second separation distance D2, the first parasitic capacitance between the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 in the first area A1 can be smaller than the second parasitic capacitance between the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 in the second area A2.

[0069] As a result, each of the unit signal lines SL1, SL2, ... and SLn may have different characteristic impedances in the first area A1 and the second area A2. For example, the characteristic impedance of each of the unit signal lines SL1, SL2, ... and SLn may be changed when it crosses the boundary between the first area A1 and the second area A2.

[0070] Specifically, the characteristic impedance of the unit signal lines SL1, SL2, ..., and SLn may be affected by the parasitic capacitance between the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2. The characteristic impedance can be expressed by the formula Z 0 =SQRT(L / C) To represent (where Z 0 is the characteristic impedance, L is the inductance, and C is the parasitic capacitance).

[0071] For example, when the first parasitic capacitance between the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 in the first area A1 is smaller than the second parasitic capacitance between the first signal lines SL11, SL21 to SLn1 and the second signal lines SL12, SL22, ... and SLn2 in the second area A2, the first characteristic impedance of each of the unit signal lines SL1, SL2, ... and SLn in the first area A1 may be greater than the second characteristic impedance of each of the unit signal lines SL1, SL2, ... and SLn in the second area A2.

[0072] Since the first area A1 is an area overlapping at least a portion of the connector CNT in a plan view, the characteristic impedance of each of the unit signal lines SL1, SL2, ..., and SLn in the first area A1 may be degraded after the connector CNT is provided. For example, due to an increase in parasitic capacitance caused by the connector CNT, the characteristic impedance of each of the unit signal lines SL1, SL2, ..., and SLn may be degraded after the connector CNT is provided. On the other hand, since the second area A2 is an area spaced apart from the connector CNT, the characteristic impedance of each of the unit signal lines SL1, SL2, ..., and SLn may be substantially unaffected by the connector CNT.

[0073] In an embodiment, the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2 may have a first structure in which the first line width W1 is less than the second line width W2 and the third line width W3 is less than the fourth line width W4 and / or a second structure in which the first separation distance D1 is greater than the second separation distance D2. Therefore, the first characteristic impedance of each of the unit signal lines SL1, SL2, ..., and SLn in the first area A1 may be greater than the second characteristic impedance of each of the unit signal lines SL1, SL2, ..., and SLn in the second area A2.

[0074] Therefore, even when the characteristic impedance of each of the unit signal lines SL1, SL2, ... and SLn in the first area A1 is degraded due to the connector CNT, the characteristic impedance of each of the unit signal lines SL1, SL2, ... and SLn in the first area A1 and the characteristic impedance of each of the unit signal lines SL1, SL2, ... and SLn in the second area A2 can be substantially the same or similar. Therefore, even after the connector CNT is set on the circuit board PCB, the signal integrity of each of the unit signal lines SL1, SL2, ... and SLn can be maintained. Therefore, the transmission performance of the high-speed signal passing through the unit signal lines SL1, SL2, ... and SLn can be improved. Therefore, the display quality of the display device DD can be improved.

[0075] In an embodiment, Figure 3 and Figure 5 As shown in , the circuit board PCB may also include a first component CP1 and a second component CP2. Each of the first component CP1 and the second component CP2 may receive an electrical signal or voltage supplied from an external device and transmit the electrical signal or voltage to the display panel DP. For example, each of the first component CP1 and the second component CP2 may include elements such as a resistor and a capacitor or a power control module.

[0076] The first component CP1 and the second component CP2 may be disposed on the base film BSF. For example, the first component CP1 and the second component CP2 may be disposed on the third insulating layer IL3. For example, the first component CP1, the second component CP2, and the unit signal lines SL1, SL2, ..., and SLn may be disposed at the same level on the base film BSF. In other words, the first component CP1, the second component CP2, the first signal lines SL11, SL21, ..., and SLn1, and the second signal lines SL12, SL22, ..., and SLn2 may be located at the same level on the base film BSF.

[0077] like Figure 3 and Figure 5 As shown in, in a plan view, the fifth portion P5 of the first signal lines SL11, SL21, ... and SLn1 and the sixth portion P6 of the second signal lines SL12, SL22, ... and SLn2 may be disposed between the first component CP1 and the second component CP2. In other words, the first component CP1 and the second component CP2 may be spaced apart from each other along the first direction DR1, with the fifth portion P5 of the first signal lines SL11, SL21, ... and SLn1 and the sixth portion P6 of the second signal lines SL12, SL22, ... and SLn2 interposed between the first component CP1 and the second component CP2. For example, in a plan view, the first component CP1 may be located in a direction opposite to the first direction DR1 from the fifth portion P5 of the first signal line SL11, SL21, ... and SLn1 and the sixth portion P6 of the second signal line SL12, SL22, ... and SLn2, and the second component CP2 may be located in the first direction DR1 from the fifth portion P5 of the first signal line SL11, SL21, ... and SLn1 and the sixth portion P6 of the second signal line SL12, SL22, ... and SLn2.

[0078] In an embodiment, Figure 5 As shown in , the height of each of the first component CP1 and the second component CP2 may be greater than the height of each of the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2. Figure 5 In the figure, the height of the first component CP1 and the height of the second component CP2 are shown to be the same, but the present invention is not necessarily limited to this.

[0079] The display device DD may further include a cover CM. The cover CM may cover at least a portion of the circuit board PCB. For example, the cover CM may cover the fifth portion P5 of the first signal lines SL11, SL21, ..., and SLn1 and the sixth portion P6 of the second signal lines SL12, SL22, ..., and SLn2. Therefore, the cover CM may protect the circuit board PCB from external impacts, etc.

[0080] In an embodiment, the cover CM may include a conductive material such as a conductive tape. However, the present invention is not necessarily limited thereto. For example, the cover CM may include an insulating material.

[0081] The cover CM may be spaced apart from the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2. For example, the cover CM may not contact the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2. Specifically, the cover CM may be spaced apart from the fifth portion P5 of the first signal lines SL11, SL21, ... and SLn1 and the sixth portion P6 of the second signal lines SL12, SL22, ... and SLn2.

[0082] For example, since the circuit board PCB includes the first component CP1 and the second component CP2 spaced apart from each other along the first direction DR1, the fifth portion P5 of the first signal line SL11, SL21, ... and SLn1 and the sixth portion P6 of the second signal line SL12, SL22, ... and SLn2 are interposed between the first component CP1 and the second component CP2, and at the same time, the height of each of the first component CP1 and the second component CP2 is greater than the height of each of the first signal lines SL11, SL21, ~SLn1 and the second signal lines SL12, SL22, ... and SLn2, the cover body CM may not contact the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 via the first component CP1 and the second component CP2.

[0083] Therefore, the degradation of the signal integrity of each of the unit signal lines SL1, SL2, ... and SLn caused by contact with the cover body CM can be prevented or reduced. For example, when the cover body CM contacts the unit signal lines SL1, SL2, ... and SLn, the strength of the contact with each of the unit signal lines SL1, SL2, ... and SLn can be distributed. Therefore, the signal integrity of the unit signal lines SL1, SL2, ... and SLn may be degraded. However, according to an embodiment, since the cover body CM is separated from the unit signal lines SL1, SL2, ... and SLn by the first component CP1 and the second component CP2, the degradation of the signal integrity of each of the unit signal lines SL1, SL2, ... and SLn caused by contact with the cover body CM can be prevented or reduced. Therefore, the transmission performance of the high-speed signal passing through the unit signal lines SL1, SL2, ... and SLn can be improved. Thus, the display quality of the display device DD can be improved.

[0084] Figure 6 According to the embodiment Figure 3 An enlarged plan view of area B in FIG.

[0085] Reference Figure 6 In an embodiment, the first portion P1 may have a first line width W1', and the second portion P2 may have a second line width W2'. The first line width W1' and the second line width W2' may be substantially the same. In other words, the line widths of the first signal lines SL11, SL21, ..., and SLn1 may not substantially change when they cross the boundary between the first area A1 and the second area A2.

[0086] In addition, the third portion P3 may have a third line width W3', and the fourth portion P4 may have a fourth line width W4'. The third line width W3' and the fourth line width W4' may be substantially the same. In other words, the line widths of the second signal lines SL12, SL22, ..., and SLn2 may not substantially change when they cross the boundary between the first area A1 and the second area A2.

[0087] In addition, the first separation distance D1' between the first portion P1 and the second portion P2 may be substantially the same as the second separation distance D2' between the third portion P3 and the fourth portion P4. In other words, the gaps between the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 may not substantially change when they cross the boundary between the first area A1 and the second area A2.

[0088] For example, when the circuit board PCB includes reference Figure 3 and Figure 5 When describing the first component CP1 and the second component CP2, the line widths of the first signal lines SL11, SL21, ... and SLn2, the line widths of the second signal lines SL12, SL22, ... and SLn2, and the gaps between the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 may not substantially change when they cross the boundary between the first area A1 and the second area A2.

[0089] Figure 7 According to the embodiment Figure 1 An enlarged plan view of area A.

[0090] Reference Figure 7 In this case, the first signal lines SL11, SL21, ..., and SLn2 and the second signal lines SL12, SL22, ..., and SLn2 may have reference Figure 4For example, when the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 have a first structure in which the first line width W1 is smaller than the second line width W2 and the third line width W3 is smaller than the fourth line width W4 and / or a second structure in which the first separation distance D1 is larger than the second separation distance D2, the second component CP2 may be omitted.

[0091] In summary, according to an embodiment, the display device DD may have: a first structure in which the line widths of the first signal lines SL11, SL21, ... and SLn1 and the line widths of the second signal lines SL12, SL22, ... and SLn2 change when they cross the boundary of the first area A1 and the second area A2; a second structure in which the gaps between the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 change when they cross the boundary of the first area A1 and the second area A2; and / or a third structure in which the second component CP2 is disposed below the unit signal lines SL1, SL2, ... and SLn.

[0092] Therefore, degradation of signal integrity of each of the unit signal lines SL1, SL2, ..., and SLn can be prevented or reduced. Therefore, transmission performance of high-speed signals through the unit signal lines SL1, SL2, ..., and SLn can be improved. Therefore, display quality of the display device DD can be improved.

[0093] Figure 8 According to the embodiment Figure 1 An enlarged plan view of area A. Fig. 9 It is along Figure 8 A cross-sectional view taken along line II-II'.

[0094] Except for including the second component CP2' instead of the second component CP2, Figure 8 and Fig. 9 The display device DD described can be used with reference to Figure 3 and Figure 5 The display devices DD described are substantially the same or similar. Therefore, in the case where details are not described, it can be assumed that these elements are at least similar to corresponding elements described elsewhere in the specification.

[0095] Reference Figure 8 and Fig. 9 In an embodiment, the circuit board PCB may include a second component CP2'. The second component CP2' may include elements such as resistors and capacitors. The second component CP2' may be a dummy element that does not substantially affect the electrical characteristics of the circuit board PCB. For example, the second component CP2' may be a zero-ohm resistor.

[0096] In a plan view, the first component CP1 and the second component CP2' may be spaced apart from each other along the first direction DR1, with the first signal lines SL11, SL21, ... and the fifth portion P5 of SLn1 and the second signal lines SL12, SL22, ... and the sixth portion P6 of SLn2 interposed therebetween. For example, in a plan view, the first component CP1 may be located in a direction opposite to the first direction DR1 from the fifth portion P5 of the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and the sixth portion P6 of SLn2, and the second component CP2' may be located in the first direction DR1 from the fifth portion P5 of the first signal lines SL11, SL21, ... and SLn1 and the sixth portion P6 of the second signal lines SL12, SL22, ... and SLn2.

[0097] The second component CP2' may be disposed on at least one of the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3. Specifically, the second component CP2' may be disposed on at least one of the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3, and may be in contact with at least one of the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3. In addition, the second component CP2' may be disposed below the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2. For example, the second component CP2' may be disposed on the base film BSF at a level lower than the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2.

[0098] For example, the second component CP2' can be arranged on a layer used as a ground layer among the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3 and directly contact the ground layer. However, the utility model is not necessarily limited to this. For example, the second component CP2' can be arranged to directly contact a layer used as a power layer among the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3, and directly contact a layer used as a signal layer among the first conductive layer MTL1, the second conductive layer MTL2, and the third conductive layer MTL3.

[0099] Since the second component CP2' is disposed on at least one of the first conductive layer MTL1, the second conductive layer MTL2 and the third conductive layer MTL3 and contacts at least one of the first conductive layer MTL1, the second conductive layer MTL2 and the third conductive layer MTL3, the upper surface of at least one insulating layer disposed on the second component CP2' and below the unit signal lines SL1, SL2, ... and SLn may have a step.

[0100] For example, the second component CP2' may be disposed on the third conductive layer MTL3 to contact the third conductive layer MTL3. In this case, the second component CP2' may be covered by the third insulating layer IL3, and the upper surface of the third insulating layer IL3 may have a step adjacent to the second component CP2'. Specifically, a portion of the upper surface of the third insulating layer IL3 (e.g., a portion of the upper surface of the third insulating layer IL3 overlapping with the second component CP2') may have a height greater than the height of each of the first signal lines SL11, SL21, ... and SLn1 and the second signal lines SL12, SL22, ... and SLn2 than the height of the second component CP2' (e.g., the height of the second component CP2').

[0101] The surface height of the first component CP1 may be greater than that of each of the first and second signal lines SL11, SL21, ..., and SLn1. For example, a portion of the third insulating layer IL3 in which the step is formed may contact the cover CM.

[0102] According to an embodiment, the circuit board PCB may include a first component CP1 and a second component CP2' spaced apart from each other along a first direction DR1, and a fifth portion P5 of the first signal line SL11, SL21, ... and SLn1 and a sixth portion P6 of the second signal line SL12, SL22, ... and SLn2 are interposed between the first component CP1 and the second component CP2'. A portion of the upper surface of the third insulating layer IL3 (e.g., a portion of the upper surface of the third insulating layer IL3 overlapping with the second component CP2') may have a height greater than the height of each of the first signal line SL11, SL21, ... and SLn1 and the second signal line SL12, SL22, ... and SLn2 by a height of the second component CP2' (e.g., the height of the second component CP2'). Therefore, the cover body CM may not contact the first signal line SL11, SL21, ... and SLn1 and the second signal line SL12, SL22, ... and SLn2. Therefore, the degradation of the signal integrity of each of the unit signal lines SL1, SL2, ... and SLn due to contact with the cover body CM can be prevented or reduced. Therefore, the transmission performance of high-speed signals passing through the unit signal lines SL1, SL2, ..., and SLn can be improved. Therefore, the display quality of the display device DD can be improved.

[0103] At the same time, according to the reference Figure 8 and Fig. 9 In the display device DD of the described embodiment, the first signal lines SL11, SL21, ..., and SLn1 and the second signal lines SL12, SL22, ..., and SLn2 may have reference Figure 4 Describe the plane structure or reference Figure 6 In the absence of detailed description, it can be assumed that these elements are at least similar to those in the reference Figure 4 and Figure 6 The corresponding elements are described similarly.

[0104] Fig.10 is a plan view showing a display device according to an embodiment.

[0105] In addition to the location of the data driver DIC', refer to Fig.10 The display device DD' described can be used with reference to Figures 1 to 9 The display devices DD described are substantially identical. Therefore, where details are not described, it can be assumed that these elements are at least similar to corresponding elements described elsewhere in the description.

[0106] Reference Fig.10In the display device DD' according to the embodiment, the data driver DIC' may be disposed on the display panel DP. For example, the data driver DIC' may be disposed in the pad area PA of the display panel DP. For example, the display device DD' may have a chip-on-glass (COG) structure or a chip-on-plastic (COP) structure.

[0107] Fig.11 is a plan view showing a display device according to an embodiment.

[0108] In addition to the position of the data driver DIC" and the position of the circuit board PCB', refer to Fig.11 The display device DD" described can be used with reference to Figures 1 to 9 The display devices DD described are substantially identical. Therefore, where details are not described, it can be assumed that these elements are at least similar to corresponding elements described elsewhere in the description.

[0109] Reference Fig.11 In the display device DD" according to the embodiment, the data driver DIC" may be disposed on the display panel DP. For example, the data driver DIC" may be disposed in the pad area PA of the display panel DP. For example, the display device DD" may have a chip-on-glass (COG) structure or a chip-on-plastic (COP) structure.

[0110] In the display device DD" according to the embodiment, the flexible circuit film FPC (see Figure 1 ). For example, the circuit board PCB' may be directly connected to the display panel DP. The circuit board PCB' may be disposed on one side of the display panel DP. Specifically, the circuit board PCB' may overlap a portion of the pad area PA. The circuit board PCB' may be electrically connected to a pad electrode disposed in the pad area PA. Therefore, the useless space of the display device DD" may be reduced. In addition, the manufacturing process of the display device DD" may be simplified and the manufacturing cost of the display device DD" may be reduced.

[0111] At the same time, in addition to arranging the location, refer to Fig.11 The circuit board PCB' (or its components) described may be compared with the reference Figures 1 to 9 The described circuit boards PCB (or components thereof) are substantially identical and, therefore, where details are not described, it may be assumed that these elements are at least similar to the described corresponding elements.

[0112] The utility model should not be interpreted as necessarily being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be detailed and complete, and will fully convey the concept of the utility model to those skilled in the art.

[0113] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention.

Claims

1. A display device, characterized in that: The display device comprises: A display panel including pixels; and a circuit board, electrically connected to the display panel, Wherein, the circuit board comprises: a base film having a first region overlapping at least a portion of the connector and a second region spaced apart from the connector; and A unit signal line is provided on the base film, the unit signal line is electrically connected to the connector, and the unit signal line has a first characteristic impedance in the first region and a second characteristic impedance in the second region, the second characteristic impedance being smaller than the first characteristic impedance.

2. The display device according to claim 1, characterized in that The unit signal line comprises: a first signal line extending on the base film beyond a boundary between the first region and the second region, wherein the first signal line includes a first portion disposed in the first region and a second portion disposed in the second region; and a second signal line extending on the base film beyond a boundary between the first region and the second region, The second signal line includes a third portion disposed in the first region and a fourth portion disposed in the second region, Wherein, the first signal line and the second signal line form a differential pair, wherein a first line width of the first portion of the first signal line is smaller than a second line width of the second portion of the first signal line, wherein a third line width of the third portion of the second signal line is smaller than a fourth line width of the fourth portion of the second signal line, wherein a first separation distance between the first portion of the first signal line and the third portion of the second signal line is greater than a second separation distance between the second portion of the first signal line and the fourth portion of the second signal line, and Wherein, a first parasitic capacitance between the first signal line and the second signal line in the first region is smaller than a second parasitic capacitance between the first signal line and the second signal line in the second region.

3. The display device according to claim 2, characterized in that The circuit board further includes a first component and a second component disposed on the base film and spaced apart from each other along a first direction, The fifth portion of the first signal line and the sixth portion of the second signal line are arranged between the first component and the second component.

4. The display device according to claim 3, characterized in that: The display device further includes: a cover body, covering the fifth portion of the first signal line and the sixth portion of the second signal line, wherein the cover is spaced apart from the fifth portion of the first signal line and the sixth portion of the second signal line, and Wherein, the cover is a conductive tape.

5. The display device according to claim 3, characterized in that: The first component, the second component, the first signal line, and the second signal line are arranged at the same level on the base film, and Wherein, a height of each of the first component and the second component is greater than a height of each of the first signal line and the second signal line.

6. The display device according to claim 3, characterized in that: The circuit board also includes: at least one conductive layer disposed on the base film, and the at least one conductive layer is below the first signal line and the second signal line; and an insulating layer, disposed on the conductive layer and the second component, and the insulating layer is below the first signal line and the second signal line, wherein the first component, the first signal line and the second signal line are arranged at the same level on the base film, wherein the second component is disposed on the conductive layer to directly contact the conductive layer, and the second component is covered by the insulating layer, and A portion of the upper surface of the insulating layer overlapping the second component has a height greater than a height of each of the first signal line and the second signal line.

7. A display device, characterized in that: The display device comprises: A display panel including pixels; and a circuit board, electrically connected to the display panel, Wherein, the circuit board comprises: matrix membrane; A first component and a second component are disposed on the base film, and the first component and the second component are spaced apart from each other along a first direction; a first signal line disposed on the base film, the first signal line extending in a second direction intersecting the first direction, wherein the first signal line includes a first portion disposed between the first component and the second component; and a second signal line, disposed on the base film, the second signal line extending in the second direction, The second signal line includes a second portion arranged between the first component and the second component.

8. The display device according to claim 7, characterized in that: The display device further includes: a cover body, covering the first portion of the first signal line and the second portion of the second signal line, wherein the cover is spaced apart from the first portion of the first signal line and the second portion of the second signal line, and The first signal line and the second signal line form a differential pair.

9. The display device according to claim 7, characterized in that: The first component, the second component, the first signal line, and the second signal line are arranged at the same level on the base film, Wherein, a height of each of the first component and the second component is greater than a height of each of the first signal line and the second signal line.

10. The display device according to claim 7, characterized in that: The circuit board also includes: at least one conductive layer disposed on the base film, and the at least one conductive layer is below the first signal line and the second signal line; and an insulating layer, disposed on the conductive layer and the second component, and the insulating layer is below the first signal line and the second signal line, wherein the first component, the first signal line and the second signal line are arranged at the same level on the base film, wherein the second component is disposed on the conductive layer to directly contact the conductive layer, and the second component is covered by the insulating layer, and A portion of the upper surface of the insulating layer overlapping the second component has a height greater than a height of each of the first signal line and the second signal line.

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