Frequency converter buffer relay pull-in detection circuit

Abstract

The utility model relates to a frequency converter buffer relay pull-in detection circuit comprising a frequency converter main circuit. The buffer relay control circuit is connected with the frequency converter main circuit and used for controlling connection and disconnection of a buffer relay in the frequency converter main circuit; the buffer relay pull-in state detection circuit is connected with the frequency converter main circuit and is used for detecting whether the voltage at the two ends of a buffer relay coil is lower than the minimum working voltage of a buffer relay and outputting a fault signal; the DSP processor is respectively connected with the buffer relay pull-in state detection circuit and the buffer relay control circuit and is used for receiving the fault signal and sending an REC signal to the buffer relay control circuit according to the fault signal, and the buffer relay control circuit controls pull-in and disconnection of the buffer relay according to the received REC signal. Therefore, the frequency converter main circuit allows the inverter circuit to output or forbids the inverter circuit to output. According to the utility model, the problem that in the power-on process of the frequency converter, when the control circuit of the buffer relay fails, the buffer relay is not closed, so that the power-on buffer resistor is damaged during the output of the inverter circuit is effectively solved.

Description

Technical Field

[0001] The utility model relates to the technical field of frequency converter buffer relays, in particular to a frequency converter buffer relay pull-in detection circuit. Background Art

[0002] The frequency converter is an electric power control device that uses frequency conversion technology and microelectronics technology to control AC motors by changing the frequency of the motor's working power supply.

[0003] At present, the buffer relay often fails to close during the use of the inverter, resulting in the power-on buffer resistor connected in parallel with the buffer relay exceeding the rated power and being damaged when the inverter circuit is output. The main reason for the buffer relay not closing is that the buffer relay control circuit fails, causing the voltage across the coil of the buffer relay to be lower than the minimum working voltage of the buffer relay and unable to work.

[0004] Therefore, there is an urgent need to provide a frequency converter buffer relay pull-in detection circuit to solve the above problems. Utility Model Content

[0005] The purpose of the utility model is to overcome the shortcomings and defects of the prior art and provide a frequency converter buffer relay closure detection circuit to solve the problem that when the control circuit of the buffer relay fails during the power-on process of the frequency converter, the buffer relay does not close, thereby causing damage to the power-on buffer resistor when the inverter circuit outputs.

[0006] The purpose of this utility model is achieved through the following technical solutions:

[0007] A frequency converter buffer relay pull-in detection circuit, comprising

[0008] Inverter main circuit;

[0009] The buffer relay control circuit is connected to the inverter main circuit and is used to control the closing and opening of the buffer relay in the inverter main circuit;

[0010] The buffer relay closure state detection circuit is connected to the inverter main circuit and is used to detect whether the voltage across the buffer relay coil is lower than the minimum working voltage of the buffer relay and output a fault signal;

[0011] The DSP processor is respectively connected to the buffer relay closure state detection circuit and the buffer relay control circuit, and is used for receiving a fault signal and sending a REC signal to the buffer relay control circuit according to the fault signal. The buffer relay control circuit controls the closure and disconnection of the buffer relay according to the received REC signal, so that the inverter main circuit allows the inverter circuit to output or prohibits the inverter circuit from outputting.

[0012] As a preferred technical solution of the utility model, the inverter main circuit includes a rectifier circuit, a power-on buffer circuit, a filter circuit, and an inverter circuit; wherein the rectifier circuit includes a rectifier bridge D1, the power-on buffer circuit includes a power-on buffer resistor R1 and a buffer relay K1, the filter circuit includes a capacitor E1 and a capacitor E2, and the inverter circuit includes an IGBT module Q1, an IGBT module Q2, an IGBT module Q3, an IGBT module Q4, an IGBT module Q5, and an IGBT module Q6.

[0013] As a preferred technical solution of the utility model, the buffer relay K1 includes a coil and a contact switch BC. When the A1 and A2 ends of the coil are energized, the contact switch BC is energized. When the A1 and A2 ends of the coil are deenergized, the contact switch BC is disconnected.

[0014] As a preferred technical solution of the utility model, the buffer relay control circuit includes a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a transistor Q7, and a photocoupler PC1. One end of the resistor R2 is connected in series with an input pin 1 of the photocoupler PC1, and the other end of the resistor R2 is connected to a +5V power supply. The input pin 2 of the photocoupler PC1 is used to receive a REC signal. The output pin 3 of the photocoupler, the resistor R3, and the resistor R4 are connected in series. The output pin 4 of the photocoupler PC1 is connected to a +24V power supply. The capacitor C1 is connected in parallel with the resistor R4. The common point of the resistor R3 and the resistor R4 is connected to the base of the transistor Q7. The end of the resistor R4 away from the resistor R3 is connected to the emitter of the transistor Q7 and is also connected to COM. The collector of the transistor Q7 is connected to the A1 end of the coil of the buffer relay K1, and the A2 end of the coil of the buffer relay K1 is connected to the +24V power supply.

[0015] As a preferred technical solution of the utility model, the buffer relay pull-in state detection circuit includes a capacitor C2, a resistor R5, a resistor R6, a voltage regulator tube Z1, and a photocoupler PC2. The common contact of the capacitor C2 and the resistor R5 is connected to the A2 end of the coil, and the common contact of the capacitor C2 and the photocoupler PC2 is connected to the A1 end of the coil. The resistor R5, the voltage regulator tube Z1, and the input end of the photocoupler PC2 are connected in series. The resistor R6 and the output pin 4 of the photocoupler PC2 are connected in series. The end of the resistor R6 away from the photocoupler PC2 is connected to a +5V power supply. The common contact of the resistor R6 and the photocoupler PC2 is used to output a fault signal FAULT, and the fault signal FAULT is sent to the DSP processor. The output pin 3 of the photocoupler PC2 is connected to GND.

[0016] Compared with the prior art, the utility model has the following beneficial effects:

[0017] The utility model detects whether the voltage across the coil of the buffer relay is lower than the minimum working voltage of the buffer relay. When the voltage across the coil of the relay is lower than the minimum working voltage of the relay, it is determined that a fault occurs in the relay control circuit, and the buffer relay closure state detection circuit outputs a fault signal to the DSP processor. The DSP processor prohibits the inverter circuit from outputting, thereby protecting the power-on buffer resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the principle diagram of the inverter buffer relay pull-in detection circuit of the utility model.

[0019] Figure 2 This is the main circuit schematic diagram of the frequency converter of the utility model. DETAILED DESCRIPTION

[0020] The present invention is further described in detail below in conjunction with embodiments and drawings, but the implementation manner of the present invention is not limited thereto.

[0021] The specific implementation process of the utility model is as follows:

[0022] like Figure 1 As shown, the inverter main circuit includes a rectifier circuit, a power-on buffer circuit, a filter circuit, and an inverter circuit; the rectifier circuit includes a rectifier bridge D1, the power-on buffer circuit includes a power-on buffer resistor R1 and a buffer relay K1, the filter circuit includes capacitors E1 and E2, and the inverter circuit includes IGBT modules Q1, IGBT modules Q2, IGBT modules Q3, IGBT modules Q4, IGBT modules Q5, and IGBT modules Q6. Among them, the buffer relay K1 includes a coil and a contact switch BC. When the A1 and A2 ends of the coil are energized, the contact switch BC is energized, and when the A1 and A2 ends of the coil are deenergized, the contact switch BC is disconnected. The working principle of the existing inverter is: the three-phase AC power supply is connected from the R, S, and T terminals, and is rectified into a unidirectional pulsating DC power supply through the rectifier bridge D1 of the rectifier circuit, and the pulsating DC power is smoothed by the filter circuit to reduce voltage fluctuations. When the inverter is just powered on, in order to prevent capacitors E1 and E2 from being subjected to excessive impact current, the power-on buffer resistor R1 will be used to limit the current. When the voltage of capacitors E1 and E2 in the filter circuit gradually rises to the preset maximum value, the buffer relay K1 is energized. After the buffer relay K1 is energized, the power-on buffer resistor R1 is short-circuited, so that the current is no longer limited and no longer participates in the circuit operation. The inverter circuit starts to work, converting the stable direct current into three-phase alternating current with adjustable frequency and voltage. The three-phase alternating current output by the inverter circuit is connected to the motor through the UVW terminal to drive the motor to run.

[0023] During the use of the inverter, the buffer relay often fails to attract, resulting in the power-on buffer resistor R1 connected in parallel with the buffer relay exceeding the rated power and being damaged when the inverter circuit is outputting. The main reason for the buffer relay not attracting is that there is a fault in the buffer relay control circuit, which makes the voltage across the coil of the buffer relay lower than the minimum working voltage of the buffer relay and cannot work. The utility model proposes a frequency converter buffer relay attraction detection circuit. When the inverter circuit is outputting, it first detects whether the buffer relay is attracted. When it is detected that the buffer relay is attracted, the inverter circuit is allowed to output; when it is detected that the buffer relay is not attracted, the inverter circuit is prohibited from outputting to protect the power-on buffer resistor R1.

[0024] like Figure 2 As shown, a frequency converter buffer relay pickup detection circuit includes

[0025] Inverter main circuit;

[0026] The buffer relay control circuit is connected to the inverter main circuit and is used to control the closing and opening of the buffer relay in the inverter main circuit;

[0027] The buffer relay closure state detection circuit is connected to the inverter main circuit and is used to detect whether the voltage across the buffer relay coil is lower than the minimum working voltage of the buffer relay and output a fault signal;

[0028] The DSP processor is respectively connected to the buffer relay closure state detection circuit and the buffer relay control circuit, and is used for receiving a fault signal and sending a REC signal to the buffer relay control circuit according to the fault signal. The buffer relay control circuit controls the closure and disconnection of the buffer relay according to the received REC signal, so that the inverter main circuit allows the inverter circuit to output or prohibits the inverter circuit from outputting.

[0029] In the embodiment of the utility model, the buffer relay control circuit includes a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a transistor Q7, and a photocoupler PC1. One end of the resistor R2 is connected in series with an input pin 1 of the photocoupler PC1, and the other end of the resistor R2 is connected to a +5V power supply. The input pin 2 of the photocoupler PC1 is used to receive a REC signal, and the REC signal is sent by a DSP processor to control the closing and disconnection of the buffer relay K1. The output pin 3 of the photocoupler, the resistor R3, and the resistor R4 are connected in series, and the output pin 4 of the photocoupler PC1 is connected to a +24V power supply. The capacitor C1 is connected in parallel with the resistor R4 to play an anti-interference role and prevent the buffer relay control circuit from being triggered by mistake. The common point of resistor R3 and resistor R4 is connected to the base of transistor Q7, the end of resistor R4 away from resistor R3 is connected to the emitter of transistor Q7 and connected to COM at the same time, the collector of transistor Q7 is connected to the A1 end of the coil of buffer relay K1, and the A2 end of the coil of buffer relay K1 is connected to the +24V power supply. Specifically, when the buffer relay control circuit receives the REC signal of the DSP processor at a low level, a current flows through the output end of the photocoupler PC1, and the current enters the base of transistor Q7 through resistor R3 to turn on transistor Q7, at which time the +24V power supply will be added to the two ends of the coil of buffer relay K1 to make buffer relay K1 close; when the REC signal sent by the DSP processor is received at a high level, no current flows through the output end of the photocoupler PC1, transistor Q7 is not turned on, at which time the +24V power supply will not be added to the two ends of the coil of buffer relay K1, and buffer relay K1 will be disconnected.

[0030] In an embodiment of the utility model, the buffer relay pull-in state detection circuit includes a capacitor C2, a resistor R5, a resistor R6, a voltage regulator tube Z1, and a photocoupler PC2. The common point of the capacitor C2 and the resistor R5 is connected to the A2 end of the coil, the common point of the capacitor C2 and the photocoupler PC2 is connected to the A1 end of the coil, the resistor R5, the voltage regulator tube Z1, and the input end of the photocoupler PC2 are connected in series, the resistor R6 and the output pin 4 of the photocoupler PC2 are connected in series, the end of the resistor R6 away from the photocoupler PC2 is connected to a +5V power supply, the common point of the resistor R6 and the photocoupler PC2 is used to output a fault signal FAULT, and the fault model FAULT is sent to the DSP processor, and the output pin 3 of the photocoupler PC2 is connected to GND. Specifically, the two ends of the capacitor C2 are respectively connected to the A1 end and the A2 end of the coil of the buffer relay K1, and the function is to filter the voltage at the two ends of the coil of the buffer relay K1 to remove the interference signal that affects the measurement result. Since the operating voltage of the Zener diode Z1 is lower than the minimum operating voltage of the buffer relay K1, when the voltage across the coil of the buffer relay K1 is not lower than the minimum operating voltage of the buffer relay K1, the voltage across the capacitor C2 will be higher than the operating voltage of the Zener diode Z1, and current will flow through the series circuit composed of the resistor R5, the Zener diode Z1, and the input end of the photocoupler PC2, and the fault signal FAULT will be output as a low level; on the contrary, when the voltage across the coil of the buffer relay K1 is lower than the minimum operating voltage of the buffer relay K1, the voltage across the coil of the buffer relay K1 is 0V, that is, there is no voltage across the coil of the buffer relay K1. At this time, the voltage across the capacitor C2 will be lower than the operating voltage of the Zener diode Z1, and no current will flow through the series circuit composed of the resistor R5, the Zener diode Z1, and the input end of the photocoupler PC2, and the fault signal FAULT will be output as a high level.

[0031] The working principle of the utility model is as follows: a three-phase AC power supply is connected from R, S, and T terminals, and is rectified into a unidirectional pulsating DC power supply through a rectifier circuit, and a power-on buffer resistor R1 limits the impact current of a capacitor E1 and a capacitor E2 when power is first turned on. When the voltage of the capacitor E1 and the capacitor E2 reaches a maximum value, a REC signal sent by a DSP processor changes from an initial high level to a low level. After a delay of a period of time, the DSP processor begins to detect a fault signal FAULT output by a buffer relay closed state detection circuit. When the detected fault signal FAULT is at a low level, it is proved that the buffer relay control circuit works normally, the voltage across the buffer relay K1 coil is not lower than the minimum working voltage of the buffer relay K1, and the DSP processor allows the inverter circuit to output; when the detected fault signal FAULT is at a high level, it is proved that a fault occurs in the buffer relay control circuit, the voltage across the buffer relay K1 coil is lower than the minimum working voltage of the buffer relay K1, and the DSP processor prohibits the inverter circuit from outputting to protect the power-on buffer resistor R1.

[0032] The above-mentioned embodiments only express the implementation methods of the utility model, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent of the utility model. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the utility model, and these all belong to the protection scope of the utility model. Therefore, the protection scope of the utility model patent shall be based on the attached claims.

Claims

1. A frequency converter buffer relay pickup detection circuit, characterized in that: include Inverter main circuit; The buffer relay control circuit is connected to the inverter main circuit and is used to control the closing and opening of the buffer relay in the inverter main circuit; The buffer relay closure state detection circuit is connected to the inverter main circuit and is used to detect whether the voltage across the buffer relay coil is lower than the minimum working voltage of the buffer relay and output a fault signal; The DSP processor is respectively connected to the buffer relay closure state detection circuit and the buffer relay control circuit, and is used for receiving a fault signal and sending a REC signal to the buffer relay control circuit according to the fault signal. The buffer relay control circuit controls the closure and disconnection of the buffer relay according to the received REC signal, so that the inverter main circuit allows the inverter circuit to output or prohibits the inverter circuit from outputting.

2. A frequency converter buffer relay pickup detection circuit according to claim 1, characterized in that: The inverter main circuit includes a rectifier circuit, a power-on buffer circuit, a filter circuit, and an inverter circuit; wherein the rectifier circuit includes a rectifier bridge D1, the power-on buffer circuit includes a power-on buffer resistor R1 and a buffer relay K1, the filter circuit includes capacitors E1 and E2, and the inverter circuit includes IGBT modules Q1, IGBT modules Q2, IGBT modules Q3, IGBT modules Q4, IGBT modules Q5, and IGBT modules Q6.

3. A frequency converter buffer relay pickup detection circuit according to claim 2, characterized in that: The buffer relay K1 includes a coil and a contact switch BC. When the A1 end and the A2 end of the coil are energized, the contact switch BC is energized. When the A1 end and the A2 end of the coil are deenergized, the contact switch BC is disconnected.

4. A frequency converter buffer relay pickup detection circuit according to claim 1, characterized in that: The buffer relay control circuit includes a resistor R2, a resistor R3, a resistor R4, a capacitor C1, a transistor Q7, and a photocoupler PC1. One end of the resistor R2 is connected in series with an input pin 1 of the photocoupler PC1, and the other end of the resistor R2 is connected to a +5V power supply. The input pin 2 of the photocoupler PC1 is used to receive a REC signal. The output pin 3 of the photocoupler, the resistor R3, and the resistor R4 are connected in series. The output pin 4 of the photocoupler PC1 is connected to a +24V power supply. The capacitor C1 is connected in parallel with the resistor R4. The common point of the resistor R3 and the resistor R4 is connected to the base of the transistor Q7. One end of the resistor R4 away from the resistor R3 is connected to the emitter of the transistor Q7 and is also connected to COM. The collector of the transistor Q7 is connected to the A1 end of the coil of the buffer relay K1, and the A2 end of the coil of the buffer relay K1 is connected to the +24V power supply.

5. The inverter buffer relay pickup detection circuit according to claim 1, characterized in that: The buffer relay closure state detection circuit includes a capacitor C2, a resistor R5, a resistor R6, a voltage regulator tube Z1, and a photocoupler PC2. The common contact of the capacitor C2 and the resistor R5 is connected to the A2 end of the coil, and the common contact of the capacitor C2 and the photocoupler PC2 is connected to the A1 end of the coil. The resistor R5, the voltage regulator tube Z1, and the input end of the photocoupler PC2 are connected in series. The resistor R6 and the output pin 4 of the photocoupler PC2 are connected in series. The end of the resistor R6 away from the photocoupler PC2 is connected to a +5V power supply. The common contact of the resistor R6 and the photocoupler PC2 is used to output a fault signal FAULT. The fault signal FAULT is sent to the DSP processor. The output pin 3 of the photocoupler PC2 is connected to GND.

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