Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof. Wherein the gate driving unit comprises a pull-up control module (the control end of the pull-up control module loads a pull-up control signal), a pull-up module (the input end of the pull-up module electrically loads the pull-up signal), a pull-down module (the input end of the pull-down module loads a pull-down signal), a pull-down control module (the control end of the pull-down control module is connected to the output end of the pull-up control module) and a voltage stabilizing module (the voltage stabilizing module is used for stabilizing the voltage; the output end of the pull-up control module, the control end of the pull-up module and the output end of the voltage stabilization module are connected to the pull-up node, and the output end of the pull-down control module and the control end of the pull-down module are connected to the pull-down node. The output end of the pull-up module and the output end of the pull-down module are both connected to the output end of the gate driving unit, and the amplitude of the pulse of the gate signal output by the output end of the gate driving unit is larger than the amplitude of the pulse in a time period outside the pulse.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display device and a driving method thereof. Background Art

[0002] GOA (Gate-driver On Array) technology is conducive to the narrow bezel design of display devices, and thus has been widely applied. However, when the existing GOA circuit generates gate signals, it is difficult to generate gate signals with effective pulses having a small pulse width and a high potential through fewer devices, which limits the application scenarios of the GOA circuit. Summary of the Invention

[0003] Embodiments of this application provide a display device and a driving method thereof to solve the problem that the existing GOA circuit is difficult to generate effective pulses with a small pulse width and a high potential through fewer devices.

[0004] Embodiments of this application provide a display device, including a gate driving circuit, where the gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes:

[0005] A pull-up control module, where a control end of the pull-up control module is electrically connected to a corresponding pull-up control signal line, and an output end of the pull-up control module is electrically connected to a corresponding pull-up node;

[0006] A pull-up module, where an input end of the pull-up module is electrically connected to a corresponding pull-up signal line, a control end of the pull-up module is electrically connected to the corresponding pull-up node, and an output end of the pull-up module is electrically connected to an output end of the gate driving unit;

[0007] A pull-down control module, where a control end of the pull-down control module is electrically connected to an output end of the pull-up control module, and an output end of the pull-down control module is electrically connected to a corresponding pull-down node;

[0008] A pull-down module, where an input end of the pull-down module is electrically connected to a corresponding pull-down signal line, a control end of the pull-down module is electrically connected to the corresponding pull-down node, and an output end of the pull-down module is electrically connected to an output end of the gate driving unit;

[0009] A voltage stabilizing module, where a control end of the voltage stabilizing module is electrically connected to the corresponding pull-down node, and an output end of the voltage stabilizing module is electrically connected to the corresponding pull-up node;

[0010] Wherein, an amplitude of a pulse of the gate signal output by the output end of the gate driving unit is greater than an amplitude of the gate signal in a period other than the corresponding pulse.

[0011] Embodiments of the present application further provide a driving method for a display device, which is applied to the display device described in any of the above, and includes:

[0012] In the first stage, the pull-up control module responds to the pull-up control signal transmitted on the pull-up control signal line, and controls the potential of the pull-up node to a corresponding effective potential according to the frame start signal or the gate signals of the previous i levels, so that the pull-up module outputs a corresponding first gate signal according to the pull-up signal transmitted on the pull-up signal line;

[0013] In the second stage after the first stage, the pull-up control module responds to the pull-up control signal, and controls the pull-down control module to turn on according to the frame start signal or the gate signals of the previous i levels, so that the potential of the pull-down node is a corresponding effective potential, so that the pull-down module outputs a corresponding second gate signal according to the pull-down signal transmitted on the pull-down signal line, and the amplitude of the effective potential of the first gate signal is greater than the amplitude of the ineffective potential of the first gate signal and the amplitude of the second gate signal.

[0014] The present application provides a display device and its driving method. The gate driving unit therein includes a pull-up control module (whose control terminal is loaded with a pull-up control signal), a pull-up module (whose input terminal is electrically loaded with a pull-up signal), a pull-down module (whose input terminal is loaded with a pull-down signal), a pull-down control module (whose control terminal is connected to the output terminal of the pull-up control module), and a voltage stabilizing module (whose control terminal is connected to the pull-down node). By connecting the output terminal of the pull-up control module, the control terminal of the pull-up module, and the output terminal of the voltage stabilizing module to the pull-up node, and connecting the output terminal of the pull-down control module and the control terminal of the pull-down module to the pull-down node, and connecting the output terminals of the pull-up module and the pull-down module to the output terminal of the gate driving unit, and the amplitude of the pulse of the gate signal output by the output terminal of the gate driving unit is greater than its amplitude during the period outside the pulse, the number of devices of the gate driving unit is reduced while a gate signal with a high-potential pulse can be formed. Description of the Drawings

[0015] Figure 1 It is an architecture diagram of the display device provided by the embodiment of the present application.

[0016] Figure 2 and Figure 3 It is a circuit diagram of the gate driving unit provided by the embodiment of the present application.

[0017] Figure 4 and Figure 5 It is a timing diagram of some signals in the gate driving unit provided by the embodiment of the present application.

[0018] Figure 6Flow chart of the driving method of the display device provided by the embodiment of the present application. Detailed implementation manners

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application. Mentioning "embodiment" in this document means that the specific features, structures or characteristics described in connection with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0020] It should be noted that the "effective potential" in the present application can be understood as the potential in the signal used to control the corresponding device to turn on, which can be the corresponding high potential or low potential.

[0021] The embodiment of the present application provides a display device, and the display device includes but is not limited to the following embodiments and combinations of the following embodiments.

[0022] In some embodiments, in combination with Figures 1 to 3As shown, the display device 100 includes a gate driving circuit 10, the gate driving circuit 10 includes a plurality of cascaded gate driving units 101, and the gate driving unit 101 includes: a pull-up control module 201, a control end of the pull-up control module 201 is electrically connected to a corresponding pull-up control signal line (for transmitting a pull-up control signal, the pull-up control signal is, for example but not limited to, a first clock signal XCK), an output end of the pull-up control module 201 is electrically connected to a corresponding pull-up node Q; a pull-up module 202, an input end of the pull-up module 202 is electrically connected to a corresponding pull-up signal line (for transmitting a pull-up signal, the pull-up signal is, for example but not limited to, transmitting a second clock signal CK), a control end of the pull-up module 202 is electrically connected to the corresponding pull-up node Q, and an output end of the pull-up module 202 is electrically connected to an output end of the gate driving unit 101; a pull-down control module 203, a control end of the pull-down control module 203 is electrically connected to an output end of the pull-up control module 201 (i.e., a pre-pull-up node K), and an output end of the pull-down control module 203 is electrically connected to a corresponding pull-down node P; a pull-down module 204, an input end of the pull-down module 204 is electrically connected to a corresponding pull-down signal line (for transmitting a pull-down signal, the pull-down signal is, for example but not limited to, a low voltage signal VGL), a control end of the pull-down module 204 is electrically connected to the corresponding pull-down node P, and an output end of the pull-down module 204 is electrically connected to an output end of the gate driving unit 101; a voltage stabilizing module 205, a control end of the voltage stabilizing module 205 is electrically connected to the corresponding pull-down node P, and an output end of the voltage stabilizing module 205 is electrically connected to the corresponding pull-up node Q; wherein, as Figure 4 and Figure 5 shown, an amplitude of a pulse p of a gate signal Gate output from an output end of the gate driving unit 101 is greater than an amplitude of the gate signal Gate during a period other than the corresponding pulse p.

[0023] Specifically, as Figure 1 shown, the display device 100 may include a display panel 30, the display panel 30 may include a plurality of sub-pixels 301 and the above-mentioned gate driving circuit 10 located on one side of the plurality of sub-pixels 301. The display device 100 may further include a timing controller 401 and at least one source driver 402. The timing controller 401 and the at least one source driver 402 may be integrated on the same chip or may be independently provided. Each gate driving unit 101 may be electrically connected between the timing controller 401 and the corresponding plurality of sub-pixels 301 for outputting a gate signal Gate transmitted to the corresponding plurality of sub-pixels 301; each source driver 402 is electrically connected between the timing controller 401 and the corresponding plurality of sub-pixels 301 for outputting a data signal Data transmitted to the corresponding plurality of sub-pixels 301.

[0024] For ease of description, here, an example is given in which multiple sub-pixels 301 are arranged in an array of n rows and m columns (both n and m are positive integers).

[0025] As Figure 1 shown, the gate driving circuit 10 can at least include n levels of gate driving units 101. At least one gate driving unit 101 in the gate driving circuit 10 is controlled by the timing controller 401, so that each gate driving unit 101 generates a corresponding gate signal Gate. The n levels of gate signals Gate are respectively transmitted to n rows of sub-pixels 301 through n gate lines (GL1 to GLn). The n pulses p respectively used to turn on the n rows of sub-pixels 301 in the n levels of gate signals can be arranged in sequence on the time axis to turn on multiple rows of sub-pixels 301 in sequence.

[0026] The source driver 402 is controlled by the timing controller 401 to generate m data signals Data respectively output to m columns of sub-pixels 301 through m data lines (DL1 to DLm). Each data signal Data can include n data voltages corresponding to n sub-pixels 301 in the same column. When each row of sub-pixels 301 is turned on, the multiple data lines respectively receive multiple data voltages corresponding to multiple sub-pixels 301 in that row, so that the multiple data voltages act on the multiple sub-pixels 301 in that row, causing the multiple sub-pixels 301 in that row to emit light. By analogy, all rows of sub-pixels 301 can be controlled to emit light in sequence to present a complete picture.

[0027] Combined with the above discussion, each level of gate driving unit 101 can be loaded with a pull-up control signal including but not limited to the above (such as but not limited to the first clock signal XCK), a pull-up signal (such as but not limited to the second clock signal CK), and a pull-down signal (such as but not limited to the low voltage signal VGL). Each level of gate driving unit 101 can generate and output a corresponding gate signal Gate through its output terminal.

[0028] Among them, the first-level gate driving unit 101 ( Figures 2 to 4Taking only the first-stage gate driving unit 101 as an example (schematically shown), the input end of the pull-up control module 201 can be loaded with the frame start signal STV, and its output end can be electrically connected to at least one corresponding subsequent stage of the gate driving unit 101 to provide the gate signal Gate of the first stage thereto; the output end of the intermediate-stage gate driving unit 101 can be electrically connected to at least one corresponding subsequent stage of the gate driving unit 101 to transmit the gate signal Gate generated by this stage of the gate driving unit 101, that is, the gate driving units 101 from the second stage to the last stage can be electrically connected to the output end of at least one previous stage of the gate driving unit 101 to obtain the required gate signal Gate; and so on, the output end of the last-stage gate driving unit 101 outputs the gate signal Gate of the last stage.

[0029] Among them, Figure 2 and Figure 3 the waveform diagrams of signals such as the first clock signal XCK, the second clock signal CK, the high-voltage signal VGH, the low-voltage signal VGL, the frame start signal STV, the signal SQ of the pull-up node Q, the signal SK of the pre-pull-up node K, and the signal SP of the pull-down node P in Figure 4 and Figure 5 can be respectively referred to. The first clock signal XCK and the second clock signal CK can be clock signals, and the high-voltage signal VGH and the low-voltage signal VGL can be constant voltage signals.

[0030] It can be understood that the pull-up control module 201 in this embodiment is controlled by a pull-up control signal to control the potential of the pull-up node Q. The pull-up module 202 is controlled by the potential of the pull-up node Q to process the pull-up signal and output it to the output end of the gate driving unit 101. Moreover, the pull-down control module 203 is controlled by the potential of the output end of the pull-up control module 201 (i.e., the pre-pull-up node K) to control the potential of the pull-down node P. Further, the pull-down module 204 is controlled by the potential of the pull-down node P to process the pull-down signal and output it to the output end of the gate driving unit 101. On this basis, this embodiment also sets a voltage stabilizing module 205 controlled by the potential of the pull-down node P, which can control at least the potential of the pull-up node Q according to the potential of the pull-down node P to play a role in stabilizing the potential of the pull-up node Q. At the same time, this embodiment controls the change of the potential of the signal at the output end of the gate driving unit 101 (i.e., the waveform of the corresponding gate signal Gate) through the collaborative action of the above-mentioned multiple modules, so as to achieve that the amplitude of the pulse p of the gate signal Gate is greater than the amplitude of the gate signal Gate during the period other than the corresponding pulse p, that is, the amplitude of the pulse p of the gate signal Gate is the high potential corresponding to the gate signal Gate. And through the action of the above-mentioned voltage stabilizing module 205, the stability of the gate signal Gate can also be improved, and only the above-mentioned multiple modules are used, avoiding using more devices to form the gate driving unit 101.

[0031] In some embodiments, as shown in Figures 2 to 5 The pull-up signal (such as the second clock signal CK) transmitted by the pull-up signal line is a clock signal, and the pull-down signal (such as the low voltage signal VGL) transmitted by the pull-down signal line is a constant voltage signal (a signal with a fixed amplitude). Among them, the pulse width of the pulse p of the gate signal Gate is equal to the duration of the effective potential of the pull-up signal. Combining the above discussion, it can be known that the pull-up module 202 is controlled by the potential of the pull-up node Q to process the pull-up signal and output it to the output end of the gate driving unit 101. And the pull-up control signal must include alternately arranged effective potentials (such as controlling the corresponding transistor in the corresponding sub-pixel 301 to conduct) and invalid potentials (such as controlling the corresponding transistor in the corresponding sub-pixel 301 to cut off). And this embodiment can be understood as at least controlling the potential of the pull-up node Q by setting the pull-up control module 201, and at least through the setting of the pull-up module 202, and then jointly realizing the processing of the pull-up signal by the pull-up module 202. At the same time, it also at least controls the potential of the pull-down node P through the pull-down control module 203, and at least through the setting of the pull-down module 204, and then jointly realizes the processing of the pull-down signal by the pull-down module 204 to generate a gate signal Gate with the pulse width of the pulse p equal to the duration of the effective potential of the pull-up control signal, thereby avoiding a relatively large pulse width of the pulse p of the gate signal Gate.

[0032] Furthermore, the amplitude of the pulse p of the gate signal Gate can also be equal to the effective potential of the pull-up signal. For example, by controlling the time-sharing operation of both the pull-up module 202 and the pull-down module 204, the amplitude of the gate signal Gate output from the output terminal of the gate driving unit 101 can be controlled to be the amplitude of the current pull-up signal or the amplitude of the current pull-down signal. Therefore, it can be considered that the potential of the pull-up node Q and the potential of the pull-down node P can respectively control the working period of the pull-up module 202 and the working period of the pull-down module 204, thereby controlling the waveform of the gate signal Gate.

[0033] In some embodiments, in combination with Figures 2 to 5 As shown, the amplitude of the pull-up signal (such as the second clock signal CK) transmitted by the pull-up signal line includes alternately arranged first amplitude a1 (such as one of the above-mentioned effective potential and ineffective potential) and second amplitude a2 (such as the other of the above-mentioned effective potential and ineffective potential). The voltage stabilization module 205 includes: a first voltage stabilization transistor T5. One of the source and drain of the first voltage stabilization transistor T5 (such as the source) is electrically connected to the output terminal of the pull-up control module 201 (i.e., the pre-pull-up node K), and the other (such as the drain) is electrically connected to the corresponding pull-up node Q. Wherein, the first voltage stabilization transistor T5 is cut off when the pull-up module 202 is turned on and the amplitude of the pull-up signal switches from the first amplitude a1 to the second amplitude a2.

[0034] Among them, "the pull-up module 202 is turned on" can be understood as when the pull-up control module 201 controls the potential of the pre-pull-up node K to be the corresponding effective potential, the first voltage stabilization transistor T5 has been turned on to transmit the effective potential of the pre-pull-up node K to the pull-up node Q, and then the pull-up module 202 is turned on. However, at this time, if the amplitude of the pull-up signal switches from the first amplitude a1 to the second amplitude a2, at least due to the coupling effect of the parasitic capacitance, after the potential of the pull-up node Q changes accordingly, it will be transmitted to the pre-pull-up node K through the first voltage stabilization transistor T5, which will at least affect the working state of the pull-down control module 203, so as to affect the waveform of the gate signal Gate.

[0035] Therefore, in this embodiment, a first voltage stabilization transistor T5 is provided between the pre-pull-up node K and the pull-up node Q, and the first voltage stabilization transistor T5 is controlled to be cut off when the pull-up module 202 is turned on and the amplitude of the pull-up signal switches from the first amplitude a1 to the second amplitude a2, which can at least avoid the influence of the current potential of the pull-up node Q on the waveform of the gate signal Gate.

[0036] For example, it can be considered that the change in the potential of the pull-up node Q caused by the switching of the first amplitude a1 to the second amplitude a2 results in the voltage difference between the potential of the gate of the first voltage stabilizing transistor T5 and the potential of the pull-up node Q being greater than or less than the threshold voltage of the first voltage stabilizing transistor T5, thereby turning off the first voltage stabilizing transistor T5.

[0037] Furthermore, it can be considered that the second amplitude a2 is greater than the first amplitude a1, that is, the first voltage stabilizing transistor T5 turns off when the pull-up module 202 is turned on and the amplitude of the pull-up signal rises from the first amplitude a1 to the second amplitude a2.

[0038] In some embodiments, in combination with Figures 2 to 5 as shown, the voltage stabilizing module 205 further includes: a second voltage stabilizing transistor T4, the gate of the second voltage stabilizing transistor T4 is electrically connected to the corresponding pull-down node P, one of the source and the drain of the second voltage stabilizing transistor T4 (for example, the source) is electrically connected to the first voltage line (for transmitting a first voltage signal, and the first voltage signal is, for example but not limited to, a high-voltage signal VGH), and the other (for example, the drain) is electrically connected to the output terminal of the pull-up control module 201 (i.e., the pre-pull-up node K); wherein, the second voltage stabilizing transistor T4 conducts when the pull-up module 202 is turned on and the pull-down module 204 is not turned on, and the first voltage signal (for example, the high-voltage signal VGH) transmitted by the first voltage line is used to stabilize the potential of the output terminal of the pull-up control module 201.

[0039] Combined with the above discussion, it can be known that the second voltage stabilizing transistor T4 is controlled to conduct or turn off by the potential of the pull-down node P. It can be considered that when the pull-down module 204 is not turned on, the potential of the pull-down node P controls the second voltage stabilizing transistor T4 to conduct to transmit the first voltage signal to the pre-pull-up node K, thereby stabilizing the potential of the pre-pull-up node K to its effective potential, and further transmitting this potential to the pull-up node Q through the conducting first voltage stabilizing transistor T5, so that the potential of the pull-up node Q is also maintained at its effective potential, thereby improving the working stability of the pull-up module 202.

[0040] In some embodiments, in combination with Figure 3 and Figure 5As shown, the voltage stabilization module 205 further includes: a third voltage stabilization transistor T8, the gate of the third voltage stabilization transistor T8 is electrically connected to the corresponding pull - down node P, one of the source and the drain of the third voltage stabilization transistor T8 (for example, the source) is electrically connected to the second voltage line (for transmitting a second voltage signal, and the second voltage signal is, for example but not limited to, a low - voltage signal VGL), and the other (for example, the drain) is electrically connected to the corresponding pull - up node Q; wherein, the third voltage stabilization transistor T8 conducts when the pull - down module 204 is turned on and the amplitude of the pull - up signal (for example, the second clock signal CK) rises or falls (for example, falls) from the first amplitude a1 to the second amplitude a2, and the second voltage signal (for example, the low - voltage signal VGL) transmitted by the second voltage line is used to pull down or pull up the potential of the corresponding pull - up node Q.

[0041] Among them, when the "pull - down module 204 is turned on", it can be understood that when the pull - up control module 201 controls the potential of the pre - pull - up node K to be the corresponding invalid potential, the pull - down control module 203 controls the potential of the pull - down node P to be the corresponding valid potential, and then the pull - down module 204 works. However, at this time, if the amplitude of the pull - up signal rises or falls, at least due to the coupling effect of parasitic capacitance, the potential of the pull - up node Q also rises or falls correspondingly, and then is transmitted to the pre - pull - up node K through the first voltage stabilization transistor T5, which at least affects the working state of the pull - down control module 203, so as to affect the waveform of the gate signal Gate.

[0042] Therefore, in this embodiment, a third voltage stabilization transistor T8 is provided between the pull - down node P and the pull - up node Q, and the third voltage stabilization transistor T8 is controlled to conduct when the pull - down module 204 is turned on and the amplitude of the pull - up signal is switched. At least, the second voltage signal can be transmitted to the pull - up node Q to try to offset the jump of the potential of the pull - up node Q due to the above reasons, thereby reducing the influence on the waveform of the gate signal Gate.

[0043] For example, it can be considered that due to the change in the potential of the pull - up node Q caused by the switching from the first amplitude a1 to the second amplitude a2, the first voltage stabilization transistor T5 is still conducting, but at this time, since the third voltage stabilization transistor T8 is also conducting, the change in the potential of the pull - up node Q can be reduced through it, thereby reducing the influence on the waveform of the gate signal Gate.

[0044] Similarly, it can be considered that the second amplitude a2 is greater than the first amplitude a1, that is, the third voltage stabilization transistor T8 conducts when the pull - down module 204 is turned on and the amplitude of the pull - up signal rises from the first amplitude a1 to the second amplitude a2, and the second voltage signal transmitted by the second voltage line is used to pull down the potential of the corresponding pull - up node Q.

[0045] In some embodiments, in combination with Figures 2 to 5 As shown, the pull - down control module 203 includes: a first pull - down control transistor T2, one of the source and drain of the first pull - down control transistor T2 (for example, the source) is electrically connected to a first voltage line (which can be the same as or different from the first voltage line above, here it is the same for example); a second pull - down control transistor T3, one of the source and drain of the second pull - down control transistor T3 (for example, the source) is electrically connected to a second voltage line (which can be the same as or different from the first voltage line above, here it is the same for example); the gates of the first pull - down control transistor T2 and the second pull - down control transistor T3 are both electrically connected to the control terminal of the pull - down control module 203; the other of the source and drain of the first pull - down control transistor T2 (for example, the drain) and the other of the source and drain of the second pull - down control transistor T3 (for example, the drain) are configured as the pull - down node P.

[0046] Wherein, the first pull - down control transistor T2 and the second pull - down control transistor T3 are alternately turned on; one of the first voltage signal (for example, the high - voltage signal VGH) transmitted by the first voltage line and the second voltage signal (for example, the low - voltage signal VGL) transmitted by the second voltage line is used to control the opening of the pull - down module 204, and the other is used to control the closing of the pull - down module 204.

[0047] It can be understood that the first pull - down control transistor T2 and the second pull - down control transistor T3 of this embodiment are both controlled by the potential of the pre - pull - up node K to be turned on or off, and the first voltage signal and the second voltage signal loaded on their sources are two constant - voltage signals with different amplitudes. By respectively setting the first pull - down control transistor T2 and the second pull - down control transistor T3 as two different ones of P - type transistors and N - type transistors, it is possible to achieve the time - division conduction of the first pull - down control transistor T2 and the second pull - down control transistor T3, so as to transmit the first voltage signal and the second voltage signal to the pull - down node P in a time - division manner, and further control the pull - down module 204 to be turned on and off in a time - division manner.

[0048] Furthermore, in order to avoid the influence of the simultaneous opening of the pull - up module 202 and the pull - down module 204 on the waveform of the gate signal Gate, the above - mentioned modules can be reasonably set to control the potential of the pull - up node Q and the potential of the pull - down node P, and further control the pull - up module 202 and the pull - down module 204 to be turned on in a time - division manner.

[0049] In some embodiments, in combination with Figures 2 to 5As shown, the pull-up control module 201 includes: a pull-up control transistor T1. The gate of the pull-up control transistor T1 is configured as the control end of the pull-up control module 201 (loading a pull-up control signal, and the pull-up control signal is, for example but not limited to, a first clock signal XCK). One of the source and drain of the pull-up control transistor T1 (for example, the source) is electrically connected to the input end of the pull-up control module 201, and the other of the source and drain of the pull-up control transistor T1 (for example, the drain) is configured as the output end of the pull-up control module 201. Wherein, the input end of the pull-up control module 201 is electrically connected to the frame start line or the output end of the previous i-stage gate driving units 101, and i is a positive integer.

[0050] Combined with the above discussion, the source of the pull-up control transistor T1 of the first-stage gate driving unit 101 is electrically connected to the frame start line to load the frame start signal STV, and the source of the pull-up control transistor T1 of the non-first-stage gate driving unit 101 is electrically connected to the output end of the previous i-stage gate driving units 101 to load the gate signals Gate of the previous i-stage. That is, the pull-up control transistor T1 is controlled by the pull-up control signal to conduct or cut off, and when conducting, transmits the frame start signal STV or the gate signals Gate of the previous i-stage to the pre-pull-up node K, so that the potential of the pre-pull-up node K is at least the amplitude of the pulse in the frame start signal STV or the gate signals Gate of the previous i-stage during the corresponding period.

[0051] In some embodiments, combined with Figures 2 to 5 As shown, the pull-up module 202 includes: a pull-up transistor T6. The gate of the pull-up transistor T6 is electrically connected to the corresponding pull-up node Q. One of the source and drain of the pull-up transistor T6 (for example, the source) is electrically connected to the pull-up signal line, and the other (for example, the drain) is electrically connected to the output end of the gate driving unit 101. The pull-down module 204 includes: a pull-down transistor T7. The gate of the pull-down transistor T7 is electrically connected to the corresponding pull-down node P. One of the source and drain of the pull-down transistor T7 (for example, the source) is electrically connected to the pull-down signal line, and the other (for example, the drain) is electrically connected to the output end of the gate driving unit 101.

[0052] As described above, the pull-up transistor T6 and the pull-down transistor T7 are respectively turned on or off under the control of the potential of the pull-up node Q and the potential of the pull-down node P. By setting the above-mentioned modules and signals, the potentials of the pull-up node Q and the pull-down node P control the pull-up transistor T6 and the pull-down transistor T7 to be turned on at different times, so that the output terminal of the gate driving unit 101 outputs the current waveform of the pull-up signal (for example, the second clock signal CK) and the current waveform of the pull-down signal (for example, the low-voltage signal VGL) at different times, thereby forming the waveform of the gate signal Gate. Among them, the pulse p of the gate signal Gate can be formed by the effective potential in the pull-up signal.

[0053] Further, the pull-up module 202 further includes: a capacitor C1, electrically connected between the other of the source and the drain of the pull-up transistor T6 (for example, the drain) and the gate of the pull-up transistor T6. It can be understood that since the capacitor C1 is connected between the output terminal of the gate driving unit 101 and the pull-up node Q, when the pull-up transistor T6 is turned on and the gate signal Gate reaches the starting point of its pulse p, it can be considered that the potential change of the gate signal Gate at this time can cause the pull-up node Q to jump correspondingly through the coupling effect of the capacitor C1, thereby increasing the conduction degree of the pull-up transistor T6 and stably outputting the current waveform (its effective potential) of the pull-up signal to make the gate signal Gate form a corresponding pulse p.

[0054] In some embodiments, as shown in Figures 2 to 5 the amplitude of the pull-up signal (for example, the second clock signal CK) transmitted by the pull-up signal line includes alternately arranged first amplitude a1 and second amplitude a2, the amplitude of the pull-up control signal (for example, the first clock signal XCK) transmitted by the pull-up control signal line includes alternately arranged third amplitude a3 and fourth amplitude a4, and the pull-down signal (for example, the low-voltage signal VGL) transmitted by the pull-down signal line is a constant voltage signal; wherein, there is a phase difference between the pull-up signal and the pull-up control signal, and the absolute value of the difference between the smaller of the first amplitude a1 and the second amplitude a2 (for example, the second amplitude a2) and the amplitude of the pull-down signal is less than the absolute value of the difference between the larger of the first amplitude a1 and the second amplitude a2 (for example, the first amplitude a1) and the amplitude of the pull-down signal.

[0055] As described above, when the pull-up control signal (e.g., the first clock signal XCK) is one of the third amplitude a3 and the fourth amplitude a4 (e.g., the third amplitude a3), the pull-up control transistor T1 is turned on, transmitting the frame start signal STV or the gate signal Gate of the previous i levels to the pre-pull-up node K. Then, combined with the functions of the voltage stabilization module 205 and the pull-down control module 203 respectively, the potential of the pull-up node Q and the potential of the pull-down node P are controlled. After that, when the pull-up control signal becomes the other of the third amplitude a3 and the fourth amplitude a4 (e.g., the fourth amplitude a4), the pull-up control transistor T1 is turned off to keep the pre-pull-up node K at the previous potential. Of course, the potential of the pre-pull-up node K can also be affected by the function of the voltage stabilization module 205 thereafter.

[0056] Among them, when the pull-up transistor T6 is turned on, the current waveform of the pull-up signal (at least including its effective potential (e.g., the first amplitude a1)) can be output to form the pulse p of the gate signal Gate. After that, when the pull-down transistor T7 is turned on, the current waveform of the pull-down signal (e.g., the low-voltage signal VGL) can be output to form the waveform after the pulse p of the gate signal Gate.

[0057] As described above, since the amplitude of the pulse p of the gate signal Gate is the high potential of the gate signal Gate, the second amplitude a2 with a smaller value and the amplitude of the pull-down signal can be basically the same to form the low potential of the gate signal Gate, while the value of the first amplitude a1 of the pulse p that forms the gate signal Gate is larger.

[0058] It should be noted that the present invention does not limit the phase difference between the first clock signal XCK and the second clock signal CK acting on the same gate driving unit 101 (e.g., Figure 4 the phase difference between the two can be greater than Figure 5 the phase difference between the two), but the periods, duty cycles, corresponding high potentials, and corresponding low potentials of the two can be equal respectively. The first clock signal XCK acting on different levels of the gate driving unit 101 can be different, and the second clock signal CK can also be different, but the phase difference between the two needs to be the same.

[0059] The present invention also does not limit the magnitude relationship between the constant voltage signal and the amplitude of the clock signal. It can be considered that the low-voltage signal VGL is closer to the low potential corresponding to the clock signal, and the high-voltage signal VGH is closer to the high potential corresponding to the clock signal.

[0060] The present invention does not limit the types of multiple transistors either, as long as the types of multiple transistors match the types of the signals they are loaded with to achieve Figure 4 or Figure 5 the described timing.

[0061] Embodiments of the present application also provide a display device, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0062] In some embodiments, as shown in Figures 1 to 3 Figure 5, the display device 100 includes a gate driving circuit 10, the gate driving circuit 10 includes a plurality of cascaded gate driving units 101, and the gate driving unit 101 includes: a pull-up control transistor T1, one of the source and drain of the pull-up control transistor T1 (for example, the source) is electrically connected to the frame start line or the output terminal of the previous i-stage gate driving unit 101, where i is a positive integer; a first voltage stabilizing transistor T5, one of the source and drain of the first voltage stabilizing transistor T5 (for example, the source) is electrically connected to the other of the source and drain of the pull-up control transistor T1 (for example, the drain), and the other of the source and drain of the first voltage stabilizing transistor T5 (for example, the drain) is electrically connected to the corresponding pull-up node Q; a pull-up transistor T6, the gate of the pull-up transistor T6 is electrically connected to the corresponding pull-up node Q, one of the source and drain of the pull-up transistor T6 (for example, the source) is electrically connected to the pull-up signal line, and the other is electrically connected to the output terminal of the gate driving unit 101; a first pull-down control transistor T2 and a second pull-down control transistor T3, the gates of the first pull-down control transistor T2 and the second pull-down control transistor T3 are both electrically connected to the other of the source and drain of the pull-up control transistor T1, one of the source and drain of the first pull-down control transistor T2 (for example, the drain) and one of the source and drain of the second pull-down control transistor T3 (for example, the drain) are electrically connected to the corresponding pull-down node P; a second voltage stabilizing transistor T4, the gate of the second voltage stabilizing transistor T4 is electrically connected to the corresponding pull-down node P, and one of the source and drain of the second voltage stabilizing transistor T4 (for example, the drain) is electrically connected to the other of the source and drain of the pull-up control transistor T1; a pull-down transistor T7, the gate of the pull-down transistor T7 is electrically connected to the corresponding pull-down node P, one of the source and drain of the pull-down transistor T7 is electrically connected to the pull-down signal line, and the other is electrically connected to the output terminal of the gate driving unit 101; a capacitor C1, which is electrically connected between the other of the source and drain of the pull-up transistor T6 (for example, the drain) and the gate.

[0063] Among them, the connection relationship and the loaded signals of the pull-up control transistor T1, the first pull-down control transistor T2, the second pull-down control transistor T3, the second voltage stabilizing transistor T4, the first voltage stabilizing transistor T5, the pull-up transistor T6, the pull-down transistor T7, and the capacitor C1 can refer to the relevant descriptions above.

[0064] As described above, the pull-up control transistor T1 is turned on or off under the control of a pull-up control signal to transmit a frame start signal or the gate signal Gate of the first i stages to the pre-pull-up node K, or to maintain its previous potential. By adding the second voltage stabilizing transistor T4 and the first voltage stabilizing transistor T5, the potential of the pull-up node Q can be controlled. By adding the first pull-down control transistor T2 and the second pull-down control transistor T3, the potential of the pull-down node P can be controlled. Further, the pull-up transistor T6 is turned on or off under the control of the potential of the pull-up node Q, and after processing the pull-up signal, it is output to the output terminal of the gate driving unit 101. The pull-down transistor T7 is turned on or off under the control of the potential of the pull-down node P, and after processing the pull-down signal, it is output to the output terminal of the gate driving unit 101.

[0065] It can be understood that in this embodiment, only the pull-up control transistor T1 to the pull-down transistor T7 and the capacitor C1 are used, and the corresponding gate signal Gate can be generated through the above connection relationship. By reasonably setting the signals acting on the gate driving unit 101, the amplitude of the pulse p of the gate signal Gate can be made greater than the amplitude of the gate signal Gate during the period other than the corresponding pulse p. Therefore, this embodiment can generate a gate signal Gate with strong stability and high-potential pulses while saving the number of devices in the gate driving unit 101.

[0066] In some embodiments, in combination with Figure 1 and Figure 3 as shown, the gate driving unit 101 further includes: a third voltage stabilizing transistor T8, the gate of the third voltage stabilizing transistor T8 is electrically connected to the corresponding pull-down node P, and one of the source and drain of the third voltage stabilizing transistor T8 (for example, the drain) is electrically connected to the pull-up node Q.

[0067] Among them, the connection relationship of the third voltage stabilizing transistor T8 and the above devices and the loaded signals can refer to the relevant descriptions above.

[0068] It can be understood that the third voltage stabilizing transistor T8 is turned on or off under the control of the potential of the pull-down node P, thereby controlling the potential of the pull-up node Q, and can reduce the change in the potential of the pull-up node Q caused by at least the change in the signal acting on the pull-up transistor T6, and improve the stability of the pull-up node Q.

[0069] In some embodiments, in combination with Figures 1 to 3 as shown, the second voltage stabilizing transistor T4 is one of an N-type transistor and a P-type transistor, and the third voltage stabilizing transistor T8 is the other of an N-type transistor and a P-type transistor.

[0070] It can be understood that since the second voltage stabilizing transistor T4 and the third voltage stabilizing transistor T8 are both controlled by the potential of the pull-down node P to conduct or cut off, in order to avoid the two conducting simultaneously and both acting on the pull-up node Q or the pre-pull-up node K, the two can be respectively set as two different ones among the N-type transistor and the P-type transistor, so that the two conduct at different times.

[0071] Furthermore, as shown in Figures 1 to 5 one of the source and drain of the second voltage stabilizing transistor T4 (for example, the source) is electrically connected to the first voltage line for transmitting the first voltage signal (for example, the high-voltage signal VGH), and one of the source and drain of the third voltage stabilizing transistor T8 (for example, the source) is electrically connected to the second voltage line for transmitting the second voltage signal (for example, the low-voltage signal VGL); wherein, the first voltage signal is used to pull up or pull down the potential of the other of the source and drain of the pull-up control transistor T1 (i.e., the pre-pull-up node K), and the second voltage signal is used to pull down or pull up the potential of the pull-up node Q.

[0072] Combined with the above discussion, the second voltage stabilizing transistor T4 and the third voltage stabilizing transistor T8 can conduct at different times to pull up or pull down the potential of the pre-pull-up node K and pull down or pull up the potential of the pull-up node Q at different times. Even if the first voltage stabilizing transistor T5 conducts, it can also play a consistent role in pulling up or pulling down the pre-pull-up node K and the pull-up node Q, so as to improve the stability of the potentials of the two.

[0073] In some embodiments, as shown in Figures 1 to 5 the gate of the pull-up control transistor T1 is electrically connected to the pull-up control signal line for transmitting the first clock signal XCK, and the pull-up signal line is used to transmit the second clock signal CK. It can be seen that both the first clock signal XCK acting on the pull-up control transistor T1 and the second clock signal CK output to the output end of the gate driving unit 101 are clock signals, that is, the pull-up control transistor T1 can conduct or cut off periodically according to the first clock signal XCK, and the pulse p of the gate signal Gate can be generated at least according to the second clock signal CK.

[0074] In some embodiments, as shown in Figures 1 to 5 the first pull-down control transistor T2 is one of an N-type transistor and a P-type transistor, and the second pull-down control transistor T3 is the other of an N-type transistor and a P-type transistor.

[0075] It can be understood that since the first pull - down control transistor T2 and the second pull - down control transistor T3 are both controlled by the potential of the pre - pull - up node K to conduct or cut off, in order to avoid both of them conducting simultaneously and acting on the pull - down node P, they can be respectively set as two different types among N - type transistors and P - type transistors, so that they conduct at different times.

[0076] Further, as shown in Figures 1 to 5 One of the source and drain of the first pull - down control transistor T2 (for example, the source) is electrically connected to the first voltage line for transmitting the first voltage signal (for example, the high - voltage signal VGH), and one of the source and drain of the second pull - down control transistor T3 (for example, the source) is electrically connected to the second voltage line for transmitting the second voltage signal (for example, the low - voltage signal VGL); wherein, one of the first voltage signal and the second voltage signal is used to control the pull - down transistor T7 to conduct, and the other is used to control the pull - down transistor T7 to cut off.

[0077] Combined with the above discussion, the first pull - down control transistor T2 and the second pull - down control transistor T3 can conduct at different times to pull up and pull down the potential of the above - mentioned pull - down node P at different times, so as to control the pull - down transistor T7 to conduct and cut off at different times. Among them, to ensure that the gate driving unit 101 effectively outputs the gate signal Gate, the pull - up transistor T6 and the pull - down transistor T7 can conduct at different times to output the current pull - up signal and the current pull - down signal as the current gate signal Gate at different times.

[0078] In some embodiments, as shown in Figures 1 to 5 The pull - up control transistor T1, the second pull - down control transistor T3, the first voltage - stabilizing transistor T5, the pull - up transistor T6 and the pull - down transistor T7 are all N - type transistors; the first pull - down control transistor T2 and the second voltage - stabilizing transistor T4 are both P - type transistors. Further, the third voltage - stabilizing transistor T8 can also be an N - type transistor. Combining the above discussion on the multiple signals acting on the gate driving unit 101 and the type of transistors, the amplitude of the pulse p of the gate signal Gate can be made greater than the amplitude of the gate signal Gate during the period other than the corresponding pulse p.

[0079] To better illustrate the above - mentioned display device, the embodiments of the present application also provide a driving method for the display device, which is applied to the display device including but not limited to the above - mentioned one. The driving method of the display device may include but not limited to the following embodiments and combinations of the following embodiments.

[0080] For ease of description, in the present invention, only the first - stage gate driving unit 101 is taken, and the type of transistors and the waveform of the signals are discussed according to the above description.

[0081] In some embodiments, in combination with Figures 1 to 6 as shown, the driving method of the display device includes but is not limited to the following steps:

[0082] S1. In the first stage, the pull-up control module responds to the pull-up control signal transmitted on the pull-up control signal line, and controls the potential of the pull-up node to a corresponding effective potential according to the frame start signal or the gate signals of the previous i levels, so that the pull-up module outputs a corresponding first gate signal according to the pull-up signal transmitted on the pull-up signal line;

[0083] That is, within the first stage t1, the pull-up control signal (for example, the first clock signal XCK) controls the pull-up control module 201 to turn on, and the effective potential of the frame start signal STV is transmitted to the pull-up node Q to make it a corresponding effective potential, so that the pull-up module 202 is turned on, and a corresponding first gate signal (at least including the pulse p of the gate signal Gate) is output according to the pull-up signal (for example, the second clock signal CK);

[0084] Among them, in combination with Figures 1 to 5 as shown, the steps within the first stage include:

[0085] S11. In the first sub-stage, the pull-up control module responds to the pull-up control signal, and controls the potential of the pull-up node to a corresponding effective potential according to the frame start signal or the gate signals of the previous i levels, so that the pull-up module outputs the invalid potential of the first gate signal according to the invalid potential of the pull-up signal;

[0086] That is, within the first sub-stage t11, although the pull-up module 202 is turned on, the pull-up signal is a corresponding invalid potential at this time (for example, the above-mentioned second amplitude a2), so the invalid potential of the first gate signal is also output at this time;

[0087] At the same time, through the role of the inverter played by the pull-down control module 203, the pull-down node P is at a corresponding low potential, so that the pull-down module 204 is not turned on;

[0088] S12. In the second sub-stage after the first sub-stage, the pull-up control module is turned off, and the pull-up module outputs the effective potential of the corresponding first gate signal according to the effective potential of the pull-up signal.

[0089] Among them, the steps within the second sub-stage include:

[0090] In the second sub-stage t12, the pull-up signal is switched from the corresponding invalid potential to the corresponding effective potential, and the voltage stabilization module controls an open circuit of the current between the output end of the pull-up control module and the pull-down node.

[0091] That is, within the second sub-phase t12, although the pull-up control signal (e.g., the first clock signal XCK) controls the pull-up control module 201 to turn off, the pre-pull-up node K remains at the previous high potential. Even if the potential of the pull-up signal undergoes an upward jump, the potential of the pull-up node Q is further raised through the coupling effect of the parasitic capacitance. However, this causes the first voltage stabilization transistor T5 in the voltage stabilization module 205 to turn off, so the pre-pull-up node K remains at the previous high potential;

[0092] Meanwhile, through the inverter function of the pull-down control module 203, the pull-down node P is at the corresponding low potential, causing the pull-down module 204 not to turn on;

[0093] Furthermore, the steps within the second sub-phase further include:

[0094] In the second sub-phase, the pull-up signal switches from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module responds to the signal of the pull-down node and controls the potential of the output terminal of the pull-up control module according to the first voltage signal.

[0095] That is, within the second sub-phase t12, the second voltage stabilization transistor T4 in the voltage stabilization module 205 is turned on under the control of the low potential of the pull-down node P, and the first voltage signal (e.g., the high voltage signal VGH) is transmitted to the pre-pull-up node K to maintain the stability of its high potential.

[0096] Following the above step S1, the following steps are further included:

[0097] S2, in the second phase after the first phase, the pull-up control module responds to the pull-up control signal and controls the pull-down control module to turn on according to the frame start signal or the gate signals of the previous i levels, so that the potential of the pull-down node is the corresponding valid potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal transmitted through the pull-down signal line. The amplitude of the valid potential of the first gate signal is greater than the amplitude of the invalid potential of the first gate signal and the amplitude of the second gate signal;

[0098] That is, within the second phase t2, the pull-up control signal (e.g., the first clock signal XCK) controls the pull-up control module 201 to turn on, and the invalid potential of the frame start signal STV is transmitted to the pull-up node Q to make it the corresponding invalid potential, so that the pull-up module 202 does not turn on;

[0099] Among them, in combination with Figures 1 to 5 As shown, the steps within the second phase include:

[0100] S21. In the third sub-stage, the pull-up control module responds to the pull-up control signal and controls the pull-down control module to turn on according to the frame start signal or the gate signals of the previous i levels, so that the potential of the pull-down node is the corresponding valid potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal;

[0101] That is, in the third sub-stage t21, through the inverter function of the pull-down control module 203, the pull-down node P is at the corresponding high potential, so that the pull-down module 204 is turned on, and the corresponding second gate signal is output according to the pull-down signal (for example, the low-voltage signal VGL), and its amplitude can be close to the amplitude of the invalid potential of the first gate signal;

[0102] S22. In the fourth sub-stage after the third sub-stage, the pull-up control module is turned off and the pull-down control module remains turned on, so that the potential of the pull-down node is the corresponding valid potential, so that the pull-down module outputs the corresponding second gate signal according to the pull-down signal.

[0103] That is, in the fourth sub-stage t22, although the pull-up control signal (for example, the first clock signal XCK) controls the pull-up control module 201 to turn off, the pre-pull-up node K remains at the previous low potential. Through the inverter function of the pull-down control module 203, the pull-down node P is at the corresponding high potential, and the pull-down module 204 remains turned on and still outputs the second gate signal according to the pull-down signal;

[0104] Further, the steps in the fourth sub-stage include:

[0105] In the fourth sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module responds to the signal of the pull-down node and controls the potential of the pull-up node according to the second voltage signal.

[0106] That is, in the fourth sub-stage t22, the pull-up signal (for example, the second clock signal CK) is switched from the corresponding invalid potential (for example, the second amplitude a2) to the corresponding valid potential (for example, the first amplitude a1). At this time, since the pull-up node Q is at the corresponding low potential, the first voltage stabilization transistor T5 is turned on. However, due to the effect of the parasitic capacitance at this time, if no interference is added, the potential of the pull-up node Q will rise, resulting in the potential of the pre-pull-up node K also rising, further affecting the high potential of the pull-down node P, and further affecting the waveform of the gate signal Gate;

[0107] However, the third voltage stabilization transistor T8 in the present invention is turned on at this time under the control of the high potential of the pull-down node P, and the second voltage signal (for example, the low-voltage signal VGL) is transmitted to the pull-up node Q to reduce the rise of the potential of the pull-up node Q, thereby avoiding affecting the waveform of the gate signal Gate.

[0108] The above has introduced in detail the display device and its driving method provided by the embodiments of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display device, characterized in that, including a gate driving circuit, the gate driving circuit including a plurality of cascaded gate driving units, and the gate driving unit including: a pull-up control module, a control end of the pull-up control module being electrically connected to a corresponding pull-up control signal line, and an output end of the pull-up control module being electrically connected to a corresponding pull-up node; a pull-up module, an input end of the pull-up module being electrically connected to a corresponding pull-up signal line, a control end of the pull-up module being electrically connected to the corresponding pull-up node, and an output end of the pull-up module being electrically connected to an output end of the gate driving unit; a pull-down control module, a control end of the pull-down control module being electrically connected to an output end of the pull-up control module, and an output end of the pull-down control module being electrically connected to a corresponding pull-down node; a pull-down module, an input end of the pull-down module being electrically connected to a corresponding pull-down signal line, a control end of the pull-down module being electrically connected to the corresponding pull-down node, and an output end of the pull-down module being electrically connected to an output end of the gate driving unit; a voltage stabilizing module, a control end of the voltage stabilizing module being electrically connected to the corresponding pull-down node, and an output end of the voltage stabilizing module being electrically connected to the corresponding pull-up node; wherein, an amplitude of a pulse of a gate signal output from the output end of the gate driving unit is greater than an amplitude of the gate signal during a period other than the corresponding pulse.

2. The display device according to claim 1, wherein The pull-up signal transmitted by the pull-up signal line is a clock signal, and the pull-down signal transmitted by the pull-down signal line is a constant voltage signal; wherein, a pulse width of the pulse of the gate signal is equal to a duration of an effective potential of the pull-up control signal transmitted by the pull-up control signal line.

3. The display device according to claim 1, characterized in that, The amplitude of the pull-up signal transmitted by the pull-up signal line includes alternately arranged first amplitude and second amplitude, and the voltage stabilizing module includes: a first voltage stabilizing transistor, one of a source and a drain of the first voltage stabilizing transistor being electrically connected to an output end of the pull-up control module, and the other being electrically connected to the corresponding pull-up node; wherein, the first voltage stabilizing transistor is turned off when the pull-up module is turned on and the amplitude of the pull-up signal rises from the first amplitude to the second amplitude.

4. The display device according to claim 3, wherein The voltage stabilizing module further includes: a second voltage stabilizing transistor, a gate of the second voltage stabilizing transistor being electrically connected to the corresponding pull-down node, one of a source and a drain of the second voltage stabilizing transistor being electrically connected to a first voltage line, and the other being electrically connected to an output end of the pull-up control module; wherein, the second voltage stabilizing transistor is turned on when the pull-up module is turned on and the pull-down module is not turned on, and a first voltage signal transmitted by the first voltage line is used to stabilize a potential of an output end of the pull-up control module.

5. The display device according to claim 3 or 4, characterized in that, The voltage stabilizing module further includes: a third voltage stabilizing transistor, a gate of the third voltage stabilizing transistor being electrically connected to the corresponding pull-down node, one of a source and a drain of the third voltage stabilizing transistor being electrically connected to a second voltage line, and the other being electrically connected to the corresponding pull-up node; Among them, the third voltage stabilizing transistor conducts when the pull-down module is turned on and the amplitude of the pull-up signal rises from the first amplitude to the second amplitude, and the second voltage signal transmitted by the second voltage line is used to pull down the potential of the corresponding pull-up node.

6. The display device according to claim 1, wherein The pull-down control module includes: A first pull-down control transistor, one of the source and drain of the first pull-down control transistor is electrically connected to the first voltage line; A second pull-down control transistor, one of the source and drain of the second pull-down control transistor is electrically connected to the second voltage line; The gates of the first pull-down control transistor and the second pull-down control transistor are configured as the control terminals of the pull-down control module; The other of the source and drain of the first pull-down control transistor and the other of the source and drain of the second pull-down control transistor are electrically connected to the corresponding pull-down node.

7. The display device according to claim 6, wherein The first pull-down control transistor and the second pull-down control transistor conduct alternately; One of the first voltage signal transmitted by the first voltage line and the second voltage signal transmitted by the second voltage line is used to control the turn-on of the pull-down module, and the other is used to control the turn-off of the pull-down module.

8. The display device according to claim 1, wherein The pull-up control module includes: A pull-up control transistor, the gate of the pull-up control transistor is configured as the control terminal of the pull-up control module, one of the source and drain of the pull-up control transistor is electrically connected to the input terminal of the pull-up control module, and the other of the source and drain of the pull-up control transistor is configured as the output terminal of the pull-up control module; Among them, the input terminal of the pull-up control module is electrically connected to the frame start line or the output terminal of the previous i-stage gate driving unit, and i is a positive integer.

9. The display device according to claim 1, wherein The pull-up module includes: A pull-up transistor, the gate of the pull-up transistor is electrically connected to the corresponding pull-up node, one of the source and drain of the pull-up transistor is electrically connected to the pull-up signal line, and the other is electrically connected to the output terminal of the gate driving unit; The pull-down module includes: A pull-down transistor, the gate of the pull-down transistor is electrically connected to the corresponding pull-down node, one of the source and drain of the pull-down transistor is electrically connected to the pull-down signal line, and the other is electrically connected to the output terminal of the gate driving unit.

10. The display device according to claim 9, wherein The pull-up module further includes: A capacitor, electrically connected between the other of the source and drain of the pull-up transistor and the gate of the pull-up transistor.

11. The display device according to claim 9 or 10, characterized in that, The amplitudes of the pull-up signals transmitted by the pull-up signal line include alternately arranged first amplitudes and second amplitudes, the amplitudes of the pull-up control signals transmitted by the pull-up control signal line are alternately arranged third amplitudes and fourth amplitudes, and the pull-down signals transmitted by the pull-down signal line are constant voltage signals; Among them, there is a phase difference between the pull-up signal and the pull-up control signal, and the absolute value of the difference between the smaller of the first amplitude and the second amplitude and the amplitude of the pull-down signal is less than the absolute value of the difference between the larger of the first amplitude and the second amplitude and the amplitude of the pull-down signal.

12. The display device according to claim 1, wherein: The pull-up control module includes a pull-up control transistor, and one of the source and drain of the pull-up control transistor is electrically connected to the frame start line or the output terminal of the previous i-stage gate driving units, where i is a positive integer; The pull-up module includes a pull-up transistor and a capacitor. The gate of the pull-up transistor is electrically connected to the corresponding pull-up node. One of the source and drain of the pull-up transistor is electrically connected to the pull-up signal line, and the other is electrically connected to the output terminal of the gate driving unit. The capacitor is electrically connected between the other of the source and drain of the pull-up transistor and the gate of the pull-up transistor; The pull-down control module includes a first pull-down control transistor and a second pull-down control transistor. The gates of the first pull-down control transistor and the second pull-down control transistor are both electrically connected to the other of the source and drain of the pull-up control transistor. One of the source and drain of the first pull-down control transistor and one of the source and drain of the second pull-down control transistor are electrically connected to the corresponding pull-down node; The pull-down module includes a pull-down transistor. The gate of the pull-down transistor is electrically connected to the corresponding pull-down node. One of the source and drain of the pull-down transistor is electrically connected to the pull-down signal line, and the other is electrically connected to the output terminal of the gate driving unit; Wherein, the voltage stabilization module includes: A first voltage stabilization transistor, one of the source and drain of the first voltage stabilization transistor is electrically connected to the other of the source and drain of the pull-up control transistor, and the other of the source and drain of the first voltage stabilization transistor is electrically connected to the corresponding pull-up node; A second voltage stabilization transistor, the gate of the second voltage stabilization transistor is electrically connected to the corresponding pull-down node, and one of the source and drain of the second voltage stabilization transistor is electrically connected to the other of the source and drain of the pull-up control transistor.

13. The display device according to claim 12, wherein, The voltage stabilization module further includes: A third voltage stabilization transistor, the gate of the third voltage stabilization transistor is electrically connected to the corresponding pull-down node, and one of the source and drain of the third voltage stabilization transistor is electrically connected to the pull-up node; Wherein, the second voltage stabilization transistor is one of an N-type transistor and a P-type transistor, and the third voltage stabilization transistor is the other of an N-type transistor and a P-type transistor.

14. The display device according to claim 13, wherein The other of the source and drain of the second voltage stabilization transistor is electrically connected to a first voltage line for transmitting a first voltage signal, and the other of the source and drain of the third voltage stabilization transistor is electrically connected to a second voltage line for transmitting a second voltage signal; Wherein, the first voltage signal is used to pull up or pull up the potential of the other of the source and drain of the control transistor, and the second voltage signal is used to pull down or pull up the potential of the pull-up node.

15. A driving method of a display device, characterized in that, The display device includes a gate driving circuit, the gate driving circuit includes a plurality of cascaded gate driving units, and the gate driving unit includes: A pull-up control module, the output end of the pull-up control module is electrically connected to a corresponding pull-up node; A pull-up module, the control end of the pull-up module is electrically connected to the corresponding pull-up node, and the output end of the pull-up module is electrically connected to the output end of the gate driving unit; A pull-down control module, the control end of the pull-down control module is electrically connected to the output end of the pull-up control module, and the output end of the pull-down control module is electrically connected to a corresponding pull-down node; A pull-down module, the control end of the pull-down module is electrically connected to the corresponding pull-down node, and the output end of the pull-down module is electrically connected to the output end of the gate driving unit; A voltage stabilizing module, the input end of the voltage stabilizing module is electrically connected to the output end of the pull-up control module, the control end of the voltage stabilizing module is electrically connected to the corresponding pull-down node, and the output end of the voltage stabilizing module is electrically connected to the corresponding pull-up node; Wherein, the driving method of the display device includes: In the first stage, the pull-up control module responds to the pull-up control signal transmitted by the pull-up control signal line, and controls the potential of the pull-up node to a corresponding effective potential according to the frame start signal or the first i-level gate signals, so that the pull-up module outputs a corresponding first gate signal according to the pull-up signal transmitted by the pull-up signal line; In the second stage after the first stage, the pull-up control module responds to the pull-up control signal, and controls the pull-down control module to turn on according to the frame start signal or the first i-level gate signals, so that the potential of the pull-down node is a corresponding effective potential, so that the pull-down module outputs a corresponding second gate signal according to the pull-down signal transmitted by the pull-down signal line, and the amplitude of the effective potential of the first gate signal is greater than the amplitude of the invalid potential of the first gate signal and the amplitude of the second gate signal.

16. The driving method of the display device according to claim 15, wherein, The steps in the first stage include: In the first sub-stage, the pull-up control module responds to the pull-up control signal, and controls the potential of the pull-up node to a corresponding effective potential according to the frame start signal or the first i-level gate signals, so that the pull-up module outputs the invalid potential of the first gate signal according to the invalid potential of the pull-up signal; In the second sub-stage after the first sub-stage, the pull-up control module is turned off, and the pull-up module outputs the effective potential of the corresponding first gate signal according to the effective potential of the pull-up signal.

17. The driving method of the display device according to claim 16, characterized in that, The steps in the second sub-stage include: In the second sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding effective potential, and the voltage stabilizing module controls a current break to be formed between the output end of the pull-up control module and the pull-down node.

18. The driving method of the display device according to claim 17, characterized in that, The steps in the second sub-stage further include: In the second sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding effective potential, and the voltage stabilizing module responds to the signal of the pull-down node, and controls the potential of the output end of the pull-up control module according to the first voltage signal.

19. The driving method of the display device according to any one of claims 15 to 18, characterized in that, The steps in the second stage include: In the third sub-stage, the pull-up control module responds to the pull-up control signal and controls the pull-down control module to turn on according to the frame start signal or the gate signals of the previous i levels, so that the potential of the pull-down node is the corresponding valid potential, and the pull-down module outputs the corresponding second gate signal according to the pull-down signal; In the fourth sub-stage after the third sub-stage, the pull-up control module is turned off and the pull-down control module remains turned on, so that the potential of the pull-down node is the corresponding valid potential, and the pull-down module outputs the corresponding second gate signal according to the pull-down signal.

20. The driving method of the display device according to claim 19, characterized in that, The steps in the fourth sub-stage include: In the fourth sub-stage, the pull-up signal is switched from the corresponding invalid potential to the corresponding valid potential, and the voltage stabilization module responds to the signal of the pull-down node and controls the potential of the pull-up node according to the second voltage signal.

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