IO device
By designing an IO device that uses CPLD chip hardware circuit to process data, the problems of large system response jitter and high transmission delay caused by software processing in the prior art are solved, and faster and more reliable data processing is achieved.
Patent Information
- Application Number
- CN202421713856.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-18
- Publication Date
- 2025-05-16
- Estimated Expiration
- 2034-07-18
AI Technical Summary
When using software for data processing in the prior art, there may be problems such as large system response jitter and high transmission delay.
An IO device is designed, including a first IO module and at least one second IO module, and the interactive data is processed through the hardware circuit of the CPLD chip, reducing the time jitter caused by software processing, and reducing the response time and transmission delay time of each module.
The processing of data through hardware circuits reduces the time jitter and delay caused by software processing, and improves the system's response speed and reliability.
Smart Images
Figure CN222882950U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of automation technology, and specifically relates to an IO device. Background Art
[0002] Remote I / O (input / output) plays an important role in modern computing and industrial automation systems. This technology connects I / O devices to remote controllers through the network to achieve remote control and monitoring.
[0003] However, when using I / O devices, large system response jitter and high transmission delay may occur when software is used for data processing. Utility Model Content
[0004] The purpose of the present application is to provide an IO device, aiming to solve the technical problems in the prior art of large system response jitter and high transmission delay that may occur when software is used for data processing.
[0005] To achieve the above object, the technical solution adopted in the present application is: an IO device, comprising: a first IO module and at least one second IO module, the first IO module is electrically connected to one of the second IO modules, the second IO modules are electrically connected in sequence, and the main control chips of the first IO module and the second IO module are CPLD chips;
[0006] The first IO module is used to receive the master station data of the master station, and send the master station data to each of the second IO modules, wherein the master station data includes the first communication data of each of the second IO modules;
[0007] It is also used to receive and store the second communication data of each second IO module, and then transmit each second communication data back to the main station;
[0008] The second IO module is used to obtain first target communication data from the master station data, and operate the external device and / or external environment according to the first target communication data;
[0009] It is also used to upload the second communication data to the first IO module, where the second communication data includes IO information of the second IO module and status information of at least one of the external device and the external environment.
[0010] In one embodiment, the first IO module includes a first CPLD chip and a communication unit, the first CPLD chip is electrically connected to the communication unit, and the first CPLD chip communicates with the master station through the communication unit.
[0011] In one embodiment, the first CPLD chip includes a first SPI interface unit, a first processing unit and a cache unit, the first processing unit is electrically connected to the cache unit and the first SPI interface unit respectively, the first SPI interface unit is electrically connected to the second IO module, and the cache unit is electrically connected to the communication unit.
[0012] In one embodiment, the first SPI interface unit includes a first SPI interface including a first input pin, a first output pin, a first clock pin and a first selection pin.
[0013] In one embodiment, the cache unit is a FIFO unit.
[0014] In one embodiment, the communication unit is an MCU unit, the MCU unit includes an ESC interface and an SRAM interface, the MCU unit communicates with the master station through the ESC interface, and the MCU unit communicates with the first CPLD chip through the SRAM interface.
[0015] In one embodiment, the second IO module includes a second CPLD chip, the second CPLD chip includes a second SPI interface unit, a third SPI interface unit, a second processing unit and an on-chip IO unit, and the second processing unit is electrically connected to the second SPI interface unit, the third SPI interface unit and the on-chip IO unit respectively;
[0016] If the second IO module of the current node is electrically connected to the first IO module and the second IO module of the next node respectively, the second SPI interface unit of the second IO module of the current node is electrically connected to the first IO module, and the third SPI interface unit of the second IO module of the current node is electrically connected to the second IO module of the next node;
[0017] If the second IO module of the current node is electrically connected to the second IO module of the previous node and the second IO module of the next node respectively, the second SPI interface unit of the second IO module of the current node is electrically connected to the second IO module of the previous node, and the third SPI interface unit of the second IO module of the current node is electrically connected to the second IO module of the next node.
[0018] In one embodiment, the second SPI interface unit includes a second input pin, a second output pin, a second clock pin, and a second selection pin;
[0019] The third SPI interface unit includes a third input pin, a third output pin, a third clock pin and a third selection pin.
[0020] In one embodiment, the master station is a Modbus master station, a PROFIBUS master station, a CANopen master station or an EtherCAT master station.
[0021] In one embodiment, the external device includes industrial equipment, Internet of Things equipment, agricultural equipment, and transportation equipment.
[0022] Compared with the prior art, the embodiments of the present application have the following beneficial effects:
[0023] The IO device of the embodiment of the present application includes a first IO module and at least one second IO module, the first IO module is electrically connected to one of the second IO modules, and the second IO modules are electrically connected in sequence. The main control chip of the first IO module and the second IO module is a CPLD chip, and the interactive data is processed by the hardware circuit of the CPLD chip, which is not affected by software vulnerabilities and crashes, reduces time jitter caused by software processing, reduces the response time of each module, and reduces transmission delay time. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0025] Figure 1 A first schematic diagram of an IO device provided in an embodiment of the present application;
[0026] Figure 2 A second schematic diagram of an IO device provided in an embodiment of the present application;
[0027] Figure 3 This is a third schematic diagram of an IO device provided in an embodiment of the present application.
[0028] Among them, the reference numerals in the figure are:
[0029] 10. First IO module; 11. First CPLD chip; 111. First SPI interface unit; 112. First processing unit; 113. Cache unit (FIFO unit); 12. Communication unit (MCU unit); 121. ESC interface; 122. SRAM interface; 20. Second IO module; 21. Second CPLD chip; 211. Second SPI interface unit; 212. Third SPI interface unit; 213. Second processing unit; 214. On-chip IO unit; 30. Master station. DETAILED DESCRIPTION
[0030] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.
[0031] In the description of the present application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0032] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0033] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0034] Please refer to Figure 1 , Figure 1 This is a first schematic diagram of an IO device provided in an embodiment of the present application. Figure 1 As shown, the device includes: a first IO module 10 and at least one second IO module 20, the first IO module 10 is electrically connected to one of the second IO modules 20, and each second IO module 20 is electrically connected in sequence. The main control chip of the first IO module 10 and the second IO module 20 is a CPLD chip.
[0035] In a possible implementation, the first IO module 10 includes a first CPLD chip 11 (Complex Programmable Logic Device) and a communication unit 12. The first CPLD chip 11 is electrically connected to the communication unit 12. The first CPLD chip 11 communicates with the master station 30 through the communication unit 12 (network communication).
[0036] In a possible implementation, the communication unit 12 is an MCU unit, which includes an ESC interface 121 and an SRAM interface 122 . The MCU unit communicates with the master station 30 via the ESC interface 121 , and communicates with the first CPLD chip 11 via the SRAM interface 122 .
[0037] In a possible implementation, the second IO module 20 includes a second CPLD chip 21 .
[0038] The second IO module 20 can expand the number of IO ports. The number of the second IO modules 20 can be increased or decreased according to actual scene requirements, and the second IO modules 20 can be increased or decreased by power-off plugging and unplugging.
[0039] Specifically, the first IO module 10 is electrically connected to a second IO module 20, the second IO module 20 electrically connected to the first IO module 10 is electrically connected to another second IO module 20, and then the second IO module 20 electrically connected to the second IO module 20 is electrically connected to another second IO module 20, and so on, and each second IO module 20 is electrically connected in series in sequence. Each IO module is a node of the series link.
[0040] The first IO module 10 is used to receive the master station data of the master station 30 and send the master station data to each second IO module 20, where the master station data includes the first communication data of each second IO module 20;
[0041] It is also used to receive and store the second communication data of each second IO module 20 and then transmit the second communication data back to the main station 30 .
[0042] In application, the first IO module 10 is generally set as the main module, and the first CPLD chip 11 of the first IO module 10 communicates with the master station 30 through a communication protocol (such as Modbus, PROFIBUS, CANopen, EtherCAT, etc.), and communicates with the second CPLD chip 21 of the second IO module 20.
[0043] In the application, the MCU (Microcontroller Unit) unit receives the master station data of the master station 30 through the ESC (EtherCAT Slave Controller) interface. The MCU unit triggers the first CPLD chip 11 to update the IO data through the SYNC synchronization interrupt. The first CPLD chip 11 receives the master station data of the master station 30 through the SRAM (Static RAM) interface and sends the master station data. Based on the second IO modules 20 connected in series, data is sent node by node so that each second IO module 20 receives the first communication data corresponding to itself.
[0044] The first CPLD chip 11 receives and stores the second communication data of each second IO module 20 , and the first CPLD chip 11 transmits each second communication data back to the master station 30 through the communication unit 12 .
[0045] In a possible implementation, the master station 30 is a Modbus (serial communication protocol) master station, a PROFIBUS (PROcess FIeld BUS) master station, a CANopen (Controller Area Network, CAN bus) master station or an EtherCAT (Control Automation Technology, Ethernet control automation technology) master station.
[0046] The second IO module 20 is used to obtain the first target communication data from the master station data, and operate the external device and / or the external environment according to the first target communication data.
[0047] It is also used to upload second communication data to the first IO module 10, where the second communication data includes IO information of the second IO module 20 and status information of at least one of an external device and an external environment.
[0048] In the application, the second CPLD chip 21 receives the data sent from the module of the previous node, obtains the first communication data corresponding to itself from the sent data, so as to obtain the first target communication data from the master station data, and then operates the external device and / or the external environment according to the first target communication data. Specifically, the external device is controlled according to the first target communication data. Information collection is performed on the external environment according to the first target communication data.
[0049] At the same time, the second CPLD chip 21 uses the acquired IO information of itself and at least one status information of the external device and the external environment as the second communication data, and then uploads the second communication data to the first CPLD chip 11 of the first IO module 10 node by node.
[0050] In applications, hardware circuits are used inside the CPLD chip to implement logical functions.
[0051] It can be understood that, through the first IO module 10 and the expandable second IO module 20, the cost and maintenance difficulty of the industrial control system can be effectively reduced, and the reliability and flexibility of the system can be improved.
[0052] The IO device of the embodiment of the present application includes a first IO module and at least one second IO module, the first IO module is electrically connected to one of the second IO modules, and the second IO modules are electrically connected in sequence. The main control chip of the first IO module and the second IO module is a CPLD chip, and the interactive data is processed by the hardware circuit of the CPLD chip, which is not affected by software vulnerabilities and crashes, reduces time jitter caused by software processing, reduces the response time of each module, and reduces transmission delay time.
[0053] Please refer to Figure 2 , Figure 2 This is a second schematic diagram of an IO device provided in an embodiment of the present application. Figure 2 As shown, the first CPLD chip 11 includes a first SPI interface unit 111, a first processing unit 112 and a cache unit 113. The first processing unit 112 is electrically connected to the cache unit 113 and the first SPI interface unit 111 respectively. The first SPI interface unit 111 is electrically connected to the second IO module 20, and the cache unit 113 is electrically connected to the communication unit 12.
[0054] In a possible implementation, the cache unit 113 is a FIFO (First In First Out) unit, which can help ensure orderly processing of data, thereby improving the efficiency and responsiveness of the system.
[0055] In a possible implementation, the first processing unit 112 is a hardware logic processing unit.
[0056] The second CPLD chip 21 includes a second SPI interface unit 211, a third SPI interface unit 212, a second processing unit 213 and an on-chip IO unit 214, and the second processing unit 213 is electrically connected to the second SPI interface unit 211, the third SPI interface unit 212 and the on-chip IO unit 214 respectively.
[0057] If the second IO module 20 of the current node is electrically connected to the first IO module 10 and the second IO module 20 of the next node respectively, the second SPI interface unit 211 of the second IO module 20 of the current node is electrically connected to the first IO module 10, and the third SPI interface unit 212 of the second IO module 20 of the current node is electrically connected to the second IO module 20 of the next node.
[0058] If the second IO module 20 of the current node is electrically connected to the second IO module 20 of the previous node and the second IO module 20 of the next node respectively, the second SPI interface unit 211 of the second IO module 20 of the current node is electrically connected to the second IO module 20 of the previous node, and the third SPI interface unit 212 of the second IO module 20 of the current node is electrically connected to the second IO module 20 of the next node.
[0059] Among them, the first SPI interface unit 111, the second SPI interface unit 211, and the third SPI interface unit 212 are constructed by CPLD and are responsible for the transmission of communication data.
[0060] In application, the first SPI interface unit 111 is the main SPI interface of the first CPLD chip 11 and is the communication initiator and controller. When the first SPI interface unit 111 is working, the communication link formed by the first IO module 10 and each second IO module 20 is in working state.
[0061] The first IO module 10 acts as a slave station of the master station 30, and the first CPLD unit exchanges data with the master station 30 through the communication protocol and the communication unit 12. Specifically, after the master station 30 sends the master station data, the cache unit 113 receives and caches the master station data. The first processing unit 112 takes out the master station data from the cache unit 113 and encapsulates it. Then the first SPI interface unit 111 initiates communication and sends the encapsulated master station data through the first SPI interface. The first processing unit 112 receives the second communication data of each second IO module 20 through the first SPI interface unit 111, and stores the second communication data in the cache unit 113 after parsing, and transmits each second communication data back to the master station 30 through the communication unit 12.
[0062] Correspondingly, in the second IO module 20 electrically connected to the first IO module 10, the second SPI interface unit 211 receives the master station data and transmits it to the second processing unit 213. The second processing unit 213 receives the master station data, automatically identifies the first communication data of this node, obtains the first target communication data, and uses the bit stream of the first target communication data as input data. When the bit stream is input, the second processing unit 213 completes the parsing of the first target communication data, controls the level of the IO pin of the on-chip IO unit 214 according to the result of the parsing, and operates the external device and the external environment. The second processing unit 213 also obtains its own IO information and at least one status information of the external device and the external environment, and then obtains the second communication data. The second processing unit 213 transmits the second communication data back to the first IO module 10 bit by bit through the second SPI interface. Among them, the communication data is in the form of a data frame.
[0063] And, the second processing unit 213 transparently transmits the first communication data of other nodes to the third SPI interface unit 212, so as to be transmitted to the second IO module 20 of the next node. And, the second communication data of the second IO module 20 of the next node is transparently transmitted to the second SPI interface unit 211, so as to be transmitted to the first IO module 10 of the previous node.
[0064] Specifically, after waiting for the first preset number of clocks, the third SPI interface unit 212 is started to send a signal (used to remove the tiny clock jitter between different modules when the data is transferred and processed by the second processing unit 213, and to remove the transmission jitter caused by the transmission delay), and then after waiting for the second preset number of SPI clocks (the time for the next node module to prepare data), the third SPI interface unit 212 interacts with the second IO module 20 of the next node. During the waiting time, the second processing unit 213 outputs redundant data from the second SPI interface unit 211 to the first IO module 10 (used to maintain stable communication). Among them, the clock required to send redundant data is almost the sum of the first preset number of clocks and the second preset number of clocks.
[0065] The working conditions of other second IO modules 20 are the same, so they are not described again here.
[0066] It is understandable that the existing IO device uses MCU software to realize communication, and each IO module is a node of the communication link. In this communication link, the node head needs to pass data downward to the last node node by node, and the last node is then passed back to the node head node by node, so that the number of data propagation is twice the number of nodes, resulting in high system transmission delay and poor system real-time performance. Through the SPI interface of the first IO module 10 and the second IO module 20 working together, duplex communication is realized, the number of data propagation in the link is halved, and the transmission delay of the system is reduced.
[0067] In this embodiment, the first CPLD chip 11 includes a first SPI interface unit 111, a first processing unit 112 and a cache unit 113, and the second CPLD chip 21 includes a second SPI interface unit 211, a third SPI interface unit 212, a second processing unit 213 and an on-chip IO unit 214, so that the first IO module 10 and the second IO module 20 communicate through the SPI interface to form a full-duplex communication system of a ring link. The full-duplex communication of the SPI interface is used to reduce the number of data transmissions in the link, and further reduce the transmission delay of the system.
[0068] Please refer to Figure 3 , Figure 3 This is a third schematic diagram of an IO device provided in an embodiment of the present application. Figure 3As shown, the first SPI interface unit 111 includes a first SPI interface including a first input pin, a first output pin, a first clock pin and a first selection pin.
[0069] The second SPI interface unit 211 includes a second input pin, a second output pin, a second clock pin and a second selection pin.
[0070] The third SPI interface unit 212 includes a third input pin, a third output pin, a third clock pin, and a third selection pin.
[0071] Among them, the input pin is SDI, the output pin is SDO, the clock pin is CLK, and the selection pin is CS.
[0072] In application, in the second IO module 20 electrically connected to the first IO module 10 , the first SDI is electrically connected to the second SDO, the first SDO is electrically connected to the second SDI, the first CLK is electrically connected to the second CLK, and the first CS is electrically connected to the second CS.
[0073] When the two second IO modules 20 are electrically connected, the third SDI of the second IO module 20 of the current node is electrically connected to the second SDO of the second IO module 20 of the next node, the third SDO of the second IO module 20 of the current node is electrically connected to the second SDI of the second IO module 20 of the next node, the third CLK of the second IO module 20 of the current node is electrically connected to the second CLK of the second IO module 20 of the next node, and the third CS of the second IO module 20 of the current node is electrically connected to the second CS of the second IO module 20 of the next node.
[0074] Specifically, based on the second IO module 20 electrically connected to the first IO module 10, the third SPI interface unit 212 is started to send a cs signal through the third CS after waiting for a first preset number of clocks, and then after waiting for a second preset number of SPI clocks, the third SDI exchanges data with the second SDO of the next node. During the waiting time, the second processing unit 213 outputs redundant data from the second SDO to the first IO module 10.
[0075] In one embodiment, the external devices include industrial equipment, Internet of Things equipment, agricultural equipment, and transportation equipment.
[0076] In the application, it is used in the field of industrial automation. Through IO devices, different machines and equipment can be controlled and detected to improve efficiency and achieve remote control. Industrial equipment includes machines and equipment.
[0077] Applied in the field of Internet of Things, IO devices can be used to remotely collect data, control and manage different IoT devices, improve efficiency and achieve remote control.
[0078] Applied in the field of intelligent agriculture, IO devices can be used to monitor and control agricultural equipment, collect environmental data, and improve production efficiency.
[0079] Applied in the field of intelligent transportation, IO devices can be used to remotely monitor and control transportation facilities, vehicles, etc., thereby improving the safety and efficiency of transportation.
[0080] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. An IO device, characterized in that: include: A first IO module and at least one second IO module, the first IO module is electrically connected to one of the second IO modules, the second IO modules are electrically connected in sequence, and the main control chips of the first IO module and the second IO module are CPLD chips; The first IO module is used to receive the master station data of the master station, and send the master station data to each of the second IO modules, wherein the master station data includes the first communication data of each of the second IO modules; It is also used for receiving and storing the second communication data of each second IO module, and then transmitting each second communication data back to the master station; The second IO module is used to obtain first target communication data from the master station data, and operate the external device and / or external environment according to the first target communication data; It is also used to upload the second communication data to the first IO module, where the second communication data includes IO information of the second IO module and status information of at least one of the external device and the external environment.
2. The device according to claim 1, characterized in that The first IO module includes a first CPLD chip and a communication unit. The first CPLD chip is electrically connected to the communication unit. The first CPLD chip communicates with the master station through the communication unit.
3. The device according to claim 2, characterized in that The first CPLD chip includes a first SPI interface unit, a first processing unit and a cache unit, the first processing unit is electrically connected to the cache unit and the first SPI interface unit respectively, the first SPI interface unit is electrically connected to the second IO module, and the cache unit is electrically connected to the communication unit.
4. The device according to claim 3, characterized in that The first SPI interface unit includes a first SPI interface including a first input pin, a first output pin, a first clock pin and a first selection pin.
5. The device according to claim 3, characterized in that The cache unit is a FIFO unit.
6. The device according to claim 2, characterized in that The communication unit is an MCU unit, and the MCU unit includes an ESC interface and an SRAM interface. The MCU unit communicates with the master station through the ESC interface, and the MCU unit communicates with the first CPLD chip through the SRAM interface.
7. The device according to claim 1, characterized in that The second IO module includes a second CPLD chip, the second CPLD chip includes a second SPI interface unit, a third SPI interface unit, a second processing unit and an on-chip IO unit, and the second processing unit is electrically connected to the second SPI interface unit, the third SPI interface unit and the on-chip IO unit respectively; If the second IO module of the current node is electrically connected to the first IO module and the second IO module of the next node respectively, the second SPI interface unit of the second IO module of the current node is electrically connected to the first IO module, and the third SPI interface unit of the second IO module of the current node is electrically connected to the second IO module of the next node; If the second IO module of the current node is electrically connected to the second IO module of the previous node and the second IO module of the next node respectively, the second SPI interface unit of the second IO module of the current node is electrically connected to the second IO module of the previous node, and the third SPI interface unit of the second IO module of the current node is electrically connected to the second IO module of the next node.
8. The device according to claim 5, characterized in that The second SPI interface unit includes a second input pin, a second output pin, a second clock pin, and a second selection pin; The third SPI interface unit includes a third input pin, a third output pin, a third clock pin and a third selection pin.
9. The device according to any one of claims 1 to 8, characterized in that The master station is a Modbus master station, a PROFIBUS master station, a CANopen master station or an EtherCAT master station.