Image processing digital board card based on DSP and FPGA

Abstract

The utility model relates to the technical field of digital image processing, and particularly discloses an image processing digital board card based on a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array), which comprises a bottom plate, a rectangular connector arranged on the bottom plate, an FPGA chip, a DSP chip, an audio acquisition and playback unit, an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) circuit unit, a conversion unit, a network transmission unit and a control unit, the rectangular connector is respectively connected with the audio acquisition and playback unit, the MOSFET circuit unit, the conversion unit, the network transmission unit and the control unit; the FPGA chip is respectively connected with the audio acquisition and playback unit, the MOSFET circuit unit, the conversion unit, the network transmission unit and the control unit; the FPGA chip is connected with the DSP chip through a GPIO interface and a configuration IO interface. An audio acquisition and playback unit, an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) circuit unit, a conversion unit, a network transmission unit and a control unit are integrated on an image digital board card, so that the board card has the capabilities of audio acquisition, playback, network transmission, 1553B interface and serial port communication.

Description

Technical Field

[0001] The utility model belongs to the technical field of digital image processing, and in particular relates to an image processing digital board based on DSP and FPGA. Background Art

[0002] With the continuous development of science and technology, digital image processing technology has been widely used in aerospace, communications, medicine, industrial production and other fields. The characteristics of digital image processing are large amounts of data processing and very time-consuming processing. In image processing digital boards, how to complete the processing of a large amount of information data in a limited time, meet the real-time requirements of the system, and quickly respond to the control of peripherals after digital image processing has always been a difficult problem that has troubled people.

[0003] In recent years, with the continuous development of electronic technology, the emergence of high-performance programmable logic devices FPGA and digital signal processors DSP has solved the problems of large data volume and slow processing speed in digital image processing. FPGA is a semi-custom circuit that can realize pipeline processing of digital image signals. DSP is a chip specially used for digital processing. It has high-speed, flexible programmability and low power consumption. It is widely used in digital image processing, speech processing, signal processing and other fields. In the actual application process, in order to detect the effect of image acquisition in real time, it is also necessary to play back the collected digital image information. During the playback process, the audio also needs to be processed and played back, which puts higher requirements on the existing image processing digital boards, so it is necessary to improve the existing image processing digital boards. Utility Model Content

[0004] In order to overcome the above-mentioned technical problems existing in the prior art, an embodiment of the utility model provides an image processing digital board based on DSP and FPGA. By integrating an audio acquisition and playback unit, a MOSFET circuit unit, a conversion unit, a network transmission unit and a control unit on the image digital board, the board has audio acquisition, playback, network transmission, 1553B interface and serial port communication capabilities.

[0005] In order to achieve the above-mentioned purpose, an embodiment of the utility model provides an image processing digital board based on DSP and FPGA, including a baseboard, and the image processing digital board based on DSP and FPGA includes: a rectangular connector, an FPGA chip, a DSP chip, an audio acquisition and playback unit, a MOSFET circuit unit, a conversion unit, a network transmission unit and a control unit configured on the baseboard; the rectangular connector is respectively connected to the audio acquisition and playback unit, the MOSFET circuit unit, the conversion unit, the network transmission unit and the control unit; the FPGA chip is respectively connected to the audio acquisition and playback unit, the MOSFET circuit unit, the conversion unit, the network transmission unit and the control unit; the FPGA chip is connected to the DSP chip through a GPIO interface and a configuration IO interface.

[0006] Preferably, the audio acquisition and playback unit includes a signal conditioning module and an audio CODEC module; the signal conditioning module is connected to the rectangular connector via multiple AUDIO IN interfaces and multiple AUDIO OUT interfaces; the audio CODEC module is connected to the FPGA chip via an I2S / SPI bus.

[0007] Preferably, the multiple AUDIO IN interfaces are 4 AUDIO IN interfaces, and the multiple AUDIO OUT interfaces are 4 AUDIO OUT interfaces.

[0008] Preferably, the MOSFET circuit unit includes a MOSFET drive circuit module and a MOSFET isolation circuit module; the MOSFET drive circuit module and the MOSFET isolation circuit module are respectively connected to the rectangular connector through corresponding GND / OPEN interfaces; the MOSFET drive circuit module and the MOSFET isolation circuit module are respectively connected to the FPGA chip through corresponding I / O ports.

[0009] Preferably, the conversion unit includes an overvoltage protection module and a conversion module, the overvoltage protection module is connected to the conversion module; the rectangular connector is connected to the overvoltage protection module, and the conversion module is connected to the FPGA chip through a UART interface; the overvoltage protection module is a TVS protection module, and the conversion module is an RS422 conversion module.

[0010] Preferably, the FPGA chip is connected to the corresponding conversion unit via two UART interfaces respectively.

[0011] Preferably, the network transmission unit includes a network transformer module and a network transmission module, the network transformer module is connected to the network transmission module via an MDI interface; the rectangular connector is connected to the network transformer module, and the network transmission module is connected to the FPGA chip via an MII interface; the network transformer module adopts a TF1102 network transformer, and the network transmission module adopts an Ethernet PHY chip.

[0012] Preferably, the control unit includes a 1553B controller; the rectangular connector is connected to the 1553B controller via a transformer coupling connection; the 1553B controller is connected to the FPGA chip via a HOST interface, and the RT address of the 1553B controller is also connected to the FPGA chip.

[0013] Preferably, the DSP and FPGA-based image processing digital board also includes: a clock unit and an SM chip configured on the baseboard; the SM chip is connected to the DSP chip, and the clock unit is connected to the FPGA chip via an FPGA clock interface, a DSP clock interface, a PHY clock interface, a 1533B clock interface and an OODEC clock interface.

[0014] Preferably, the FPGA chip is also connected to a 128Mb PROM memory, 3 BPI NORFLASH memories and a first debug port module on the baseboard; the 128Mb PROM memory is connected to the FPGA chip via a BPI interface; each BPI NOR FLASH memory is connected to the FPGA chip via a CE interface and a parallel port interface; the first debug port module is connected to the FPGA chip via a JTAG interface.

[0015] Through the technical solution provided by the utility model, the utility model has at least the following technical effects:

[0016] By integrating audio CODEC, Ethernet PHY, 1553B and RS422 interface chips on the DSP and FPGA-based image processing digital board, the board has audio acquisition, playback, network transmission, 1553B interface and serial port communication capabilities, so that the board can be used in professional fields such as voice processing, signal processing and image processing.

[0017] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present utility model and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present utility model, but do not constitute a limitation on the embodiments of the present utility model. In the accompanying drawings:

[0019] Figure 1 It is a structural schematic diagram of an image processing digital board based on DSP and FPGA provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0020] The specific implementation of the embodiment of the utility model is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the utility model, and is not used to limit the embodiment of the utility model.

[0021] The terms "system" and "network" in the embodiments of the present invention can be used interchangeably. "Multiple" refers to two or more than two. In view of this, in the embodiments of the present invention, "multiple" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the previous and subsequent associated objects are in an "or" relationship. In addition, it should be understood that in the description of the embodiments of the present invention, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0022] See also Figure 1 , a schematic diagram of the structure of a digital image processing board based on DSP and FPGA provided in an embodiment of the utility model, the digital image processing board based on DSP and FPGA includes a baseboard, and a rectangular connector, an FPGA chip, a DSP chip, an audio acquisition and playback unit, a MOSFET circuit unit, a conversion unit, a network transmission unit and a control unit configured on the baseboard, the FPGA chip is connected to the DSP chip through a GPIO interface and a configuration IO interface, the FPGA chip is also respectively connected to the audio acquisition and playback unit, the MOSFET circuit unit, the conversion unit, the network transmission unit and the control unit, and the rectangular connector is also respectively connected to the audio acquisition and playback unit, the MOSFET circuit unit, the conversion unit, the network transmission unit and the control unit.

[0023] In an embodiment of the utility model, the operating system of the image processing digital board based on DSP and FPGA is the domestic Ruihua operating system. All chips in the image processing digital board are domestic chips. The model of the rectangular connector is CRM372-080-331-5700. The rectangular connector is connected to an external device as a medium for transmitting signals between the external device and the image processing digital board based on DSP and FPGA. The rectangular connector is also connected to a power supply unit. The external device can output 3.3V / 15W or 5V / 15W power to the power supply unit through the rectangular connector, so that the power supply unit outputs power to each module in the image processing digital board based on DSP and FPGA provided in this embodiment.

[0024] Specifically, the audio acquisition and playback unit includes a signal conditioning module and an audio CODEC module. The audio CODEC module processes audio data with a sampling depth of 24 bits and supports 2-way acquisition and 2-way output. The signal conditioning module is connected to the rectangular connector through 4 AUDIOIN interfaces so that an external device can transmit the audio signal to the signal conditioning module through the rectangular connector. The signal conditioning module is connected to the audio CODEC module in two ways. The signal conditioning module processes the audio signal and transmits it to the audio CODEC module. The audio CODEC module processes the audio signal and transmits it to the FPGA chip through the I2S bus. The FPGA chip is connected to the DSP chip through the GPIO interface and the configuration IO interface, and transmits the processed audio signal to the DSP chip. Similarly, the FPGA chip is connected to the audio CODEC module through the SPI bus, and transmits the audio signal to the audio CODEC module. The audio CODEC module is connected to the signal conditioning module in two ways, and transmits the processed audio signal to the signal conditioning module. The signal conditioning module is connected to the rectangular connector through 4 AUDIO OUT interfaces, and transmits the processed audio signal to the external device through the rectangular connector.

[0025] Furthermore, the MOSFET circuit unit includes a MOSFET driving circuit module and a MOSFET isolation circuit module. The FPGA chip is connected to the MOSFET driving circuit through two I / O ports to transmit self-test data to the MOSFET driving circuit. The MOSFET driving circuit module is then connected to the rectangular connector through two GND / OPEN interfaces to transmit the self-test data to an external device through the rectangular connector. For the MOSFET isolation circuit module, the rectangular connector is connected to the MOSFET isolation circuit module through eight GND / OPEN interfaces. The external device transmits data to the MOSFET isolation circuit through the rectangular connector in a digital quantity input manner. The MOSFET isolation circuit is then connected to the FPGA chip through eight I / O ports to transmit the data to the FPGA chip.

[0026] In this embodiment, the conversion unit includes an overvoltage protection module and a conversion module. The overvoltage protection module is a TVS protection module, and the conversion module is an RS422 conversion module. This embodiment is provided with two conversion units, that is, two TVS protection modules and two RS422 conversion modules are provided; the FPGA chip is connected to the two RS422 conversion modules respectively through two UART interfaces, the two RS422 conversion modules are connected to the two TVS protection modules respectively, and the two TVS protection modules are connected to the rectangular connectors respectively. Data can be transmitted between the external device and the FPGA chip through the rectangular connector using the RS422 data transmission protocol. The network transmission unit includes a network transformer module and a network transmission module. The network transformer module uses a network transformer. The chip of the network transformer uses a domestic chip, for example, the model is TF1102, which is produced by Tianfu manufacturer. The network transmission module uses an Ethernet PHY chip; the FPGA chip is connected to the Ethernet PHY chip through the MII interface, the Ethernet PHY chip is connected to the T31S1113BM network transformer through the MDI interface, and the T31S1113BM network transformer is connected to the rectangular connector. The FPGA chip supports Ethernet PHY data transmission between the external device through the rectangular connector. The control unit includes a 1553B controller. The rate of the 1553B controller is 1Mbps, it has redundant dual channels, and supports BC, BM and RT modes. The FPGA chip is connected to the 1553B controller through the HOST interface. The RT address of the 1553B controller is also connected to the FPGA chip. The 1553B controller is connected to the rectangular connector through a transformer coupling connection. The FPGA chip and the external device can communicate through the rectangular connector using the 1553B bus protocol to transmit data, and the transmitted data is complete and accurate.

[0027] In this embodiment, the baseboard of the digital image processing board based on DSP and FPGA is also configured with a clock unit and an SM chip. The clock unit is connected to the FPGA chip through five interfaces, namely, the FPGA clock interface, the DSP clock interface, the PHY clock interface, the 1533B clock interface and the OODEC clock interface; the bit width of the DDR in the SM chip is 64 bits, the memory capacity of the DDR is 2GB, and the rate is 1600Mbpst, and the SM chip is connected to the DSP chip. The FPGA chip is connected to a PROM memory with a memory capacity of 128Mb and three BPI NOR FLASH memories on the baseboard, and the capacity of each BPI NOR FLASH memory is 1Gb. The PROM memory is connected to the FPGA chip through the BPI interface, and each of the three BPI NOR FLASH memories is connected to the FPGA chip through the CE interface and the parallel port interface; the FPGA chip is also connected to a first debugging port on the baseboard through the JTAG interface, and the first debugging port is used to debug or test the FPGA chip.

[0028] As an optimization, the baseboard of the DSP and FPGA-based image processing digital board also integrates NAND FLASH memory and SPI FLASH memory. Both the FPGA chip and the DSP chip are connected to the NAND FLASH memory through the EMIF interface. The memory capacity of the NAND FLASH memory is 1Gb; the DSP chip is connected to the SPI FLASH memory through the SIP / CSO interface.

[0029] Furthermore, the DSP chip is also configured with a level conversion module. The DSP chip is connected to the level conversion module through the UART interface and the JTAG interface. The level conversion module is connected to the second debug port through the I / O interface. The DSP chip outputs the level to the level conversion module. After conversion by the level conversion module, the level conversion module outputs a 3.3V level to the second debug port. The second debug port is used to debug or test the DSP chip.

[0030] In this embodiment, the FPGA chip is configured with a power input interface and a clock input interface, and the DSP chip is configured with a power input interface, a clock input interface, and a startup configuration input interface; the model of the DSP chip is FT-M6678N, the main frequency is 1GHz, and the number of cores is 8; the FPGA chip adopts a domestic chip, for example, the model is K7-325T, the resource is 325T, and this model of FPGA chip is produced by Fudan Microelectronics Manufacturer; the power consumption of the image processing digital board based on DSP and FPGA is less than or equal to 9W, and its weight without structural parts does not exceed 150g, its length is 181mm, and its width is 80mm.

[0031] The DSP and FPGA-based image processing digital board provided in this embodiment adopts a domestic 8-core DSP+FPGA as the main control, and is equipped with 2GBDDR3 memory and 2Gb Flash storage, has high-performance floating-point computing capabilities and rich programmable logic, and supports audio acquisition, playback, network transmission, 1553B interface and serial port communication capabilities by integrating interface chips such as audio CODEC, Ethernet PHY, 1553B and RS422. The DSP and FPGA-based image processing digital board provided in this embodiment can be used in professional fields such as voice processing, signal processing and image processing.

[0032] The optional implementation modes of the embodiments of the utility model are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the utility model are not limited to the specific details in the above implementation modes. Within the technical concept of the embodiments of the utility model, the technical scheme of the embodiments of the utility model can be subjected to various simple modifications, and these simple modifications all belong to the protection scope of the embodiments of the utility model.

[0033] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the utility model will not further describe various possible combinations.

[0034] In addition, various implementations of the embodiments of the present utility model can also be arbitrarily combined, as long as they do not violate the concept of the embodiments of the present utility model, they should also be regarded as the contents disclosed in the embodiments of the present utility model.

Claims

1. A digital image processing board based on DSP and FPGA, comprising a baseboard, characterized in that: The DSP and FPGA-based image processing digital board includes: a rectangular connector, an FPGA chip, a DSP chip, an audio acquisition and playback unit, a MOSFET circuit unit, a conversion unit, a network transmission unit, and a control unit configured on the base plate; The rectangular connector is respectively connected to the audio acquisition and playback unit, the MOSFET circuit unit, the conversion unit, the network transmission unit and the control unit; The FPGA chip is respectively connected to the audio acquisition and playback unit, the MOSFET circuit unit, the conversion unit, the network transmission unit and the control unit; The FPGA chip is connected to the DSP chip via a GPIO interface and a configuration IO interface.

2. The image processing digital board based on DSP and FPGA according to claim 1, characterized in that: The audio acquisition and playback unit includes a signal conditioning module and an audio CODEC module; The signal conditioning module is connected to the rectangular connector via a plurality of AUDIO IN interfaces and a plurality of AUDIO OUT interfaces; The audio CODEC module is connected to the FPGA chip via an I2S / SPI bus.

3. The image processing digital board based on DSP and FPGA according to claim 2, characterized in that: The multiple AUDIO IN interfaces are 4 AUDIO IN interfaces, and the multiple AUDIO OUT interfaces are 4 AUDIO OUT interfaces.

4. The image processing digital board based on DSP and FPGA according to claim 1, characterized in that: The MOSFET circuit unit includes a MOSFET driving circuit module and a MOSFET isolation circuit module; The MOSFET driving circuit module and the MOSFET isolation circuit module are respectively connected to the rectangular connector through corresponding GND / OPEN interfaces; The MOSFET driving circuit module and the MOSFET isolation circuit module are respectively connected to the FPGA chip through corresponding I / O ports.

5. The image processing digital board based on DSP and FPGA according to claim 1, characterized in that: The conversion unit includes an overvoltage protection module and a conversion module, and the overvoltage protection module is connected to the conversion module; The rectangular connector is connected to the overvoltage protection module, and the conversion module is connected to the FPGA chip via a UART interface; The overvoltage protection module is a TVS protection module, and the conversion module is an RS422 conversion module.

6. The image processing digital board based on DSP and FPGA according to claim 5, characterized in that: The FPGA chip is connected to the corresponding conversion unit via two UART interfaces.

7. The image processing digital board based on DSP and FPGA according to claim 1, characterized in that: The network transmission unit includes a network transformer module and a network transmission module, and the network transformer module is connected to the network transmission module via an MDI interface; The rectangular connector is connected to the network transformer module, and the network transmission module is connected to the FPGA chip via the MII interface; The network transformer module adopts the TF1102 network transformer, and the network transmission module adopts the Ethernet PHY chip.

8. The image processing digital board based on DSP and FPGA according to claim 1, characterized in that: The control unit includes a 1553B controller; The rectangular connector is connected to the 1553B controller via a transformer coupling connection; The 1553B controller is connected to the FPGA chip via a HOST interface, and the RT address of the 1553B controller is also connected to the FPGA chip.

9. The image processing digital board based on DSP and FPGA according to claim 1, characterized in that: The DSP and FPGA-based image processing digital board also includes: a clock unit and an SM chip configured on the baseboard; The SM chip is connected to the DSP chip, and the clock unit is connected to the FPGA chip via an FPGA clock interface, a DSP clock interface, a PHY clock interface, a 1533B clock interface and an OODEC clock interface.

10. The image processing digital board based on DSP and FPGA according to claim 1, characterized in that: The FPGA chip is also connected to a 128Mb PROM memory, 3 BPI NOR FLASH memories and a first debug port module on the baseboard; The 128Mb PROM memory is connected to the FPGA chip via a BPI interface; Each BPI NOR FLASH memory is connected to the FPGA chip via a CE interface and a parallel port interface; The first debug port module is connected to the FPGA chip via a JTAG interface.

Images