Pixel and display device

Abstract

The utility model relates to a pixel and a display device. The pixel includes: a first transistor including a second electrode and a first electrode electrically connected to a first power supply line supplying a first driving power supply, the first transistor having a gate electrode connected to a first node; a second transistor including a second electrode and a first electrode electrically connected to the data line, and a gate electrode electrically connected to the first scan line; a light-emitting element having a second electrode electrically connected to a second power supply line supplying a second driving power supply; a third transistor turned on between the data line and the first electrode of the light emitting element, and having a gate electrode electrically connected to the second scan line; a fourth transistor turned on between a second node turned on with the second electrode of the first transistor and the first electrode of the light emitting element, and having a gate electrode electrically connected to a light emission control line; a first capacitor having a first electrode connected to a second electrode of the second transistor and a second electrode connected to the first node; and a second capacitor connected between the first power supply line and the first node.

Description

Technical Field

[0001] The utility model relates to a pixel and a display device equipped with the pixel. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has become prominent. As a result, the use of display devices such as liquid crystal display devices (Liquid Crystal Display Device) and organic light emitting display devices (Organic Light Emitting Display Device) has increased.

[0003] Recently, head mounted display devices (HMD) are being developed. A head mounted display device is a display device that enables a user to wear glasses or a helmet to form a focus at a distance close to the user's eyes to experience virtual reality (VR) or augmented reality (AR). High-resolution panels are suitable for head mounted display devices, so pixels that can be applied to high-resolution panels are required. Utility Model Content

[0004] An object of the present invention is to provide a pixel applicable to a high-resolution panel and a display device having the same.

[0005] According to an embodiment of the utility model, a pixel comprises: a first transistor, including a second electrode and a first electrode electrically connected to a first power line supplying a first driving power source, and a gate electrode connected to a first node; a second transistor, including a second electrode and a first electrode electrically connected to a data line, and a gate electrode electrically connected to a first scanning line; a light-emitting element, a second electrode electrically connected to a second power line supplying a second driving power source; a third transistor connected between the data line and the first electrode of the light-emitting element, and a gate electrode electrically connected to a second scanning line; a fourth transistor connected between a second node connected to the second electrode of the first transistor and the first electrode of the light-emitting element, and a gate electrode electrically connected to a light-emitting control line; a first capacitor, a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the first node; and a second capacitor connected between the first power line and the first node.

[0006] According to an embodiment, the pixel further includes: a fifth transistor connected between the first node and the second node, and a gate electrode of the fifth transistor is electrically connected to a third scan line.

[0007] According to an embodiment, the pixel further includes: a sixth transistor connected between the first node and the first electrode of the light emitting element, and having a gate electrode electrically connected to the second scan line.

[0008] According to an embodiment, in a horizontal period in which a data signal is supplied to the pixel, during at least a portion of a first period, the second transistor to the sixth transistor are set to an on state, and during the first period, a voltage of a reference power supply having a voltage value between the first driving power supply and the second driving power supply is supplied to the data line.

[0009] According to an embodiment, during the first period, the third transistor, the fifth transistor and the sixth transistor are set to an off state at least once.

[0010] According to an embodiment, in the horizontal period, during a second period after the first period, the second transistor and the fifth transistor are set to a conductive state, and during the second period, the voltage of the reference power supply is supplied to the data line.

[0011] According to an embodiment, in the horizontal period, during a third period after the second period, the second transistor is set to a turned-on state, and during the third period, a voltage of the data signal is supplied to the data line.

[0012] According to an embodiment, the pixel further includes: a sixth transistor connected between the first electrode of the first capacitor and the first electrode of the light emitting element, and having a gate electrode electrically connected to the second scanning line.

[0013] According to an embodiment, the third scan line and the second scan line are the same scan line.

[0014] According to an embodiment, in a horizontal period in which a data signal is supplied to the pixel, during at least a portion of a first period, the second transistor to the sixth transistor are set to an on state, and during the first period, a voltage of a reference power supply having a voltage value between the first driving power supply and the second driving power supply is supplied to the data line.

[0015] According to an embodiment, during the first period, the third transistor, the fifth transistor and the sixth transistor are set to an off state at least once.

[0016] According to an embodiment, in the horizontal period, during a second period after the first period, the second transistor, the third transistor, the fifth transistor and the sixth transistor are set to a conductive state, and during the second period, the voltage of the reference power supply is supplied to the data line.

[0017] According to an embodiment, in the horizontal period, during a third period after the second period, the second transistor is set to a turned-on state, and during the third period, a voltage of the data signal is supplied to the data line.

[0018] The display device according to the embodiment of the utility model comprises: a pixel connected to a first scan line, a second scan line, a third scan line, a data line and a light emitting control line; a pixel located in an i-th (i is an integer greater than 0) pixel row and a j-th (j is an integer greater than 0) pixel column comprises: a first transistor, comprising a second electrode and a first electrode electrically connected to a first power line supplying a first driving power source, and a gate electrode connected to a first node; a second transistor, comprising a second electrode and a first electrode electrically connected to a j-th data line, and turned on when a first scan signal is supplied to the i-th first scan line; a light emitting element, the second electrode of which is connected to a first power line supplying a second driving power source; Two power lines are electrically connected; a third transistor is connected between the jth data line and the first electrode of the light emitting element, and is turned on when the second scan signal is supplied to the i-th second scan line; a fourth transistor is connected between the second node connected to the second electrode of the first transistor and the first electrode of the light emitting element, and is turned off when the light emitting control signal is supplied to the kth (k is an integer greater than 0) light emitting control line; a first capacitor, the first electrode of which is connected to the second electrode of the second transistor, and the second electrode of which is connected to the first node; and a second capacitor is connected between the first power line and the first node.

[0019] According to an embodiment, the pixel located in the i-th pixel row and the j-th pixel column further includes: a fifth transistor, which is connected between the first node and the second node and is turned on when a third scan signal is supplied to the i-th third scan line; and a sixth transistor, which is connected between the first node and the first electrode of the light-emitting element and is turned on when the second scan signal is supplied to the i-th second scan line.

[0020] According to an embodiment, the horizontal period in which the data signal is supplied to the pixel located in the i-th pixel row and the j-th pixel column includes a first period, a second period and a third period, and the display device further comprises: a data driving unit for supplying a voltage of a reference power supply having a voltage value between the first driving power supply and the second driving power supply to the j-th data line during the first period and the second period, and supplying the data signal during the third period; a first scanning driving unit for supplying the first scanning signal to the i-th first scanning line during the first period to the third period; a second scanning driving unit for supplying the second scanning signal to the i-th second scanning line during the first period; a third scanning driving unit for supplying the third scanning signal to the i-th third scanning line during the first period and the second period; and a light-emitting driving unit for supplying the light-emitting control signal to the k-th light-emitting control line during the second period and the third period.

[0021] According to an embodiment, the second scan driving part supplies a gate-off voltage to the i-th second scan line at least once in the first period, and the third scan driving part supplies a gate-off voltage to the i-th third scan line at least once in the first period.

[0022] According to an embodiment, the pixel located in the i-th pixel row and the j-th pixel column further includes: a fifth transistor, which is connected between the first node and the second node and is turned on when a third scan signal is supplied to the i-th third scan line; and a sixth transistor, which is connected between the first electrode of the first capacitor and the first electrode of the light-emitting element and is turned on when the second scan signal is supplied to the i-th second scan line.

[0023] According to an embodiment, the horizontal period in which the data signal is supplied to the pixel located in the i-th pixel row and the j-th pixel column includes a first period, a second period and a third period, and the display device further comprises: a data driving unit for supplying a voltage of a reference power supply having a voltage value between the first driving power supply and the second driving power supply to the j-th data line during the first period and the second period, and supplying the data signal during the third period; a first scanning driving unit for supplying the first scanning signal to the i-th first scanning line during the first period to the third period; a second scanning driving unit for supplying the second scanning signal to the i-th second scanning line during the first period and the second period; a third scanning driving unit for supplying the third scanning signal to the i-th third scanning line during the first period and the second period; and a light-emitting driving unit for supplying the light-emitting control signal to the k-th light-emitting control line during the second period and the third period.

[0024] According to an embodiment, the i-th second scan line and the i-th third scan line are set as the same scan line, and the second scan driving unit and the third scan driving unit are set as the same driving unit.

[0025] The subject of the present invention is not limited to the above-mentioned subject, and a person skilled in the art can clearly understand another technical subject not mentioned from the following description.

[0026] The pixel according to the embodiment of the present invention can use six transistors and two capacitors to compensate for the threshold voltage of the driving transistor, and thus can be applicable to a high-resolution display device.

[0027] The pixel according to the embodiment of the present invention can transmit the data signal by coupling of the capacitor, so the voltage range of the data signal can be set to be wide.

[0028] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be made without departing from the concept and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 FIG. 1 is a diagram showing a display device according to an embodiment of the present invention.

[0030] Figure 2 It is shown Figure 1 A diagram of an embodiment of a scanning driving unit and a light emitting driving unit is shown.

[0031] Figure 3 is a diagram showing a pixel according to an embodiment of the present invention.

[0032] Figure 4 It is shown Figure 3 FIG. 1 is a waveform diagram of an embodiment of a pixel driving method shown in FIG.

[0033] Figure 5a to Figure 5d is shown corresponding to Figure 4 FIG. 5 is a diagram of an embodiment of a driving waveform of a pixel working process.

[0034] Figure 6 It is shown Figure 3 A graph of the current deviation of the pixel is shown.

[0035] Figure 7 It is shown Figure 3 FIG. 1 is a diagram showing an embodiment of a method for driving a pixel.

[0036] Figure 8 is a diagram showing a pixel according to an embodiment of the present invention.

[0037] Fig. 9 It is shown Figure 8 FIG. 1 is a diagram showing an embodiment of a method for driving a pixel.

[0038] Figures 10a to 10d is shown corresponding to Fig. 9 FIG. 5 is a diagram of an embodiment of a driving waveform of a pixel working process.

[0039] Fig.11 It is shown Figure 8 A graph of the current deviation of the pixel is shown.

[0040] Fig.12 is a diagram showing a pixel according to an embodiment of the present invention.

[0041] Fig.13 It is shown Figure 8 FIG. 1 is a diagram showing an embodiment of a method for driving a pixel. DETAILED DESCRIPTION

[0042] Hereinafter, with reference to the attached drawings, a plurality of embodiments of the present invention will be described in detail so that a person with ordinary knowledge in the technical field to which the present invention belongs can easily implement the present invention. The present invention can be implemented in various forms and is not limited to the embodiments described herein.

[0043] In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same reference numerals are used throughout the specification for the same or similar components. Therefore, the reference numerals described above can also be used in other drawings.

[0044] In addition, for the sake of convenience, the size and thickness of each structure appearing in the drawings are arbitrarily shown, so the present invention is not necessarily limited to the situation shown in the drawings. In the drawings, in order to clearly present multiple layers and regions, the thickness may be exaggerated.

[0045] In the description, the expression "same" may mean "substantially the same". That is, it may be the same to the extent that a person with ordinary knowledge can accept it as the same. Other expressions may also be expressions in which "substantially" is omitted.

[0046] Some embodiments are related to functional blocks, units and / or modules and are described in the attached drawings. Those skilled in the art will understand that such blocks, units and / or modules are physically implemented by logic circuits, individual components, microprocessors, hard-wire circuits, storage elements, wiring connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, software programming and control can be used to perform the various functions discussed in the utility model, which can be selectively driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented by a combination of dedicated hardware that performs a part of the function and a processor that performs other functions (for example, one or more programmed microprocessors and related circuits). In addition, in some embodiments, blocks, units and / or modules can also be physically separated into more than two individual blocks, units and / or modules that interact within the scope of the concept of the utility model. In addition, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the concept of the present invention.

[0047] The "connection" between two structures may be used to include both electrical connection and physical connection, and need not be limited to this. For example, the "connection" used with reference to a circuit diagram may mean electrical connection, while the "connection" used with reference to a cross-sectional view or a plan view may mean physical connection.

[0048] Although the terms first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can also be the second component within the technical concept of the present invention.

[0049] On the other hand, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms. In addition, each embodiment disclosed below can be implemented alone, or combined with at least one other embodiment to implement in a composite manner.

[0050] Figure 1 FIG. 1 is a diagram showing a display device according to an embodiment of the present invention. Figure 2 It is shown Figure 1 A diagram of an embodiment of a scanning driving unit and a light emitting driving unit is shown.

[0051] Reference Figure 1 According to an embodiment of the present invention, the display device 100 may include a pixel unit 110 (or a panel), a timing control unit 120, a scan driver 130, a data driver 140, a light driver 150, and a power supply unit 160. The above structures may be implemented as separate integrated circuits, and two or more of the above structures may be combined into one integrated circuit. In addition, the scan driver 130 and the light driver 150 may be formed in the pixel unit 110.

[0052] The pixel portion 110 may include pixels PX (here, n, m, o are integers greater than 0) connected to the first scan lines SL11, SL12, ..., SL1n, the second scan lines SL21, SL22, ..., SL2n, the third scan lines SL31, SL32, ..., SL3n, the data lines DL1, DL2, ..., DLm, the light emitting control lines EL1, EL2, ..., ELo, and the power lines PL1 and PL2.

[0053] As an example, a pixel PXij (refer to Figure 3 ) can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the k-th light-emitting control line ELk and the j-th data line DLj (here, i is an integer less than n, j is an integer less than m, and k is an integer less than o). Here, k can be the same as i, or a number less than i. As an example, when each of the light-emitting control lines (EL1 to ELo) is connected to the pixels PX located on one horizontal line, k can be the same number as i. As an example, when each of the light-emitting control lines (EL1 to ELo) is connected to the pixels PX located on more than two horizontal lines, k can be a number less than i.

[0054] When the first scan signal is supplied to the first scan lines SL11 to SL1n, the pixel PX is selected by horizontal line units (for example, the pixels PX connected to the same scan line can be classified into one horizontal line (or, pixel row)), and the pixel PX selected by the first scan signal can receive a data signal from the data line (any one of DL1 to DLm) connected to itself. The pixel PX receiving the data signal can generate light of a predetermined brightness corresponding to the voltage of the data signal.

[0055] The scan driving part 130 may receive a scan driving signal SCS from the timing control part 120. The scan driving signal SCS may include at least one scan start signal and a clock signal required for driving the scan driving part 130. The scan driving part 130 may generate a first scan signal, a second scan signal, and a third scan signal while shifting the scan start signal corresponding to the clock signal.

[0056] For this reason, Figure 2 As shown, the scan driving unit 130 may include a first scan driving unit 132 , a second scan driving unit 134 and a third scan driving unit 136 .

[0057] The first scan driver 132 may receive the first scan start signal FLM1 and generate a first scan signal while shifting the first scan start signal FLM1 in accordance with the clock signal. The first scan driver 132 may sequentially supply the first scan signal to the first scan lines SL11 to SL1n.

[0058] The second scan driver 134 may receive the second scan start signal FLM2 and generate a second scan signal while shifting the second scan start signal FLM2 in accordance with the clock signal. The second scan driver 134 may sequentially supply the second scan signal to the second scan lines SL21 to SL2n.

[0059] The third scan driver 136 may receive the third scan start signal FLM3 and generate a third scan signal while shifting the third scan start signal FLM3 in accordance with the clock signal. The third scan driver 136 may sequentially supply the third scan signal to the third scan lines SL31 to SL3n.

[0060] The first scan signal, the second scan signal, and the third scan signal may set a gate-on voltage so that a transistor included in the pixel PX may be turned on.

[0061] As an example, the low-level first scan signal, the second scan signal, and the third scan signal can be supplied to the P-type transistor, and the high-level first scan signal, the second scan signal, and the third scan signal can be supplied to the N-type transistor. The transistor receiving the first scan signal, the second scan signal, or the third scan signal can be turned on corresponding to the first scan signal, the second scan signal, or the third scan signal.

[0062] Thereafter, the case where the first scan signal, the second scan signal, or the third scan signal is supplied may mean the case where the gate-on voltage is supplied to the first scan line SL1, the second scan line SL2, or the third scan line SL3. Also, the case where the first scan signal, the second scan signal, or the third scan signal is not supplied may mean the case where the gate-off voltage is supplied to the first scan line SL1, the second scan line SL2, or the third scan line SL3.

[0063] exist Figure 2 , the first scan driver 132, the second scan driver 134, and the third scan driver 136 are shown so as to be connected to each of the first scan line SL1, the second scan line SL2, and the third scan line SL3, but the embodiments of the utility model are not limited thereto. As an example, at least two scan lines (at least two of SL1, SL2, and SL3) of the first scan line SL1, the second scan line SL2, and the third scan line SL3 may also be driven by one scan driver.

[0064] The data driving unit 140 may receive the output data Dout and the data driving signal DCS from the timing control unit 120. The data driving signal DCS may include a sampling signal and / or a timing signal required for driving the data driving unit 140. The data driving unit 140 may generate a data signal based on the data driving signal DCS and the output data Dout. As an example, the data driving unit 140 may generate an analog data signal based on the grayscale of the output data Dout. In 1 horizontal period 1H (reference Figure 4 ), the data driving unit 140 may sequentially supply the voltage of the reference power source Vref and the voltage Vdata of the data signal to the data lines DL1 to DLm. The reference power source Vref may be set to a positive voltage.

[0065] The light driving unit 150 may receive a light driving signal ECS from the timing control unit 120. The light driving signal ECS may include a light start signal and a clock signal required for driving the light driving unit 150. The light driving unit 150 may generate a light control signal while shifting the light start signal in accordance with the clock signal.

[0066] As an example, Figure 2 As shown, the light emitting driving unit 150 may receive the light emitting start signal EFLM and generate a light emitting control signal while shifting the light emitting start signal EFLM in accordance with the clock signal. The light emitting driving unit 150 may sequentially supply the light emitting control signal to the light emitting control lines (EL1 to ELo). The light emitting control signal may be set to a gate-off voltage so that the transistor included in the pixel PX may be turned off.

[0067] As an example, a high-level light-emitting control signal may be supplied to a P-type transistor, and a low-level light-emitting control signal may be supplied to an N-type transistor. The transistor receiving the light-emitting control signal may be turned off in response to the light-emitting control signal. Then, the case where the light-emitting control signal is supplied may mean the case where the gate-off voltage is supplied to the light-emitting control line EL. And, the case where the light-emitting control signal is not supplied may mean the case where the gate-on voltage is supplied to the light-emitting control line EL.

[0068] The timing control unit 120 may receive input data Din and a control signal CS from the host system through an interface. As an example, the timing control unit 120 may receive input data Din and a control signal CS from at least one of a GPU (Graphics Processing Unit), a CPU (Central Processing Unit), and an AP (Application Processor) included in the host system. The control signal CS may include various signals including a clock signal.

[0069] The timing control unit 120 may generate a scan driving signal SCS, a data driving signal DCS and a light emitting driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS and the light emitting driving signal ECS may be supplied to the scan driving unit 130, the data driving unit 140 and the light emitting driving unit 150, respectively.

[0070] The timing control unit 120 may rearrange the input data Din according to the specification of the display device 100. In addition, the timing control unit 120 may correct the input data Din to generate the output data Dout, and supply the output data Dout to the data driving unit 140. In an embodiment, the timing control unit 120 may correct the input data Din corresponding to the optical measurement result measured in the process.

[0071] The power supply unit 160 may generate various power sources required for driving the display device 100. For example, the power supply unit 160 may generate a first driving power source VDD and a second driving power source VSS.

[0072] The first driving power source VDD may be a power source that supplies a driving current to the pixel PX. The second driving power source VSS may be a power source that receives a driving current from the pixel PX. During a period in which the pixel PX is set to a light emitting state, the first driving power source VDD may be set to a voltage higher than the second driving power source VSS.

[0073] The first driving power VDD generated in the power supply unit 160 may be supplied to the first power line PL1, and the second driving power VSS may be supplied to the second power line PL2. The first power line PL1 and the second power line PL2 may be connected to the pixel PX, but the present invention is not limited thereto.

[0074] In an embodiment, the first power line PL1 may be composed of a plurality of power lines, and the plurality of power lines are connected to different pixels PX. In an embodiment, the second power line PL2 may be composed of a plurality of power lines, and the plurality of power lines are connected to different pixels PX. That is, in an embodiment of the present utility model, the pixel PX may be connected to any one of the first power lines PL1 and any one of the second power lines PL2.

[0075] Figure 3 is a diagram showing a pixel according to an embodiment of the present invention. Figure 3 , pixels located on the i-th horizontal line and the j-th vertical line are shown.

[0076] Reference Figure 3 According to an embodiment of the present invention, the pixel PXij can be connected to the corresponding signal lines SL1i, SL2i, SL3i, ELk, and DLj. For example, the pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the k-th light emitting control line ELk, and the j-th data line DLj. In an embodiment, the pixel PXij can also be connected to the first power line PL1 and the second power line PL2.

[0077] The pixel PXij according to the embodiment of the present invention may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0078] The light emitting element LD may be connected between the first power line PL1 and the second power line PL2. As an example, the first electrode (or anode electrode) of the light emitting element LD may be electrically connected to the first power line PL1 via the third node N3, the fourth transistor M4, the second node N2, and the first transistor M1, and the second electrode (or cathode electrode) of the light emitting element LD may be electrically connected to the second power line PL2. The light emitting element LD may generate light of a predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0079] The light emitting element LD may be an organic light emitting diode. In addition, the light emitting element LD may be an inorganic light emitting diode such as a micro LED or a quantum dot light emitting diode. In addition, the light emitting element LD may be a composite element of organic and inorganic substances. Figure 3 In the figure, the pixel PXij is shown to include a single light emitting element LD, but in another embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD are connected in series, in parallel, or in series and parallel.

[0080] The pixel circuit may include a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 , a first capacitor C1 , and a second capacitor C2 .

[0081] The first transistor M1 to the sixth transistor M6 can be configured in various forms such as MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), TFT (Thin Film Transistor), FET (Field Effect Transistor), BJT (Bipolar Junction Transistor), etc.

[0082] In an embodiment, the first to sixth transistors M1 to M6 may be formed as P-type transistors, but this is exemplary, and at least one of the first to sixth transistors M1 to M6 may be replaced by an N-type transistor.

[0083] The first electrode of the first transistor M1 (or the driving transistor) may be electrically connected to the first power line PL1, and the second electrode may be connected to the second node N2. Here, the state of being connected includes the meaning of being electrically connected. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 as described above may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD in accordance with the voltage of the first node N1.

[0084] The second transistor M2 may be connected between the data line DLj and the first electrode of the first capacitor C1. Also, the gate electrode of the second transistor M2 may be electrically connected to the first scan line SL1i. When the first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 as above is turned on to electrically connect the data line DLj and the first electrode of the first capacitor C1.

[0085] The third transistor M3 may be connected between the data line DLj and the third node N3. Also, the gate electrode of the third transistor M3 may be electrically connected to the second scan line SL2i. When the second scan signal GR is supplied to the second scan line SL2i, the third transistor M3 is turned on to electrically connect the data line DLj and the third node N3.

[0086] The fourth transistor M4 may be connected between the second node N2 and the third node N3 (i.e., the first electrode of the light emitting element LD). In addition, the gate electrode of the fourth transistor M4 may be electrically connected to the light emitting control line ELk. When the light emitting control signal EM is supplied to the light emitting control line ELk, the fourth transistor M4 as above is turned off, and when the light emitting control signal EM is not supplied to the light emitting control line ELk, the fourth transistor M4 is turned on. If the fourth transistor M4 is turned off, the first transistor M1 and the light emitting element LD may be electrically disconnected.

[0087] The fifth transistor M5 may be turned on between the first node N1 and the second node N2. Also, the gate electrode of the fifth transistor M5 may be electrically connected to the third scan line SL3i. When the third scan signal GC is supplied to the third scan line SL3i, the fifth transistor M5 as above is turned on to electrically connect the first node N1 and the second node N2. In this case, the gate electrode (i.e., the first node N1) and the second electrode (i.e., the second node N2) of the first transistor M1 are electrically connected, so the first transistor M1 may be turned on in a diode form.

[0088] The first electrode of the sixth transistor M6 may be connected to the first node N1, and the second electrode may be connected to the third node N3. Furthermore, the gate electrode of the sixth transistor M6 may be electrically connected to the second scan line SL2i. When the second scan signal GR is supplied to the second scan line SL2i, the sixth transistor M6 is turned on to electrically connect the first node N1 and the third node N3.

[0089] The first electrode of the first capacitor C1 may be connected to the second electrode of the second transistor M2, and the second electrode may be connected to the first node N1. The first capacitor C1 as described above may change the voltage of the first node N1 in accordance with the voltage supplied from the second transistor M2. As an example, the first capacitor C1 may be driven as a coupling capacitor.

[0090] The first electrode of the second capacitor C2 may be electrically connected to the first power line PL1, and the second electrode may be connected to the first node N1. That is, the second capacitor C2 may be connected between the first power line PL1 and the first node N1. The second capacitor C2 may store the voltage of the first node N1.

[0091] Figure 4 It is shown Figure 3 FIG. 1 is a waveform diagram of an embodiment of a pixel driving method shown in FIG.

[0092] Reference Figure 4 , a horizontal period 1H (or a specific horizontal period) for supplying data signals to pixels PXij located at an i-th horizontal line and a j-th vertical line may be divided into a first period T1, a second period T2, and a third period T3.

[0093] The data driving unit 140 may supply the voltage of the reference power supply Vref to the data line DLj during the first period T1 and the second period T2, and supply the voltage Vdata of the data signal during the third period T3. The reference power supply Vref may be set to a voltage between the first driving power supply VDD and the second driving power supply VSS. As an example, when the reference power supply Vref is supplied to the first electrode of the light emitting element LD, it may be set to a voltage at which the light emitting element LD is turned off. The voltage Vdata of the data signal may be set to a predetermined voltage within the voltage range of the data signal corresponding to the grayscale.

[0094] The scan driver 130 (or the first scan driver 132) may supply the first scan signal GW to the first scan line SL1i during the first period T1 to the third period T3. The scan driver 130 (or the second scan driver 134) may supply the second scan signal GR to the second scan line SL2i during the first period T1. The scan driver 130 (or the third scan driver 136) may supply the third scan signal GC to the third scan line SL3i during the first period T1 and the second period T2. The light emitting driver 150 may supply the light emitting control signal EM to the light emitting control line ELk during the second period T2 and the third period T3.

[0095] During the first period T1, the voltage of the reference power supply Vref may be supplied to the first electrode of the first capacitor C1, the first node N1, the second node N2, and the third node N3. During the first period T1, the first capacitor C1, the second capacitor C2, and the light emitting element LD may be initialized by the voltage of the reference power supply Vref. The first period T1 as above may be named as an initialization period.

[0096] During the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the second capacitor C2. The second period T2 may be named a threshold voltage compensation period.

[0097] The third period T3 is a period in which the voltage Vdata of the data signal is supplied from the data line DLj to the pixel PXij. During the third period T3, a voltage corresponding to the data signal may be applied to the first node N1. The third period T3 as above may be named a data writing period.

[0098] During the fourth period T4, the first transistor M1 may control the amount of current flowing from the first driving power source VDD to the second driving power source VSS via the light emitting element LD corresponding to the voltage of the first node N1. During the fourth period T4, the light emitting element LD may emit light at a brightness corresponding to the amount of current supplied from the first transistor M1. The fourth period T4 as above may be named as a light emitting period.

[0099] Figure 5a to Figure 5d is shown corresponding to Figure 4 FIG. 5 is a diagram of an embodiment of a driving waveform of a pixel working process.

[0100] Reference Figure 5a During the first period T1, the first scan signal GW is supplied to the first scan line SL1i, the second scan signal GR is supplied to the second scan line SL2i, and the third scan signal GC is supplied to the third scan line SL3i. Also, the emission control signal EM is not supplied to the emission control line ELk during the first period T1.

[0101] If the first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 is turned on. If the second transistor M2 is turned on, the voltage of the reference power source Vref from the data line DLj may be supplied to the first electrode of the first capacitor C1.

[0102] When the second scan signal GR is supplied to the second scan line SL2i, the third transistor M3 and the sixth transistor M6 are turned on. When the third transistor M3 and the sixth transistor M6 are turned on, the voltage of the reference power source Vref from the data line DLj can be supplied to the first node N1 and the third node N3.

[0103] If the voltage of the reference power supply Vref is supplied to the first node N1, the first capacitor C1 can be initialized by the voltage of the reference power supply Vref. As an example, during the first period T1, the voltage of the reference power supply Vref can be supplied to the first electrode and the second electrode of the first capacitor C1, thereby initializing the first capacitor C1. In addition, if the voltage of the reference power supply Vref is supplied to the first node N1, the second capacitor C2 can be initialized to the voltage of the reference power supply Vref.

[0104] If the voltage of the reference power supply Vref is supplied to the third node N3, the light emitting element LD can be initialized by the voltage of the reference power supply Vref. As an example, a parasitic capacitor (not shown) of the light emitting element LD can be discharged by the voltage of the reference power supply Vref. Additionally, if the voltage of the reference power supply Vref is supplied to the third node N3, the light emitting element LD can be set to a non-luminous state. For this purpose, the voltage of the reference power supply Vref can be set to make the light emitting element LD non-luminous.

[0105] If the third scan signal GC is supplied to the third scan line SL3i, the fifth transistor M5 is turned on. If the fifth transistor M5 is turned on, the first node N1 and the second node N2 may be electrically connected. At this time, the second node N2 may be initialized to the voltage of the reference power supply Vref.

[0106] If the light emission control signal EM is not supplied to the light emission control line ELk, the fourth transistor M4 is set to a turned-on state. If the fourth transistor M4 is turned on, the second node N2 and the third node N3 may be electrically connected.

[0107] During the first period T1, the second transistor M2 to the sixth transistor M6 can be set to a conductive state, so that the voltage of the reference power source Vref from the data line DLj is supplied to the first node N1, the second node N2 and the third node N3. Therefore, the first capacitor C1, the second capacitor C2 and the light emitting element LD can be initialized by the voltage of the reference power source Vref.

[0108] Reference Figure 5b During the second period T2, the first scan signal GW is supplied to the first scan line SL1i, so the second transistor M2 remains in the on state. During the second period T2, the third scan signal GC is supplied to the third scan line SL3i, so the fifth transistor M5 remains in the on state.

[0109] During the second period T2, the supply of the second scan signal GR to the second scan line SL2i is interrupted. If the supply of the second scan signal GR to the second scan line SL2i is interrupted, the third transistor M3 and the sixth transistor M6 are turned off.

[0110] During the second period T2, the light emitting control signal EM is supplied to the light emitting control line ELk. If the light emitting control signal EM is supplied to the light emitting control line ELk, the fourth transistor M4 is turned off.

[0111] If the fifth transistor M5 is turned on, the first transistor M1 is turned on in a diode form. If the first transistor M1 is turned on in a diode form, a voltage obtained by subtracting an absolute value threshold voltage of the first transistor M1 from the first driving power source VDD may be applied to the first node N1.

[0112] If the second transistor M2 is turned on, the voltage of the reference power source Vref is supplied to the first electrode of the first capacitor C1. Then, during the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in each of the first capacitor C1 and the second capacitor C2.

[0113] Reference Figure 5c During the third period T3, the first scan signal GW is supplied to the first scan line SL1i, so the second transistor M2 maintains a turned-on state.

[0114] If the second transistor M2 is turned on, the voltage Vdata of the data signal from the data line DLj is supplied to the first electrode of the first capacitor C1. If the voltage Vdata of the data signal is supplied to the first electrode of the first capacitor C1, the voltage of the first electrode of the first capacitor C1 changes from the voltage of the reference power supply Vref to the voltage Vdata of the data signal. At this time, the voltage of the first node N1 also changes through coupling of the first capacitor C1.

[0115] Here, the voltage variation of the first node N1 may be determined corresponding to the ratio of the first capacitor C1 to the second capacitor C2. As an example, the voltage of the first node N1 may be changed from the voltage obtained by subtracting the absolute value threshold voltage of the first transistor M1 from the first driving power source VDD to a value equivalent to the multiplication of the voltage variation of the first electrode of the first capacitor C1 and C1 / (C1+C2). When the voltage variation of the first node N1 is controlled by the ratio of the first capacitor C1 to the second capacitor C2 as described above, the voltage range of the data signal may be sufficiently wide.

[0116] For example, when the data signal is directly supplied to the gate electrode of the first transistor M1, the voltage range of the data signal is set to be relatively narrow. When the data signal has a narrow voltage range, various grayscales (for example, 256 grayscales) need to be represented by the narrow voltage range, so it is difficult to represent the correct grayscale.

[0117] On the contrary, when the voltage supplied to the gate electrode of the first transistor M1 is controlled by the ratio of the first capacitor C1 and the second capacitor C2 as in the embodiment of the utility model of the present application, the voltage range of the data signal can be set to be sufficiently wide. As an example, a voltage corresponding to the value multiplied by the voltage of the data signal and C1 / (C1+C2) can be transmitted to the gate electrode of the first transistor M1, thereby setting the voltage range of the data signal to be wide. When the data signal has a wide voltage range, grayscale can be easily embodied.

[0118] During the third period T3, the second capacitor C2 stores the voltage of the first node N1. Here, the voltage of the first node N1 can be determined by the threshold voltage of the first transistor M1 and the voltage Vdata of the data signal, so during the third period T3, the second capacitor C2 stores a voltage corresponding to the data signal and the threshold voltage of the first transistor M1. Additionally, during the third period T3, the third transistor M3 to the sixth transistor M6 are set to a cut-off state.

[0119] Reference Figure 5d During the fourth period T4, the scan signals GW, GR, GC are not supplied to the scan lines SL1i, SL2i, SL3i. In this case, the second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned off.

[0120] During the fourth period T4, the supply of the light emitting control signal EM to the light emitting control line ELk is interrupted, and thus the fourth transistor M4 is turned on. If the fourth transistor M4 is turned on, the first transistor M1 and the light emitting element LD are electrically connected.

[0121] The fourth transistor M4 is set to a conducting state, so that the current supplied from the first transistor M1 can be supplied to the light emitting element LD. That is, during the fourth period T4, the first transistor M1 can control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD corresponding to the voltage of the first node N1. At this time, the light emitting element LD can emit light at a brightness corresponding to the amount of current supplied from the first transistor M1.

[0122] Figure 6 It is shown Figure 3 The current deviation of the pixel is shown in FIG. Figure 6 In FIG. 1 , the X axis is shown as grayscale and the Y axis is shown as current deviation. The current deviation is the change in the driving current corresponding to the change in the threshold voltage of the first transistor M1 expressed as a percentage [%). As an example, Figure 6 It represents the current deviation when the threshold voltage of the first transistor M1 changes to −50 mV and +50 mV.

[0123] Reference Figure 6, when the threshold voltage of the first transistor M1 changes to -50 mV and +50 mV, the current deviation can be set to about -4.56% to +4%. That is, the pixel PXij of the embodiment of the present invention can stably compensate for the threshold voltage of the first transistor M1.

[0124] Figure 7 It is shown Figure 3 FIG. 1 is a diagram showing an embodiment of a method for driving a pixel. Figure 7 When explaining, omit Figure 4 Repeated description of the same parts.

[0125] Reference Figure 3 as well as Figure 7 A horizontal period 1H (or a specific horizontal period) in which a data signal is supplied to a pixel PXij located at an i-th horizontal line and a j-th vertical line may be divided into a first period T1a, a second period T2, and a third period T3.

[0126] During the first period T1a, the second scan signal GR may be supplied to the second scan line SL2i at least twice. As an example, during the first period T1a, the gate-on voltage, the gate-off voltage, and the gate-on voltage may be sequentially supplied to the second scan line SL2i. In this case, during the first period T1a, the third transistor M3 and the sixth transistor M6 may be set to be sequentially turned on, turned off, and turned on.

[0127] During the first period T1a, the third scan signal GC may be supplied to the third scan line SL3i at least twice. As an example, during the first period T1a, the gate-on voltage, the gate-off voltage, and the gate-on voltage may be sequentially supplied to the third scan line SL3i. In this case, during the first period T1a, the fifth transistor M5 may be set to be sequentially turned on, turned off, and turned on. Here, the turn-on period of the third transistor M3, the turn-on period of the sixth transistor M6, and the turn-on period of the fifth transistor M5 may overlap.

[0128] Additionally, during the first period T1a, the second transistor M2 may be turned on by the first scan signal GW supplied to the first scan line SL1i. Also, during the first period T1a, the emission control signal EM is not supplied to the emission control line ELk, so the fourth transistor M4 may be turned on.

[0129] In the first period T1a, if the second transistor M2 to the sixth transistor M6 are turned on, then Figure 5a As shown, the voltage of the reference power source Vref is supplied to the first node N1, the second node N2, and the third node N3, so that the first capacitor C1, the second capacitor C2, and the light emitting element LD can be initialized.

[0130] In the first period T1a, if the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned off, the reference power source Vref is not supplied to the first node N1, the second node N2, and the third node N3.

[0131] In such Figure 7 In the driving method shown, during the first period T1a, the first node N1, the second node N2, and the third node N3 can be initialized at least twice while the second scan signal GR and the third scan signal GC are supplied multiple times (or the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned off at least once). In this case, the first capacitor C1, the second capacitor C2, and the light emitting element LD can be initialized slightly more stably.

[0132] Figure 8 is a diagram showing a pixel according to an embodiment of the present invention. Figure 8 In , the pixels located on the i-th horizontal line and the j-th vertical line are shown. Figure 8 When explaining, omit Figure 3 Repeated description of the same structure.

[0133] Reference Figure 8 According to an embodiment of the present invention, the pixel PXaij can be connected to the corresponding signal lines SL1i, SL2i, SL3i, ELk, and DLj. For example, the pixel PXaij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the k-th light emitting control line ELk, and the j-th data line DLj. In an embodiment, the pixel PXaij can also be connected to the first power line PL1 and the second power line PL2.

[0134] According to an embodiment of the present invention, a pixel PXaij may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0135] The light emitting element LD may be turned on between the first power line PL1 and the second power line PL2. The light emitting element LD may generate light of predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0136] The pixel circuit may include a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 a , a first capacitor C1 , and a second capacitor C2 .

[0137] The first electrode of the sixth transistor M6a may be connected to the first electrode of the first capacitor C1, and the second electrode may be connected to the third node N3. Furthermore, the gate electrode of the sixth transistor M6a may be electrically connected to the second scan line SL2i. When the second scan signal GR is supplied to the second scan line SL2i, the sixth transistor M6a as described above may be turned on to electrically connect the first electrode of the first capacitor C1 and the third node N3.

[0138] Fig. 9 It is shown Figure 8 FIG. 1 is a diagram showing an embodiment of a method for driving a pixel.

[0139] Reference Fig. 9 , a horizontal period 1H (or a specific horizontal period) in which a data signal is supplied to pixels PXaij located at an i-th horizontal line and a j-th vertical line may be divided into a first period T1b, a second period T2b, and a third period T3b.

[0140] The data driving unit 140 may supply the voltage of the reference power supply Vref to the data line DLj during the first period T1b and the second period T2b, and supply the voltage Vdata of the data signal during the third period T3b. The reference power supply Vref may be set to a voltage between the first driving power supply VDD and the second driving power supply VSS. As an example, when the reference power supply Vref is supplied to the first electrode of the light emitting element LD, it may be set to a voltage at which the light emitting element LD is turned off. The voltage Vdata of the data signal may be set to a predetermined voltage within the voltage range of the data signal corresponding to the grayscale.

[0141] The scan driver 130 (or the first scan driver 132) may supply the first scan line SL1i with the first scan signal GW during the first period T1b to the third period T3b. The scan driver 130 (or the second scan driver 134) may supply the second scan line SL2i with the second scan signal GR during the first period T1b and the second period T2b. The scan driver 130 (or the third scan driver 136) may supply the third scan line SL3i with the third scan signal GC during the first period T1b and the second period T2b. The light emitting driver 150 may supply the light emitting control signal EM to the light emitting control line ELk during the second period T2b and the third period T3b.

[0142] During the first period T1b, the voltage of the reference power supply Vref may be supplied to the first electrode of the first capacitor C1, the first node N1, the second node N2, and the third node N3. During the first period T1b, the first capacitor C1, the second capacitor C2, and the light emitting element LD may be initialized by the voltage of the reference power supply Vref. The first period T1b as above may be named an initialization period.

[0143] During the second period T2b, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in the second capacitor C2. The second period T2b may be named a threshold voltage compensation period.

[0144] The third period T3b is a period in which the voltage Vdata of the data signal is supplied from the data line DLj to the pixel PXij. During the third period T3b, a voltage corresponding to the data signal may be applied to the first node N1. The third period T3b as above may be named a data writing period.

[0145] During the fourth period T4b, the first transistor M1 may control the amount of current flowing from the first driving power source VDD to the second driving power source VSS via the light emitting element LD corresponding to the voltage of the first node N1. During the fourth period T4b, the light emitting element LD may emit light at a brightness corresponding to the amount of current supplied from the first transistor M1. The fourth period T4b as above may be named as a light emitting period.

[0146] Figures 10a to 10d is shown corresponding to Fig. 9 FIG. 5 is a diagram of an embodiment of a driving waveform of a pixel working process.

[0147] Reference Fig.10a During the first period T1b, the first scan signal GW is supplied to the first scan line SL1i, the second scan signal GR is supplied to the second scan line SL2i, and the third scan signal GC is supplied to the third scan line SL3i. Also, during the first period T1b, the emission control signal EM is not supplied to the emission control line ELk.

[0148] If the first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 is turned on. If the second transistor M2 is turned on, the voltage of the reference power source Vref from the data line DLj may be supplied to the first electrode of the first capacitor C1.

[0149] If the second scan signal GR is supplied to the second scan line SL2i, the third transistor M3 and the sixth transistor M6a are turned on. If the third transistor M3 and the sixth transistor M6a are turned on, the voltage of the reference power source Vref from the data line DLj can be supplied to the third node N3.

[0150] If the third scan signal GC is supplied to the third scan line SL3i, the fifth transistor M5 is turned on. If the fifth transistor M5 is turned on, the first node N1 and the second node N2 may be electrically connected.

[0151] If the light emission control signal EM is not supplied to the light emission control line ELk, the fourth transistor M4 is set to a turned-on state. If the fourth transistor M4 is turned on, the second node N2 and the third node N3 may be electrically connected.

[0152] During the first period T1b, the second transistor M2 to the sixth transistor M6a can be set to a conductive state, so that the voltage of the reference power source Vref from the data line DLj is supplied to the first node N1, the second node N2 and the third node N3. Therefore, the first capacitor C1, the second capacitor C2 and the light emitting element LD can be initialized by the voltage of the reference power source Vref.

[0153] Reference Fig.10b During the second period T2b, the first scan signal GW is supplied to the first scan line SL1i, so the second transistor M2 remains in the on state. During the second period T2b, the second scan signal GR is supplied to the second scan line SL2i, so the third transistor M3 and the sixth transistor M6a remain in the on state. During the second period T2b, the third scan signal GC is supplied to the third scan line SL3i, so the fifth transistor M5 remains in the on state.

[0154] During the second period T2b, the light emitting control signal EM is supplied to the light emitting control line ELk. If the light emitting control signal EM is supplied to the light emitting control line ELk, the fourth transistor M4 is turned off.

[0155] If the fifth transistor M5 is turned on by the third scan signal GC, the first transistor M1 is turned on as a diode. If the first transistor M1 is turned on as a diode, a voltage obtained by subtracting an absolute value threshold voltage of the first transistor M1 from the first driving power source VDD may be applied to the first node N1.

[0156] If the second transistor M2 is turned on, the voltage of the reference power source Vref is supplied to the first electrode of the first capacitor C1. Then, during the second period T2, a voltage corresponding to the threshold voltage of the first transistor M1 may be stored in each of the first capacitor C1 and the second capacitor C2.

[0157] If the third transistor M3 and the sixth transistor M6a are turned on, the voltage of the reference power source Vref is supplied to the third node N3. Then, the light emitting element LD can be initialized by the reference power source Vref.

[0158] Reference Fig.10c During the third period T3b, the first scan signal GW is supplied to the first scan line SL1i, so the second transistor M2 maintains a turned-on state.

[0159] If the second transistor M2 is turned on, the voltage Vdata of the data signal from the data line DLj is supplied to the first electrode of the first capacitor C1. If the voltage Vdata of the data signal is supplied to the first electrode of the first capacitor C1, the voltage of the first electrode of the first capacitor C1 changes from the voltage of the reference power supply Vref to the voltage Vdata of the data signal. At this time, the voltage of the first node N1 also changes through coupling of the first capacitor C1.

[0160] Here, the voltage variation of the first node N1 may be determined corresponding to the ratio of the first capacitor C1 to the second capacitor C2. As an example, the voltage of the first node N1 may be changed from the voltage obtained by subtracting the absolute value threshold voltage of the first transistor M1 from the first driving power source VDD to a value equivalent to the multiplication of the voltage variation of the first electrode of the first capacitor C1 and C1 / (C1+C2). When the voltage variation of the first node N1 is controlled by the ratio of the first capacitor C1 to the second capacitor C2 as described above, the voltage range of the data signal may be sufficiently wide.

[0161] During the third period T3b, the second capacitor C2 stores the voltage of the first node N1. Here, the voltage of the first node N1 can be determined by the threshold voltage of the first transistor M1 and the voltage Vdata of the data signal, so during the third period T3b, the second capacitor C2 stores a voltage corresponding to the data signal and the threshold voltage of the first transistor M1. Additionally, during the third period T3b, the third transistor M3 to the sixth transistor M6a are set to a cut-off state.

[0162] Reference Fig.10d During the fourth period T4b, the scan signals GW, GR, GC are not supplied to the scan lines SL1i, SL2i, SL3i. In this case, the second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6a are turned off.

[0163] During the fourth period T4b, the supply of the light emitting control signal EM to the light emitting control line ELk is interrupted, and thus the fourth transistor M4 is turned on. If the fourth transistor M4 is turned on, the first transistor M1 and the light emitting element LD are electrically connected.

[0164] The fourth transistor M4 is set to a conducting state, so that the current supplied from the first transistor M1 can be supplied to the light emitting element LD. That is, during the fourth period T4b, the first transistor M1 can control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD corresponding to the voltage of the first node N1. At this time, the light emitting element LD can emit light at a brightness corresponding to the amount of current supplied from the first transistor M1.

[0165] On the other hand, in an embodiment of the present utility model, Figure 8 The pixel PXaij shown can also be driven as Figure 4 In this case, during the second period T2, the supply of the second scan signal GR may be interrupted and the third transistor M3 and the sixth transistor M6a may be turned off. Even if the third transistor M3 and the sixth transistor M6a are turned off, the threshold voltage of the first transistor M1 may be stably compensated during the second period T2.

[0166] Fig.11 It is shown Figure 8 The current deviation of the pixel is shown in FIG. Fig.11 In FIG. 1 , the X axis is shown as grayscale and the Y axis is shown as current deviation. The current deviation is the change in the driving current corresponding to the change in the threshold voltage of the first transistor M1 expressed as a percentage [%). As an example, Fig.11 It represents the current deviation when the threshold voltage of the first transistor M1 changes to −50 mV and +50 mV.

[0167] Reference Fig.11 , when the threshold voltage of the first transistor M1 changes to -50mV and +50mV, the current deviation can be set to about -5.73% to +5.95%. That is, the pixel PXaij of the embodiment of the present invention can stably compensate for the threshold voltage of the first transistor M1.

[0168] Fig.12 is a diagram showing a pixel according to an embodiment of the present invention. Fig.12 In , the pixels located on the i-th horizontal line and the j-th vertical line are shown. Fig.12 When explaining, omit Figure 8 Repeated description of the same structure.

[0169] Reference Fig.12 According to an embodiment of the present invention, the pixel PXbij can be connected to the corresponding signal lines SL1i, SL2i, ELk, and DLj. For example, the pixel PXbij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the k-th light emitting control line ELk, and the j-th data line DLj. In an embodiment, the pixel PXbij can also be connected to the first power line PL1 and the second power line PL2.

[0170] The pixel PXbij according to the embodiment of the present invention may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0171] The light emitting element LD may be turned on between the first power line PL1 and the second power line PL2. The light emitting element LD may generate light of predetermined brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0172] The pixel circuit may include a first transistor M1 , a second transistor M2 , a third transistor M3 , a fourth transistor M4 , a fifth transistor M5 a , a sixth transistor M6 a , a first capacitor C1 , and a second capacitor C2 .

[0173] The fifth transistor M5a may be turned on between the first node N1 and the second node N2. Also, the gate electrode of the fifth transistor M5a may be electrically connected to the second scan line SL2i. When the second scan signal GR is supplied to the second scan line SL2i, the fifth transistor M5a is turned on to electrically connect the first node N1 and the second node N2.

[0174] and Figure 8 The pixel PXaij is compared with Fig.12 In the pixel PXbij, only the fifth transistor M5a is connected to the second scan line SL2i, and the other structures are the same. When the fifth transistor M5a is connected to the second scan line SL2i, the Figure 8 The third scan line SL3i is shown.

[0175] like Fig. 9 As shown, the second scanning signal GR and the third scanning signal GC are supplied at the same timing, so Fig.12 The driving method of the pixel PXbij is Figure 8 Therefore, the pixel PXaij for Fig.12 Description of the driving method of the pixel PXbij.

[0176] Fig.13 It is shown Figure 8 FIG. 1 is a diagram showing an embodiment of a method for driving a pixel. Fig.13 When explaining, omit Fig. 9 Repeated description of the same part.

[0177] Reference Figure 8 as well as Fig.13 , a horizontal period 1H (or a specific horizontal period) in which data signals are supplied to pixels PXaij located at an i-th horizontal line and a j-th vertical line may be divided into a first period T1c, a second period T2b, and a third period T3b.

[0178] During the first period T1c, the second scan signal GR may be supplied to the second scan line SL2i at least twice. As an example, during the first period T1c, the gate-on voltage, the gate-off voltage, and the gate-on voltage may be sequentially supplied to the second scan line SL2i. In this case, during the first period T1c, the third transistor M3 and the sixth transistor M6a may be set to be sequentially turned on, turned off, and turned on.

[0179] During the first period T1c, the third scan signal GC may be supplied to the third scan line SL3i at least twice. As an example, during the first period T1c, the gate-on voltage, the gate-off voltage, and the gate-on voltage may be sequentially supplied to the third scan line SL3i. In this case, during the first period T1c, the fifth transistor M5 may be set to be sequentially turned on, turned off, and turned on. Here, the turn-on period of the third transistor M3, the turn-on period of the sixth transistor M6a, and the turn-on period of the fifth transistor M5 may overlap.

[0180] Additionally, during the first period T1c, the second transistor M2 may be turned on by the first scan signal GW supplied to the first scan line SL1i. Also, during the first period T1c, the emission control signal EM is not supplied to the emission control line ELk, so the fourth transistor M4 may be turned on.

[0181] In the first period T1c, if the second transistor M2 to the sixth transistor M6a are turned on, then Fig.10a As shown, the voltage of the reference power source Vref is supplied to the first node N1, the second node N2, and the third node N3, so that the first capacitor C1, the second capacitor C2, and the light emitting element LD can be initialized.

[0182] In the first period T1c, if the third transistor M3, the fifth transistor M5, and the sixth transistor M6a are turned off, the reference power source Vref is not supplied to the first node N1, the second node N2, and the third node N3.

[0183] exist Fig.13 In the driving method shown, during the first period T1c, the first node N1, the second node N2, and the third node N3 can be initialized at least twice while the second scan signal GR and the third scan signal GC are supplied multiple times (or the third transistor M3, the fifth transistor M5, and the sixth transistor M6a are turned off at least once). In this case, the first capacitor C1, the second capacitor C2, and the light emitting element LD can be initialized slightly more stably.

[0184] The above description is made with reference to the preferred embodiments of the present invention, but those skilled in the art will appreciate that various modifications and changes may be made to the present invention without departing from the concept and scope of the present invention as described in the claims.

Claims

1. A pixel, characterized in that: have: A first transistor including a second electrode and a first electrode electrically connected to a first power line supplying a first driving power source, and a gate electrode connected to a first node; A second transistor includes a second electrode and a first electrode electrically connected to the data line, and a gate electrode electrically connected to the first scan line; The light emitting element, the second electrode is electrically connected to a second power line supplying a second driving power source; A third transistor is connected between the data line and the first electrode of the light emitting element, and a gate electrode is electrically connected to the second scanning line; a fourth transistor connected between a second node connected to the second electrode of the first transistor and the first electrode of the light emitting element, and having a gate electrode electrically connected to a light emitting control line; a first capacitor, a first electrode of which is connected to the second electrode of the second transistor, and a second electrode of which is connected to the first node; as well as A second capacitor is connected between the first power line and the first node.

2. The pixel according to claim 1, characterized in that The pixel also has: A fifth transistor is connected between the first node and the second node, and a gate electrode is electrically connected to the third scan line.

3. The pixel according to claim 2, characterized in that The pixel also has: A sixth transistor is connected between the first node and the first electrode of the light emitting element, and a gate electrode is electrically connected to the second scan line.

4. The pixel according to claim 3, characterized in that In a horizontal period when a data signal is supplied to the pixel, during at least a portion of a first period, the second to sixth transistors are set to a conductive state, During the first period, a voltage of a reference power source having a voltage value between the first driving power source and the second driving power source is supplied to the data line.

5. The pixel according to claim 4, characterized in that During the first period, the third transistor, the fifth transistor, and the sixth transistor are set to an off state at least once.

6. The pixel according to claim 4, characterized in that In the horizontal period, during a second period after the first period, the second transistor and the fifth transistor are set to a conducting state, During the second period, the voltage of the reference power source is supplied to the data line.

7. The pixel according to claim 6, characterized in that In the horizontal period, during a third period after the second period, the second transistor is set to a conducting state, During the third period, the voltage of the data signal is supplied to the data line.

8. The pixel according to claim 2, characterized in that The pixel also has: A sixth transistor is connected between the first electrode of the first capacitor and the first electrode of the light emitting element, and a gate electrode is electrically connected to the second scan line.

9. The pixel according to claim 8, characterized in that The third scan line and the second scan line are the same scan line.

10. The pixel according to claim 8, characterized in that In a horizontal period when a data signal is supplied to the pixel, during at least a portion of a first period, the second to sixth transistors are set to a conductive state, During the first period, a voltage of a reference power source having a voltage value between the first driving power source and the second driving power source is supplied to the data line.

11. The pixel according to claim 10, characterized in that During the first period, the third transistor, the fifth transistor, and the sixth transistor are set to an off state at least once.

12. The pixel according to claim 10, characterized in that In the horizontal period, during a second period after the first period, the second transistor, the third transistor, the fifth transistor, and the sixth transistor are set to a conducting state, During the second period, the voltage of the reference power source is supplied to the data line.

13. The pixel according to claim 12, characterized in that In the horizontal period, during a third period after the second period, the second transistor is set to a conducting state, During the third period, the voltage of the data signal is supplied to the data line.

14. A display device, characterized in that: have: The pixel is connected to the first scan line, the second scan line, the third scan line, the data line and the light emitting control line; The pixel located in the i-th pixel row and the j-th pixel column has: A first transistor including a second electrode and a first electrode electrically connected to a first power line supplying a first driving power source, and a gate electrode connected to a first node; a second transistor including a second electrode and a first electrode electrically connected to the j-th data line and turned on when the first scan signal is supplied to the i-th first scan line; The light emitting element, the second electrode is electrically connected to a second power line supplying a second driving power source; a third transistor connected between the j-th data line and the first electrode of the light emitting element and turned on when the second scan signal is supplied to the i-th second scan line; a fourth transistor connected between a second node connected to the second electrode of the first transistor and the first electrode of the light emitting element and turned off when a light emitting control signal is supplied to the kth light emitting control line; a first capacitor, a first electrode of which is connected to the second electrode of the second transistor, and a second electrode of which is connected to the first node; as well as a second capacitor connected between the first power line and the first node, Here, i is an integer greater than or equal to 0, j is an integer greater than or equal to 0, and k is an integer greater than or equal to 0.

15. The display device according to claim 14, characterized in that: The pixel located in the i-th pixel row and the j-th pixel column further comprises: a fifth transistor connected between the first node and the second node and turned on when a third scan signal is supplied to an i-th third scan line; as well as A sixth transistor is connected between the first node and the first electrode of the light emitting element and is turned on when the second scan signal is supplied to the i-th second scan line.

16. The display device according to claim 15, characterized in that: The horizontal period during which the data signal is supplied to the pixels located in the i-th pixel row and the j-th pixel column includes a first period, a second period, and a third period. The display device further comprises: a data driving unit configured to supply a voltage of a reference power source having a voltage value between the first driving power source and the second driving power source to the j-th data line during the first period and the second period, and to supply the data signal during the third period; A first scan driving unit, configured to supply the first scan signal to the i-th first scan line during the first period to the third period; a second scan driving unit, configured to supply the second scan signal to the i-th second scan line during the first period; A third scan driving unit, configured to supply the third scan signal to the i-th third scan line during the first period and the second period; as well as The light-emitting driving unit is used to supply the light-emitting control signal to the k-th light-emitting control line during the second period and the third period.

17. The display device according to claim 16, characterized in that: The second scan driving unit supplies a gate-off voltage to the i-th second scan line at least once in the first period, The third scan driving part supplies a gate-off voltage to the i-th third scan line at least once in the first period.

18. The display device according to claim 14, characterized in that: The pixel located in the i-th pixel row and the j-th pixel column further comprises: a fifth transistor connected between the first node and the second node and turned on when a third scan signal is supplied to an i-th third scan line; as well as A sixth transistor is connected between the first electrode of the first capacitor and the first electrode of the light emitting element and is turned on when the second scan signal is supplied to the i-th second scan line.

19. The display device according to claim 18, characterized in that The horizontal period during which the data signal is supplied to the pixels located in the i-th pixel row and the j-th pixel column includes a first period, a second period, and a third period. The display device further comprises: a data driving unit configured to supply a voltage of a reference power source having a voltage value between the first driving power source and the second driving power source to the j-th data line during the first period and the second period, and to supply the data signal during the third period; A first scan driving unit, configured to supply the first scan signal to the i-th first scan line during the first period to the third period; A second scan driving unit, configured to supply the second scan signal to the i-th second scan line during the first period and the second period; A third scan driving unit, configured to supply the third scan signal to the i-th third scan line during the first period and the second period; as well as The light-emitting driving unit is used to supply the light-emitting control signal to the k-th light-emitting control line during the second period and the third period.

20. The display device according to claim 19, characterized in that The i-th second scanning line and the i-th third scanning line are set to be the same scanning line, The second scanning driving unit and the third scanning driving unit are set to be the same driving unit.

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