Communication system board card based on FPGA

Abstract

The utility model relates to the technical field of communication system processing, and particularly discloses a communication system board card based on an FPGA (Field Programmable Gate Array), which comprises a first radio frequency signal processing unit, a second radio frequency signal processing unit and a plurality of VPX interfaces, the first radio frequency signal processing unit comprises a first FPGA chip, a first ADC module and a first SPI FLASH, and the first FPGA chip is connected with the first ADC module and the first SPI FLASH; the second radio frequency signal processing unit comprises a second FPGA chip, a second ADC module and a second SPI FLASH, the second FPGA chip is in communication connection with the first FPGA chip, and the second FPGA chip is connected with the second ADC module and the second SPI FLASH; and the first FPGA chip and the second FPGA chip are connected with the plurality of VPX interfaces and are used for processing the received first radio frequency signal and outputting a processed second radio frequency signal. A structure of FPGA + ADC + DAC is adopted, and a high-speed optical port or a RapidIO data communication interface is adopted, so that high-speed data transmission is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of communication system processing, and particularly relates to a communication system board based on FPGA. Background Art

[0002] At present, in the communication system board, the broadband radio frequency signal processing module is implemented by using the VPX architecture based on FPGA. The number of channels for synchronous sampling of radio frequency signals supported by this architecture and the number of channels for synchronous output of radio frequency signals are small, and a high-speed data communication interface cannot be used, so high-speed data transmission cannot be achieved. However, in the actual application process, the speed requirement for transmitting data is constantly increasing, and the current board structure cannot meet the requirements.

[0003] Therefore, it is urgent to improve the original board structure to meet the condition of having a plurality of channels for synchronous sampling of radio frequency signals, and at the same time, a high-speed data communication interface can be used to meet the requirement of high-speed data transmission. Summary of the Utility Model

[0004] In order to overcome the above technical problems existing in the prior art, an embodiment of the utility model provides a communication system board based on FPGA. In the communication system board, for the broadband radio frequency signal processing module, an FPGA + ADC + DAC structure is adopted, and a high-speed optical port or a RapidIO data communication interface is adopted to achieve high-speed data transmission.

[0005] In order to achieve the above object, an embodiment of the utility model provides a communication system board based on FPGA. The communication system board based on FPGA includes: a first radio frequency signal processing unit, a second radio frequency signal processing unit, and a plurality of VPX interfaces; the first radio frequency signal processing unit includes a first FPGA chip, a first ADC module, and a first SPI FLASH. The first FPGA chip is connected to the first ADC module through a first GTH transceiver, and the first FPGA chip is connected to the first SPI FLASH; the second radio frequency signal processing unit includes a second FPGA chip, a second ADC module, and a second SPI FLASH. The second FPGA chip is communicatively connected to the first FPGA chip through a corresponding interface. The second FPGA chip is connected to the second ADC module through a second GTH transceiver, and the second FPGA chip is connected to the second SPI FLASH; the first FPGA chip and the second FPGA chip are connected to the plurality of VPX interfaces for processing the received first radio frequency signal and outputting the processed second radio frequency signal.

[0006] Preferably, the models of the first FPGA chip and the second FPGA chip are both: V7-690T; the models of the first ADC module and the second ADC module are both: CS1237.

[0007] Preferably, the first radio frequency signal processing unit further includes: N first linear regulators, X first DC / DC regulators, and a first jitter attenuator, all of which are connected to the first FPGA chip; the second radio frequency signal processing unit further includes M second linear regulators, Y second DC / DC regulators, and a second jitter attenuator, all of which are connected to the second FPGA chip; N and M are positive integers greater than 2, N is less than M, X and Y are positive integers greater than 0, and X is less than Y.

[0008] Preferably, the first linear regulator and the second linear regulator are both LDO linear regulators; the first DC / DC regulator and the second DC / DC regulator both include a first regulator module and a second regulator module; the models of the first jitter attenuator and the second jitter attenuator are both: BR9155S.

[0009] Preferably, the model of the first regulator module is AH5333, and the model of the second regulator module is ET631.

[0010] Preferably, the second FPGA chip communicates with the first FPGA chip through corresponding GPIO interfaces, GTH interfaces, and LVDS interfaces.

[0011] Preferably, the first radio frequency signal processing unit is connected to the plurality of VPX interfaces through a first SRIO interface, a first GPIO interface, and a first LVDS interface; the second radio frequency signal processing unit is connected to the plurality of VPX interfaces through a second SRIO interface, a second GPIO interface, a second LVDS interface, and a SPIO interface.

[0012] Preferably, the second radio frequency signal processing unit is connected to a plurality of DAC modules, each DAC module is configured with a corresponding filter, and each filter is connected to a corresponding VPX interface for outputting radio frequency signals.

[0013] Preferably, the second radio frequency signal processing unit is further configured with a broadband phase-locked loop frequency synthesizer, and the broadband phase-locked loop frequency synthesizer is connected to the second FPGA chip.

[0014] Preferably, the model of the DAC module is: BLAD14D125, and the model of the broadband phase-locked loop frequency synthesizer is: TW6214C.

[0015] Through the technical solution provided by the present utility model, the present utility model has at least the following technical effects:

[0016] In the communication system board, for the broadband radio frequency signal processing module, an FPGA + ADC + DAC structure is adopted, and a high-speed optical port or a RapidIO data communication interface is adopted to achieve high-speed data transmission. This communication system board can be applied to application scenarios such as communication processing systems, phased array radars, and software radio systems.

[0017] Other features and advantages of the embodiments of the present utility model will be described in detail in the subsequent specific implementation part. Brief Description of the Drawings

[0018] The drawings are used to provide a further understanding of the embodiments of the present utility model, and constitute a part of the specification. Together with the following specific implementation, they are used to explain the embodiments of the present utility model, but do not constitute a limitation to the embodiments of the present utility model. In the drawings:

[0019] Figure 1 It is a schematic structural diagram of a communication system board based on FPGA provided by the embodiments of the present utility model. Detailed Description of the Preferred Embodiments

[0020] The following will describe in detail the specific implementation of the embodiments of the present utility model with reference to the drawings. It should be understood that the specific implementation described herein is only used to explain and illustrate the embodiments of the present utility model, and is not used to limit the embodiments of the present utility model.

[0021] The terms "system" and "network" in the embodiments of the present utility model can be used interchangeably. "Plurality" means two or more. In view of this, in the embodiments of the present utility model, "plurality" can also be understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " generally represents an "or" relationship between the associated objects before and after, unless otherwise specified. In addition, it should be understood that in the description of the embodiments of the present utility model, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0022] Please refer to Figure 1, an embodiment of the present utility model provides a communication system board based on FPGA. The communication system board based on FPGA includes a first radio frequency signal processing unit, a second radio frequency signal processing unit, and multiple VPX interfaces. The first radio frequency signal processing unit includes a first FPGA chip, a first ADC module, and a first SPI FLASH. The first FPGA chip is connected to the first ADC module through a first GTH transceiver, and the first FPGA chip is connected to the first SPI FLASH; the second radio frequency signal processing unit includes a second FPGA chip, a second ADC module, and a second SPI FLASH. The second FPGA chip is communicatively connected to the first FPGA chip through corresponding interfaces. The second FPGA chip is connected to the second ADC module through a second GTH transceiver, and the second FPGA chip is connected to the second SPI FLASH; the first FPGA chip and the second FPGA chip are connected to the multiple VPX interfaces, and are used for processing the received first radio frequency signal and outputting the processed second radio frequency signal.

[0023] In this embodiment, all chips in the communication system board based on FPGA are domestic chips, and the communication system board is a board based on a 6U VPX architecture. The board of this architecture supports multiple communication protocols and interfaces. Communication and interconnection between each module in the board are carried out through multiple VPX interfaces. The multiple VPX interfaces include P0 interface to P8 interface. Among them, the P0 interface is a power supply interface, the P1 interface, P4 interface, and P5 interface are all digital interfaces, the P2 interface and P3 interface are both fiber optic radio frequency interfaces, and the P7 interface and P8 interface are both radio frequency interfaces.

[0024] Specifically, the first radio frequency processing unit includes a first FPGA chip, a first ADC module connected to the first FPGA chip, 1 first jitter attenuator, 4 first linear regulators, a first DC / DC regulator, and a first SPI FLASH. The model of the first FPGA chip is V7-690T, and the manufacturer is Shenzhen Guowei Co., Ltd. The first FPGA chip is connected to the first ADC module through an interface implemented by using a first GTH transceiver. The configuration of the first GTH transceiver is that each GTH transceiver can provide 4 channels for sending and receiving data. The first ADC module is an analog-to-digital converter, and the analog-to-digital converter is a chip with the model CS1237 produced by XinHai Technology Co., Ltd., and its bit width is 24 bits. The position of the first jitter attenuator is adjacent to the position of the first ADC module, and the model of the first jitter attenuator is the BR9155S chip produced by Britecom (Xi'an) Electronic Technology Co., Ltd. The 4 linear regulators are all LDO linear regulators. Among them, the positions of 3 LDO linear regulators are adjacent to the position of the jitter attenuator, and the position of the other LDO linear regulator is adjacent to the position of the DC / DC regulator. The models of the 3 LDO linear regulators are all AMS1117-ADJ, and they are all produced by PengxinSheng Electronics Co., Ltd. The first DC / DC regulator includes 1 first regulator module and 1 second regulator module. The first regulator module is a chip with the model AH5333 produced by Zhenbang Micro Technology Co., Ltd., and the second regulator module is a chip with the model ET631 produced by Lixin Micro. The memory capacity of the first SPI FLASH is 512Mb.

[0025] Furthermore, the first FPGA chip in the first radio frequency processing unit is connected to the P4 interface among multiple VPX interfaces through an SRIO interface with 4 channels, and is also connected to the P4 interface through a GPIO interface with 16 channels. The first FPGA chip is further connected to the P1 interface among multiple VPX interfaces through an LVDS interface with 6 channels. Both the P1 interface and the P4 interface are digital interfaces. The first FPGA chip can also be connected to the VPX interface through an LVDS interface with 12 channels, so that the first FPGA chip can receive the first radio frequency signal and process the first radio frequency signal.

[0026] In this embodiment, the second radio frequency processing unit includes a second FPGA chip, a second ADC module connected to the second FPGA chip, one second jitter attenuator, six second linear regulators, a second DC / DC regulator, and a second SPI FLASH. Among them, the second FPGA chip is communicatively connected to the first FPGA chip through 30 interfaces implemented using third-generation GTH transceivers, an LVDS interface with 36 channels, and a GPIO interface with 20 channels. The configuration of the third-generation GTH transceiver is such that each GTH transceiver can provide 4 channels for transmitting and receiving data, and the model of the second FPGA chip is also V7-690T. The second ADC module includes four analog-to-digital converters, and the models of these four analog-to-digital converters are all CS1237. The second FPGA chip is connected to each analog-to-digital converter through an interface implemented using a second-generation GTH transceiver to establish a communication connection between the second FPGA chip and the second ADC module. The configuration of the second-generation GTH transceiver is such that each GTH transceiver can provide 4 channels for transmitting and receiving data. Since the second FPGA chip is connected to four analog-to-digital converters, four second-generation GTH transceivers are provided. The position of the second jitter attenuator is adjacent to the position of the second ADC module, and the model of the second jitter attenuator is HMC7044. The six second linear regulators are also LDO regulators. Among them, the positions of five LDO regulators are adjacent to the position of the second ADC module, and the position of the other LDO regulator is adjacent to the position of the second SPI FLASH. The models of the six LDO regulators are all AMS1117-ADJ. The second DC / DC regulator includes one first regulator module and three second regulator modules. Among them, the positions of two second regulator modules are adjacent to the position of the second ADC module, and the positions of the other second regulator module and the first regulator module are both adjacent to the position of the second SPI FLASH. The model of the first regulator module is AH5333, and the models of the three second regulator modules are all ET631. The memory capacity of the second SPI FLASH is also 512 Mb.

[0027] Specifically, the second FPGA chip in the second radio frequency processing unit is connected to the P5 interface among multiple VPX interfaces through a GPIO interface with 10 channels, and is also connected to the P5 interface through three SPIO interfaces with 4 channels each. The second FPGA chip is further connected to the P1 interface among multiple VPX interfaces through an LVDS interface with 6 channels. Both the P1 interface and the P5 interface are digital interfaces. The second FPGA chip can also be connected to the VPX interface through an SRIO interface with 4 channels, so that the second FPGA chip can receive the first radio frequency signal and process the first radio frequency signal.

[0028] Further, the second radio frequency processing unit is also connected to two DAC modules. Specifically, the second FPGA chip in the second radio frequency processing unit is communicatively connected to the two DAC modules through a LVDS interface with 56 channels. The two DAC modules are two digital-to-analog converters, both of which are BLAD14D125 chips produced by Shanghai Belling, with a bit width of 14 bits and a conversion rate of 2.5 GSPS. Each digital-to-analog converter is correspondingly configured with a filter, so two filters are provided. Each filter is connected to the P7 interface and the P8 interface among multiple VPX interfaces. The P7 interface and the P8 interface are both radio frequency interfaces, so that the second FPGA chip can output the processed second radio frequency signal.

[0029] In this embodiment, the second radio frequency signal processing unit is further configured with a broadband phase-locked loop frequency synthesizer. The broadband phase-locked loop frequency synthesizer is connected to the second FPGA chip in the second radio frequency signal processing unit, and the position of the broadband phase-locked loop frequency synthesizer is adjacent to the positions of the two DAC modules. The broadband phase-locked loop frequency synthesizer is a TW6214C chip produced by Topway Electronic Technology (Shanghai) Co., Ltd.

[0030] The receiving performance of the FPGA-based communication system board provided in this embodiment is: SNR: 54 dBFS, SFDR: 70 dBFS, and the intermediate frequency signal input is 500 MHz / 0 dBm; the transmitting performance of the FPGA-based communication system board is: signal power: -1.6 dBm, SFDR: 50 dBc, and the intermediate frequency signal output is 520 MHz. The power consumption of this communication system board is less than or equal to 40 W, and the size is 233 mm in length and 160 mm in width.

[0031] The FPGA-based communication system board provided in this embodiment adopts a 6U VPX architecture of FPGA + ADC + DAC, supports synchronous sampling of 8 radio frequency signals and synchronous output of 2 radio frequency signals, and can adopt a high-speed optical port or a RapidIO data communication interface externally. The two radio frequency signal processing units in this communication system board are both connected to the VPX interface through SRIO interface, GPIO interface, LVDS interface and SPIO interface, which can realize high-speed data transmission, so that this communication system board can be applied to application scenarios such as communication processing systems, phased array radars, and software radio systems.

[0032] The optional implementation manners of the embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above implementation manners. Within the technical concept scope of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention.

[0033] In addition, it should be noted that, in the above specific embodiments, the various specific technical features described can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the embodiments of the present utility model will not separately describe various possible combination manners.

[0034] In addition, any combination can be made among the various different embodiments of the embodiments of the present utility model, as long as it does not violate the idea of the embodiments of the present utility model, and it should also be regarded as the content disclosed by the embodiments of the present utility model.

Claims

1. A communication system board based on FPGA, characterized in that: The FPGA-based communication system board includes: a first radio frequency signal processing unit, a second radio frequency signal processing unit, and a plurality of VPX interfaces; The first radio frequency signal processing unit includes a first FPGA chip, a first ADC module and a first SPI FLASH, the first FPGA chip is connected to the first ADC module through a first GTH transceiver, and the first FPGA chip is connected to the first SPI FLASH; The second RF signal processing unit includes a second FPGA chip, a second ADC module and a second SPI FLASH, the second FPGA chip is connected to the first FPGA chip through corresponding interface communication, the second FPGA chip is connected to the second ADC module through a second GTH transceiver, and the second FPGA chip is connected to the second SPI FLASH; The first FPGA chip and the second FPGA chip are connected to the multiple VPX interfaces and are used to process the received first RF signal and output the processed second RF signal.

2. The FPGA-based communication system board according to claim 1, characterized in that: The models of the first FPGA chip and the second FPGA chip are both: V7-690T; the models of the first ADC module and the second ADC module are both: CS1237.

3. The FPGA-based communication system board according to claim 1, characterized in that: The first RF signal processing unit further includes: N first linear regulators, X first DC / DC regulators and a first jitter attenuator, wherein the first linear regulators, the first DC / DC regulators and the first jitter attenuator are all connected to the first FPGA chip; The second RF signal processing unit further includes M second linear regulators, Y second DC / DC regulators and a second jitter attenuator, and the second linear regulators, the second DC / DC regulators and the second jitter attenuator are all connected to the second FPGA chip; The N and the M are positive integers greater than 2, the N is smaller than the M, the X and the Y are positive integers greater than 0, the X is smaller than the Y.

4. The FPGA-based communication system board according to claim 3, characterized in that: The first linear regulator and the second linear regulator are both LDO linear regulators; the first DC / DC regulator and the second DC / DC regulator both include a first regulator module and a second regulator module; the first jitter attenuator and the second jitter attenuator are both of model: BR9155S.

5. The FPGA-based communication system board according to claim 4, characterized in that: The model of the first voltage regulator module is AH5333, and the model of the second voltage regulator module is ET631.

6. The FPGA-based communication system board according to claim 1, characterized in that: The second FPGA chip is communicatively connected to the first FPGA chip via corresponding GPIO interface, GTH interface and LVDS interface.

7. The FPGA-based communication system board according to claim 1, characterized in that: The first RF signal processing unit is connected to the multiple VPX interfaces through a first SRIO interface, a first GPIO interface and a first LVDS interface; the second RF signal processing unit is connected to the multiple VPX interfaces through a second SRIO interface, a second GPIO interface, a second LVDS interface and a SPIO interface.

8. The FPGA-based communication system board according to claim 1, characterized in that: The second RF signal processing unit is connected to a plurality of DAC modules, each DAC module is configured with a corresponding filter, and each filter is connected to a corresponding VPX interface for outputting RF signals.

9. The FPGA-based communication system board according to claim 8, characterized in that: The second radio frequency signal processing unit is also configured with a broadband phase-locked loop frequency synthesizer, and the broadband phase-locked loop frequency synthesizer is connected to the second FPGA chip.

10. The FPGA-based communication system board according to claim 9, characterized in that: The model of the DAC module is: BLAD14D125, and the model of the broadband phase-locked loop frequency synthesizer is: TW6214C.

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