Function multiplexing SM4 encryption circuit based on assembly line mode
By implementing the functional multiplexing of the SM4 encryption circuit based on pipeline mode on the FPGA, and using the time-sharing multiplexing of the key expansion module and the wheel scrambling module, the problem of resource consumption and delay of the SM4 algorithm on the FPGA is solved, and the scrambling effect with low resource consumption and low latency is achieved.
Patent Information
- Application Number
- CN202422041400.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-22
- Publication Date
- 2025-05-30
- Estimated Expiration
- 2034-08-22
AI Technical Summary
The SM4 algorithm based on FPGA is difficult to balance efficiency and resource consumption, the data processing efficiency of the cyclic SM4 algorithm is low, while the resource occupancy rate of the pipelined SM4 cryptographic algorithm is too high.
The SM4 encryption circuit based on pipeline mode is adopted to achieve low logic consumption and low processing delay through time-sharing multiplexing of the key expansion module and the wheel scrambling module.
It greatly reduces logic resource consumption, reduces data scrambling delay, and realizes SM4 scrambling circuit with low logic consumption and low processing delay.
Smart Images
Figure CN222928407U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of symmetric scrambling algorithm circuits, in particular to an SM4 encryption circuit with low resource consumption and low delay, which is based on a pipeline mode and realized by time-sharing multiplexing of a key expansion module and a round scrambling module. Background Technique
[0002] Digitalization, networking, and intelligence are the characteristics of the information age. During the development of the Internet of Things and cloud computing, a large amount of data has been generated and stored in various storage devices. These storage devices carry a large amount of important data, and scrambling the data before storage is an important means to prevent data leakage from storage devices. The core technology of data scrambling is the data scrambling algorithm. The SM4 cryptographic algorithm has become an international standard and is applicable to encrypting and decrypting a large amount of data in storage systems.
[0003] Through specific programming, the hardware circuit of the SM4 algorithm can be implemented inside the FPGA, which can not only avoid the low efficiency problem caused by the serial operation of the processor and the performance instability problem in different scenarios, but also avoid the problem of high tape-out cost and non-changeability after tape-out brought by using dedicated chips. In view of the hardware implementation method of the FPGA and the characteristics of programmability, reconfigurability, and easy iteration, implementing the SM4 algorithm with the FPGA is an efficient and feasible way. However, it is difficult to balance efficiency and resource consumption for the SM4 algorithm implemented based on the FPGA. The data processing efficiency of the cyclic SM4 algorithm is low, while the resource occupancy rate of the pipeline SM4 cryptographic algorithm is too high. Content of the Utility Model
[0004] In view of this, the utility model proposes a function multiplexing SM4 encryption circuit based on a pipeline mode. The utility model is based on a pipeline mode and realizes low logic consumption and low processing delay through time-sharing multiplexing of a key expansion module and a round scrambling module.
[0005] The technical solution adopted by the utility model is as follows:
[0006] A function multiplexing SM4 encryption circuit based on a pipeline mode, including a multiplexing control module, 32 cascaded function multiplexing modules, and 32 key storage modules, and the 32 function multiplexing modules and the 32 key storage modules are connected in one-to-one correspondence;
[0007] The function multiplexing module includes a transformation circuit, an L transformation circuit, an L' transformation circuit, and a one-bit-two-choice data selector. The L transformation circuit and the L' transformation circuit are connected in parallel between the transformation circuit and the one-bit-two-choice data selector;
[0008] The key storage module includes a round key generation parameter storage space and a round key storage space;
[0009] The multiplexing control module includes a round counter circuit and a register strobe circuit, and the register strobe circuit outputs a 32-bit signal;
[0010] After the round counter circuit is reset, the count is 0. Thereafter, with the clock signal, the count is incremented, and when the count reaches 32, it remains unchanged. When the count of the round counter circuit is 0, all 32-bit signals output by the register strobe circuit are 0. When the count of the round counter circuit is n≥1, the 32-bit signal output by the register strobe circuit is 2 n-1 +2 n-2 +...+2 0 ;
[0011] The 32-bit signal output by the register strobe circuit corresponds to 32 control bits. The 32 control bits control the two-to-one data selectors of 32 function multiplexing modules from the cascaded primary stage to the cascaded final stage in order from the low bit to the high bit. When the control bit is 0, the two-to-one data selector selects the L' transformation circuit. The function multiplexing module reads the round key generation parameters from the round key generation parameter storage space of the corresponding key storage module, performs an expansion operation on the incoming key, stores the generated round key in the round key storage space of the corresponding key storage module, and passes the key expansion operation value backward. When the control bit is 1, the two-to-one data selector selects the L transformation circuit. The function multiplexing module reads the round key from the round key storage space of the corresponding key storage module, performs a round scrambling on the incoming data, and passes the scrambled data backward.
[0012] Furthermore, the key storage module is a BRAM storage circuit.
[0013] The beneficial effects of the present utility model are as follows:
[0014] 1. In the present utility model, by multiplexing the functions of the round scrambling module and the key generation module, the consumption of logic resources is greatly reduced.
[0015] 2. The present utility model utilizes the pipeline follow-up mode of the key and the data, which greatly reduces the data scrambling delay.
[0016] In summary, based on the pipeline mode, the present utility model realizes an SM4 scrambling circuit with low logic consumption and low processing delay through the time-sharing multiplexing of the key expansion module and the round scrambling module. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is the overall structural schematic diagram of an embodiment of the present utility model.
[0018] Figure 2 is the structural schematic diagram of the function multiplexing module.
[0019] Figure 3 It is a schematic structural diagram of the multiplexing control module. Specific implementation manners
[0020] The present utility model will be further described in detail below with reference to the accompanying drawings.
[0021] A function multiplexing SM4 encryption circuit based on a pipeline mode, as Figure 1 shown, includes a multiplexing control module, 32 cascaded function multiplexing modules 1 to 32, and 32 key storage modules. Among them:
[0022] The function multiplexing module can be time-division multiplexed as a round scrambling module or a round key generation module;
[0023] The multiplexing control module is used to respond to external key update control information, and control the 32-level function multiplexing module through 32 control bits to determine whether it implements the round scrambling function or the round key generation function;
[0024] The key storage module includes a round key generation parameter storage space and a round key storage space, and is used to provide round key generation parameters during the key generation process, store round keys, and provide round scrambling during the round scrambling process. When the multiplexing control module implements the round scrambling function, the round key storage space of the key storage module outputs externally. When the multiplexing control module implements the round key generation function, the round key generation parameter storage space of the key storage module outputs externally, and at the same time, the round key storage space receives input data and stores the round key.
[0025] As Figure 2 shown, the function multiplexing module internally includes a transformation circuit, an L transformation circuit, an L' transformation circuit, and a one-to-two data selector, and the one-to-two data selector is implemented through a multi-to-one MUX circuit. Each multi-to-one MUX circuit is gated through a control bit of the multiplexing control module.
[0026] When the control bit SeL of the multiplexing control module is 0, the multi-to-one MUX circuit gates the L' transformation circuit, and the function multiplexing module implements the round key generation function. At this time, the input Datain of the primary function multiplexing module is the externally input key. Each level of the function multiplexing module reads the round key generation parameter Cki from the round key generation parameter storage space, performs an expansion operation on the incoming key, stores the generated round key Rki of this level in the round key storage space of the key storage module, and passes the key expansion operation value of this level backward.
[0027] When the control bit SeL of the multiplexing control module is 1, the multiplexer (MUX) circuit selects the L transformation circuit, and the function multiplexing module implements the round scrambling function. At this time, the input Datain of the primary function multiplexing module is the plaintext input externally, and the input Datain of the subsequent function multiplexing module is the scrambled data output by the previous function multiplexing module. Each function multiplexing module reads the round key Rki from the round key storage space of its own key storage module, performs round scrambling on the input data of its own level, and outputs the scrambled data backward. The output Dataout of the last function multiplexing module is the final ciphertext.
[0028] As Figure 3 shown, the multiplexing control module includes a round counter circuit and a register selection circuit. The register selection circuit is implemented through the RTL_REG circuit and outputs a 32-bit signal SeL[31:0], corresponding to 32 control bits. The 32 control bits control the multiplexer (MUX) circuits of 32 function multiplexing modules from the cascaded primary to the cascaded last level in sequence from the low bit to the high bit.
[0029] The data externally input to this SM4 encryption circuit is the key and the plaintext. When the external key is input, the reset signal Rst is passed to the round counter circuit, and the count is 0 at this time. After that, with the accumulation of the clock signal Clk, the count is accumulated and maintained after reaching 32.
[0030] When the count of the round counter circuit is 0, all 32-bit signals output by the register selection circuit are 0; when the count of the round counter circuit is n≥1, the 32-bit signal output by the register selection circuit is 2 in binary representation n-1 +2 n-2 +...+2 0 .
[0031] The specific working process of this circuit is as follows:
[0032] First, the key is updated. The reset signal Rst is set high, and the key is read at the first clock. At this time, the 32-level multiplexing module is used as the key generation module.
[0033] Then, at the second clock, the reset signal Rst is set low, and at the same time the plaintext data is input. Under the action of the multiplexing control module, the first-level function multiplexing module is used as the round scrambling module, and the subsequent 31-level function multiplexing modules are used as the key generation modules.
[0034] At the third clock, under the action of the multiplexing control module, the first two-level function multiplexing modules are used as the round scrambling modules, and the subsequent 30-level function multiplexing modules are used as the key generation modules.
[0035] At the fourth clock, under the action of the multiplexing control module, the first three-level function multiplexing modules are used as the round scrambling modules, and the subsequent 29-level function multiplexing modules are used as the key generation modules.
[0036] At the 5th clock, under the action of the multiplexing control module, the first 4 - stage function multiplexing module is used as the round scrambling module, and the last 28 - stage function multiplexing module is used as the key generation module.
[0037] At the 6th clock, under the action of the multiplexing control module, the first 5 - stage function multiplexing module is used as the round scrambling module, and the last 27 - stage function multiplexing module is used as the key generation module.
[0038] At the 7th clock, under the action of the multiplexing control module, the first 6 - stage function multiplexing module is used as the round scrambling module, and the last 26 - stage function multiplexing module is used as the key generation module.
[0039] At the 8th clock, under the action of the multiplexing control module, the first 7 - stage function multiplexing module is used as the round scrambling module, and the last 25 - stage function multiplexing module is used as the key generation module.
[0040] At the 9th clock, under the action of the multiplexing control module, the first 8 - stage function multiplexing module is used as the round scrambling module, and the last 24 - stage function multiplexing module is used as the key generation module.
[0041] At the 10th clock, under the action of the multiplexing control module, the first 9 - stage function multiplexing module is used as the round scrambling module, and the last 23 - stage function multiplexing module is used as the key generation module.
[0042] At the 11th clock, under the action of the multiplexing control module, the first 10 - stage function multiplexing module is used as the round scrambling module, and the last 22 - stage function multiplexing module is used as the key generation module.
[0043] At the 12th clock, under the action of the multiplexing control module, the first 11 - stage function multiplexing module is used as the round scrambling module, and the last 21 - stage function multiplexing module is used as the key generation module.
[0044] At the 13th clock, under the action of the multiplexing control module, the first 12 - stage function multiplexing module is used as the round scrambling module, and the last 20 - stage function multiplexing module is used as the key generation module.
[0045] At the 14th clock, under the action of the multiplexing control module, the first 13 - stage function multiplexing module is used as the round scrambling module, and the last 19 - stage function multiplexing module is used as the key generation module.
[0046] At the 15th clock, under the action of the multiplexing control module, the first 14 - stage function multiplexing module is used as the round scrambling module, and the last 18 - stage function multiplexing module is used as the key generation module.
[0047] At the 16th clock, under the action of the multiplexing control module, the first 15 - stage function multiplexing module is used as the round scrambling module, and the last 17 - stage function multiplexing module is used as the key generation module.
[0048] At the 17th clock, under the action of the multiplexing control module, the first 16 - stage function multiplexing module is used as the round scrambling module, and the last 16 - stage function multiplexing module is used as the key generation module.
[0049] At the 18th clock, under the action of the multiplexing control module, the first 17 - stage function multiplexing module is used as the round scrambling module, and the last 15 - stage function multiplexing module is used as the key generation module.
[0050] At the 19th clock, under the action of the multiplexing control module, the first 18 - stage function multiplexing module is used as the round scrambling module, and the last 14 - stage function multiplexing module is used as the key generation module.
[0051] At the 20th clock, under the action of the multiplexing control module, the first 19 - stage function multiplexing module is used as the round scrambling module, and the last 13 - stage function multiplexing module is used as the key generation module.
[0052] At the 21st clock, under the action of the multiplexing control module, the first 20 - stage function multiplexing module is used as the round scrambling module, and the last 12 - stage function multiplexing module is used as the key generation module.
[0053] At the 22nd clock, under the action of the multiplexing control module, the first 21 - stage function multiplexing module is used as the round scrambling module, and the last 11 - stage function multiplexing module is used as the key generation module.
[0054] At the 23rd clock, under the action of the multiplexing control module, the first 22 - stage function multiplexing module is used as the round scrambling module, and the last 10 - stage function multiplexing module is used as the key generation module.
[0055] At the 24th clock, under the action of the multiplexing control module, the first 23 - stage function multiplexing module is used as the round scrambling module, and the last 9 - stage function multiplexing module is used as the key generation module.
[0056] At the 25th clock, under the action of the multiplexing control module, the first 24 - stage function multiplexing module is used as the round scrambling module, and the last 8 - stage function multiplexing module is used as the key generation module.
[0057] At the 26th clock, under the action of the multiplexing control module, the first 25 - stage function multiplexing module is used as the round scrambling module, and the last 7 - stage function multiplexing module is used as the key generation module.
[0058] At the 27th clock, under the action of the multiplexing control module, the first 26 - stage function multiplexing module is used as the round scrambling module, and the last 6 - stage function multiplexing module is used as the key generation module.
[0059] At the 28th clock, under the action of the multiplexing control module, the first 27 - stage function multiplexing module is used as the round scrambling module, and the last 5 - stage function multiplexing module is used as the key generation module.
[0060] At the 29th clock, under the action of the multiplexing control module, the first 28 - stage function multiplexing module is used as the round scrambling module, and the last 4 - stage function multiplexing module is used as the key generation module.
[0061] At the 30th clock, under the action of the multiplexing control module, the first 29 - stage function multiplexing module is used as the round scrambling module, and the last 3 - stage function multiplexing module is used as the key generation module.
[0062] At the 31st clock, under the action of the multiplexing control module, the first 30 - stage function multiplexing module is used as the round scrambling module, and the last 2 - stage function multiplexing module is used as the key generation module.
[0063] At the 32nd clock, under the action of the multiplexing control module, the first 31 - stage function multiplexing module is used as the round scrambling module, and the last 1 - stage function multiplexing module is used as the key generation module.
[0064] At the 33rd clock, under the action of the multiplexing control module, all - stage function multiplexing modules are used as the round scrambling module.
[0065] At the 34th clock, the scrambling of the plaintext data that entered the module at the 2nd clock is completed.
[0066] When the key needs to be updated, it is necessary to wait for the current data to pass through all multiplexing modules and then output the ciphertext. Then, set Rst high to reset each part of the circuit, repeat the above process, all multiplexing modules are used as the key generation module, and under the action of the multiplexing control module, they are gradually transformed into the round scrambling module with the clock count. The scrambled data will be continuously output after the 33rd clock when the plaintext data enters the circuit.
[0067] The multiplexing control module of the present utility model outputs 32 - bit control bits according to the clock relationship with 1 - bit control bits, successively implements the function multiplexing module as the round scrambling function, and successively implements the key storage module as the round key providing function. Thus, a multiplexing design is carried out in terms of module composition, making full use of the similarity between the round scrambling module and the key expansion module, and multiplexing the two to save resource consumption. At the same time, by analyzing the time - division multiplexing relationship between the two, the round scrambling process is closely followed after the key expansion process, achieving the effect of low latency.
Claims
1. A functional multiplexing SM4 encryption circuit based on pipeline mode, characterized in that: It includes a multiplexing control module, 32 cascaded function multiplexing modules, and 32 key storage modules, and the 32 function multiplexing modules and the 32 key storage modules are connected one by one; The function multiplexing module includes Conversion circuit, L conversion circuit, L' conversion circuit, two-choice data selector, L conversion circuit and L' conversion circuit are connected in parallel Between the conversion circuit and the two-to-one data selector; The key storage module includes a round key generation parameter storage space and a round key storage space; The multiplexing control module includes a round counter circuit and a register gating circuit, and the register gating circuit outputs a 32-bit signal; After the round counter circuit is reset, the count is 0. After that, the count is accumulated with the clock signal, and the count is maintained after it reaches 32; When the round counter circuit counts to 0, the 32-bit signal output by the register gating circuit is 0; when the round counter circuit counts to n ≥ 1, the 32-bit signal output by the register gating circuit is 2 in binary representation. n-1 +2 n-2 +...+2 0 ; The 32-bit signal output by the register gating circuit corresponds to 32 control bits, and the 32 control bits control the two-to-one data selectors of the 32 function multiplexing modules from the primary stage of the cascade to the final stage of the cascade in order from the low bit to the high bit; When the control bit is 0, the two-choice data selector enables the L' transformation circuit, and the function multiplexing module reads the round key generation parameters from the round key generation parameter storage space of the corresponding key storage module, performs an expansion operation on the incoming key, stores the generated round key in the round key storage space of the corresponding key storage module, and passes the key expansion operation value backward; when the control bit is 1, the two-choice data selector enables the L transformation circuit, and the function multiplexing module reads the round key from the round key storage space of the corresponding key storage module, performs round scrambling on the incoming data, and passes the scrambled data backward.
2. The function multiplexing SM4 encryption circuit based on pipeline mode according to claim 1, characterized in that: The key storage module is a BRAM storage circuit.