Display substrate, display panel and display device

Abstract

The utility model provides a display substrate, a display panel and a display device, relates to the technical field of display, and aims to improve the phenomenon of non-uniform display. The display substrate comprises a display area and a fan-out area, and the fan-out area is located on one side of the display area in the first direction. The display substrate comprises at least one fan-out line, at least one compensation line and a plurality of check blocks which are arranged in a fan-out area, one first fan-out line is electrically connected with one compensation line, each compensation line comprises a plurality of compensation line segments which are connected, and the compensation line segments are arranged in the first direction. In the first direction, at least parts of every two adjacent compensation line segments are opposite to form a first gap, and the check blocks are located in the first gaps. The display substrate can be applied to a display panel to realize picture display.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display substrate, a display panel, and a display device. Background Art

[0002] In the process of manufacturing a display substrate, it is necessary to coat an alignment film material on the surface of the display substrate. The alignment film formed after the alignment film material is cured is used to control the initial alignment (i.e., the pretilt angle) of liquid crystal molecules.

[0003] However, the alignment film material has fluidity and is likely to flow back from the area outside the display area to the display area, resulting in non-uniform thickness of the alignment film in each area of the display area, causing the problem of display mura (display non-uniformity). Summary of the Utility Model

[0004] This application provides a display substrate, a display panel, and a display device, aiming to improve the phenomenon of display non-uniformity.

[0005] To achieve the above object, the embodiments of this application provide the following technical solutions:

[0006] On the one hand, a display substrate is provided. The display substrate includes a display area and a fan-out area. Along a first direction, the fan-out area is located on one side of the display area. The display substrate includes at least one fan-out trace, at least one compensation line, and a plurality of stoppers disposed in the fan-out area. One fan-out trace is electrically connected to one compensation line. The compensation line includes a plurality of connected compensation segments arranged along the first direction. In the first direction, at least a part of two adjacent compensation segments is opposite to form a first gap, and the stopper is located in the first gap.

[0007] In the display substrate provided by the embodiments of this application, multiple fan-out traces are provided in the fan-out area. The lengths and resistances of the multiple fan-out traces are different. By electrically connecting the compensation line to the fan-out trace with a smaller length and resistance, the length and resistance of the fan-out trace are compensated, so that the lengths and resistances of the multiple fan-out traces are as close as possible and the impedances are close, avoiding the problem of display color deviation caused by a large impedance difference between the multiple fan-out traces.

[0008] Moreover, the compensation line includes a plurality of connected compensation line segments arranged in a first direction. The compensation line adopts a non-linear winding design, so that there are gaps in the compensation line. The gaps in the compensation line are fully filled by the stoppers, which is beneficial to the surface flattening of the film layer above the compensation line. During the process of coating the alignment film material (for example, Polyimide (PI)), the alignment film material can flow into the display area in the first direction, which can prevent the alignment film material from aggregating at the gaps, thereby avoiding the alignment film material aggregated at the gaps from flowing back to the display area from the fan-out area. After the alignment film material is cured to form the alignment film, it is beneficial to improve the thickness uniformity of the alignment film in each area of the display area, thereby improving the PI mura phenomenon and the quality of the display screen.

[0009] In some embodiments, the display substrate further includes a substrate, and the first fan-out trace, the second fan-out trace, the compensation line, and the stoppers are all disposed on the substrate. The shape of the positive projection of the stopper on the substrate is the same as the shape of the first gap of the compensation line on the substrate, and each side of the positive projection of the stopper on the substrate corresponds to and is parallel to each side of the first gap of the compensation line on the substrate.

[0010] In some embodiments, along a second direction perpendicular to the first direction, the boundary of the stopper does not exceed the boundary of the compensation line, and the distance range between the boundary of the stopper and the boundary of the compensation line is 0 to 3 μm.

[0011] In some embodiments, the compensation line further includes a plurality of connection line segments. The connection line segments are straight line segments extending in the first direction, and the compensation line segments are straight line segments extending in a second direction. The compensation line segments and the connection line segments are alternately connected, and the second direction is perpendicular to the first direction. The shape of the positive projection of the first gap of the compensation line on the substrate is a rectangle, and the shape of the positive projection of the stopper on the substrate is a rectangle. Moreover, the four sides of the positive projection of the stopper on the substrate correspond to and are parallel to the four sides of the positive projection of the first gap of the compensation line on the substrate one by one.

[0012] In some embodiments, the ratio range of the dimension of the stopper in the first direction to the dimension in the second direction is 0.066 to 0.15.

[0013] In some embodiments, the compensation line further includes a plurality of connection line segments, and two adjacent compensation line segments are sequentially connected by at least two connection line segments. The shape of the positive projection of the first gap of the compensation line on the substrate is a polygon, and the shape of the positive projection of the stopper on the substrate is a polygon. Moreover, the multiple sides of the positive projection of the stopper on the substrate correspond to and are parallel to the multiple sides of the positive projection of the first gap of the compensation line on the substrate one by one.

[0014] In some embodiments, the compensation line segments are straight line segments, and the minimum included angle between the compensation line segments and the first direction is an acute angle. Two adjacent compensation line segments are directly connected, and the minimum included angle between two adjacent compensation line segments is greater than 0 and less than 180°. The shape of the positive projection of the first gap of the compensation line on the substrate is triangular, and the shape of the positive projection of the stopper on the substrate is triangular. Moreover, the three sides of the positive projection of the stopper on the substrate correspond to and are parallel to the three sides of the positive projection of the first gap of the compensation line on the substrate.

[0015] In some embodiments, the compensation line segments are arcs, and the inner sides of the arcs of two adjacent compensation line segments face each other to form a first gap. The shape of the positive projection of the first gap of the compensation line on the substrate is circular, and the shape of the positive projection of the stopper on the substrate is circular.

[0016] In some embodiments, the display substrate further includes a substrate, and a plurality of conductive layers stacked on the substrate. Any one of the plurality of conductive layers includes a fan-out trace and a compensation line, and another conductive layer includes a stopper.

[0017] In some embodiments, along the direction perpendicular to the substrate, the depth range of the first gap of the compensation line is 3000 Å to 4500 Å, and the thickness range of the stopper is 3000 Å to 4500 Å.

[0018] In some embodiments, the display substrate further includes an alignment film, the alignment film covers the side of the plurality of conductive layers away from the substrate, and at least a part of the alignment film is located in the fan-out region.

[0019] In some embodiments, the display substrate includes a plurality of fan-out traces and a plurality of compensation lines. A part of the plurality of fan-out traces is electrically connected to the compensation line as the first fan-out trace, and another part is not electrically connected to the compensation line as the second fan-out trace. Along the direction parallel to the boundary between the fan-out region and the display region, the plurality of second fan-out traces are disposed on opposite sides of the plurality of first fan-out traces.

[0020] Among the plurality of first fan-out traces, at least one first fan-out trace has a compensation line with a length greater than that of the compensation line of another first fan-out trace. The number of compensation line segments and first gaps of the longer compensation line is greater than that of the shorter compensation line. And the number of stoppers in the first gap of the longer compensation line is greater than that of the shorter compensation line in the first gap.

[0021] In some embodiments, a channel is formed between two adjacent compensation lines, the channel extends along the first direction, and the first gap of the compensation line is connected to the channel.

[0022] In some embodiments, the first fan-out wiring and the second fan-out wiring both include straight line segments extending in a first direction. A second gap is formed between two adjacent straight line segments along a direction parallel to the boundary between the fan-out region and the display region. The display substrate further includes a plurality of barrier ribs disposed in the fan-out region, and the barrier ribs are located in the second gap.

[0023] In some embodiments, the display substrate further includes a plurality of data lines, and the plurality of data lines extend from the display region to the fan-out region. One data line is electrically connected to one fan-out wiring.

[0024] On the other hand, a display panel is provided, which includes the display substrate in any of the above embodiments, and a counter substrate disposed opposite to the display substrate.

[0025] On yet another hand, a display device is provided, which includes the display panel in the above embodiments, and a controller electrically connected to the display panel.

[0026] The above display panel and display device have the same structure and beneficial technical effects as the display substrate provided in some of the above embodiments, and will not be elaborated herein. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the present application, the drawings required to be used in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and do not represent the actual sizes of the products and the actual processes of the methods involved in the embodiments of the present application.

[0028] Figure 1 A structural diagram of a display substrate provided by an embodiment of the present application;

[0029] Figure 2 For Figure 1 A partial cross-sectional view of the display substrate in along the section line A-A';

[0030] Figure 3 For Figure 1 A partial enlarged view of the display substrate in at M;

[0031] Figure 4 For Figure 3 A partial enlarged view of the display substrate in at N;

[0032] Figure 5 For Figure 4 A partial cross-sectional view of the display substrate in along the section line B-B';

[0033] Figure 6 For Figure 3Partial enlarged view of the display substrate at P;

[0034] Figure 7 is Figure 6 Partial cross-sectional view of the display substrate along section line C-C' in;

[0035] Figure 8 Another partial enlarged view of the display substrate provided by the embodiment of the present application at N;

[0036] Figure 9 is Figure 8 Partial cross-sectional view of the display substrate along section line B-B' in;

[0037] Figure 10 Another partial enlarged view of the display substrate provided by the embodiment of the present application at P;

[0038] Figure 11 is Figure 10 Partial cross-sectional view of the display substrate along section line C-C' in;

[0039] Figures 12 to 14 Line type diagrams of multiple compensation lines provided by the embodiment of the present application;

[0040] Figures 15 to 17 Another several partial cross-sectional views of the display substrate along section line C-C' provided by the embodiment of the present application;

[0041] Figure 18 Structural diagram of the display panel provided by the embodiment of the present application;

[0042] Figure 19 Structural diagram of the display device provided by the embodiment of the present application. Detailed implementation manners

[0043] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0044] Unless otherwise required by the context, in the entire specification and claims, the term "comprising" is interpreted as an open, inclusive meaning, that is, "including, but not limited to".

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0046] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0047] In addition, the use of "based on" means open and inclusive, because a process, step, calculation, or other action "based on" one or more of the said conditions or values may, in practice, be based on additional conditions or values beyond the said ones.

[0048] It should be understood that when a layer or element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0049] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Therefore, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] Embodiments of the present application provide a display substrate. Figure 1 It is a structural diagram of a display substrate provided by an embodiment of the present application. Figure 2 It is Figure 1 a partial cross-sectional view of the display substrate in along the section line A-A'. Figure 3 It is Figure 1 a partial enlarged view of the display substrate at M in . Figure 4 It is Figure 3 a partial enlarged view of the display substrate at N in . Figure 5 It is Figure 4 a partial cross-sectional view of the display substrate in along the section line B-B'.Figure 6 is Figure 3 a partial enlarged view of the display substrate in at P; Figure 7 is Figure 6 a partial cross-sectional view of the display substrate in along the section line C-C';

[0051] Refer to Figure 1 , the display substrate 1 includes a display area (Active Area, AA) 2 and a fanout area 3. Along the first direction X, the fanout area 3 is located on one side of the display area 2.

[0052] A plurality of sub-pixels P are provided in the display area 2 of the display substrate 1. For the convenience of description, in this application, it is taken as an example that the plurality of sub-pixels P are arranged in an array. The plurality of sub-pixels P include multiple columns and multiple rows. Each column of sub-pixels P extends along the first direction X, and each row of sub-pixels P extends along the second direction Y. The first direction X intersects with the second direction Y. For example, the first direction X is perpendicular to the second direction Y.

[0053] Refer to Figure 2 , the display substrate 1 includes a first substrate 110 and a plurality of conductive layers stacked on the first substrate 110. Exemplarily, the plurality of conductive layers include a gate conductive layer Gate, an active film layer ACT, a source-drain conductive layer SD, a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 stacked in sequence.

[0054] Each sub-pixel P includes a thin film transistor 111 located on the first substrate 110. The thin film transistor 111 includes an active layer 112, a source electrode 113, a drain electrode 114, a gate electrode 115, and a gate insulating layer 116. The source electrode 113 and the drain electrode 114 are respectively in contact with the active layer 112.

[0055] Exemplarily, the gate electrode 115 of the thin film transistor 111 is located in the gate conductive layer Gate, the active layer 112 is located in the active film layer ACT, and the gate insulating layer 116 is located between the gate conductive layer Gate and the active film layer ACT, serving to isolate the gate electrode 115 from the active layer 112. The source electrode 113 and the drain electrode 114 are located in the source-drain conductive layer SD, and the source electrode 113 and the drain electrode 114 can be directly overlapped on the active layer 112.

[0056] Refer to Figure 2, the display substrate 1 further includes a first passivation layer 117 and a planarization layer 118, and the first passivation layer 117 and the planarization layer 118 sequentially cover the source electrode 113 and the drain electrode 114 of the thin film transistor 111. The display substrate 1 further includes a common electrode 119, an auxiliary electrode 120, and a pixel electrode 121. The common electrode 119 is disposed on a side of the planarization layer 118 away from the first substrate 110, and the auxiliary electrode 120 is disposed on a side of the common electrode 119 away from the first substrate 110. The auxiliary electrode 120 is directly in electrical contact with the common electrode 119 to achieve parallel connection, which can reduce the impedance of the transmission path of the common voltage signal and reduce the voltage drop of the common voltage signal during transmission.

[0057] In some examples, as Figure 2 shown, the pixel electrode 121 and the common electrode 119 may be disposed on different layers. The common electrode 119 is located in the first conductive layer M1, the auxiliary electrode 120 is located in the second conductive layer M2, and the pixel electrode 121 is located in the third conductive layer M3. In this case, an insulating layer 122 is provided between the pixel electrode 121 and the common electrode 119. The pixel electrode 121 sequentially penetrates through the insulating layer 122, the auxiliary electrode 120, the common electrode 119, the planarization layer 118, and the first passivation layer 117, and is electrically connected to the drain electrode 114 of the thin film transistor 111.

[0058] In other examples, the pixel electrode 121 and the common electrode 119 may also be disposed on the same layer. In this case, both the pixel electrode 121 and the common electrode 119 are comb structures including a plurality of strip-shaped sub-electrodes.

[0059] Referring to Figure 2 , the display substrate 1 further includes an alignment film 123. The alignment film 123 covers a side of the plurality of conductive layers away from the first substrate 110. The display substrate 1 can be applied to a thin film transistor liquid crystal display (TFT-LCD). The alignment film 123 is used to control the initial alignment of liquid crystal molecules, that is, to determine the arrangement direction of liquid crystal molecules when no electric field is applied.

[0060] Referring to Figure 1 and Figure 2 , the display substrate 1 further includes a plurality of gate lines 4 and a plurality of data lines 5. Each gate line 4 extends along the second direction Y, and each data line 5 extends along the first direction X. The gate electrode 115 of the thin film transistor 111 in each row of sub-pixels P is electrically connected to a gate line 4, and the source electrode 113 of the thin film transistor 111 in each column of sub-pixels P is electrically connected to a data line 5.

[0061] Referring to Figure 1, the display substrate 1 further includes a gate driving circuit 6, and the gate driving circuit 6 can be disposed on a side along the extending direction of the gate lines 4, so as to facilitate the electrical connection between the gate driving circuit 6 and the plurality of gate lines 4. The gate driving circuit 6 is configured to transmit a gate scanning signal to the plurality of gate lines 4.

[0062] In some examples, the gate driving circuit 6 can be a gate driving IC. In other examples, the gate driving circuit 6 can also be a GOA (full English name: Gate Driver on Array) circuit, that is, the gate driving circuit 6 is directly integrated on the display substrate 1. Among them, setting the gate driving circuit 6 as a GOA circuit compared with setting it as a gate driving IC, on the one hand, can reduce the manufacturing cost of the display substrate 1, and on the other hand, can also narrow the frame width of the display device.

[0063] See Figure 1 , the display substrate 1 further includes a plurality of fan-out traces 7 disposed in the fan-out region 3. The plurality of data lines 5 extend from the display region 2 to the fan-out region 3, and one data line 5 is electrically connected to one fan-out trace 7. The display substrate 1 further includes a data driving circuit 8, and the data driving circuit 8 can be disposed on a side along the extending direction of the data lines 5. For example, the data driving circuit 8 is disposed on a side of the fan-out region 3 away from the display region 2. The plurality of fan-out traces 7 are electrically connected to the data driving circuit 8, and the data driving circuit 8 transmits a data voltage signal to the plurality of data lines 5 through the plurality of fan-out traces 7.

[0064] In some examples, the data driving circuit 8 can adopt a data driving IC, and the data driving IC is bonded to the plurality of fan-out traces 7.

[0065] Based on this, the gate 115 of the thin film transistor 111 in each row of sub-pixels P receives a gate scanning signal from the same gate line 4, and the source 113 of the thin film transistor 111 in each column of sub-pixels P receives a data voltage signal from the same data line 5, so as to control the thin film transistor 111 in each sub-pixel P to conduct. The drain 114 of the thin film transistor 111 transmits a pixel voltage signal to the pixel electrode 121 to realize the driving of the plurality of sub-pixels P.

[0066] See Figure 1 , generally, the data driving circuit 8 is close to the middle region of the fan-out region 3. Therefore, among the plurality of fan-out traces 7, the fan-out traces 7 close to the middle region of the fan-out region 3 have a smaller length, and the fan-out traces 7 far from the middle region of the fan-out region 3 have a larger length, so that the fan-out traces 7 close to the middle region of the fan-out region 3 have a smaller resistance, and the fan-out traces 7 far from the middle region of the fan-out region 3 have a larger resistance.

[0067] In order to make the resistances of the plurality of fan-out traces 7 close, see Figure 1 and Figure 3, the display substrate 1 further includes a compensation line 73 disposed in the fan-out region 3. Among the plurality of fan-out traces 7, the fan-out traces 7 near the middle region of the fan-out region 3 are electrically connected to the compensation line 73, and the fan-out traces 7 and the compensation line 73 together serve as the first fan-out traces 71. Moreover, the fan-out traces 7 far from the middle region of the fan-out region 3 are not electrically connected to the compensation line 73, and these fan-out traces 7 are used as the second fan-out traces 72. Along the direction parallel to the boundary between the fan-out region 3 and the display region 2 (for example, the direction Y), the plurality of second fan-out traces 72 are disposed on opposite sides of the plurality of first fan-out traces 71.

[0068] The compensation line 73 is used to compensate for the length of the shorter fan-out traces 7 to compensate for the resistance of the shorter fan-out traces 7, so that the resistance of the compensated first fan-out traces 71 is as close as possible to the resistance of the second fan-out traces 72, making the impedance of the first fan-out traces 71 and the second fan-out traces 72 close, and avoiding the problem of display color deviation caused by a large impedance difference among the plurality of fan-out traces 7.

[0069] Exemplarily, continue to refer to Figure 1 , along the direction Y, from the middle of the plurality of fan-out traces 7 to both sides, the length of the fan-out traces 7 decreases in sequence, and the resistance of the fan-out traces 7 decreases in sequence. The resistances of the plurality of fan-out traces 7 are different, and different resistance compensation values are required. In order to make the resistances of the plurality of fan-out traces 7 close, the lengths of the plurality of compensation lines 73 can be set differently to meet the different resistance compensation value requirements of the plurality of fan-out traces 7.

[0070] For example, refer to Figure 1 and Figure 3 , among the plurality of first fan-out traces 71, there is at least one first fan-out trace 71 whose length and resistance of the fan-out trace 7 are greater than those of another first fan-out trace 71. The compensation line 73 connected to the fan-out trace 7 with a larger length and resistance is set shorter and has a smaller resistance, and the compensation line 73 connected to the fan-out trace 7 with a smaller length and resistance is set longer and has a larger resistance, so that the impedances of the different first fan-out traces 71 are close, and avoiding the problem of display color deviation caused by a large impedance difference among the plurality of first fan-out traces 71.

[0071] In the embodiments of the present application, among the plurality of first fan-out traces 71 with resistance compensation and the plurality of second fan-out traces 72, the resistance between adjacent two fan-out traces is close, and the difference between the maximum resistance and the minimum resistance among the plurality of fan-out traces is less than 20 Ω.

[0072] Refer to Figures 3 to 5 , both the first fan-out traces 71 and the second fan-out traces 72 include straight line segments 70 extending along the first direction X. Along the direction parallel to the boundary between the fan-out region 3 and the display region 2 (for example, the direction Y), a gap F is formed between adjacent two straight line segments 70.

[0073] Exemplarily, the first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 are all located in the gate conductive layer Gate. A gap F is formed between two adjacent straight line segments 70. Grooves will be formed on the surface of the film layer above the gap F. During the process of coating the alignment film material (for example, Polyimide (PI)), the alignment film material is likely to accumulate in large quantities in the grooves, and the alignment film material accumulated in the grooves is likely to flow back from the fan-out region 3 to the display region 2, resulting in uneven thickness of the alignment film 123 in each region of the display region 2. In the case of displaying a low gray-scale image (for example, 32 gray scales or 64 gray scales), obvious PI mura (display unevenness) - like display anomalies can be macroscopically found, reducing the display quality.

[0074] And, referring to Figure 6 and Figure 7 , the compensation line 73 includes a plurality of connected compensation line segments 74. The plurality of compensation line segments 74 are arranged along the first direction X. In the first direction X, at least part of two adjacent compensation line segments 74 are opposite to each other to form a gap G. Moreover, the lengths of the plurality of compensation lines 73 are different. The greater the length of the compensation line 73, the more the number of compensation line segments 74 and gaps G in the compensation line 73.

[0075] Exemplarily, the compensation line 73 further includes a plurality of connection line segments 75. The connection line segments 75 are straight line segments extending along the first direction X, and the compensation line segments 74 are straight line segments extending along the second direction Y. The compensation line segments 74 and the connection line segments 75 are alternately connected, and the second direction Y is perpendicular to the first direction X.

[0076] For example, the shape of the orthographic projection of the compensation line 73 on the first substrate 110 can be bow-shaped (or called serpentine). The first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 are all located in the gate conductive layer Gate. A gap G will be formed between two adjacent compensation line segments 74 of the compensation line 73. Grooves will be formed on the surface of the film layer above the gap G. During the process of coating the alignment film material, the alignment film material is likely to accumulate in large quantities in the grooves, and the alignment film material accumulated in the grooves is likely to flow back from the fan-out region 3 to the display region 2, resulting in uneven thickness of the alignment film 123 in each region of the display region 2. In the case of displaying a low gray-scale image, obvious PI mura - like display anomalies can be macroscopically found, reducing the display quality.

[0077] To solve the above problems, an embodiment of the present application further provides a display substrate, Figure 8 is a partial enlarged view of another display substrate provided by an embodiment of the present application at N; Figure 9 is Figure 8 a partial cross-sectional view of the display substrate in Figure 10 along the section line B - B'; is a partial enlarged view of another display substrate provided by an embodiment of the present application at P;Figure 11 is Figure 10 a partial cross-sectional view of the display substrate in [FIG.] along the section line C-C'.

[0078] Refer to Figure 8 and Figure 9 , the display substrate 1 further includes a plurality of barrier ribs 76 disposed in the fan-out region 3. The barrier ribs 76 are located in the gap F and can fully fill the gap F between two adjacent straight line segments 70, which is beneficial to the surface planarization of the film layer above the gap F. During the process of coating the alignment film material, the alignment film material flows into the display region 2 along the first direction X, which can prevent the alignment film material from accumulating at the gap F, thereby preventing the alignment film material accumulated at the gap F from flowing back from the fan-out region 3 to the display region 2. After the alignment film material is cured to form the alignment film 123, it is beneficial to improve the thickness uniformity of the alignment film 123 in each region of the display region 2, thereby improving the phenomenon of PI mura and enhancing the quality of the display screen.

[0079] Exemplarily, when the first fan-out trace 71, the second fan-out trace 72, and the compensation line 73 are all located in the gate conductive layer Gate, the barrier ribs 76 can be disposed in the source-drain conductive layer SD, and the barrier ribs 76 fill the gap F between two adjacent straight line segments 70. The barrier ribs 76 and the straight line segments 70 are located in different conductive layers, preventing the barrier ribs 76 and the straight line segments 70 from being in the same conductive layer and avoiding short circuits between adjacent straight line segments 70 during the patterning of the gate conductive layer Gate to form the barrier ribs 76.

[0080] Continue to refer to Figure 10 and Figure 11 , the display substrate 1 further includes a plurality of stoppers 77 disposed in the fan-out region 3. The stoppers 77 are located in the gap G and can fully fill the gap G of the compensation line 73, which is beneficial to the surface planarization of the film layer above the compensation line 73. During the process of coating the alignment film material, the alignment film material flows into the display region 2 along the first direction X, which can prevent the alignment film material from accumulating at the gap G, thereby preventing the alignment film material accumulated at the gap G from flowing back from the fan-out region 3 to the display region 2. After the alignment film material is cured to form the alignment film 123, it is beneficial to improve the thickness uniformity of the alignment film 123 in each region of the display region 2, thereby improving the phenomenon of PI mura and enhancing the quality of the display screen.

[0081] Moreover, the lengths of the plurality of compensation lines 73 are different. The greater the length of the compensation line 73, the more the number of compensation line segments 74 and the number of gaps G in the compensation line 73, and the more the number of stoppers 77 to be provided.

[0082] Exemplarily, when the first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 are all located in the gate conductive layer Gate, the stopper 77 can be disposed in the source-drain conductive layer SD, and the stopper 77 fills the gap G of the compensation line 73. The stopper 77 and the compensation line 73 are located in different conductive layers, avoiding short circuits between adjacent compensation lines 73 during the patterning of the gate conductive layer Gate to form the stopper 77 when the stopper 77 and the compensation line 73 are in the same conductive layer.

[0083] Moreover, the material of the gate conductive layer Gate may include copper or aluminum. Along the direction Z perpendicular to the first substrate 110, the thickness range of the gate conductive layer Gate is 3000 Å to 4500 Å, that is, the thickness range of the compensation line 73 is 3000 Å to 4500 Å, and the depth range of the gap G of the compensation line 73 is also 3000 Å to 4500 Å. In this case, the thickness range of the stopper 77 can be set to 3000 Å to 4500 Å, so that the thickness of the stopper 77 is close to the depth of the gap G of the compensation line 73, which is beneficial for the stopper 77 to fill the gap G of the compensation line 73.

[0084] For example, when the depth of the gap G of the compensation line 73 is 3000 Å, the thickness of the stopper 77 is 3000 Å; when the depth of the gap G of the compensation line 73 is 3500 Å, the thickness of the stopper 77 is 3500 Å; when the depth of the gap G of the compensation line 73 is 3750 Å, the thickness of the stopper 77 is 3750 Å; when the depth of the gap G of the compensation line 73 is 4000 Å, the thickness of the stopper 77 is 4000 Å; when the depth of the gap G of the compensation line 73 is 4500 Å, the thickness of the stopper 77 is 4500 Å. The thickness of the stopper 77 is equal to the depth of the gap G of the compensation line 73, and the stopper 77 can fill the gap G of the compensation line 73.

[0085] In some embodiments, referring to Figure 10 , the shape of the positive projection of the stopper 77 on the first substrate 110 is the same as the shape of the positive projection of the gap G of the compensation line 73 on the first substrate 110. Each side of the positive projection of the stopper 77 on the first substrate 110 corresponds to and is parallel to each side of the positive projection of the gap G of the compensation line 73 on the first substrate 110.

[0086] Through the above setting method, the shape of the positive projection of the stopper 77 is the same as the shape of the positive projection of the gap G of the compensation line 73, and each side of the positive projection of the stopper 77 corresponds to and is parallel to each side of the positive projection of the gap G, enabling the contour of the stopper 77 to be adapted to the contour of the gap G. In the X-Y plane direction, it is beneficial for the stopper 77 to fill the gap G of the compensation line 73.

[0087] Exemplarily, the shape of the orthographic projection of the compensation line 73 on the first substrate 110 is bow-shaped, the shape of the orthographic projection of the gap G of the compensation line 73 on the first substrate 110 is rectangular, and the shape of the orthographic projection of the stopper 77 on the first substrate 110 is also rectangular. The four sides of the orthographic projection of the stopper 77 on the first substrate 110 correspond to and are parallel to the four sides of the orthographic projection of the gap G of the compensation line 73 on the first substrate 110, and the contour of the stopper 77 is adapted to the contour of the gap G, which is beneficial to the stopper 77 filling the gap G of the compensation line 73 in the X-Y plane direction.

[0088] Moreover, the ratio range of the dimension (width) of the stopper 77 along the first direction X to the dimension (length) of the stopper 77 along the second direction Y is 0.066 to 0.15. Exemplarily, the ratio of the two can be 0.066, 0.1, 0.108, 0.13, or 0.15. For example, the dimension (width) of the stopper 77 along the first direction X ranges from 1 μm to 1.5 μm, and the dimension (length) of the stopper 77 along the second direction Y ranges from 10 μm to 15 μm. By setting the length and width of the stopper 77 to be close to the length and width of the gap G, it is convenient for the stopper 77 to fill the gap G of the compensation line 73.

[0089] In some embodiments, referring to Figure 10 , along the second direction Y, the boundary E1 of the stopper 77 does not exceed the boundary E2 of the compensation line 73, and the distance range between the boundary E1 of the stopper 77 and the boundary E2 of the compensation line 73 is 0 to 3 μm. For example, the distance between the boundary E1 of the stopper 77 and the boundary E2 of the compensation line 73 is 0, 1 μm, 1.5 μm, 2.5 μm, or 3 μm.

[0090] It can be understood that within the range allowed by the manufacturing process accuracy, the distance between the boundary E1 of the stopper 77 and the boundary E2 of the compensation line 73 in the second direction Y is minimized as much as possible. The smaller the distance between the boundary E1 of the stopper 77 and the boundary E2 of the compensation line 73, the better the filling effect of the stopper 77 on the gap G of the compensation line 73.

[0091] Moreover, when the distance between the boundary E1 of the stopper 77 and the boundary E2 of the compensation line 73 is 0, the stopper 77 completely fills the gap G of the compensation line 73.

[0092] In some embodiments, referring to Figure 10 , a channel T is formed between two adjacent compensation lines 73, and the channel T extends along the first direction X. The gap G of the compensation line 73 is communicated with the channel T.

[0093] It can be understood that in the case where the stopper 77 is not provided, a groove will be formed on the surface of the film layer above the gap G. Similarly, a groove will also be formed on the surface of the film layer above the channel T, and the groove extends along the first direction X.

[0094] Since the stopper 77 is provided in the gap G, the surface of the film layer above the gap G is flat. During the process of coating the alignment film material, the alignment film material will not accumulate at the gap G, but will flow from the fan-out region 3 to the display region 2 along the groove, enabling more alignment film material to flow into the display region 2 in the first direction X, which is beneficial to improving the thickness uniformity of the alignment film 123 in various regions of the display region 2.

[0095] Moreover, in the embodiments of the present application, the winding design of the compensation line 73 is not limited to the above-mentioned bow shape, and can also be a zigzag shape, an S shape or other irregular line-shaped winding designs.

[0096] Figures 12 to 14 It is a line type diagram of various compensation lines provided by the embodiments of the present application.

[0097] See Figure 12 , the compensation line 73 includes a plurality of compensation line segments 74, the plurality of compensation line segments 74 are arranged along the first direction X, the compensation line segments 74 are straight line segments, and the minimum included angle between the compensation line segments 74 and the first direction X is an acute angle, that is, the compensation line segments 74 are neither parallel nor perpendicular to the first direction X. Two adjacent compensation line segments 74 are directly connected, and the minimum included angle between two adjacent compensation line segments 74 is greater than 0 and less than 180°, that is, the winding design of the compensation line 73 is a zigzag shape.

[0098] In the first direction X, at least a part of two adjacent compensation line segments 74 are opposite to form a gap G, and the shape of the positive projection of the gap G on the first substrate 110 is a triangle. In this case, the shape of the positive projection of the stopper 77 on the first substrate 110 is a triangle, and the three sides of the positive projection of the stopper 77 on the first substrate 110 correspond to and are parallel to the three sides of the positive projection of the gap G on the first substrate 110 one by one, and the contour of the stopper 77 is adapted to the contour of the gap G, which is beneficial to the stopper 77 filling the gap G of the compensation line 73, beneficial to the surface flattening of the film layer above the compensation line 73, and can avoid the alignment film material from accumulating at the gap G during the process of coating the alignment film material.

[0099] See Figure 13 , the compensation line 73 includes a plurality of compensation line segments 74, the plurality of compensation line segments 74 are arranged along the first direction X, the compensation line segments 74 are arcs, the arcs of two adjacent compensation line segments 74 are directly connected, and the inner sides of the arcs of two adjacent compensation line segments 74 are opposite to form a gap G, that is, the winding design of the compensation line 73 is an S shape.

[0100] The shape of the orthographic projection of the gap G of the compensation line 73 on the first substrate 110 is circular. In this case, the shape of the orthographic projection of the stopper 77 on the first substrate 110 is also circular. The contour of the stopper 77 is adapted to the contour of the gap G, which is beneficial for the stopper 77 to fill the gap G of the compensation line 73, beneficial for planarizing the surface of the film layer above the compensation line 73, and can avoid the alignment film material from aggregating at the gap G during the process of coating the alignment film material.

[0101] See Figure 14 , the compensation line 73 includes a plurality of compensation line segments 74, and the plurality of compensation line segments 74 are arranged along the first direction X. The compensation line 73 further includes a plurality of connection line segments 75. Two adjacent compensation line segments 74 are sequentially connected by at least two connection line segments 75, and the winding of the compensation line 73 is designed as an irregular line type.

[0102] In the first direction X, at least a part of two adjacent compensation line segments 74 are opposite to form a gap G. The shape of the orthographic projection of the gap G on the first substrate 110 is polygonal. In this case, the shape of the orthographic projection of the stopper 77 on the first substrate 110 is polygonal. The multiple sides of the orthographic projection of the stopper 77 on the first substrate 110 correspond to and are parallel to the multiple sides of the orthographic projection of the gap G on the first substrate 110. The contour of the stopper 77 is adapted to the contour of the gap G, which is beneficial for the stopper 77 to fill the gap G of the compensation line 73, beneficial for planarizing the surface of the film layer above the compensation line 73, and can avoid the alignment film material from aggregating at the gap G during the process of coating the alignment film material.

[0103] In some examples, see Figure 14 , two adjacent compensation line segments 74 are sequentially connected by two connection line segments 75. The shape of the orthographic projection of the gap G is pentagonal. In this case, the shape of the orthographic projection of the stopper 77 is pentagonal. The multiple sides of the orthographic projection of the stopper 77 correspond to and are parallel to the multiple sides of the orthographic projection of the gap G. The contour of the stopper 77 is adapted to the contour of the gap G.

[0104] In other examples, two adjacent compensation line segments 74 are sequentially connected by three connection line segments 75. The shape of the orthographic projection of the gap G is hexagonal. In this case, the shape of the orthographic projection of the stopper 77 is hexagonal. The multiple sides of the orthographic projection of the stopper 77 correspond to and are parallel to the multiple sides of the orthographic projection of the gap G. The contour of the stopper 77 is adapted to the contour of the gap G. The embodiments of the present application are not limited thereto.

[0105] In addition, in the embodiments of the present application, the conductive layers where the compensation line 73 and the stopper 77 are located are not limited to the above, and the two can be located in any two different conductive layers.

[0106] Figures 15 to 17Partial cross-sectional views of several other display substrates provided by embodiments of the present application along the section line C-C'.

[0107] Referring to Figure 15 , the first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 are all located in the gate conductive layer Gate. The stopper 77 can be disposed in the first conductive layer M1, and the stopper 77 fills the gap G of the compensation line 73. The stopper 77 and the compensation line 73 are located in different conductive layers to prevent a short circuit between adjacent compensation lines 73 during the patterning of the gate conductive layer Gate to form the stopper 77.

[0108] Referring to Figure 16 , the first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 are all located in the gate conductive layer Gate. The stopper 77 can be disposed in the second conductive layer M2, and the stopper 77 fills the gap G of the compensation line 73. The stopper 77 and the compensation line 73 are located in different conductive layers to prevent a short circuit between adjacent compensation lines 73 during the patterning of the gate conductive layer Gate to form the stopper 77.

[0109] Referring to Figure 17 , the first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 are all located in the gate conductive layer Gate. The stopper 77 can be disposed in the third conductive layer M3, and the stopper 77 fills the gap G of the compensation line 73. The stopper 77 and the compensation line 73 are located in different conductive layers to prevent a short circuit between adjacent compensation lines 73 during the patterning of the gate conductive layer Gate to form the stopper 77.

[0110] In the embodiments of the present application, the first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 are not limited to being disposed in the gate conductive layer Gate. The first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 can also be disposed in other conductive layers. In this case, the stopper 77 and the compensation line 73 are disposed in different conductive layers to prevent a short circuit between adjacent compensation lines 73.

[0111] Similarly, the conductive layers where the straight segment 70 and the bar 76 are located are not limited to the above, and the two can be located in any two different conductive layers. For example, when the first fan-out wiring 71, the second fan-out wiring 72, and the compensation line 73 are all located in the gate conductive layer Gate, the bar 76 can also be disposed in the first conductive layer M1, the second conductive layer M2, or the third conductive layer M3.

[0112] For another example, the first outgoing line 71, the second outgoing line 72, and the compensation line 73 can also be disposed in other conductive layers except the gate conductive layer Gate. In this case, the barrier strip 76 and the straight line segment 70 are disposed in different conductive layers to avoid short circuits between adjacent compensation lines 73.

[0113] An embodiment of the present application further provides a display panel. Figure 18 It is a structural diagram of the display panel provided by the embodiment of the present application.

[0114] Referring to Figure 18 , the display panel 10 includes the display substrate 1 in any of the above embodiments, the counter substrate 20, and the liquid crystal layer 21 disposed between the display substrate 1 and the counter substrate 20.

[0115] During the process of the display panel 10 displaying an image, the pixel electrode 121 receives a pixel voltage signal, and the common electrode 119 receives a common voltage signal. A planar electric field is formed between the two. Under the drive of this electric field, the liquid crystal molecules in the liquid crystal layer 21 rotate in the plane, causing birefringence to control the light transmittance.

[0116] The counter substrate 20 includes a second substrate 201 and a color filter layer 202 disposed on the second substrate 201. In this case, the counter substrate 20 can also be referred to as a color filter (CF) substrate. Among them, the color filter layer 202 at least includes a red photoresist unit, a green photoresist unit, and a blue photoresist unit. The red photoresist unit, the green photoresist unit, and the blue photoresist unit are respectively directly opposite to the sub-pixels P on the display substrate 1. The counter substrate 20 further includes a black matrix pattern 203 disposed on the second substrate 201, and the black matrix pattern 203 is used to separate the red photoresist unit, the green photoresist unit, and the blue photoresist unit.

[0117] An embodiment of the present application further provides a display device, and the display device can be a TFT-LCD. Figure 19 It is a structural diagram of the display device provided by the embodiment of the present application.

[0118] Referring to Figure 19 , the display device 100 includes the display panel 10 in the above embodiment and a controller 30 electrically connected to the display panel 10. The controller 30 can be disposed on the non-display side of the display panel 10 and is used to control the display panel 10 to display an image.

[0119] The above display device can be any device that displays images whether in motion (e.g., video) or stationary (e.g., still images), and whether text or otherwise. More specifically, it is contemplated that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photo frames, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0120] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application, thinking of changes or substitutions, should be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized in that: It comprises a display area and a fan-out area, wherein along a first direction, the fan-out area is located at one side of the display area; The display substrate comprises: At least one fan-out trace is arranged in the fan-out area; At least one compensation line is arranged in the fan-out area, the fan-out line is electrically connected to the compensation line; the compensation line includes a plurality of connected compensation line segments, the plurality of compensation line segments are arranged along the first direction; in the first direction, at least parts of two adjacent compensation line segments relatively form a first gap; A plurality of stoppers are arranged in the fan-out area, and the stoppers are located in the first gap.

2. The display substrate according to claim 1, characterized in that: The display substrate further comprises a substrate, and the fan-out wiring, the compensation line and the block are all arranged on the substrate; The shape of the orthographic projection of the stopper on the substrate is the same as the shape of the orthographic projection of the first gap of the compensation line on the substrate; Each side of the orthographic projection of the stopper on the substrate corresponds to and is parallel to each side of the orthographic projection of the first gap of the compensation line on the substrate.

3. The display substrate according to claim 2, characterized in that: Along a second direction perpendicular to the first direction, the boundary of the block does not exceed the boundary of the compensation line, and the distance between the boundary of the block and the boundary of the compensation line is in a range of 0 to 3 μm.

4. The display substrate according to claim 2 or 3, characterized in that: The compensation line further includes a plurality of connecting line segments, wherein the connecting line segments are straight line segments extending along the first direction, and the compensation line segments are straight line segments extending along a second direction, the compensation line segments are alternately connected with the connecting line segments, and the second direction is perpendicular to the first direction; The shape of the orthographic projection of the first gap of the compensation line on the substrate is a rectangle, and the shape of the orthographic projection of the stopper on the substrate is a rectangle; The four sides of the orthographic projection of the blocking block on the substrate correspond one-to-one and are parallel to the four sides of the orthographic projection of the first gap of the compensation line on the substrate.

5. The display substrate according to claim 4, characterized in that: The ratio of the size of the stopper along the first direction to the size of the stopper along the second direction is in a range of 0.066 to 0.

15.

6. The display substrate according to claim 2 or 3, characterized in that: The compensation line further comprises a plurality of connecting line segments, and two adjacent compensation line segments are sequentially connected by at least two connecting line segments; The orthographic projection shape of the first gap of the compensation line on the substrate is a polygon, and the orthographic projection shape of the stopper on the substrate is a polygon; The multiple sides of the orthographic projection of the blocking block on the substrate correspond one-to-one and are parallel to the multiple sides of the orthographic projection of the first gap of the compensation line on the substrate.

7. The display substrate according to claim 2 or 3, characterized in that: The compensation line segment is a straight line segment, and the minimum angle between the compensation line segment and the first direction is an acute angle; two adjacent compensation line segments are directly connected, and the minimum angle between the two adjacent compensation line segments is greater than 0 and less than 180°; The orthographic projection shape of the first gap of the compensation line on the substrate is a triangle, and the orthographic projection shape of the stopper on the substrate is a triangle; The three sides of the orthographic projection of the blocking block on the substrate correspond one-to-one and are parallel to the three sides of the orthographic projection of the first gap of the compensation line on the substrate.

8. The display substrate according to claim 2 or 3, characterized in that: The compensation line segment is an arc, and the inner sides of the arcs of two adjacent compensation line segments relatively form the first gap; The orthographic projection shape of the first gap of the compensation line on the substrate is a circle, and the orthographic projection shape of the stopper on the substrate is a circle.

9. The display substrate according to claim 1, characterized in that: The display substrate further comprises a substrate, and a plurality of conductive layers stacked on the substrate; Any one of the plurality of conductive layers includes the fan-out trace and the compensation line, and another conductive layer includes the stopper.

10. The display substrate according to claim 9, characterized in that: Along a direction perpendicular to the substrate, a depth of the first gap of the compensation line ranges from 3000 angstroms to 4500 angstroms, and a thickness of the stopper ranges from 3000 angstroms to 4500 angstroms.

11. The display substrate according to claim 9 or 10, characterized in that: The display substrate further comprises an alignment film, wherein the alignment film covers a side of the plurality of conductive layers away from the substrate, and at least a portion of the alignment film is located in the fan-out region.

12. The display substrate according to claim 1, characterized in that: The display substrate comprises a plurality of fan-out routing lines and a plurality of compensation lines, a portion of the plurality of fan-out routing lines being electrically connected to the compensation lines as first fan-out routing lines, and another portion of the plurality of fan-out routing lines being not electrically connected to the compensation lines as second fan-out routing lines; the plurality of second fan-out routing lines being arranged on opposite sides of the plurality of first fan-out routing lines in a direction parallel to a boundary between the fan-out area and the display area; Among the multiple first fan-out routing lines, the length of the compensation line of at least one first fan-out routing line is greater than the length of the compensation line of another first fan-out routing line, the number of compensation line segments and first gaps of the longer compensation line is greater than the number of compensation line segments and first gaps of the shorter compensation line; and the number of stoppers in the first gap of the longer compensation line is greater than the number of stoppers in the first gap of the shorter compensation line.

13. The display substrate according to claim 12, characterized in that: A channel is formed between two adjacent compensation lines, the channel extends along the first direction, and the first gap of the compensation line is connected to the channel.

14. The display substrate according to claim 12 or 13, characterized in that: The first fan-out routing line and the second fan-out routing line both include a straight line segment extending along the first direction, and a second gap is formed between two adjacent straight line segments along a direction parallel to a boundary between the fan-out area and the display area; The display substrate further includes a plurality of barrier strips disposed in the fan-out region, and the barrier strips are located in the second gap.

15. The display substrate according to claim 1, characterized in that: The display substrate further includes a plurality of data lines, wherein the plurality of data lines extend from the display area to the fan-out area; A data line is electrically connected to a fan-out trace.

16. A display panel, characterized in that: include: The display substrate according to any one of claims 1 to 15; The counter-box substrate is arranged opposite to the display substrate.

17. A display device, characterized in that: include: The display panel as claimed in claim 16; A controller is electrically connected to the display panel.

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