Display panel and display device

Abstract

The utility model relates to the technical field of display, and provides a display panel and a display device, and the display panel comprises a plurality of pixel driving circuits, a plurality of data lines, a source electrode driving circuit, a plurality of data connecting lines, a plurality of grid lines and a grid electrode driving circuit. One end of the data connecting line is connected with the source driving circuit, the other end of the data connecting line is connected with the plurality of data lines, and the source driving circuit is used for providing data signals for the plurality of data lines through the data connecting line; the gate driving circuit provides a gate driving signal for the pixel driving circuit through a gate line; wherein the plurality of data lines form a plurality of data line groups, each data line group comprises a plurality of data lines, and the plurality of data lines connected to the same data connecting line are located in different data line groups; the gate drive circuit is used for controlling the pixel drive circuits connected with different data line groups to perform time-sharing scanning, and the scanning of the pixel drive circuits includes writing data signals into the pixel drive circuits. The arrangement can improve the display effect of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, a data connection line is connected to multiple data lines through multiple switch transistors. This setting may cause the data line to leak electricity through the switch transistors, thereby affecting the display effect.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Utility Model Content

[0004] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes:

[0005] A plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect;

[0006] a plurality of data lines, wherein the data lines are connected to a plurality of the pixel driving circuits distributed in the second direction;

[0007] Source driver circuit;

[0008] a plurality of data connection lines, one end of each of the data connection lines being connected to the source driving circuit, and the other end of each of the data connection lines being connected to the plurality of data lines, wherein the source driving circuit is used to provide data signals to the plurality of data lines through the data connection lines;

[0009] a plurality of gate lines, wherein the gate lines are connected to a plurality of the pixel driving circuits distributed in the first direction;

[0010] A gate driving circuit, providing a gate driving signal to the pixel driving circuit through the gate line;

[0011] Wherein, the plurality of data lines form a plurality of data line groups, the data line groups include the plurality of data lines, and the plurality of data lines connected to the same data connection line are located in different data line groups;

[0012] The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to perform time-sharing scanning, and the scanning of the pixel driving circuit includes writing the data signal into the pixel driving circuit.

[0013] In an exemplary embodiment of the present disclosure, the plurality of gate lines include a plurality of scanning gate lines, and the same scanning gate line is connected to at least some pixel driving circuits connected to different data line groups.

[0014] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes:

[0015] One or more switch circuits, the switch circuits are connected between two nodes, the switch circuits are also connected to the scan gate line, and the switch circuits are used to respond to the signal of the scan gate line to conduct the two nodes;

[0016] One or more control circuits are arranged corresponding to the switch circuits, the control circuits and the corresponding switch circuits are connected in series between the two nodes, the control circuits are connected to the control signal terminal, and the control circuits are used to respond to the signal of the control signal terminal to conduct the two nodes;

[0017] The pixel driving circuits connected to different data line groups are respectively connected to different control signal terminals.

[0018] In an exemplary embodiment of the present disclosure, the pixel driving circuits connected to the same data line group form a pixel driving circuit group, and the control signal terminal is used to output a conduction level when the pixel driving circuit connected thereto is in a scanning period, and the control signal terminal is used to output an off level when the pixel driving circuit group to which the pixel driving circuit connected thereto is located is in a non-scanning period.

[0019] In an exemplary embodiment of the present disclosure, the plurality of scanning gate lines include a first gate line, and the one or more switch circuits include:

[0020] A data writing circuit is connected to the data writing node, the data line, and the first gate line, and the data writing circuit is used to respond to the signal of the first gate line to connect the data writing node and the data line;

[0021] One or more control circuits include:

[0022] a first control circuit, wherein the first control circuit and the data writing circuit are connected in series between the data writing node and the data line, the first control circuit is also connected to a control signal terminal, and the first control circuit is used to respond to a signal at the control signal terminal to connect the data writing node and the data line;

[0023] The gate driving circuit is used for controlling the pixel driving circuits connected to different data line groups to write the data signal in time-sharing manner through the first gate line.

[0024] In an exemplary embodiment of the present disclosure, the display panel further includes a light emitting unit, and the pixel driving circuit further includes:

[0025] A driving transistor, wherein the driving transistor provides a driving current to the light emitting unit according to a gate voltage thereof;

[0026] The plurality of scanning gate lines include a reset signal line, and the one or more switch circuits include:

[0027] a first reset circuit connected to the reset signal line, the gate of the driving transistor, and the initial signal line, the first reset circuit being used to respond to a signal of the reset signal line to conduct the gate of the driving transistor and the initial signal line;

[0028] a second reset circuit connected to the reset signal line, the first electrode of the light emitting unit, and the initial signal line, the second reset circuit being used to respond to a signal of the reset signal line to conduct the first electrode of the light emitting unit and the initial signal line;

[0029] a compensation circuit connected to the first gate line, the gate of the driving transistor, and the second electrode of the driving transistor, the compensation circuit being used to respond to a signal of the first gate line to connect the gate of the driving transistor and the second electrode of the driving transistor;

[0030] One or more control circuits include:

[0031] a second control circuit, wherein the second control circuit and the first reset circuit are connected in series between the gate of the driving transistor and the initial signal line, and the second control circuit and the compensation circuit are connected in series between the gate of the driving transistor and the second electrode of the driving transistor, the second control circuit is also connected to the control signal terminal, and the second control circuit is used to respond to the signal of the control signal terminal to turn on the gate of the driving transistor and the second electrode of the driving transistor, and turn on the gate of the driving transistor and the initial signal line;

[0032] A third control circuit and the second reset circuit are connected in series between the first electrode of the light-emitting unit and the initial signal line, the third control circuit is also connected to the control signal terminal, and the third control circuit is used to respond to the signal of the control signal terminal to turn on the first electrode of the light-emitting unit and the initial signal line;

[0033] The scanning of the pixel driving circuit includes inputting the signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor, and the gate driving circuit is used to control the pixel driving circuits connected to different data line groups through the reset signal line to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-sharing manner.

[0034] In an exemplary embodiment of the present disclosure, the first electrode of the driving transistor forms the data writing node, and the data writing circuit includes:

[0035] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a gate electrode of the fourth transistor is connected to the first gate line;

[0036] The first control circuit comprises:

[0037] an eighth transistor, a first electrode connected to the second electrode of the fourth transistor, a second electrode connected to the data writing node, and a gate connected to the control signal terminal;

[0038] The first reset circuit comprises:

[0039] a first transistor, wherein a first electrode of the first transistor is connected to the initial signal line, and a gate of the first transistor is connected to the reset signal line;

[0040] The compensation circuit comprises:

[0041] a second transistor, a second electrode of which is connected to the second electrode of the driving transistor, and a gate of which is connected to the first gate line;

[0042] The second control circuit comprises:

[0043] a ninth transistor, wherein a first electrode is connected to the second electrode of the first transistor and the first electrode of the second transistor, a second electrode is connected to the gate of the driving transistor, and a gate is connected to the control signal terminal;

[0044] The second reset circuit comprises:

[0045] a seventh transistor, a first electrode connected to the initial signal line, and a gate connected to the reset signal line;

[0046] The third control circuit comprises:

[0047] A tenth transistor has a first electrode connected to the second electrode of the seventh transistor, a second electrode connected to the first electrode of the light-emitting unit, and a gate connected to the control signal terminal.

[0048] In an exemplary embodiment of the present disclosure, in the same pixel driving circuit, the initial signal line is multiplexed as the control signal terminal.

[0049] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes:

[0050] One or more switch circuits, wherein the control end of the switch circuit is connected to the scan gate line;

[0051] One or more gating circuits, the gating circuits and the switch circuits are arranged correspondingly, the switch circuits are connected to the scanning gate lines through the corresponding gating circuits, the gating circuits are also connected to the gating signal terminal, and the gating circuits are used to respond to the signal of the gating signal terminal to conduct the control terminal of the switch circuit and the scanning gate line;

[0052] The pixel driving circuits connected to different data line groups are respectively connected to different selection signal terminals.

[0053] In an exemplary embodiment of the present disclosure, the plurality of scanning gate lines include a first gate line, and the one or more switch circuits include:

[0054] A data writing circuit is connected to the data writing node, the data line and the first gate line, and the data writing circuit is used to respond to the signal of the first gate line to connect the data writing node and the data line;

[0055] One or more gating circuits include:

[0056] a first gating circuit, the data writing circuit is connected to the first gate line through the first gating circuit, and the first gating circuit is used to respond to the signal of the gating signal end to connect the data writing circuit and the first gate line;

[0057] The gate driving circuit is used for controlling the pixel driving circuits connected to different data line groups to write the data signal in time-sharing manner through the first gate line.

[0058] In an exemplary embodiment of the present disclosure, the display panel further includes a light emitting unit, and the pixel driving circuit further includes:

[0059] A driving transistor, wherein the driving transistor provides a driving current to the light emitting unit according to a gate voltage thereof;

[0060] The plurality of scanning gate lines include a reset signal line, and the one or more switch circuits include:

[0061] a first reset circuit connected to the reset signal line, the gate of the driving transistor, and the initial signal line, the first reset circuit being used to respond to a signal of the reset signal line to conduct the gate of the driving transistor and the initial signal line;

[0062] a second reset circuit connected to the reset signal line, the first electrode of the light emitting unit, and the initial signal line, the second reset circuit being used to respond to a signal of the reset signal line to conduct the first electrode of the light emitting unit and the initial signal line;

[0063] a compensation circuit connected between the gate electrode of the driving transistor and the second electrode of the driving transistor, the compensation circuit being connected to the first gate line through the first gating circuit, and the compensation circuit being used for responding to a signal of the first gate line to conduct the gate electrode of the driving transistor and the second electrode of the driving transistor;

[0064] One or more gating circuits include:

[0065] a second gating circuit, wherein the first reset circuit and the second reset circuit are connected to the reset signal line through the second gating circuit, and the second gating circuit is used for responding to the signal of the gating signal terminal to connect the reset signal line and the first reset circuit and the second reset circuit;

[0066] The scanning of the pixel driving circuit includes inputting an initial signal of the initial signal line to the first electrode of the light emitting unit and the gate of the driving transistor;

[0067] The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the initial signal of the initial signal line to the first electrode of the light emitting unit and the gate of the driving transistor in a time-sharing manner through the reset signal line.

[0068] In an exemplary embodiment of the present disclosure, the first electrode of the driving transistor forms the data writing node, and the data writing circuit includes:

[0069] a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor;

[0070] The compensation circuit comprises:

[0071] a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor;

[0072] The first gating circuit comprises:

[0073] an eighth transistor, a first electrode of which is connected to the first gate line, a second electrode of which is connected to the gate of the fourth transistor and the gate of the second transistor, and a gate of which is connected to the selection signal terminal;

[0074] The first reset circuit comprises:

[0075] a first transistor, wherein a first electrode of the first transistor is connected to the initial signal line, and a second electrode of the first transistor is connected to the gate of the driving transistor;

[0076] The second reset circuit comprises:

[0077] a seventh transistor, a first electrode of which is connected to the initial signal line, and a second electrode of which is connected to the first electrode of the light-emitting unit;

[0078] The second gating circuit comprises:

[0079] A tenth transistor has a first electrode connected to the reset signal line, a second electrode connected to the gate of the first transistor and the gate of the seventh transistor, and a gate connected to the selection signal terminal.

[0080] In an exemplary embodiment of the present disclosure, the plurality of gate lines include a plurality of scanning gate lines, the first direction is a row direction, a row of pixel driving circuits corresponds to a plurality of the same scanning gate lines, and among the plurality of the same scanning gate lines corresponding to a row of pixel driving circuits, the scanning gate lines are connected to the pixel driving circuits connected to the same data line group, and the pixel driving circuits connected to different data line groups are connected to different scanning gate lines.

[0081] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0082] A plurality of gating circuits, each row of the pixel driving circuits is provided with a plurality of the gating circuits corresponding to the pixel driving circuits in the same row, and the plurality of the gating circuits corresponding to the pixel driving circuits in the same row are provided in one-to-one correspondence with a plurality of the same scanning gate lines, and the plurality of the same scanning gate lines corresponding to a row of the pixel driving circuits are respectively connected to the same signal output terminal of the gate driving circuit through the gating circuits corresponding thereto;

[0083] The gating circuit is connected to the gating signal terminal, and is used for responding to the signal of the gating signal terminal to conduct the scanning gate line and the output terminal of the gate driving circuit;

[0084] The gating circuits corresponding to the pixel driving circuits connected to different data line groups are connected to different gating signal terminals.

[0085] In an exemplary embodiment of the present disclosure, the pixel driving circuits connected to the same data line group form a pixel driving circuit group, the selection signal terminal is used to output a conduction level when the pixel driving circuit connected thereto is in a scanning period, and the selection signal terminal is used to output an off level when the pixel driving circuit group to which the pixel driving circuit connected thereto belongs is in a non-scanning period.

[0086] In an exemplary embodiment of the present disclosure, the gate driving circuit includes multiple sub-gate driving circuits, and multiple scanning gate lines of the same type corresponding to the same row of pixel driving circuits are respectively arranged corresponding to the multiple sub-gate driving circuits, and the multiple sub-gate driving circuits are respectively used to scan the pixel driving circuits connected thereto at different time periods.

[0087] In an exemplary embodiment of the present disclosure, the second direction is a column direction, the display panel includes a plurality of pixel units, and the pixel unit includes a plurality of pixel driving circuits adjacent to each other in the first direction;

[0088] The data line group is connected to a plurality of columns of pixel units.

[0089] In an exemplary embodiment of the present disclosure, the plurality of data lines form two data line groups, one data line group is connected to the pixel units in odd columns, and the other data line group is connected to the pixel units in even columns.

[0090] In an exemplary embodiment of the present disclosure, the data connection line is directly connected to the data line.

[0091] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0092] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0094] Figure 1 It is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed in the present invention;

[0095] Figure 2 for Figure 1 A timing diagram of each node in a driving method of the pixel driving circuit shown;

[0096] Figure 3 A schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0097] Figure 4 A schematic diagram of the connection structure between a source driving circuit and a data line in a display panel;

[0098] Figure 5 for Figure 4 The timing diagram of each node in a driving method of the display panel is shown;

[0099] Figure 6 A schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0100] Figure 7 for Figure 6 A schematic diagram of the structure of a pixel driving circuit in the display panel shown;

[0101] Figure 8 for Figure 6 The timing diagram of each node in a driving method of the display panel is shown;

[0102] Fig. 9 for Figure 6 A schematic structural diagram of a pixel driving circuit in another exemplary embodiment of a display panel shown;

[0103] Fig.10 for Figure 6 The timing diagram of each node in a driving method of the display panel is shown;

[0104] Fig.11 It is a structural schematic diagram of another exemplary embodiment of the display panel disclosed in the present invention;

[0105] Fig.12 for Fig.11 The timing diagram of each node in a driving method of the display panel is shown;

[0106] Fig.13 It is a structural schematic diagram of a gate driving circuit in an exemplary embodiment of a display panel disclosed in the present invention;

[0107] Fig.14 It is a structural schematic diagram of another exemplary embodiment of the display panel disclosed in the present invention;

[0108] Fig.15 for Fig.14 A schematic structural diagram of a gate driving circuit in an exemplary embodiment of a display panel is shown;

[0109] Fig.16 for Fig.14 FIG. 1 is a schematic structural diagram of a gate driving circuit in another exemplary embodiment of a display panel. DETAILED DESCRIPTION

[0110] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0111] The terms "a", "an", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to indicate an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0112] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance; the term "plurality" refers to two or more; the term "and / or" includes any and all combinations of one or more associated listed items. In particular, reference to "the / the" object or "an" object is also intended to indicate one of a possible plurality of such objects.

[0113] Unless otherwise specified or explained, the terms "connection", "fixation", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0114] Further, in the description of the present disclosure, it should be understood that the directional words such as "upper", "lower", "inner", "outer" and the like described in the exemplary embodiments of the present disclosure are described at the angles shown in the accompanying drawings and should not be understood as limitations on the exemplary embodiments of the present disclosure. It should also be understood that, in the context, when it is mentioned that an element or feature is connected to one or more "upper", "lower", or "inner", "outer" of another element, it can not only be directly connected to the "upper", "lower", "inner", "outer" of another element or elements, but can also be indirectly connected to the "upper", "lower", "inner", "outer" of another element or elements through an intermediate element.

[0115] like Figure 1FIG. 1 is a schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Among them, the first electrode of the fourth transistor T4 is connected to the data line Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate line G1; the first electrode of the fifth transistor T5 is connected to the first power line VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal line EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate line G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, the gate is connected to the enable signal line EM, the first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, and the gate is connected to the reset signal line Re; the second electrode of the first transistor T1 is connected to the node N, the first electrode is connected to the initial signal line Vinit, and the gate is connected to the reset signal line Re; the first electrode of the capacitor C is connected to the node N, and the second electrode is connected to the first power line VDD. The pixel driving circuit can be connected to a light-emitting unit L, and the pixel driving circuit is used to drive the light-emitting unit L to emit light. The first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit L is connected to the second power supply terminal VSS. Among them, the first transistor T1 , the second transistor T2 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be P-type transistors.

[0116] like Figure 2 As shown, Figure 1 The timing diagram of each node in a driving method of the pixel driving circuit shown in the figure, wherein EM represents the timing diagram of the enable signal line, Re represents the timing diagram of the reset signal line, and G1 represents the timing diagram of the first gate line.

[0117] The pixel driving circuit driving method may include a reset phase t1, a data writing phase t2, and a light emitting phase t3. In the reset phase, the reset signal line Re outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal line Vinit inputs an initial signal to the gate of the driving transistor T3 and the first electrode of the light emitting unit. In the data writing phase, the first gate line G1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and the data line Da outputs a data signal to write a compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. Light emitting phase: the enable signal line EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current I of the driving transistor in the pixel driving circuit of the present disclosure is (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Wherein, I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.

[0118] like Figure 3As shown, it is a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure. The display panel may include a timing controller, a source driving circuit, a gate driving circuit and a pixel array, the timing controller is respectively connected to the source driving circuit and the gate driving circuit, and the source driving circuit is respectively connected to a plurality of data lines (Da1 to Dan). The gate driving circuit includes: a scanning driving circuit and a light-emitting driving circuit. The scanning driving circuit is respectively connected to a plurality of scanning gate lines (S1 to Sm), and the light-emitting driving circuit is respectively connected to a plurality of enable signal lines (E1 to Eo). The scanning gate line and the enable signal line form a gate line. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a pixel driving circuit and a light-emitting unit connected to the pixel driving circuit, and the pixel driving circuit may be respectively connected to the scanning gate line, the enable signal line and the data line. In an exemplary embodiment, the timing controller may provide the grayscale value and control signal suitable for the specification of the source driving circuit to the source driving circuit, may provide the clock signal, scanning start signal, etc. suitable for the specification of the scanning driving circuit to the scanning driving circuit, and may provide the clock signal, emission stop signal, etc. suitable for the specification of the light-emitting driving circuit to the light-emitting driving circuit. The source driving circuit may generate the data voltage to be provided to the data lines Da1, Da2, Da3, ... and Dan using the grayscale value and control signal received from the timing controller. For example, the source driving circuit may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data lines Da1 to Dan in units of pixel rows, and n may be a natural number. The scanning driving circuit may generate the scanning signal to be provided to the scanning gate lines S1, S2, S3, ... and Sm by receiving the clock signal, scanning start signal, etc. from the timing controller. For example, the scanning driving circuit may sequentially provide the scanning signal with the on-level pulse to the scanning gate lines S1 to Sm. For example, the scan drive circuit may be constructed in the form of a shift register, and may generate a scan signal by sequentially transmitting a scan start signal provided in the form of a conduction level pulse to a next level circuit under the control of a clock signal, and m may be a natural number. The light-emitting drive circuit may generate an emission signal to be provided to enable signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting drive circuit may sequentially provide an emission signal with a cut-off level pulse to enable signal lines E1 to Eo. For example, the light-emitting drive circuit may be constructed in the form of a shift register, and may generate an emission signal by sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next level circuit under the control of a clock signal, and o may be a natural number.

[0119] In related technologies, such as Figure 4As shown in FIG. 1 , it is a schematic diagram of the connection structure between the source driving circuit and the data line in a display panel. A data output terminal of the source driving circuit can be connected to two data lines Da through a data connection line DL, wherein a data connection line DL is connected to different data lines Da through switch transistors Tx1 and Tx2 respectively, the gate of the switch transistor Tx1 is connected to the first selection signal terminal MUX1, and the gate of the switch transistor Tx2 is connected to the second selection signal terminal MUX2. Figure 5 As shown, Figure 4 The timing diagram of each node in a driving method of the display panel shown in the figure. Among them, EM represents the timing diagram of the enable signal line in the pixel driving circuit, Re is the timing diagram of the reset signal line in the pixel driving circuit, G1 is the timing diagram of the first gate line in the pixel driving circuit, MUX1 is the timing diagram of the first selection signal terminal, and MUX2 is the timing diagram of the second selection signal terminal. After the reset stage t1 of the pixel driving circuit and before the data writing stage t2, the first selection signal terminal MUX1 and the second selection signal terminal MUX2 turn on the switching transistors Tx1 and Tx2 in sequence, and the source driving circuit inputs the data signal to the data line Da connected to the switching transistor Tx1 in the first time period ta, and then inputs the data signal to the data line Da connected to the switching transistor Tx2 in the second time period tb, thereby realizing data writing of all data lines. This setting can not only save the number of source driving circuits, but also facilitate the setting of data connection lines DL.

[0120] However, if Figure 5 As shown, the data writing phase t2 of the pixel driving circuit needs to be performed after the first period ta and the second period tb. Due to the off leakage current of the switching transistor, in the second period tb, the data signal on the data line Da will leak through the switching transistor Tx1, resulting in display abnormalities such as vertical lines on the display panel.

[0121] Based on this, this exemplary embodiment provides a display panel, wherein the display panel includes: a plurality of pixel driving circuits, a plurality of data lines, a source driving circuit, a plurality of data connection lines, a plurality of gate lines, and a gate driving circuit. The plurality of pixel driving circuits are arrayed along a first direction and a second direction, and the first direction and the second direction intersect; the data line connects the plurality of pixel driving circuits distributed in the second direction; one end of the data connection line connects the source driving circuit, and the other end of the data connection line connects the plurality of data lines, and the source driving circuit is used to provide data signals to the plurality of data lines through the data connection line; the gate line connects the plurality of pixel driving circuits distributed in the first direction; the gate driving circuit provides a gate driving signal to the pixel driving circuit through the gate line; wherein the plurality of data lines form a plurality of data line groups, the data line group includes the plurality of data lines, and the plurality of data lines connected to the same data connection line are located in different data line groups; the gate driving circuit is used to control the pixel driving circuits connected to different data line groups to perform time-sharing scanning, and the scanning of the pixel driving circuit includes writing the data signal to the pixel driving circuit.

[0122] In this exemplary embodiment, the gate driving circuit performs time-sharing scanning on the pixel driving circuits connected to different data line groups, that is, after the gate driving circuit scans the pixel driving circuits connected to one group of data line groups, it scans the pixel driving circuits connected to another group of data line groups. This setting can make the source driving circuit provide data signals to the data lines synchronously with the pixel driving circuit writing data, thereby improving the above-mentioned data line leakage problem.

[0123] like Figure 6 , which is a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure. R represents a pixel driving circuit for driving a red light-emitting unit, G represents a pixel driving circuit for driving a green light-emitting unit, and B represents a pixel driving circuit for driving a blue light-emitting unit. The first direction X may be a row direction, and the second direction Y may be a column direction. Adjacent pixel driving circuits R, G, and B in the first direction X form a pixel unit Pix. Figure 6 As shown, the plurality of data lines Da form two data line groups: a first data line group Daz1 and a second data line group Daz2. The pixel units Pix in odd columns are connected to the first data line group Daz1, and the pixel units in even columns are connected to the second data line group Daz2.

[0124] like Figure 6 As shown, the plurality of gate lines include a plurality of scanning gate lines Gs, and the same scanning gate line Gs at least connects pixel driving circuits connected to some different data line groups. For example, the scanning gate line Gs connects all pixel driving circuits in the same row.

[0125] like Figure 7 As shown, Figure 6 The schematic diagram of the structure of the pixel driving circuit in the display panel is shown. The pixel driving circuit is used to drive the light-emitting unit L in the display panel. The pixel driving circuit includes: a driving transistor T3, a capacitor C, a plurality of switching circuits CT, and a light-emitting control circuit 5. The light-emitting control circuit 5 is connected to the first power line VDD, the first electrode of the driving transistor T3, the enable signal line EM, the first electrode of the light-emitting unit, and the second electrode of the driving transistor T3. The light-emitting control circuit 5 is used to respond to the signal of the enable signal line EM to connect the first power line VDD and the first electrode of the driving transistor, and to connect the second electrode of the driving transistor and the first electrode of the light-emitting unit. The capacitor C is connected between the first power line VDD and the gate of the driving transistor T3. The switching circuit CT is connected between two nodes, and the switching circuit CT is also connected to the scanning gate line Gs. The switching circuit CT is used to respond to the signal of the scanning gate line Gs to turn on the two nodes. Figure 7 As shown, the pixel driving circuit also includes: a plurality of control circuits KT, the control circuits KT and the switch circuits CT are arranged correspondingly, the control circuits KT and the corresponding switch circuits CT are connected in series between the two nodes, the control circuit KT is connected to the control signal terminal CK, and the control circuit KT is used to respond to the signal of the control signal terminal CK to turn on the two nodes; wherein the pixel driving circuits connected to different data line groups are respectively connected to different control signal terminals.

[0126] like Figure 7 As shown, the multiple switch circuits CT include: a data writing circuit 1, a first reset circuit 2, a second reset circuit 3, and a compensation circuit 4, and the multiple scanning gate lines Gs include a reset signal line and a first gate line G1. The data writing circuit 1 is connected to the data line Da, the first electrode of the driving transistor T3, and the first gate line G1. The data writing circuit 1 is used to respond to the signal of the first gate line G1 to conduct the data line Da and the first electrode of the driving transistor T3. The first reset circuit 2 is connected to the reset signal line Re, the gate of the driving transistor T3, and the initial signal line Vinit. The first reset circuit 2 is used to respond to the signal of the reset signal line Re to connect the initial signal line Vinit and the gate of the driving transistor T3. The second reset circuit 3 is connected to the first electrode of the light-emitting unit, the initial signal line Vinit, and the reset signal line Re. The second reset circuit 3 is used to respond to the signal of the reset signal line Re to connect the initial signal line Vinit and the first electrode of the light-emitting unit. The compensation circuit 4 is connected to the gate of the driving transistor T3, the second electrode of the driving transistor, and the first gate line G1. The compensation circuit 4 is used to respond to the signal of the first gate line G1 to connect the gate and the second electrode of the driving transistor.

[0127] like Figure 7As shown, the multiple control circuits KT include: a first control circuit KT1, a second control circuit KT2, and a third control circuit KT3. The first control circuit KT1 and the data writing circuit 1 are connected in series between the first electrode of the driving transistor T3 and the data line Da, and the first control circuit KT1 is also connected to the control signal terminal CK. The first control circuit KT1 is used to respond to the signal of the control signal terminal CK to connect the first electrode of the driving transistor T3 and the data line Da. The second control circuit KT2 and the first reset circuit 2 are connected in series between the gate of the driving transistor T3 and the initial signal line Vinit, and the second control circuit KT2 and the compensation circuit 4 are connected in series between the gate of the driving transistor and the second electrode of the driving transistor. The second control circuit KT2 is also connected to the control signal terminal CK, and the second control circuit KT2 is used to respond to the signal of the control signal terminal CK to turn on the gate of the driving transistor T3 and the second electrode of the driving transistor, and turn on the gate of the driving transistor and the initial signal line Vinit. The third control circuit KT3 and the second reset circuit 3 are connected in series between the first electrode of the light-emitting unit L and the initial signal line Vinit. The third control circuit KT3 is also connected to the control signal terminal CK. The third control circuit KT3 is used to respond to the signal of the control signal terminal CK to turn on the first electrode of the light-emitting unit L and the initial signal line Vinit.

[0128] like Figure 7As shown, the data writing circuit 1 includes: a fourth transistor T4, the first electrode of the fourth transistor T4 is connected to the data line, and the gate is connected to the first gate line; the first control circuit KT1 includes: an eighth transistor T8,: the first electrode of the eighth transistor T8 is connected to the second electrode of the fourth transistor, the second electrode is connected to the data writing node, and the gate is connected to the control signal terminal; the first reset circuit 2 includes: a first transistor T1, the first electrode of the first transistor T1 is connected to the initial signal line, and the gate is connected to the reset signal line; the compensation circuit 4 includes: a second transistor T2, the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor, and the gate is connected to the first gate line; The second control circuit KT2 includes: a ninth transistor T9, the first electrode of the ninth transistor T9 is connected to the second electrode of the first transistor T1 and the first electrode of the second transistor T2, the second electrode is connected to the gate of the driving transistor T3, and the gate is connected to the control signal terminal CK; the second reset circuit 3 includes: a seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, and the gate is connected to the reset signal line Re; the third control circuit KT3 includes: a tenth transistor T10, the first electrode of the tenth transistor T10 is connected to the second electrode of the seventh transistor T7, the second electrode is connected to the first electrode of the light-emitting unit L, and the gate is connected to the control signal terminal CK. The light-emitting control circuit 5 includes: a fifth transistor T5 and a sixth transistor T6, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal line EM, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the first electrode of the light-emitting unit L, and the gate is connected to the enable signal line EM. In this exemplary embodiment, the first transistor T1 , the second transistor T2 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , the ninth transistor T9 , and the tenth transistor T10 may be P-type transistors.

[0129] It should be understood that in other exemplary embodiments, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may also be N-type transistors.

[0130] In this exemplary embodiment, the pixel driving circuits connected to the same data line group form a pixel driving circuit group, and the control signal terminal CK is used to output a conduction level when the pixel driving circuit connected thereto is in a scanning period. For example, the control signal terminal CK is used to output a conduction level when the pixel driving circuit group to which the pixel driving circuit connected thereto is located is in a scanning period, and the control signal terminal is used to output an off level when the pixel driving circuit group to which the pixel driving circuit connected thereto is located is in a non-scanning period. It should be noted that the scanning of the pixel driving circuit includes Figure 2 The reset phase and data writing phase shown. The off level represents the level of turning off the target circuit, and the on level represents the level of turning on the target circuit. Accordingly, the gate driving circuit can be used to control the pixel driving circuits connected to different data line groups through the reset signal line to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-sharing manner, and the gate driving circuit can be used to control the pixel driving circuits connected to different data line groups through the first gate line to write the data signal in a time-sharing manner.

[0131] For example, Figure 8 As shown, Figure 6 The timing diagram of each node in a driving method of the display panel is shown. Among them, CK1 represents the timing diagram of the control signal terminal connected to the pixel driving circuit connected to the first data line group Daz1, and CK2 represents the timing diagram of the control signal terminal connected to the pixel driving circuit connected to the second data line group Daz2.

[0132] In the first half of a frame T, the control signal end connected to the odd-numbered pixel units connected to the first data line group Daz1 outputs a low level, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 in the odd-numbered pixel units are turned on, the data connection line DL outputs a data signal through the data signal line in the first data line group Daz1, and the gate drive circuit drives the odd-numbered pixel units row by row through the reset signal line Re and the first gate line G1. At the same time, the control signal end connected to the even-numbered pixel units connected to the second data line group Daz2 outputs a high level, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 in the even-numbered pixel units are turned off, and the even-numbered pixel units are not scanned, thereby maintaining the state of the previous frame.

[0133] In the second half of a frame T, the control signal end connected to the even-numbered column pixel unit connected to the second data line group Daz2 outputs a low level, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 in the even-numbered column pixel unit are turned on, the data connection line DL outputs a data signal through the data signal line in the second data line group Daz2, and the gate drive circuit drives the even-numbered column pixel unit row by row through the reset signal line Re and the first gate line G1. At the same time, the control signal end connected to the odd-numbered column pixel unit connected to the first data line group Daz1 outputs a high level, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 in the odd-numbered column pixel unit are turned off, and the odd-numbered column pixel unit is not scanned, thereby maintaining the state of the previous frame.

[0134] like Figure 7 As shown, the initial signal for resetting the gate of the driving transistor T3 and the first electrode of the light emitting unit L is a low level signal. Accordingly, in the same pixel driving circuit, the initial signal line Vinit can be multiplexed as the control signal terminal CK.

[0135] In this exemplary embodiment, the signal line for connecting the control signal terminal can extend in the column direction, so that the odd-numbered column pixel units and the even-numbered column pixel units can be connected to different control signal terminals. In addition, the signal line for connecting the control signal terminal can also extend in the row direction. Accordingly, each row of pixel driving circuits can be provided with two signal lines for connecting the control signal terminal, and the two signal lines are respectively connected to the control signal terminals of the odd-numbered column pixel units and the even-numbered column pixel units.

[0136] like Fig. 9 As shown, Figure 6 A schematic diagram of the structure of a pixel driving circuit in another exemplary embodiment of a display panel is shown. The pixel driving circuit is used to drive a light-emitting unit L in a display panel. The pixel driving circuit includes: a driving transistor T3, a capacitor C, a plurality of switch circuits CT, and a light-emitting control circuit 5. The light-emitting control circuit 5 is connected to a first power line VDD, a first electrode of the driving transistor T3, an enable signal line EM, a first electrode of the light-emitting unit, and a second electrode of the driving transistor T3. The light-emitting control circuit 5 is used to respond to a signal of the enable signal line EM to connect the first power line VDD and the first electrode of the driving transistor, and to connect the second electrode of the driving transistor and the first electrode of the light-emitting unit. The capacitor C is connected between the first power line VDD and the gate of the driving transistor T3. The control end of the switch circuit CT is connected to the scanning gate line. Fig. 9As shown, the pixel driving circuit also includes a plurality of gating circuits XT, the gating circuits XT and the switching circuits CT are arranged correspondingly, the switching circuits CT are connected to the scanning gate lines via the gating circuits XT corresponding thereto, the gating circuits XT are also connected to the gating signal terminal MUX, and the gating circuits XT are used to respond to the signal of the gating signal terminal MUX to turn on the control terminal of the switching circuit CT and the scanning gate line; wherein the pixel driving circuits connected to different data line groups are respectively connected to different gating signal terminals.

[0137] like Fig. 9 As shown, the plurality of scanning gate lines Gs include a reset signal line and a first gate line G1, and the plurality of switch circuits CT include: a data writing circuit 1, a first reset circuit 2, a second reset circuit 3, and a compensation circuit 4. The data writing circuit 1 is connected to the data line Da, the first electrode of the driving transistor T3, and the first gate line G1, and the data writing circuit 1 is used to respond to the signal of the first gate line G1 to conduct the data line Da and the first electrode of the driving transistor T3. The first reset circuit 2 is connected to the reset signal line Re, the gate of the driving transistor T3, and the initial signal line Vinit, and the first reset circuit 2 is used to respond to the signal of the reset signal line Re to connect the initial signal line Vinit and the gate of the driving transistor T3. The second reset circuit 3 is connected to the first electrode of the light-emitting unit, the initial signal line Vinit, and the reset signal line Re, and the second reset circuit 3 is used to respond to the signal of the reset signal line Re to connect the initial signal line Vinit and the first electrode of the light-emitting unit. The compensation circuit 4 is connected to the gate of the driving transistor T3, the second electrode of the driving transistor, and the first gate line G1, and the compensation circuit 4 is used to respond to the signal of the first gate line G1 to connect the gate and the second electrode of the driving transistor.

[0138] like Fig. 9 As shown, the plurality of gating circuits include a first gating circuit XT1 and a second gating circuit XT2. The data writing circuit 1 and the compensation circuit 4 are connected to the first gate line G1 through the first gating circuit XT1, and the first gating circuit XT1 is used to respond to the signal of the gating signal terminal MUX to connect the first gate line G1 and the data writing circuit 1 and the compensation circuit 4; the first reset circuit 2 and the second reset circuit 3 are connected to the reset signal line Re through the second gating circuit XT2, and the second gating circuit XT2 is used to respond to the signal of the gating signal terminal MUX to connect the reset signal line Re and the first reset circuit 2 and the second reset circuit 3.

[0139] like Fig. 9As shown, the data writing circuit 1 includes: a fourth transistor T4, the first electrode of the fourth transistor T4 is connected to the data line; the compensation circuit 4 includes: a second transistor T2, the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3, and the second electrode is connected to the second electrode of the driving transistor T3; the first gating circuit includes: an eighth transistor T8, the first electrode of the eighth transistor T8 is connected to the first gate line G1, the second electrode is connected to the gate of the fourth transistor T4 and the gate of the second transistor T2, and the gate is connected to the gating signal terminal MUX; the first reset circuit 2 includes: a first transistor T1, the first electrode of the first transistor T1 is connected to the initial signal line Vinit, and the second electrode is connected to the gate of the driving transistor T3; the second reset circuit includes: a seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, and the second electrode is connected to the first electrode of the light-emitting unit L; the second gating circuit includes: a tenth transistor T10, the first electrode of the tenth transistor T10 is connected to the reset signal line Re, the second electrode is connected to the gate of the first transistor T1 and the gate of the seventh transistor T7, and the gate is connected to the gating signal terminal MUX. In the present exemplary embodiment, the first transistor T1 , the second transistor T2 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , the seventh transistor T7 , the eighth transistor T8 , and the tenth transistor T10 may be P-type transistors.

[0140] It should be understood that in other exemplary embodiments, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 may also be N-type transistors.

[0141] In this exemplary embodiment, the pixel driving circuits connected to the same data line group form a pixel driving circuit group, and the selection signal terminal MUX is used to output a conduction level when the pixel driving circuit connected thereto is in a scanning period. For example, the selection signal terminal MUX is used to output a conduction level when the pixel driving circuit group to which the pixel driving circuit connected thereto is located is in a scanning period, and the selection signal terminal MUX is used to output an off level when the pixel driving circuit group to which the pixel driving circuit connected thereto is located is in a non-scanning period. The scanning of the pixel driving circuit includes Figure 2The reset phase and data writing phase shown. Accordingly, the gate driving circuit can be used to control the pixel driving circuits connected to different data line groups through the reset signal line to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-sharing manner, and the gate driving circuit can be used to control the pixel driving circuits connected to different data line groups through the first gate line to write the data signal in a time-sharing manner.

[0142] For example, Fig.10 As shown, Figure 6 The timing diagram of each node in a driving method of the display panel is shown. Among them, MUX1 represents the timing diagram of the strobe signal terminal connected to the pixel driving circuit connected to the first data line group Daz1, and MUX2 represents the timing diagram of the strobe signal terminal connected to the pixel driving circuit connected to the second data line group Daz2.

[0143] In the first half of a frame T, the strobe signal terminal connected to the odd-numbered pixel units connected to the first data line group Daz1 outputs a low level, the eighth transistor T8 and the tenth transistor T10 in the odd-numbered pixel units are turned on, the data link line DL outputs a data signal through the data signal line in the first data line group Daz1, and the gate drive circuit drives the odd-numbered pixel units row by row through the reset signal line Re and the first gate line G1. At the same time, the strobe signal terminal connected to the even-numbered pixel units connected to the second data line group Daz2 outputs a high level, the eighth transistor T8 and the tenth transistor T10 in the even-numbered pixel units are turned off, and the even-numbered pixel units are not scanned, thereby maintaining the state of the previous frame.

[0144] In the second half of a frame T, the strobe signal end connected to the even-numbered column pixel unit connected to the second data line group Daz2 outputs a low level, the eighth transistor T8 and the tenth transistor T10 in the even-numbered column pixel unit are turned on, the data link line DL outputs a data signal through the data signal line in the second data line group Daz2, and the gate drive circuit drives the even-numbered column pixel unit row by row through the reset signal line Re and the first gate line G1. At the same time, the strobe signal end connected to the odd-numbered column pixel unit connected to the first data line group Daz1 outputs a high level, the eighth transistor T8 and the tenth transistor T10 in the odd-numbered column pixel unit are turned off, and the odd-numbered column pixel unit is not scanned, thereby maintaining the state of the previous frame.

[0145] In this exemplary embodiment, the signal line for connecting the strobe signal terminal can extend in the column direction, so that the odd-numbered column pixel units and the even-numbered column pixel units can be connected to different strobe signal terminals. In addition, the signal line for connecting the strobe signal terminal can also extend in the row direction. Accordingly, each row of pixel driving circuits can be provided with two signal lines for connecting the strobe signal terminal, and the two signal lines are respectively connected to the strobe signal terminals of the odd-numbered column pixel units and the even-numbered column pixel units.

[0146] like Figure 7 , 9 As shown, the data write node where the data write circuit 1 writes the data signal is the first electrode of the driving transistor. It should be understood that in other exemplary embodiments, the pixel driving circuit can also be other structures, and accordingly, the data write node where the data write circuit 1 writes the data signal can also be located at other positions. In addition, in pixel driving circuits of other structures, the switch circuit CT in the pixel driving circuit can also have other connection relationships with the driving transistor. In the same pixel driving circuit, the number of control circuits can be set according to the number of switch circuits, and the number of gating circuits can be set according to the number of scanning gate lines.

[0147] like Fig.11 As shown, it is a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed in the present invention. Adjacent pixel driving circuits R, G, and B in a first direction X form a pixel unit Pix. A plurality of data lines Da form two data line groups: a first data line group Daz1 and a second data line group Daz2. The pixel units Pix in odd columns are connected to the first data line group Daz1, and the pixel units in even columns are connected to the second data line group Daz2. Two scanning gate lines Gs of the same type are arranged corresponding to a row of pixel driving circuits, one gate line is connected to the pixel driving circuit connected to the first data line group Daz1, and the other gate line is connected to the pixel driving circuit connected to the second data line group Daz2.

[0148] It should be noted that the same type of scanning gate lines refers to scanning gate lines that provide gate drive signals to the same type of transistors in each pixel driving circuit. For example, the first gate line G1 is a scanning gate line, and the reset signal line Re is a scanning gate line. In this exemplary embodiment, each row of pixel driving circuits can be correspondingly provided with two reset signal lines Re and two first gate lines G1.

[0149] like Fig.11As shown, the display panel further includes: a plurality of gating circuits XT, two of which are arranged corresponding to each row of the pixel driving circuits: a first gating circuit XT1 and a second gating circuit XT2, which are arranged one-to-one with the two gating circuits corresponding to the same row of pixel driving circuits and two scanning gate lines of the same type, and the two scanning gate lines Gs of the same type corresponding to a row of pixel driving circuits are respectively connected to the same signal output terminal of the gate driving circuit through the two gating circuits corresponding thereto; the gating circuit XT is connected to the gating signal terminal MUX, and the gating circuit XT is used to respond to the signal of the gating signal terminal MUX to conduct the scanning gate line Gs and the output terminal of the gate driving circuit; wherein, the gating circuits XT corresponding to the pixel driving circuits connected to different data line groups are connected to different gating signal terminals MUX. For example, the first gating circuit XT1 corresponding to the pixel driving circuit connected to the first data line group Daz1 is connected to the first gating signal terminal MUX1, and the second gating circuit XT2 corresponding to the pixel driving circuit connected to the second data line group Daz2 is connected to the second gating signal terminal MUX2.

[0150] In this exemplary embodiment, the gate circuit XT may be integrated into the border area of ​​the display panel.

[0151] In this exemplary embodiment, the first gating circuit XT1 may include an eighth transistor T8, the gate of the eighth transistor T8 is connected to the first gating signal terminal MUX1, the first electrode is connected to the output terminal of the gate driving circuit, and the second electrode is connected to the corresponding scanning gate line Gs. The second gating circuit XT2 includes a ninth transistor T9, the gate of the ninth transistor T9 is connected to the second gating signal terminal MUX2, the first electrode is connected to the output terminal of the gate driving circuit, and the second electrode is connected to the corresponding scanning gate line Gs. The eighth transistor T8 and the ninth transistor T9 may be P-type transistors.

[0152] like Fig.12 As shown, Fig.11 The timing diagram of each node in a driving method of the display panel is shown, wherein MUX1 represents the timing diagram of the first selection signal terminal, and MUX2 represents the timing diagram of the second selection signal terminal.

[0153] In the first half of a frame T, the first selection signal terminal MUX1 outputs a low level, the first selection circuit XT1 connected to the odd-numbered column pixel unit is turned on, the data connection line DL outputs a data signal through the data signal line in the first data line group Daz1, and the gate driving circuit drives the odd-numbered column pixel unit row by row through the reset signal line Re and the first gate line G1 connected to the first selection circuit XT1. At the same time, the second selection signal terminal MUX2 outputs a high level, the second selection circuit XT2 connected to the even-numbered column pixel unit is turned off, and the even-numbered column pixel unit is not scanned, thereby maintaining the previous frame state.

[0154] In the second half of a frame T, the second selection signal terminal MUX2 outputs a low level, the second selection circuit XT2 connected to the even-numbered column pixel unit is turned on, the data connection line DL outputs a data signal through the data signal line in the second data line group Daz2, and the gate driving circuit drives the even-numbered column pixel unit row by row through the reset signal line Re and the first gate line G1 connected to the second selection circuit XT2. At the same time, the first selection signal terminal MUX1 outputs a high level, the first selection circuit XT1 connected to the odd-numbered column pixel unit is turned off, and the odd-numbered column pixel unit is not scanned, thereby maintaining the previous frame state.

[0155] It should be understood that in other exemplary embodiments, the display panel may include other numbers of data line groups, for example, the display panel may include n data line groups, and accordingly, a row of pixel driving circuits is provided with n same-type scanning gate lines Gs, and among the n same-type scanning gate lines Gs corresponding to a row of pixel driving circuits, the scanning gate lines Gs are connected to the pixel driving circuits connected to the same data line group, and the pixel driving circuits connected to different data line groups are connected to different scanning gate lines. n is a positive integer greater than or equal to 2. Accordingly, the display panel further includes: a plurality of gating circuits XT, n gating circuits are provided corresponding to each row of the pixel driving circuits, and the n gating circuits corresponding to the same row of pixel driving circuits and the n same-type scanning gate lines are provided one-to-one, and the n same-type scanning gate lines Gs corresponding to a row of pixel driving circuits are respectively connected to the same signal output terminal of the gate driving circuit through the n gating circuits XT corresponding thereto; wherein, the gating circuits corresponding to the pixel driving circuits connected to different data line groups are connected to different gating signal terminals. The pixel driving circuits connected to the same data line group form a pixel driving circuit group, and the strobe signal terminal can be used to output a conduction level when the pixel driving circuit connected thereto is in a scanning period, and the strobe signal terminal is used to output a shutdown level when the pixel driving circuit group to which the pixel driving circuit connected thereto belongs is in a non-scanning period. This setting can also realize time-sharing scanning of the display panel.

[0156] like Fig.13 FIG. 1 is a schematic diagram of a gate drive circuit in an exemplary embodiment of a display panel disclosed in the present invention. Figure 6-Figure 12 In the display panel shown, the gate driving circuit may include a plurality of cascaded shift register units GOA, and the output end OUT of the upper shift register unit is connected to the input end of the adjacent lower shift register unit, so that the output signal output by the upper shift register unit is used as the input signal of the lower shift register unit. It should be understood that in other exemplary embodiments, the output end of the upper shift register unit may also be connected to the input end of the alternate lower shift register unit.

[0157] In this exemplary embodiment, the reset signal line Re and the first gate line G1 can be connected to the same group of cascaded shift register units, and among the reset signal line Re and the first gate line G1 connected to the same row of pixel driving circuits, the reset signal line Re can be connected to the output end of the upper shift register unit, and the first gate line G1 can be connected to the output end of the lower shift register unit. It should be understood that in other exemplary embodiments, the gate driving circuit can also include two groups of cascaded shift register units, and the two groups of shift register units are respectively connected to the reset signal line Re and the first gate line G1.

[0158] In this exemplary embodiment, Fig.13 As shown, the input end of the first-stage shift register unit GOA is connected to the initialization signal end STV, and the initialization signal end STV inputs the initial signal to the first-stage shift register unit GOA, and the gate drive circuit starts to output the shift signal step by step. Figure 6-Figure 12 In the display panel shown, multiple initial signals can be output in time-sharing manner through the initialization signal terminal STV to realize the gate drive circuit to scan the pixel drive circuits connected to different data line groups in time-sharing manner. For example, in the first half of a frame, the initialization signal terminal STV outputs the initial signal, and the gate drive circuit scans the pixel units of the odd columns; in the second half of a frame, the initialization signal terminal STV outputs the initial signal again, and the gate drive circuit scans the pixel units of the even columns. In addition, there can be an interleaved period between the scanning periods of the pixel drive circuits connected to different data line groups, and the interleaved period can be the scanning duration of one or more pixel drive circuit rows. The interleaved period can be realized by the timing of the initial signal, and the interleaved period can be used to avoid confusion in the output of the gate drive circuit.

[0159] It should be understood that in other exemplary embodiments, the shift register unit can also achieve the opposite scanning direction of the odd-numbered column pixel units and the even-numbered column pixel units through its internal structure setting. For example, the odd-numbered column pixel units are scanned from the first row to the last row, and the even-numbered column pixel units are reversely scanned from the last row to the first row, and the input signal of the shift register unit corresponding to the last row of the even-numbered column pixel units can be provided by the output signal of the shift register unit corresponding to the last row of the odd-numbered column pixel units. In addition, there can be an interleaved period between the scanning periods of the pixel driving circuits connected to different data line groups, and the interleaved period can be the scanning duration of one or more pixel driving circuit rows, and the interleaved period can be realized by the timing of the clock signal end in the shift register unit.

[0160] like Fig.14As shown, it is a schematic diagram of the structure of another exemplary embodiment of the display panel of the present disclosure, wherein each row of pixel driving circuits is correspondingly provided with two scanning gate lines Gs of the same type, and the gate driving circuit includes two sub-gate driving circuits, and the two scanning gate lines Gs of the same type corresponding to the pixel driving circuits of the same row are respectively provided corresponding to the two sub-gate driving circuits, and the plurality of sub-gate driving circuits are respectively used to scan the pixel driving circuits connected thereto at different time periods. For example, one sub-gate driving circuit scans the odd-numbered columns of pixel units in the first half of a frame, and the other sub-gate driving circuit scans the even-numbered columns of pixel units in the second half of a frame.

[0161] like Fig.15 As shown, Fig.14 A schematic diagram of the structure of a gate driving circuit in an exemplary embodiment of a display panel is shown. The two sub-gate driving circuits include: a first sub-gate driving circuit Gd1 and a second sub-gate driving circuit Gd2. The first sub-gate driving circuit Gd1 and the second sub-gate driving circuit Gd2 are cascaded, wherein the output terminal OUT of the a-th level shift register unit GOA is connected to the input terminal of the a+b-th level shift register unit. a and b are positive integers greater than or equal to 1. The output terminal of the shift register unit is connected to the scanning gate line Gs. The first-stage shift register unit GOA of the first sub-gate driving circuit Gd1 receives the first initial signal STV1, and the first sub-gate driving circuit Gd1 can be used to scan the odd-numbered column pixel units. For example, the first sub-gate driving circuit Gd1 can provide a gate driving signal to the first gate line connected to the odd-numbered column pixel units; the first-stage shift register unit GOA of the second sub-gate driving circuit Gd2 receives the second initial signal STV2, and the second sub-gate driving circuit Gd2 can be used to scan the even-numbered column pixel units. For example, the second sub-gate driving circuit Gd2 can provide a gate driving signal to the first gate line connected to the even-numbered column pixel units.

[0162] like Fig.16 As shown, Fig.14 A schematic diagram of the structure of a gate driving circuit in another exemplary embodiment of a display panel is shown. The two sub-gate driving circuits include: a first sub-gate driving circuit Gd1 and a second sub-gate driving circuit Gd2. The output end of the last-stage shift register unit GOA in the first sub-gate driving circuit Gd1 is connected to the input end of the first-stage shift register unit in the second sub-gate driving circuit Gd2. The output end of the shift register unit is connected to the scanning gate line Gs. The first sub-gate driving circuit Gd1 can be used to scan odd-numbered column pixel units, for example, the first sub-gate driving circuit Gd1 can provide a gate driving signal to the first gate line connected to the odd-numbered column pixel units; the second sub-gate driving circuit Gd2 can be used to scan even-numbered column pixel units, for example, the second sub-gate driving circuit Gd2 can provide a gate driving signal to the first gate line connected to the even-numbered column pixel units.

[0163] It should be noted that Fig.13 , 15 16 only exemplarily illustrate some of the shift register units, and this exemplary embodiment does not limit the number of shift register units in the gate driving circuit. Figure 6 , 11 14 only exemplarily show part of the pixel driving circuits, and the present exemplary embodiment does not limit the number of pixel driving circuits.

[0164] In this exemplary embodiment, Figure 6 , 11 As shown in 14, the display panel includes a plurality of pixel units, and the pixel unit includes three pixel driving circuits R, G, and B adjacent to each other in the first direction; the data line group connects a plurality of columns of the pixel units. This setting can make the pixel driving circuits in the pixel unit scan synchronously, thereby avoiding the color deviation problem of the display panel. In this exemplary embodiment, the pixel units in the display panel are distributed in Real RGB mode. It should be understood that in other exemplary embodiments, the pixel units in the display panel can also be distributed in other ways, and accordingly, the pixel units can include other numbers of pixel unit circuits. For example, the pixel units in the display panel can be distributed in RGBG mode, and accordingly, the pixel units include four pixel driving circuits R, G, B, and G adjacent to each other in the first direction. In addition, it should be understood that in other exemplary embodiments, the pixel driving circuits located in the same pixel unit can also be connected to different data line groups.

[0165] In this exemplary embodiment, Figure 6 , 11 As shown in FIG. 14, the plurality of data lines form two data line groups: a first data line group Daz1 and a second data line group Daz2. The first data line group Daz1 is connected to the pixel units of the odd columns, and the second data line group Daz2 is connected to the pixel units of the even columns. This setting can make the pixel units of the odd columns and the pixel units of the even columns driven in a time-sharing manner, thereby avoiding the split screen phenomenon of the display panel.

[0166] In this exemplary embodiment, Figure 6 , 11 As shown in FIG. 14 , this exemplary embodiment controls the time-sharing scanning of the pixel driving circuits connected to different data line groups through the gate driving circuit. Accordingly, the data link line DL and the data line Da are directly connected, that is, no transistor is set between the data link line DL and the data line Da.

[0167] In this exemplary embodiment, the gate driving circuit includes a light-emitting driving circuit for providing the gate driving circuit to the enable signal line EM. The light-emitting driving circuit can also control the time-sharing scanning of the pixel driving circuits connected to different data line groups. Figure 6 , 11 In the embodiment shown in 14, the light-emitting driving circuit drives the odd-numbered columns of pixel units to scan row by row in the first half of a frame, and drives the even-numbered columns of pixel units to scan row by row in the second half of a frame. In the second half of a frame, even if the light-emitting driving circuit provides a gate driving signal to the even-numbered columns of pixel units, the odd-numbered columns of pixel units will only be briefly blacked out, thereby not affecting the overall display of the display panel. Of course, the light-emitting driving circuit may also be the same as Figure 6 , 11 14, by connecting a control circuit in series to the light-emitting control circuit in the pixel driving circuit, or by setting a gating circuit between the light-emitting control circuit and the enable signal line, or by setting a gating circuit between the light-emitting driving circuit and the enable signal line, or by setting two sub-light-emitting driving circuits, it is achieved that the gate driving signal provided by the light-emitting driving circuit to the pixel driving circuit group does not affect other pixel driving circuit groups.

[0168] In this exemplary embodiment, the display panel may be packaged by using COF (Chip On Film) technology, and the source driving circuit may be connected to the data line via a data connection line integrated on the chip on film.

[0169] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

[0170] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and embodiments are to be considered merely as exemplary, and the true scope and spirit of the present disclosure are indicated by the claims.

[0171] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel comprises: A plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect; a plurality of data lines, wherein the data lines are connected to a plurality of the pixel driving circuits distributed in the second direction; Source driver circuit; a plurality of data connection lines, one end of each of the data connection lines being connected to the source driving circuit, and the other end of each of the data connection lines being connected to the plurality of data lines, wherein the source driving circuit is used to provide data signals to the plurality of data lines through the data connection lines; a plurality of gate lines, wherein the gate lines are connected to a plurality of the pixel driving circuits distributed in the first direction; A gate driving circuit, providing a gate driving signal to the pixel driving circuit through the gate line; Wherein, the plurality of data lines form a plurality of data line groups, the data line groups include the plurality of data lines, and the plurality of data lines connected to the same data connection line are located in different data line groups; The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to perform time-sharing scanning, and the scanning of the pixel driving circuit includes writing the data signal into the pixel driving circuit.

2. The display panel according to claim 1, wherein: The plurality of gate lines include a plurality of scanning gate lines, and the same scanning gate line is connected to at least some pixel driving circuits connected to different data line groups.

3. The display panel according to claim 2, wherein: The pixel driving circuit comprises: One or more switch circuits, the switch circuits are connected between two nodes, the switch circuits are also connected to the scan gate line, and the switch circuits are used to respond to the signal of the scan gate line to conduct the two nodes; One or more control circuits are arranged corresponding to the switch circuits, the control circuits and the corresponding switch circuits are connected in series between the two nodes, the control circuits are connected to the control signal terminal, and the control circuits are used to respond to the signal of the control signal terminal to conduct the two nodes; The pixel driving circuits connected to different data line groups are respectively connected to different control signal terminals.

4. The display panel according to claim 3, wherein: The pixel driving circuits connected to the same data line group form a pixel driving circuit group, and the control signal end is used to output a conduction level when the pixel driving circuit connected to it is in a scanning period, and the control signal end is used to output an off level when the pixel driving circuit group to which the pixel driving circuit connected to it belongs is in a non-scanning period.

5. The display panel according to claim 3, wherein: The plurality of scanning gate lines include a first gate line, and the one or more switch circuits include: A data writing circuit is connected to the data writing node, the data line, and the first gate line, and the data writing circuit is used to respond to the signal of the first gate line to connect the data writing node and the data line; One or more control circuits include: a first control circuit, wherein the first control circuit and the data writing circuit are connected in series between the data writing node and the data line, the first control circuit is also connected to a control signal terminal, and the first control circuit is used to respond to a signal at the control signal terminal to connect the data writing node and the data line; The gate driving circuit is used for controlling the pixel driving circuits connected to different data line groups to write the data signal in time-sharing manner through the first gate line.

6. The display panel according to claim 5, wherein: The display panel further includes a light emitting unit, and the pixel driving circuit further includes: A driving transistor, wherein the driving transistor provides a driving current to the light emitting unit according to a gate voltage thereof; The plurality of scanning gate lines include a reset signal line, and the one or more switch circuits include: a first reset circuit connected to the reset signal line, the gate of the driving transistor, and the initial signal line, the first reset circuit being used to respond to a signal of the reset signal line to conduct the gate of the driving transistor and the initial signal line; a second reset circuit connected to the reset signal line, the first electrode of the light emitting unit, and the initial signal line, the second reset circuit being used to respond to a signal of the reset signal line to conduct the first electrode of the light emitting unit and the initial signal line; a compensation circuit connected to the first gate line, the gate of the driving transistor, and the second electrode of the driving transistor, the compensation circuit being used to respond to a signal of the first gate line to connect the gate of the driving transistor and the second electrode of the driving transistor; One or more control circuits include: a second control circuit, wherein the second control circuit and the first reset circuit are connected in series between the gate of the driving transistor and the initial signal line, and the second control circuit and the compensation circuit are connected in series between the gate of the driving transistor and the second electrode of the driving transistor, the second control circuit is also connected to the control signal terminal, and the second control circuit is used to respond to the signal of the control signal terminal to turn on the gate of the driving transistor and the second electrode of the driving transistor, and turn on the gate of the driving transistor and the initial signal line; A third control circuit and the second reset circuit are connected in series between the first electrode of the light-emitting unit and the initial signal line, the third control circuit is also connected to the control signal terminal, and the third control circuit is used to respond to the signal of the control signal terminal to turn on the first electrode of the light-emitting unit and the initial signal line; The scanning of the pixel driving circuit includes inputting the signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor, and the gate driving circuit is used to control the pixel driving circuits connected to different data line groups through the reset signal line to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-sharing manner.

7. The display panel according to claim 6, wherein: The first electrode of the driving transistor forms the data writing node, and the data writing circuit includes: a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a gate electrode of the fourth transistor is connected to the first gate line; The first control circuit comprises: an eighth transistor, a first electrode connected to the second electrode of the fourth transistor, a second electrode connected to the data writing node, and a gate connected to the control signal terminal; The first reset circuit comprises: a first transistor, wherein a first electrode of the first transistor is connected to the initial signal line, and a gate of the first transistor is connected to the reset signal line; The compensation circuit comprises: a second transistor, a second electrode of which is connected to the second electrode of the driving transistor, and a gate of which is connected to the first gate line; The second control circuit comprises: a ninth transistor, wherein a first electrode is connected to the second electrode of the first transistor and the first electrode of the second transistor, a second electrode is connected to the gate of the driving transistor, and a gate is connected to the control signal terminal; The second reset circuit comprises: a seventh transistor, a first electrode connected to the initial signal line, and a gate connected to the reset signal line; The third control circuit comprises: A tenth transistor has a first electrode connected to the second electrode of the seventh transistor, a second electrode connected to the first electrode of the light-emitting unit, and a gate connected to the control signal terminal.

8. The display panel according to claim 6, wherein: In the same pixel driving circuit, the initial signal line is multiplexed as the control signal terminal.

9. The display panel according to claim 2, wherein: The pixel driving circuit comprises: One or more switch circuits, wherein the control end of the switch circuit is connected to the scan gate line; One or more gating circuits, the gating circuits and the switch circuits are arranged correspondingly, the switch circuits are connected to the scanning gate lines through the corresponding gating circuits, the gating circuits are also connected to the gating signal terminal, and the gating circuits are used to respond to the signal of the gating signal terminal to conduct the control terminal of the switch circuit and the scanning gate line; The pixel driving circuits connected to different data line groups are respectively connected to different selection signal terminals.

10. The display panel according to claim 9, wherein: The plurality of scanning gate lines include a first gate line, and the one or more switch circuits include: A data writing circuit is connected to the data writing node, the data line and the first gate line, and the data writing circuit is used to respond to the signal of the first gate line to connect the data writing node and the data line; One or more gating circuits include: a first gating circuit, the data writing circuit is connected to the first gate line through the first gating circuit, and the first gating circuit is used to respond to the signal of the gating signal end to connect the data writing circuit and the first gate line; The gate driving circuit is used for controlling the pixel driving circuits connected to different data line groups to write the data signal in time-sharing manner through the first gate line.

11. The display panel according to claim 10, wherein: The display panel further includes a light emitting unit, and the pixel driving circuit further includes: A driving transistor, wherein the driving transistor provides a driving current to the light emitting unit according to a gate voltage thereof; The plurality of scanning gate lines include a reset signal line, and the one or more switch circuits include: a first reset circuit connected to the reset signal line, the gate of the driving transistor, and the initial signal line, the first reset circuit being used to respond to a signal of the reset signal line to conduct the gate of the driving transistor and the initial signal line; a second reset circuit connected to the reset signal line, the first electrode of the light emitting unit, and the initial signal line, the second reset circuit being used to respond to a signal of the reset signal line to conduct the first electrode of the light emitting unit and the initial signal line; a compensation circuit connected between the gate electrode of the driving transistor and the second electrode of the driving transistor, the compensation circuit being connected to the first gate line through the first gating circuit, and the compensation circuit being used for responding to a signal of the first gate line to conduct the gate electrode of the driving transistor and the second electrode of the driving transistor; One or more gating circuits include: a second gating circuit, wherein the first reset circuit and the second reset circuit are connected to the reset signal line through the second gating circuit, and the second gating circuit is used for responding to the signal of the gating signal terminal to connect the reset signal line and the first reset circuit and the second reset circuit; The scanning of the pixel driving circuit includes inputting an initial signal of the initial signal line to the first electrode of the light emitting unit and the gate of the driving transistor; The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the initial signal of the initial signal line to the first electrode of the light emitting unit and the gate of the driving transistor in a time-sharing manner through the reset signal line.

12. The display panel according to claim 11, wherein: The first electrode of the driving transistor forms the data writing node, and the data writing circuit includes: a fourth transistor, wherein a first electrode of the fourth transistor is connected to the data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; The compensation circuit comprises: a second transistor, wherein a first electrode of the second transistor is connected to the gate electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; The first gating circuit comprises: an eighth transistor, a first electrode of which is connected to the first gate line, a second electrode of which is connected to the gate of the fourth transistor and the gate of the second transistor, and a gate of which is connected to the selection signal terminal; The first reset circuit comprises: a first transistor, wherein a first electrode of the first transistor is connected to the initial signal line, and a second electrode of the first transistor is connected to the gate of the driving transistor; The second reset circuit comprises: a seventh transistor, a first electrode of which is connected to the initial signal line, and a second electrode of which is connected to the first electrode of the light-emitting unit; The second gating circuit comprises: A tenth transistor has a first electrode connected to the reset signal line, a second electrode connected to the gate of the first transistor and the gate of the seventh transistor, and a gate connected to the selection signal terminal.

13. The display panel according to claim 1, wherein: The multiple gate lines include multiple scanning gate lines, the first direction is the row direction, and a row of pixel driving circuits corresponds to multiple same scanning gate lines. Among the multiple same scanning gate lines corresponding to a row of pixel driving circuits, the scanning gate lines are connected to the pixel driving circuits connected to the same data line group, and the pixel driving circuits connected to different data line groups are connected to different scanning gate lines.

14. The display panel according to claim 13, wherein: The display panel further includes: A plurality of gating circuits, each row of the pixel driving circuits is provided with a plurality of the gating circuits corresponding to the pixel driving circuits in the same row, and the plurality of the gating circuits corresponding to the pixel driving circuits in the same row are provided in one-to-one correspondence with a plurality of the same scanning gate lines, and the plurality of the same scanning gate lines corresponding to a row of the pixel driving circuits are respectively connected to the same signal output terminal of the gate driving circuit through the gating circuits corresponding thereto; The gating circuit is connected to the gating signal terminal, and is used to respond to the signal of the gating signal terminal to conduct the scanning gate line and the output terminal of the gate driving circuit; The gating circuits corresponding to the pixel driving circuits connected to different data line groups are connected to different gating signal terminals.

15. The display panel according to claim 9 or 14, wherein: The pixel driving circuits connected to the same data line group form a pixel driving circuit group, and the selection signal terminal is used to output a conduction level when the pixel driving circuit connected to it is in a scanning period, and the selection signal terminal is used to output an off level when the pixel driving circuit group to which the pixel driving circuit connected to it belongs is in a non-scanning period.

16. The display panel according to claim 13, wherein: The gate driving circuit includes multiple sub-gate driving circuits, and multiple scanning gate lines of the same type corresponding to the same row of pixel driving circuits are respectively arranged corresponding to the multiple sub-gate driving circuits, and the multiple sub-gate driving circuits are respectively used to scan the pixel driving circuits connected thereto at different time periods.

17. The display panel according to any one of claims 1 to 14 and 16, wherein: The second direction is a column direction, the display panel includes a plurality of pixel units, and the pixel unit includes a plurality of pixel driving circuits adjacent to each other in the first direction; The data line group connects a plurality of columns of pixel units.

18. The display panel according to claim 17, wherein: The plurality of data lines form two data line groups, one data line group is connected to the pixel units in odd columns, and the other data line group is connected to the pixel units in even columns.

19. The display panel according to any one of claims 1 to 14 and 16, wherein: The data connection line is directly connected to the data line.

20. A display device, wherein: The display device comprises the display panel according to any one of claims 1-19.

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