Readout electronics system and scintillator neutron detector system

Abstract

The utility model provides a readout electronics system and a scintillator neutron detector system. The readout electronics system comprises a pre-amplification circuit board which is used for receiving an electric signal output by a scintillator neutron detector for detecting incident neutrons, and comprises an electric signal processing chip, the electric signal processing chip converts an electric signal received from the scintillator neutron detector into a digital signal; the digital processing circuit board is used for processing the digital signals to obtain neutron flight time information of the incident neutrons and neutron hit position information of the incident neutrons on the scintillator neutron detector; wherein the pre-amplification circuit board comprises a plurality of electric signal processing chips, each electric signal processing chip comprises a plurality of mutually independent signal processing channels, and the plurality of electric signal processing chips realize parallel processing of a plurality of electric signals output by the scintillator neutron detector.

Description

Technical Field

[0001] The present disclosure relates to the technical field of neutron detectors, and particularly to a readout electronics system and a scintillator neutron detector system. Background Art

[0002] Neutrons are ideal probes for studying the microscopic structure of matter. Neutron scattering technology has been applied to multiple disciplinary fields such as condensed matter physics, materials science, chemistry, earth science, and biomedicine.

[0003] Observing the microscopic structure of matter using neutron scattering technology requires high-performance neutron detectors. Currently, the mainstream neutron detectors include 3 He gas detectors, semiconductor detectors, and scintillator detectors, etc.

[0004] Due to the advantages of the scintillator neutron detector such as being able to be spliced in large areas and having high cost performance, it is increasingly applied to the field of neutron detection.

[0005] The task of the readout electronics system is to process the output electrical signal of the scintillator neutron detector, and then obtain information such as the neutron flight time and the neutron hit position. The acquisition of the neutron flight time information and the neutron hit position information can be calculated using an FPGA (Field-Programmable Gate Array), which belongs to the prior art.

[0006] It is necessary to continuously improve the structure of the scintillator neutron detector and the readout electronics system to improve the detection efficiency and the position resolution. Summary of the Utility Model

[0007] The present disclosure provides a new readout electronics system and a scintillator neutron detector system.

[0008] According to one aspect of the present disclosure, there is provided a readout electronics system, including:

[0009] A preamplifier circuit board, which is used to receive the electrical signal output by the scintillator neutron detector for detecting incident neutrons. The preamplifier circuit board includes an electrical signal processing chip, and the electrical signal processing chip converts the electrical signal received from the scintillator neutron detector into a digital signal;

[0010] A digital processing circuit board, which processes the digital signal to obtain the neutron flight time information of the incident neutron and the neutron hit position information of the incident neutron on the scintillator neutron detector;

[0011] Among them, the pre-amplification circuit board includes a plurality of the electrical signal processing chips, each of the electrical signal processing chips includes a plurality of mutually independent signal processing channels, and the plurality of electrical signal processing chips perform parallel processing on the multiplexed electrical signals output by the scintillator neutron detector;

[0012] Among them, the digital processing circuit board includes:

[0013] An FPGA, which is used to execute the processing of the digital signals to obtain the neutron flight time information and the neutron hit position information;

[0014] A synchronous trigger circuit, which receives a synchronous trigger signal in the form of a low-voltage differential signal from outside the readout electronics system, converts the synchronous trigger signal in the form of a low-voltage differential signal into a synchronous trigger signal in the form of a low-voltage transistor-transistor logic signal and transmits it to the FPGA, so that the FPGA can periodically transmit the neutron flight time information and the neutron hit position information to a host computer outside the readout electronics system based on the synchronous trigger signal;

[0015] A power supply circuit, which is connected to the FPGA and supplies power to the power-consuming components of the digital processing circuit board and the power-consuming components of the pre-amplification circuit board via the FPGA.

[0016] For the readout electronics system according to at least one embodiment of the present disclosure, the signal processing channel is composed of a voltage-sensitive preamplifier, two-stage RC shaping circuits, a discrimination circuit, and a threshold circuit;

[0017] The electrical signal is first amplified by the voltage-sensitive preamplifier, then filtered and shaped by the two-stage RC shaping circuits, the electrical signal processed by the two-stage RC shaping circuits and the threshold signal preset by the threshold circuit are sent to the discrimination circuit for comparison, and the discrimination circuit discriminates the electrical signal processed by the two-stage RC shaping circuits and outputs a pulse signal as the digital signal.

[0018] For the readout electronics system according to at least one embodiment of the present disclosure, the pre-amplification circuit board is further configured with a calibration circuit, which can generate calibration signals and send them to the voltage-sensitive preamplifiers of each of the electrical signal processing chips to fan out to each of the signal processing channels, so that the readout electronics system can perform self-check or fault detection.

[0019] For the readout electronics system according to at least one embodiment of the present disclosure, the power supply circuit includes a plurality of step-down DC-DC switching power supply modules, which respectively supply power to each power-consuming unit of the FPGA.

[0020] According to the readout electronics system of at least one embodiment of the present disclosure, a voltage-current monitoring circuit is further configured on the digital processing circuit board. The voltage-current monitoring circuit is used to monitor the voltage and current provided by a voltage module (i.e., a high-voltage module) outside the readout electronics system to the scintillator neutron detector via the digital processing circuit board and the preamplification circuit board.

[0021] According to the readout electronics system of at least one embodiment of the present disclosure, the power supply circuit further includes a first cascaded power supply module. The first cascaded power supply module is used to supply power to the voltage-current monitoring circuit. The first cascaded power supply module is composed of a buck DC-DC switching power supply module and a low-dropout linear regulator power supply module in cascade.

[0022] According to the readout electronics system of at least one embodiment of the present disclosure, both the preamplification circuit board and the digital processing circuit board are configured with pin connectors to achieve board-to-board connection between the preamplification circuit board and the digital processing circuit board and realize signal transmission.

[0023] According to the readout electronics system of at least one embodiment of the present disclosure, the digital processing circuit board is further configured with a temperature measurement circuit. The temperature measurement circuit monitors the temperature of the digital processing circuit board, and the temperature measurement circuit is communicatively connected to the FPGA;

[0024] The power supply circuit further includes a second cascaded power supply module. The second cascaded power supply module is used to supply power to the temperature measurement circuit. The second cascaded power supply module is composed of a boost DC-DC switching power supply module and two low-dropout linear regulator power supply modules;

[0025] The boost DC-DC switching power supply module boosts the operating voltage input to the digital processing circuit board and converts it into a positive voltage and a negative voltage, which are respectively input to the two low-dropout linear regulator power supply modules. The voltages output by the two low-dropout linear regulator power supply modules are provided to the temperature measurement circuit.

[0026] According to the readout electronics system of at least one embodiment of the present disclosure, the power supply circuit further includes a third cascaded power supply module. The third cascaded power supply module is used to supply power to each electrical signal processing chip of the preamplification circuit board via the FPGA;

[0027] The third cascaded power supply module is composed of a buck DC-DC switching power supply module and a low-dropout linear regulator power supply module. The buck DC-DC switching power supply module steps down the operating voltage input to the digital processing circuit board to a positive voltage. This positive voltage is divided into two paths. One path directly supplies the digital circuit of the electrical signal processing chip, and the other path is input into the low-dropout linear regulator power supply module. After being stepped down again by the low-dropout linear regulator power supply module, it is supplied to the analog circuit of the electrical signal processing chip.

[0028] According to another aspect of the present disclosure, there is provided a scintillator neutron detector system, including: a scintillator neutron detector, the scintillator neutron detector includes a scintillator, a light guide glue, and a photoelectric conversion array. After an incident neutron hits the scintillator, an optical signal is generated. The optical signal is transmitted to the photoelectric conversion array through the light guide glue, and the photoelectric conversion array converts the optical signal into the electrical signal; and a readout electronics system according to any one of the embodiments of the present disclosure, the readout electronics system processes the electrical signal. Brief Description of the Drawings

[0029] The drawings illustrate exemplary embodiments of the present disclosure and are used together with the description to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure, and the drawings are included in this specification and form a part of this specification.

[0030] Figure 1 It is a schematic diagram of the overall structure of a scintillator neutron detector system according to an embodiment of the present disclosure.

[0031] Figure 2 It is a schematic diagram of the structure of a photoelectric conversion array according to an embodiment of the present disclosure.

[0032] Figure 3 It is a schematic diagram of the overall structure of a readout electronics system according to an embodiment of the present disclosure.

[0033] Figure 4 It is a schematic diagram of the circuit structure of an ASIC chip according to an embodiment of the present disclosure.

[0034] Figure 5 It is a schematic diagram of the circuit structure of a calibration circuit according to an embodiment of the present disclosure.

[0035] Figure 6 It is a circuit structure diagram of a power supply circuit according to an embodiment of the present disclosure.

[0036] Figure 7 It shows the circuit structure of a temperature measurement circuit according to an embodiment of the present disclosure.

[0037] Figure 8The circuit structure of the voltage and current monitoring circuit according to an embodiment of the present disclosure is shown.

[0038] Figure 9 The circuit structure of the EEPROM circuit according to an embodiment of the present disclosure is shown.

[0039] Figure 10 The circuit structure of the SFP interface circuit according to an embodiment of the present disclosure is shown.

[0040] Figure 11 The circuit structure of the synchronous trigger circuit according to an embodiment of the present disclosure is shown. Detailed Embodiments

[0041] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the relevant content and do not limit the present disclosure. Additionally, it should be noted that for the convenience of description, only the parts related to the present disclosure are shown in the drawings.

[0042] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. The technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings and embodiments.

[0043] Unless otherwise specified, the exemplary embodiments / Examples shown are understood to provide exemplary features of various details of some ways that can implement the technical concept of the present disclosure in practice. Therefore, unless otherwise specified, without departing from the technical concept of the present disclosure, the features of various embodiments / Examples can be additionally combined, separated, interchanged, and / or rearranged.

[0044] In the drawings, cross-hatching and / or shading are generally used to make the boundaries between adjacent components clear. Thus, unless stated, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for the specific material, material properties, dimensions, proportions, commonality between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. Additionally, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of the components may be exaggerated. When the exemplary embodiments can be implemented differently, the specific process sequences can be performed in an order different from that described. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to that described. Additionally, the same reference numerals represent the same components.

[0045] When a component is referred to as being "on" or "above" another component, "connected to" or "coupled to" another component, the component can be directly on the other component, directly connected to or directly coupled to the other component, or there can be intervening components. However, when a component is referred to as being "directly on" another component, "directly connected to" or "directly coupled to" another component, there are no intervening components. For this reason, the term "connected" can refer to physical connection, electrical connection, etc., and can have or not have intervening components.

[0046] For descriptive purposes, the present disclosure may use spatial relative terms such as "under", "below", "beneath", "lower", "above", "on", "over", "upper", and "side (e.g., in "sidewall")" etc., so as to describe the relationship between one component and another (other) component as shown in the drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacturing. For example, if the device in the drawings is flipped, a component described as being "under" or "beneath" another component or feature will then be positioned "above" the other component or feature. Thus, the exemplary term "under" can encompass both the "above" and "below" orientations. In addition, the device can be otherwise positioned (e.g., rotated 90 degrees or at other orientations), and accordingly, the spatial relative descriptors used herein are to be interpreted.

[0047] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms. In addition, when the terms "comprise" and / or "include" and their variants are used in this specification, it is stated that there are the stated features, integers, steps, operations, components, assemblies, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, assemblies, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, so they are used to explain the inherent deviations of measured values, calculated values, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0048] Figure 1 is a schematic diagram of the overall structure of a scintillator neutron detector system according to an embodiment of the present disclosure.

[0049] Figure 2 is a schematic diagram of the structure of a photoelectric conversion array according to an embodiment of the present disclosure.

[0050] Reference Figure 1and Figure 2 , in some embodiments of the present disclosure, the scintillator neutron detector system 1000 of the present disclosure includes a scintillator neutron detector 100 and a readout electronics system 200.

[0051] Reference Figure 1 , the scintillator neutron detector 100 of the present disclosure includes a scintillator 101, a light guide adhesive 102, and a photoelectric conversion array 103. In some embodiments of the present disclosure, the scintillator 101 may be lithium glass, and the photoelectric conversion array 103 may be a silicon photomultiplier (SiPM) array.

[0052] Hereinafter, the scintillator neutron detector 100 of the present disclosure will be described by taking lithium glass as an example of the scintillator 101 and a silicon photomultiplier as the photoelectric conversion unit of the photoelectric conversion array 103.

[0053] In lithium glass 6 Li undergoes a nuclear reaction with neutrons, generating scintillation light; the light guide adhesive 102 serves as a light propagation medium to conduct the scintillation light to the silicon photomultiplier (SiPM); the silicon photomultiplier converts the received optical signal into an electrical signal and transmits it to the readout electronics system 200 for processing.

[0054] In the present disclosure, both the silicon photomultiplier and the light guide adhesive can use commercial silicon photomultipliers and light guide adhesives. For example, the SiPM can use the MicroFJ-30035-TSV of ON Semiconductor, and the single-chip size of the SiPM is 3mm×3mm. Exemplarily, multiple SiPMs are used and closely arranged. Each row and column consists of 16 SiPMs, and the center distance between any two adjacent SiPMs is 3.16mm. The two-dimensional arrangement of the SiPM array (i.e., the photoelectric conversion array) is as Figure 2 shown.

[0055] The present disclosure mainly improves the readout electronics system of the scintillator neutron detector system.

[0056] The task of the readout electronics system is to process the output electrical signal of the scintillator neutron detector, and then obtain information such as the neutron flight time and the neutron hit position. The acquisition of the neutron flight time information and the neutron hit position information can be obtained by using an FPGA (Field-Programmable Gate Array), that is, a field-programmable logic gate array for calculation, which belongs to the prior art and will not be elaborated in this disclosure. If a traditional single-channel discrete readout design scheme is adopted, the scale of the readout electronics system is large, the integration level is low, and the power consumption is high, which is not conducive to the expansion and application of the scintillator neutron detector system. Based on the application specific integrated circuit (ASIC) technology, this disclosure has developed an ASIC chip and developed a new type of readout electronics system.

[0057] Figure 3 It is a schematic diagram of the overall structure of the readout electronics system according to an embodiment of this disclosure.

[0058] Reference Figure 3 In some embodiments of this disclosure, the readout electronics system 200 is composed of a preamplifier circuit board 201 and a digital processing circuit board 202.

[0059] The preamplifier circuit board 201 takes the ASIC chip 2011 ( Figure 3 which shows multiple ASIC chips) as the core, amplifies and filters the weak electrical signal output by the SiPM (i.e., the photoelectric conversion unit), and then compares it with the discrimination threshold, so as to eliminate the influence of interference signals such as gamma rays and thermal noise, and output a digital signal; the digital processing circuit board 202 preferably takes a field-programmable gate array (Field-Programmable Gate Array, FPGA) as the core, collects and processes the digital signal output by the preamplifier circuit board 201, so as to obtain data such as the neutron flight time and the hit position, and transmits the data to the host computer (i.e., a computer device) through a communication network for recording and subsequent processing.

[0060] Figure 4 It is a schematic diagram of the circuit structure of an ASIC chip according to an embodiment of this disclosure.

[0061] Reference Figure 4 In some embodiments of this disclosure, the ASIC chip 2011 has 32 independent signal processing channels, which can process 32 electrical signals output by the scintillator neutron detector 100 in parallel. Those skilled in the art can adjust the number of channels in the ASIC chip 2011 based on the number of SiPMs in the SiPM array under the inspiration of the technical solution of this disclosure, and all fall within the protection scope of this disclosure.

[0062] Reference Figure 4 Each signal processing channel of the ASIC chip 2011 consists of a voltage-sensitive preamplifier, a two-stage RC shaping circuit, a discrimination circuit, and a threshold circuit.

[0063] The working process of the ASIC chip 2011 of the present disclosure is as follows: when a neutron hits the scintillator 101 (which can be a scintillation screen, for example: a lithium glass scintillation screen), a nuclear reaction occurs with Li or B in the scintillator 101, emitting an optical signal, and the optical signal is converted into an electrical signal (a weak electrical signal) by the SiPM; then the electrical signal is amplified by the voltage-sensitive preamplifier of a signal processing channel of the ASIC chip 2011, and then passes through the circuit filters and shapes the amplified electrical signal, filters out high-frequency noise, and improves the signal-to-noise ratio; then, the signal output by the voltage-sensitive preamplifier is sent to the discrimination circuit and compared with the threshold preset by the threshold circuit, thereby excluding interference signals such as SiPM thermal noise and gamma, and at the same time generating a pulse signal with an LVTTL level. The pulse signal is transmitted to the FPGA through Figure 3 the 400pins connector (which can be adjusted to other types of connectors) exemplarily shown in, and processed by the FPGA, and information such as the neutron flight time and the neutron hit position can be obtained. The processing process of the FPGA is prior art. The FPGA can use an existing commercial FPGA.

[0064] In some embodiments of the present disclosure, reference Figure 4 The present disclosure also configures a calibration circuit in the ASIC chip 2011 to implement the normal working mode and the calibration working mode of the ASIC chip 2011.

[0065] Reference Figure 4 The normal working mode of the ASIC chip 2011 is used for the online processing of neutron signals, and the calibration working mode is used for the self-check and fault detection of the readout electronics system 200.

[0066] In the normal working mode, the ASIC chip 2011 receives the output signal of the scintillator neutron detector 100, conditions and digitizes the signal, and then sends the digitized signal to the FPGA of the digital processing circuit board 202 for processing.

[0067] In the calibration working mode, reference Figure 4 First, the calibration circuit generates the required calibration signal (generates the required calibration signal based on Vdc), and sends it to the dedicated input pin of the calibration signal of the ASIC chip 2011, and is fanned out to each channel by each voltage-sensitive preamplifier inside the ASIC chip 2011, so as to perform the self-check and fault detection of the readout electronics system 200.

[0068] Figure 5 It is a schematic circuit diagram of a scaling circuit according to an embodiment of the present disclosure. It should be noted that Figure 5 the capacitance value and resistance value of the scaling circuit in are exemplary and should not be construed as a limitation on the circuit structure of the scaling circuit of the present disclosure.

[0069] Referring to Figure 5 , the working principle of the scaling circuit is as follows:

[0070] When entering the scaling working mode, the switch S1 is usually open, and the capacitor C1 is charged to the same value as the DC voltage Vdc_calib. The FPGA issues a Start signal, and the switch S1 closes. The capacitor C1 immediately discharges through the resistor R2, resistor R3, and switch S1, and a negative exponential signal can be generated at point A, whose amplitude is Vdc_calib. The negative exponential signal is further amplified by the non-inverting amplifier circuit. After the FPGA issues a Control signal, the scaling signal Vcalib is output. This signal is transmitted to the voltage-sensitive preamplifier to perform scaling calibration and self-test on each single-signal processing channel of the ASIC chip 1011.

[0071] The DC voltage Vdc_calib is the input signal of the scaling circuit. This signal can be generated by an external digital-to-analog converter (DAC), and the FPGA can be used to control the magnitude of this signal. Vdc_calib determines the output amplitude of the scaling signal; the Start signal can be a pulse signal with a frequency of 25 Hz and a duty cycle of 50%, which is used to control the analog switch S1. This signal is issued by the FPGA. By controlling the analog switch S1, a scaling signal for calibration can be generated; the Control signal is used to control whether the ASIC chip 2011 starts scaling calibration; Vcalib is the scaling signal, and this signal is output to each single-signal processing channel to check whether the channel gain, bias current, etc. of each signal processing channel of the ASIC chip 2011 are normal. The external DAC can be selected, such as the AD9744 of Analog Devices, Inc. The AD9744 is a 14-bit DAC, and the magnitude of its output voltage can be controlled using standard binary data encoding.

[0072] Referring again to Figure 3 and Figure 4, the scintillator neutron detector 100 of the present disclosure may have 256 SiPMs (photoelectric conversion units, the quantity can be adjusted), corresponding to 256 output signals. The preamplification circuit board 201 exemplarily integrates 8 ASIC chips 2011, and each ASIC chip 2011 processes the signals output by 32 SiPMs. The present disclosure can achieve the board-to-board connection between the preamplification circuit board 201 and the digital processing circuit board 202 through connectors with 400 pins (such as APM6-100 and APF6-100) of Samtec company to realize the transmission of signals.

[0073] Continue to refer to Figure 3 , and the digital processing circuit board 202 of the present disclosure will be described in detail.

[0074] The digital processing circuit board 202 collects and processes the output signals of the preamplification circuit board 201, and transmits the digitized data to the host computer through gigabit Ethernet for recording and subsequent processing.

[0075] Refer to Figure 3 , in some embodiments of the present disclosure, the digital processing circuit board 202 includes a main control chip (such as FPGA), a power supply circuit, Double-Data-Rate 3 synchronous dynamic RAM (DDR3), Electrically Erasable Programmable Read Only Memory (EEPROM), FLASH memory (FLASH), a temperature measurement circuit, a synchronous trigger circuit, an SFP interface circuit, and a voltage and current monitoring circuit.

[0076] The main control chip of the present disclosure can adopt an ARM processor, a digital signal processor (DSP), an FPGA, etc.

[0077] Compared with ARM and DSP, FPGA has the advantages of flexibility, reconfigurability, low latency, and the ability to process data in parallel. The present disclosure preferably selects XC7K325T-2FFG900I of the Kintex-7 series of Xilinx company as the main control chip.

[0078] Refer to Figure 3 , for the readout electronics system 200 to work stably and reliably, a stable power supply is required. The power supply circuit can be divided into two categories: linear power supply and switch mode power supply (DC-DC).

[0079] The Low Dropout regulator (LDO) is a linear power supply widely used currently. The LDO makes the transistor or field-effect transistor work in the linear region, compares the output voltage with the set reference voltage to achieve feedback, and then generates the required voltage. The output ripple voltage of the LDO is low, usually only dozens of μV. RMS And the electromagnetic interference is small, but for this type of power supply to work properly, it is necessary to ensure that the difference between the input and output is greater than the minimum voltage difference, and the conversion efficiency is not high.

[0080] The DC-DC makes the power element work in the saturation region or the cut-off region, and generates the required voltage by controlling the saturation time and cut-off time of the power element. The DC-DC has the advantages of high conversion efficiency and wide input voltage range, but its output voltage ripple is relatively large.

[0081] In this disclosure, the power supply required for the analog circuit is generated by a power supply circuit composed of a combination and cascade of DC-DC and LDO. After stepping down the input voltage through a buck DC-DC, the subsequent LDO is used to convert it into the required voltage. This design method provides a more stable voltage for the load on the basis of ensuring the power supply efficiency; the power supply required for the digital circuit is directly generated by the buck DC-DC.

[0082] Figure 6 It is the circuit structure diagram of the power supply circuit of an embodiment of this disclosure.

[0083] Reference Figure 3 , the readout electronics system 200 is preferably powered by a +12V input (+12V is the operating voltage).

[0084] Since when the FPGA starts up, the FPGA core voltage requires a current of more than ten amperes, this disclosure preferably uses the TPS53355 chip of Texas Instruments as the buck DC-DC to supply power to the FPGA core. This chip has a wide input voltage range of 1.5V to 15V, a wide output range of 0.6V to 5.5V, and the output current can reach 30A, which can meet the power supply requirements of the FPGA core.

[0085] The high-speed transceivers of the FPGA ( Figure 6 The FPGA MGTAVCC, FPGA MGTAVTT, FPGA MGTVCCAUX in

[0086] The DDR BANK of the FPGA (that isFigure 6 In the FPGA DDR BANK), TPS62130 is used as a step-down DC-DC to provide a voltage of +1.5V.

[0087] The I / O BANK of the FPGA (i.e., Figure 6 In the FPGA I / O BANK) uses TPS62130 as a step-down DC-DC to provide a voltage of +3.3V.

[0088] Since the analog circuits (temperature measurement circuit, voltage and current monitoring circuit) have high requirements for the power supply quality, the present disclosure uses a cascaded manner of DC-DC (step-down DC-DC or boost DC-DC) and LDO for power supply.

[0089] Refer to Figure 6 , the voltage and current monitoring circuit requires +5VA power supply. The present disclosure preferably uses TPS62130 as a step-down DC-DC to convert +12V to +5.8V, and then uses an LDO to convert +5.8V to +5VA to supply power to the voltage and current monitoring circuit. The LDO can be LT1764 of ADI Corporation. The maximum input voltage of this chip is 20V, and the output voltage range is from 1.21V to 20V.

[0090] Refer to Figure 6 , the temperature measurement circuit requires ±12VA power supply. A boost DC-DC such as WRA1215SD of Mornsun can be used to convert the +12V input by the readout electronics system 200 to ±15V. After +15V passes through an LDO chip LT1763 of ADI Corporation, a supply voltage of +12VA is generated. After -15V passes through an LDO chip LT1175 of ADI Corporation, a supply voltage of -12VA is generated. WRA1215SD has a wide input voltage range of 9V to 18V and dual outputs of ±15V. The input voltage of LT1763 can reach up to 20V at most, and the output voltage range is from 1.22V to 20V. The input voltage of LT1175 can reach up to -20V at most, and the output voltage range is from -3.8V to -19.3V.

[0091] Refer to Figure 3 and Figure 6 , the ASIC chip requires +3.3V and +1.8VA. Among them, +3.3V supplies power to the digital part of the ASIC, and +1.8VA supplies power to the analog part of the ASIC. The present disclosure can use TPS61230 as a step-down DC-DC to generate 3.3V, and then pass 3.3V through an LDO (such as LT1764) to generate 1.8VA, so as to provide a power supply for the ASIC chip.

[0092] Figure 7 Fig. shows the circuit structure of the temperature measurement circuit according to an embodiment of the present disclosure.

[0093] In some embodiments of the present disclosure, with reference to Figure 3 , the readout electronics system 200 may include two temperature measurement circuits. Among them, one temperature measurement circuit obtains the ambient temperature information of the SiPM (silicon photomultiplier) and provides a reference for high-voltage compensation (with reference to Figure 3 ); the other temperature measurement circuit monitors the temperature of the digital processing circuit board and provides a reference for monitoring whether the readout electronics system is operating normally.

[0094] The present disclosure uses a negative temperature coefficient thermistor (Negative Temperature Coefficient, NTC) for temperature measurement.

[0095] With reference to Figure 7 , the working principle of the temperature measurement circuit is as follows: The NTC resistor, i.e., resistor R1, is connected in series with the precision resistor R2. The same current flows through them. The voltages across resistor R1 and resistor R2 (precision resistor) are measured by two instrumentation amplifiers and an ADC (preferably a 24-bit high-precision analog-to-digital converter (Analog to Digital Converter, ADC)). The FPGA calculates the resistance value of the NTC resistor from the voltage data, obtains the linear relationship between the resistance value of the NTC resistor and the temperature, and thus obtains the temperature to be measured.

[0096] To improve the measurement accuracy, the present disclosure uses a current source (preferably 100 μA) as the excitation source. The excitation source can use, for example, REF200AU from Texas Instruments Incorporated. This chip can generate a current of 100 μA with an accuracy of up to ±0.25%. The thermistor can be selected as NTCG163 from TDK Corporation, with a resistance value of 10 KΩ at 25 °C and a resistance tolerance of ±0.5%; the precision resistor R2 can use a 10 KΩ resistor with an accuracy of 0.1%. The instrumentation amplifier can use, for example, INA128 from Texas Instruments Incorporated. This chip can directly measure the voltage across the resistor and has a low offset voltage of up to 50 μV and a common-mode rejection ratio of up to 120 dB, enabling accurate measurement of the voltage across the resistor.

[0097] A high-precision ADC is a prerequisite for accurate temperature measurement. To accurately read the voltages of the NTC resistor and the precision resistor, an ADC such as ADS1220 from Texas Instruments Incorporated can be used. This chip is a 24-bit four-channel ADC, and it can transmit data through the SPI interface to the FPGA (i.e., the FPGA in Figure 3 ).

[0098] Figure 7 In Figure 7 , R1 is the NTC resistor and R2 is the high-precision resistor. For the temperature measurement circuit shown in

[0099] U R1= IR1, U R2 = IR2;

[0100] Then the resistance value of resistor R1 is:

[0101] R1 = U R1 R2 / U R2 ;

[0102] By monitoring the resistance value of the NTC resistor, the temperature to be measured such as the ambient temperature can be monitored.

[0103] Figure 8 The circuit structure of the voltage and current monitoring circuit according to an embodiment of the present disclosure is shown.

[0104] The high-voltage module (providing high-voltage input, Figure 3 the high-voltage module is not shown) working properly is a prerequisite for the scintillator neutron detector, i.e., the front-end detector, to work properly. In order to ensure the stable and reliable operation of the high-voltage module, the output voltage and current of the high-voltage module must be monitored in real time.

[0105] Refer to Figure 8 , the present disclosure monitors the high-voltage module by using the method of resistor voltage division.

[0106] Working principle:

[0107] The ADC preferably uses a precision ADC, such as a 16-bit precision ADC, whose allowable input range is 0 to 4.096V. The output voltage of the high-voltage module is divided by resistors R2 and R3 in series, and the output voltage range of resistor R3 is controlled between 2.3636V and 3.00V. Then, the measured voltage is followed 1:1 by a voltage follower ( Figure 8 the voltage follower in the lower middle of Figure 3 ). The voltage follower serves two purposes: on the one hand, it isolates the front and rear stages and protects the ADC; on the other hand, it stabilizes the output voltage. The output of the voltage follower enters the 16-bit precision ADC, and the analog-to-digital conversion is performed by the 16-bit precision ADC, and the converted voltage signal is sent to the FPGA (i.e., the FPGA in

[0108] The essence of current measurement is to measure the potential difference across a resistor. A sampling resistor R1 is connected to the high-voltage output terminal (i.e., V_HV) of the high-voltage module, preferably a sampling resistor with high precision and low resistance. Current monitoring is achieved by measuring the potential difference across the sampling resistor. The resistance value of the sampling resistor can be 0.02Ω, which does not affect the magnitude of the high-voltage output voltage. When high voltage is output, the current flowing through the sampling resistor R1 generates a voltage difference across R1. Subsequently, a current detection amplifier, such as a high-precision current detection amplifier LT6105, is used to amplify the voltage difference across the sampling resistor R1, and then it is followed by a voltage follower for 1:1 following. Finally, it enters a 16-bit precision ADC to achieve analog-to-digital conversion, and the converted current signal is sent to the FPGA (i.e., Figure 3 the FPGA in

[0109] To achieve high-precision measurement, the 16-bit precision ADC of the present disclosure can be the 16-bit, 8-channel AD7689 of Analog Devices, Inc. It can convert analog quantities into digital quantities. When using the internal reference source reference voltage of 4.096V, the minimum resolution is 62.5uV; the voltage follower can adopt the AD8630 of Analog Devices, Inc. It has four channels, zero drift, rail-to-rail output, and the bandwidth-gain product can reach 2.5MHz.

[0110] Figure 9 The circuit structure of the EEPROM circuit of an embodiment of the present disclosure is shown.

[0111] Figure 3 Each circuit module in the readout electronics system in

[0112] needs to be configured through a host computer, and the FPGA does not have the function of power-off protection. Therefore, the present disclosure uses EEPROM to store the configuration information of each circuit module. It is a storage chip whose data is not lost after power-off. Figure 9 EEPROM has the function of power-off protection. Data can be written to and erased from it through the FPGA. A 24LC02 chip of CEAAMATE Company can be used, which is a 2048-bit serial EEPROM chip that is fully compatible with the Inter-Integrated Circuit (IIC) protocol communication and can store 2Kbit of data. Its circuit structure is as

[0113] shown.

[0114] In neutron scattering experiments, when the neutron flux is relatively large, there is a situation of high-concurrency data generation. To address this situation, the present disclosure introduces a DDR3 cache mechanism. Refer to Figure 3 , to improve the processing ability for high-concurrency data. DDR3 is the third-generation double data rate synchronous dynamic random access memory, which has a high data transmission speed, low power consumption, and better stability.

[0115] Preferably, the present disclosure uses two MT41K256M16 DDR3 chips from Micron. This chip has a capacity of 256 MB, a high-speed data transmission function, and a latency time of only nanoseconds, which can meet the requirements of the readout electronics system for data storage and readout.

[0116] Refer to Figure 3 , after digitization, the hit position and time-of-flight information of neutrons need to be transmitted to the host computer. The host computer acquires the data and performs storage and analysis processing. At the same time, the configuration information of each circuit module of the readout electronics system requires the host computer to issue it to complete the configuration and initialization.

[0117] Figure 3 In

[0118] Preferably, the present disclosure uses an SFP interface circuit as the fiber optic communication circuit of the present disclosure. Figure 10 shows the circuit structure of the SFP interface circuit of an embodiment of the present disclosure. Specifically, SFP5819 can be used to achieve fiber optic communication. SFP5819 can convert electrical signals into optical signals and then perform high-rate transmission through optical fibers.

[0119] Refer to Figure 3 , in order to obtain accurate neutron time-of-flight under the same trigger condition during the experiment, the present disclosure configures a synchronous trigger circuit. As Figure 3 shown, the external synchronous trigger signal can be sent to the synchronous trigger circuits of multiple scintillator neutron detector systems to achieve precise synchronization of multiple devices.

[0120] To ensure the synchronization and accuracy of data, the synchronous trigger signal of the present disclosure preferably uses low-voltage differential signaling (LVDS) for transmission. Differential signals have the advantages of strong anti-interference ability and long transmission distance, which can ensure the stability and accuracy of the signal during transmission.

[0121] To isolate the external synchronous trigger signal from the FPGA of the digital processing circuit board 202, the SN65LVDS2 chip of Texas Instruments can be selected to convert the LVDS differential signal into a Low Voltage Transistor-Transistor Logic (LVTTL) signal and then connect it to the FPGA, thus effectively protecting the FPGA. Figure 11 The circuit structure of the synchronous trigger circuit according to an embodiment of the present disclosure is shown. The FPGA sends the neutron hit position and neutron flight time information to the host computer via the SFP interface circuit in cycles of the synchronous trigger signal.

[0122] It should be noted that Figures 2 to 11 parameters such as the model numbers of the specific components shown in the present disclosure are exemplary and should not be construed as limitations on the relevant circuit structures of the present disclosure. Those skilled in the art Figures 2 to 11 under the inspiration of the relevant text descriptions, adjusting or reselecting the model numbers of specific components and the like all fall within the scope of the present disclosure.

[0123] The scintillator neutron detector and the readout electronics system (using Figure 2 the photoelectric conversion array shown) in some embodiments of the present disclosure can achieve an effective detection area of 53.56×53.56 mm², a maximum counting rate of up to 20 KHz / cm², and a position resolution of up to 3.16 mm×3.16 mm, realizing the design of a readout electronics system with high counting rate and high position resolution.

[0124] In the description of this specification, the descriptions with reference to terms such as "one embodiment / way", "some embodiments / ways", "example", "specific example" or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment / way or example are included in at least one embodiment / way or example of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / way or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments / ways or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments / ways or examples described in this specification and the features of different embodiments / ways or examples.

[0125] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0126] Those skilled in the art should understand that the above-described embodiments are merely for clearly illustrating the present disclosure and are not intended to limit the scope of the present disclosure. For those skilled in the art, other changes or modifications can be made based on the above disclosure, and these changes or modifications are still within the scope of the present disclosure.

Claims

1. A readout electronics system, characterized in that include: A preamplifier circuit board, the preamplifier circuit board is used to receive the electrical signal output by the scintillator neutron detector when detecting incident neutrons, the preamplifier circuit board includes an electrical signal processing chip, the electrical signal processing chip converts the electrical signal received from the scintillator neutron detector into a digital signal; as well as Digital processing circuit board; Wherein, the preamplifier circuit board includes a plurality of the electrical signal processing chips, each of which includes a plurality of mutually independent signal processing channels, and the plurality of electrical signal processing chips realize parallel processing of the multi-channel electrical signals output by the scintillator neutron detector; Wherein, the digital processing circuit board comprises: FPGA, the FPGA is used to process the digital signal to obtain neutron flight time information and neutron impact position information of incident neutrons; a synchronization trigger circuit, wherein the synchronization trigger circuit receives a synchronization trigger signal in the form of a low voltage differential signal from outside the readout electronics system, converts the synchronization trigger signal in the form of a low voltage differential signal into a synchronization trigger signal in the form of a low voltage triode-triode logic signal, and transmits the synchronization trigger signal to the FPGA, so that the FPGA can periodically transmit neutron flight time information and neutron impact position information to a host computer outside the readout electronics system based on the synchronization trigger signal; and A power supply circuit is connected to the FPGA, and supplies power to power-requiring components of the digital processing circuit board and power-requiring components of the preamplifier circuit board via the FPGA.

2. The readout electronics system according to claim 1, characterized in that The signal processing channel is composed of a voltage-sensitive preamplifier, a two-stage RC shaping circuit, a discrimination circuit and a threshold circuit; The electrical signal is first amplified by the voltage-sensitive preamplifier, and then filtered and shaped by the two-stage RC shaping circuit. The electrical signal processed by the two-stage RC shaping circuit and the threshold signal pre-set by the threshold circuit are sent to the discrimination circuit for comparison. The discrimination circuit discriminates the electrical signal processed by the two-stage RC shaping circuit and outputs a pulse signal as the digital signal.

3. The readout electronics system according to claim 2, characterized in that The preamplifier circuit board is also configured with a calibration circuit, which can generate a calibration signal and send it to the voltage-sensitive preamplifier of each of the electrical signal processing chips to fan out to each of the signal processing channels, so that the readout electronics system can perform self-test or fault detection.

4. The readout electronics system according to claim 1, characterized in that The power supply circuit includes a plurality of step-down DC-DC switching power supply modules, which respectively supply power to each power-demanding unit of the FPGA.

5. The readout electronics system according to claim 1, characterized in that The digital processing circuit board is also provided with a voltage and current monitoring circuit, which is used to monitor the voltage and current provided to the scintillator neutron detector by the voltage module outside the readout electronics system via the digital processing circuit board and the preamplifier circuit board.

6. The readout electronics system according to claim 5, characterized in that The power supply circuit also includes a first cascade power supply module, which is used to power the voltage and current monitoring circuit. The first cascade power supply module is composed of a step-down DC-DC switching power supply module and a low voltage difference linear regulator power supply module cascaded.

7. The readout electronics system according to claim 1, characterized in that The preamplifier circuit board and the digital processing circuit board are both configured with pin-type connectors to achieve board-to-board connection between the preamplifier circuit board and the digital processing circuit board, thereby achieving signal transmission.

8. The readout electronics system according to claim 1, characterized in that The digital processing circuit board is also provided with a temperature measuring circuit, which monitors the temperature of the digital processing circuit board, and the temperature measuring circuit is communicatively connected with the FPGA; The power supply circuit also includes a second cascade power supply module, which is used to supply power to the temperature measurement circuit, and the second cascade power supply module is composed of a boost DC-DC switching power supply module and two low voltage drop linear regulator power supply modules; The step-up DC-DC switching power supply module steps up and converts the working voltage input to the digital processing circuit board into one positive voltage and one negative voltage, which are respectively input into the two low voltage difference linear regulator power supply modules. The voltage output by the two low voltage difference linear regulator power supply modules is provided to the temperature measurement circuit.

9. The readout electronics system according to claim 1, characterized in that The power supply circuit further includes a third cascade power supply module, and the third cascade power supply module is used to supply power to each electrical signal processing chip of the preamplifier circuit board via the FPGA; The third cascade power supply module is composed of a step-down DC-DC switching power supply module and a low voltage difference linear regulator power supply module. The step-down DC-DC switching power supply module steps down the working voltage input to the digital processing circuit board and converts it into a positive voltage. The positive voltage is divided into two paths, one path is directly provided to the digital circuit of the electrical signal processing chip, and the other path is input to the low voltage difference linear regulator power supply module, and is provided to the analog circuit of the electrical signal processing chip after being stepped down again by the low voltage difference linear regulator power supply module.

10. A scintillator neutron detector system, characterized in that: include: A scintillator neutron detector, wherein the scintillator neutron detector comprises a scintillator, a light-guiding glue and a photoelectric conversion array, wherein an incident neutron generates a light signal after hitting the scintillator, and the light signal is transmitted to the photoelectric conversion array via the light-guiding glue, and the photoelectric conversion array converts the light signal into the electrical signal; as well as The readout electronics system of any one of claims 1 to 9, wherein the readout electronics system processes the electrical signal.

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