Data transmission system

Abstract

The utility model provides a data transmission system. The data transmission system comprises a first mainboard, a second mainboard, a first cable, a second cable and a clock synchronization backboard, the first cable is respectively connected with the first mainboard and the clock synchronization backboard and is used for transmitting a first clock signal and a data signal; and the second cable is respectively connected with the second mainboard and the clock synchronization backboard and is used for transmitting the second clock signal and the data signal. Through the independent clock synchronization backboard, the first cable connected with the first mainboard and the second cable connected with the second mainboard, the length of the cable between the first mainboard and the second mainboard can be increased, and the framework flexibility of the data transmission system is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of servers, and in particular to a data transmission system. Background Art

[0002] With the upgrade and development of server products, more and more systems are interconnected by cables to achieve data transmission between systems.

[0003] In the prior art, two systems are directly connected by a cable, and data transmission between the systems is carried out through a clock synchronization device in the main control system.

[0004] However, in the prior art, when two systems perform data transmission, it is necessary to control the length of the cable between the systems to ensure the signal quality of the transmitted data. Therefore, it will cause the problem that the architecture of the data transmission system is not flexible. Summary of the Utility Model

[0005] The utility model provides a data transmission system to achieve the effect of improving the architecture flexibility of the data transmission system.

[0006] In a first aspect, the utility model provides a data transmission system, including:

[0007] A first main board, a second main board, a first cable, a second cable, and a clock synchronization backplane;

[0008] The first cable is respectively connected to the first main board and the clock synchronization backplane, and is used for transmitting a first clock signal and a data signal;

[0009] The second cable is respectively connected to the second main board and the clock synchronization backplane, and is used for transmitting a second clock signal and the data signal.

[0010] For the data transmission system as described above, wherein the clock synchronization backplane includes a clock generator and a clock buffer; wherein, the clock buffer is connected to the clock generator and is used for receiving an initial clock signal sent by the clock generator; the clock buffer is connected to the first main board through the first cable and is used for sending the first clock signal to the first main board through the first cable; the clock buffer is connected to the second main board through the second cable and is used for sending the second clock signal to the second main board through the second cable.

[0011] The data transmission system as described above, wherein the first main board includes a first main board controller, and the second main board includes a second main board controller; wherein, the first main board controller is connected to the clock buffer through the first cable, and is configured to receive the first clock signal, receive and / or transmit the data signal through the first cable; the second main board controller is connected to the clock buffer through the second cable, and is configured to receive the second clock signal, receive and / or transmit the data signal through the second cable.

[0012] The data transmission system as described above, wherein the first main board further includes a first connector;

[0013] The first connector is connected to the first main board controller through a circuit board clock line for transmitting the first clock signal; the first connector is connected to the first main board controller through a circuit board bus for transmitting the data signal; the first connector is connected to the clock buffer through the first cable for transmitting the first clock signal and the data signal.

[0014] The data transmission system as described above, wherein the second main board further includes a second connector;

[0015] The second connector is connected to the second main board controller through a circuit board clock line for transmitting the second clock signal; the second connector is connected to the second main board controller through a circuit board bus for transmitting the data signal; the second connector is connected to the clock buffer through the second cable for transmitting the second clock signal and the data signal.

[0016] The data transmission system as described above, wherein the clock synchronization backplane further includes a third connector; the third connector is connected to the clock buffer through a circuit board clock line for transmitting the first clock signal; the third connector is connected to the first main board controller through the first cable for transmitting the first clock signal and the data signal.

[0017] The data transmission system as described above, wherein the clock synchronization backplane further includes a fourth connector; the fourth connector is connected to the clock buffer through a circuit board clock line for transmitting the first clock signal; the fourth connector is connected to the second main board controller through the second cable for transmitting the second clock signal and the data signal; the fourth connector is connected to the third connector through a circuit board bus for transmitting the data signal.

[0018] The data transmission system as described above, wherein the lengths and / or materials of the first cable, the second cable, the circuit board clock line and the circuit board bus included in the first main board, the circuit board clock line and the circuit board bus included in the second main board, and the circuit board clock line and the circuit board bus included in the clock synchronization backplane are set such that the transmission delay increment for transmitting the data signal is less than a preset transmission delay increment threshold.

[0019] The data transmission system as described above, wherein at least one of the first main board and the second main board is a server main board.

[0020] The data transmission system as described above, wherein the system further includes at least one third main board and at least one third cable; wherein the third main board and the third cable are in one-to-one correspondence; each of the third cables is respectively connected to the corresponding third main board and the clock synchronization backplane for transmitting a third clock signal and the data signal. The data transmission system provided by the present invention can increase the cable length between the first main board and the second main board through a separate clock synchronization backplane, the first cable connecting the first main board, and the second cable connecting the second main board, improving the flexibility of the architecture of the data transmission system; wherein each of the third main boards includes a third main board controller and a fifth connector; the fifth connector is connected to the third main board controller through a circuit board clock line for transmitting the third clock signal; the fifth connector is connected to the third main board controller through a circuit board bus for transmitting the data signal; the fifth connector is connected to the clock synchronization backplane through the corresponding third cable for transmitting the third clock signal and the data signal.

[0021] In addition to the technical problems solved by the present invention, the technical features constituting the technical solution, and the beneficial effects brought by these technical features of the technical solution described above, other technical problems that the data transmission system provided by the present invention can solve, other technical features included in the technical solution, and the beneficial effects brought by these technical features will be further described in detail in the specific implementation manner. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1Schematic diagram of the structure and internal connection relationship of a data transmission system provided by the first embodiment of the present utility model;

[0024] Figure 2 Schematic diagram of the structure and internal connection relationship of a data transmission system provided by the second embodiment of the present utility model.

[0025] Through the above-mentioned drawings, specific embodiments of the present utility model have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present utility model in any way, but to illustrate the concept of the present utility model to those skilled in the art by referring to specific embodiments.

[0026] Description of reference numerals:

[0027] 100 - Data transmission system;

[0028] 1 - First main board;

[0029] 2 - Second main board;

[0030] 3 - First cable;

[0031] 4 - Second cable;

[0032] 5 - Clock synchronization backplane;

[0033] 6 - Clock generator;

[0034] 7 - Clock buffer;

[0035] 8 - First main board controller;

[0036] 9 - Second main board controller;

[0037] 10 - First connector;

[0038] 11 - Second connector;

[0039] 12 - Third connector;

[0040] 13 - Fourth connector;

[0041] 14 - Circuit board bus;

[0042] 15 - Circuit board clock line.

[0043] Through the above-mentioned drawings, specific embodiments of the present utility model have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present utility model in any way, but to illustrate the concept of the present utility model to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present utility model clearer and more understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0045] In the prior art, two systems are directly connected by a cable, and data transmission between the systems is carried out through a clock synchronization device in the main control system. However, in the prior art, when two systems perform data transmission, it is necessary to control the length of the cable between the systems to ensure the signal quality of the transmitted data. Therefore, it will cause the problem that the architecture of the data transmission system is not flexible.

[0046] To solve the above technical problems, the present utility model proposes a data transmission system: by a separate clock synchronization backplane, a first cable connecting the first main board and a second cable connecting the second main board, the cable length between the first main board and the second main board can be increased, and the flexibility of the architecture of the data transmission system is improved.

[0047] Figure 1 It is a schematic diagram of the structure and internal connection relationship of a data transmission system provided in the first embodiment of the present utility model.

[0048] As Figure 1 shown, this embodiment provides a data transmission system, and the data transmission system 100 includes:

[0049] A first main board 1, a second main board 2, a first cable 3, a second cable 4, and a clock synchronization backplane 5;

[0050] Specifically, the first main board 1 is the main board of a data transmission terminal for data transmission, and the second main board 2 is the main board of another data terminal for data transmission. The clock synchronization backplane 5 is a backplane that generates and sends clock signals for data transmission. A cable is used to connect devices and transmit signals. Among them, the present utility model does not limit the type of the cable, and any cable that can connect devices and transmit signals can be used as the cable provided by the present utility model. Specifically, the first cable 3 and the second cable 4 are cables that connect different devices in the data transmission system 100.

[0051] The first cable 3 is respectively connected to the first main board 1 and the clock synchronization backplane 5, and is used to transmit a first clock signal and a data signal;

[0052] Specifically, the first cable 3 is used to connect the first main board 1 and the clock synchronization backplane 5 in the data transmission system 100. The signals transmitted by the first cable 3 are the first clock signal and the data signal. Among them, the first clock signal is the clock signal sent by the clock synchronization backplane 5 to the first main board 1 for triggering the first main board 1 to perform data transmission. The data signal is the signal carrying the data to be transmitted that is mutually transmitted between the first main board 1 and the second main board 2.

[0053] The second cable 4 is respectively connected to the second main board 2 and the clock synchronization backplane 5, and is used to transmit the second clock signal and the data signal; among them, the second clock signal is used to trigger the second main board 2.

[0054] Specifically, the second cable 4 is used to connect the second main board 2 and the clock synchronization backplane 5 in the data transmission system 100. The signals transmitted by the second cable 4 are the second clock signal and the data signal. Among them, the second clock signal is the clock signal sent by the clock synchronization backplane 5 to the second main board 2 for triggering the second main board 2 to perform data transmission. The data signal is the signal carrying the data to be transmitted that is mutually transmitted between the first main board 1 and the second main board 2 described above.

[0055] Among them, the first clock signal and the second clock signal are the clock signals sent by the clock synchronization backplane 5 at the same time.

[0056] Optionally, based on the above description of the first clock signal, the second clock signal and the data signal, during the data transmission process, if the first main board 1 is the data sending end and the second main board 2 is the data receiving end, then after the first main board 1 receives the first clock signal sent by the clock synchronization backplane 5, it will encode the data to be transmitted according to a preset encoding method, and transmit the encoded data to be transmitted to the clock synchronization backplane 5 in the form of a data signal through the first cable 3; the clock synchronization backplane 5 then transmits the received data signal to the second main board 2 through the second cable 4; after receiving the data signal, if the second main board 2 receives the second clock signal sent by the clock synchronization backplane 5, it will decode the received data signal according to a preset decoding method to obtain the decoded data to be transmitted, and complete the data transmission from the first main board 1 to the second main board 2.

[0057] Optionally, based on the above descriptions of the first clock signal, the second clock signal, and the data signal, during data transmission, if the second main board 2 is the data sender and the first main board 1 is the data receiver, after receiving the second clock signal sent by the clock synchronization backplane 5, the second main board 2 will encode the data to be transmitted according to a preset encoding method, and transmit the encoded data to be transmitted to the clock synchronization backplane 5 in the form of a data signal through the second cable 4; the clock synchronization backplane 5 then transmits the received data signal to the first main board 1 through the first cable 3; after receiving the data signal, if the first main board 1 receives the first clock signal sent by the clock synchronization backplane 5, it will decode the received data signal according to a preset decoding method to obtain the data to be transmitted after decoding, completing the data transmission from the second main board 2 to the first main board 1.

[0058] Optionally, among the first main board 1 and the second main board 2, there is a main control device main board and a slave control device main board. Among them, the main control device main board is used to control the data transmission direction. For example, the main control device can control the data signal to be transmitted from the first main board 1 to the second main board 2, or control the data signal to be transmitted from the second main board 2 to the first main board 1.

[0059] The data transmission system provided in this embodiment can increase the cable length between the first main board and the second main board through a separate clock synchronization backplane, the first cable connected to the first main board, and the second cable connected to the second main board, improving the flexibility of the architecture of the data transmission system.

[0060] Figure 2 It is a schematic diagram of the structure and internal connection relationship of a data transmission system provided in the second embodiment of the present utility model. On the basis of Figure 1 the shown embodiment, the composition of each device is described in detail.

[0061] As Figure 2 shown, this embodiment provides a data transmission system 100, which includes:

[0062] A first main board 1, a second main board 2, a first cable 3, a second cable 4, and a clock synchronization backplane 5; the first cable 3 is respectively connected to the first main board 1 and the clock synchronization backplane 5 for transmitting the first clock signal and the data signal; the second cable 4 is respectively connected to the second main board 2 and the clock synchronization backplane 5 for transmitting the second clock signal and the data signal; among them, the second clock signal is used to trigger the second main board 2.

[0063] Specifically, for the specific description of the above content, reference can be made to Figure 1 the description in the shown embodiment, which will not be elaborated here.

[0064] Optionally, the clock synchronization backplane 5 includes a clock generator 6 and a clock buffer 7;

[0065] Specifically, the clock generator 6, denoted as CLK Gen in English, is used to generate an initial clock signal, where the initial clock signal is a clock signal for triggering data transmission between the first main board 1 and the second main board 2.

[0066] Among them, the clock buffer 7, denoted as Clk buffer in English, is connected to the clock generator 6 and is used to receive the initial clock signal sent by the clock generator 6; specifically, after receiving the initial clock signal sent by the clock generator 6, the clock buffer 7 can perform expansion processing on the received initial clock signal. After the expansion processing, the initial clock signal is expanded into multiple initial clock signals, where the number of the multiple clock signals corresponds to the number of devices for data transmission. For example, if the data transmission is between two devices, the clock buffer 7 expands the initial clock signal into two paths, namely the first clock signal and the second clock signal as described above. Among them, the multiple clock signals obtained by expanding through the clock buffer 7 are the same clock signal, that is, the first clock signal and the second clock signal described above are the same clock signal.

[0067] Among them, the clock buffer 7 is connected to the first main board 1 through the first cable 3 and is used to send the first clock signal to the first main board 1 through the first cable 3; the clock buffer 7 is connected to the second main board 2 through the second cable 4 and is used to send the second clock signal to the second main board 2 through the second cable 4.

[0068] Specifically, the descriptions of the first main board 1, the second main board 2, the first cable 3, and the second cable 4 can refer to Figure 1 the description of the illustrated embodiment, which will not be elaborated here. As described above for the clock buffer 7, the clock buffer 7 can expand the initial clock signal into two paths, namely the first clock signal and the second clock signal. After the clock buffer 7 generates the first clock signal and the second clock signal, at the same time, the first clock signal is sent to the first main board 1 through the first cable 3, and the second clock signal is sent to the second main board 2 through the second cable 4.

[0069] Optionally, the first main board 1 includes a first main board controller 8, and the second main board 2 includes a second main board controller 9; among them, the first main board controller 8 is connected to the clock buffer 7 through the first cable 3 and is used to receive the first clock signal, receive and / or send data signals through the first cable 3; the second main board controller 9 is connected to the clock buffer 7 through the second cable 4 and is used to receive the second clock signal, receive and / or send data signals through the second cable 4.

[0070] Specifically, the first main board controller 8 is a device for controlling in the first main board 1. In addition to controlling the first main board 1 to perform the data transmission process described above, the first main board controller 8 also controls the first main board 1 to implement other functions of the first main board 1, such as processes of data processing for the data to be sent or the received data, etc. The second main board controller 9 is a device for controlling in the second main board 2. Similar to the description of the first main board controller 8 above, in addition to controlling the second main board 2 to perform the data transmission process described above, the second main board controller 9 also controls the second main board 2 to implement other functions of the second main board 2, such as processes of data processing for the data to be sent or the received data, etc.

[0071] Optionally, the first main board 1 further includes a first connector 10; the first connector 10 is connected to the first main board controller 8 through a circuit board clock line 15 for transmitting a first clock signal; the first connector 10 is connected to the first main board controller 8 through a circuit board bus 14 for transmitting a data signal; the first connector 10 is connected to a clock buffer 7 through a first cable 3 for transmitting the first clock signal and the data signal.

[0072] Specifically, the circuit board clock line 15 is a type of circuit board trace for transmitting the clock signal described above, and the circuit board bus 14 is a type of circuit board trace for transmitting the data signal described above. Specifically, a connector is a device for realizing signal transmission between various devices in the data transmission system 100 through various transmission lines. Among them, the first connector 10 is a connector provided in the first main board 1. The first connector 10 includes a plurality of ports. The present invention does not limit the number of ports included in the first connector 10. Optionally, the first connector 10 may include three ports. One port is connected to the first cable 3 for transmitting the first clock signal sent by the clock synchronization backplane 5, or the data signal sent by the clock synchronization backplane 5, or transmitting the data signal to the clock synchronization backplane 5; another port is connected to the circuit board clock line 15 for transmitting the first clock signal to the clock synchronization backplane 5; the remaining one port is connected to the circuit board bus 14 for transmitting the data signal to the first main board controller 8, or transmitting the data signal sent by the first main board controller 8.

[0073] Optionally, the second main board 2 further includes a second connector 11; the second connector 11 is connected to the second main board controller 9 through a circuit board clock line 15 for transmitting a second clock signal; the second connector 11 is connected to the second main board controller 9 through a circuit board bus 14 for transmitting a data signal; the second connector 11 is connected to the clock buffer 7 through a second cable 4 for transmitting the second clock signal and the data signal.

[0074] Specifically, based on the above descriptions of the circuit board clock line 15, the circuit board bus 14, and the connectors, the second connector 11 is a connector disposed in the second main board 2. Among them, the second connector 11 includes a plurality of ports. The present utility model does not limit the number of ports included in the second connector 11. Optionally, the second connector 11 may include three ports. One port is connected to the second cable 4 and is used to transmit the second clock signal sent by the clock synchronization backplane 5, or transmit the data signal sent by the clock synchronization backplane 5, or transmit the data signal to the clock synchronization backplane 5. Another port is connected to the circuit board clock line 15 and is used to transmit the second clock signal to the clock synchronization backplane 5. The remaining one port is connected to the circuit board bus 14 and is used to transmit the data signal to the second main board controller 9, or transmit the data signal sent by the second main board controller 9.

[0075] Optionally, the clock synchronization backplane 5 further includes a third connector 12; the third connector 12 is connected to the clock buffer 7 through the circuit board clock line 15 and is used to transmit the first clock signal; the third connector 12 is connected to the first main board controller 8 through the first cable 3 and is used to transmit the first clock signal and the data signal.

[0076] Specifically, the third connector 12 is a connector disposed in the second main board 2. Among them, the third connector 12 includes a plurality of ports. The present utility model does not limit the number of ports included in the third connector 12. Optionally, the third connector 12 may include at least two ports. One port is connected to the first cable 3 and is used to transmit the first clock signal to the first main board 1, that is, transmit the first clock signal to the port of the first connector 10 connected to the first cable 3, so that the port of the first connector 10 connected to the circuit board clock line 15 transmits the first clock signal to the first main board controller 8, or transmit the data signal to the first main board 1, that is, transmit the data signal to the port of the first connector 10 connected to the first cable 3, so that the port of the first connector 10 connected to the circuit board bus 14 transmits the data signal to the first main board controller 8, or transmit the data signal sent by the first main board 1. Another port is connected to the circuit board clock line 15 and is used to transmit the first clock signal sent by the clock buffer 7.

[0077] Optionally, the clock synchronization backplane 5 further includes a fourth connector 13; the fourth connector 13 is connected to the clock buffer 7 through the circuit board clock line 15 and is used to transmit the first clock signal; the fourth connector 13 is connected to the second main board controller 9 through the second cable 4 and is used to transmit the second clock signal and the data signal; the fourth connector 13 is connected to the third connector 12 through the circuit board bus 14 and is used to transmit the data signal.

[0078] Specifically, the fourth connector 13 is another connector disposed in the second main board 2. The fourth connector 13 includes a plurality of ports. The present utility model does not limit the number of ports included in the fourth connector 13. Optionally, the fourth connector 13 may include three ports. One port is connected to the second cable 4 for transmitting a second clock signal to the second main board 2, that is, transmitting the second clock signal to the port of the second connector 11 connected to the second cable 4, so that the port of the second connector 11 connected to the circuit board clock line 15 transmits the second clock signal to the second main board controller 9, or transmitting a data signal to the second main board 2, that is, transmitting the data signal to the port of the second connector 11 connected to the second cable 4, so that the port of the second connector 11 connected to the circuit board bus 14 transmits the data signal to the second main board controller 9, or transmitting the data signal sent by the second main board 2; Another port is connected to the circuit board clock line 15 for transmitting the second clock signal sent by the clock buffer 7; The remaining one port is connected to the circuit board bus 14 to be connected to one port of the third connector 12 described above. Here, one port of the third connector 12 described here is one port other than the two ports of the third connector 12 described above. The functions of the port of the third connector 12 and the remaining one port described in the fourth connector 13 are both for completing data transmission between the two connectors included in the clock backplane. Specifically, the remaining one port described in the fourth connector 13 is for transmitting the data signal transmitted by the corresponding port of the third connector 12, or transmitting the data signal to the corresponding port of the third connector 12. The corresponding port of the third connector 12 is for transmitting the data signal transmitted by the remaining one port described in the fourth connector 13, or transmitting the data signal to the remaining one port described in the fourth connector 13.

[0079] Optionally, the lengths and / or materials of the first cable 3, the second cable 4, the circuit board clock line 15 and the circuit board bus 14 included in the first main board 1, the circuit board clock line 15 and the circuit board bus 14 included in the second main board 2, and the circuit board clock line 15 and the circuit board bus 14 included in the clock synchronization backplane 5 are set such that the transmission delay increment of transmitting the data signal is less than a preset transmission delay increment threshold. Specifically, the present utility model does not limit the lengths and materials of the connecting lines in the data transmission system 100, that is, the lengths of the first cable 3 and the second cable 4, and the lengths and materials of the circuit board clock lines 15 and the circuit board buses 14 included in the first main board 1, the second main board 2, and the clock synchronization backplane 5. Any setting of the lengths and materials of the connecting lines that can make the transmission delay increment of the data signal received by the data receiving end less than the preset transmission delay increment threshold can be used as the setting of the lengths and materials of the connecting lines provided in this application.

[0080] Among them, the calculation of the transmission delay increment of the data signal is obtained by the data receiving end. For example, if the second main board 2 is the main board of the data sending end and the first main board 1 is the main board of the data receiving end, then the first main board 1 can calculate the transmission delay increment of the received data signal.

[0081] Specifically, the calculation process of the transmission delay increment of the data signal received by the data receiving end is as follows:

[0082] First, determine the reference clock signal. For example, if the second main board 2 is the main board of the data sending end and the first main board 1 is the main board of the data receiving end, then the first clock signal is the reference clock signal.

[0083] Secondly, determine the transmission delay increment when each clock signal and data signal are transmitted on each connection line of the data transmission system 100. Among them, when the clock signal or data signal is transmitted on different types of connection lines, the transmission delay increment generated per unit length is different. For example, if the clock signal or data signal is transmitted in the cable, the transmission delay increment generated per unit length is 0.133 ns. If the clock signal or data signal is transmitted on the circuit board trace, such as in the circuit board clock line 15 or the circuit board bus 14, the transmission delay increment generated per unit length is 0.165 ns. Therefore, the lengths of each connection line of the data transmission system 100 and the connection lines on which each clock signal and data signal are transmitted can be obtained, and then according to the transmission delay increment generated per unit length when the clock signal or data signal is transmitted on different types of connection lines described above, determine the transmission delay increment when each clock signal and data signal are transmitted on each connection line of the data transmission system 100. For example, if the second main board 2 is the main board of the data sending end and the first main board 1 is the main board of the data receiving end, the connection lines on which each clock signal and data signal are transmitted are: the first clock signal is transmitted on the first cable 3, the circuit board clock line 15 between the clock buffer 7 and the third connector 12 in the clock synchronization backplane 5, and the circuit board clock line 15 between the first connector 10 and the first main board controller 8 in the first main board 1; the second clock signal is transmitted on the second cable 4, the circuit board clock line 15 between the clock buffer 7 and the fourth connector 13 in the clock synchronization backplane 5, and the circuit board clock line 15 between the second connector 11 and the second main board controller 9 in the second main board 2; the data signal is transmitted on the circuit board bus 14 between the second connector 11 and the second main board controller 9 in the second main board 2, the second cable 4, the circuit board bus 14 between the fourth connector 13 and the third connector 12 in the clock synchronization backplane 5, the first cable 3, and the circuit board bus 14 between the first connector 10 and the first main board controller 8 in the first main board 1.

[0084] Finally, based on the determined reference clock signal and the transmission delay increments of each clock signal and data signal on each connection line of the data transmission system 100, determine the transmission delay increment of the data signal received by the data receiving end. For example: If the second main board 2 is the main board of the data sending end and the first main board 1 is the main board of the data receiving end, and the first clock signal is determined as the reference clock signal, the sum of the transmission delay increments of the second clock signal on each connection line of the data transmission system 100 and the transmission delay increments of the data signal on each connection line of the data transmission system 100 can be calculated first, and then the difference between it and the transmission delay increment of the first clock signal on each connection line of the data transmission system 100 is determined as the transmission delay increment of the data signal received by the first main board 1.

[0085] Optionally, according to the above description of the calculation process of the transmission delay increment of the data signal received by the data receiving end, the transmission delay increment of the data signal received by the data receiving end can be reduced by adjusting the lengths of the connection lines in the data transmission system 100, thereby improving the signal quality of data transmission. Among them, the adjustment of the cable length can be carried out by directly replacing cables of different lengths, and the adjustment of the circuit board trace length can be carried out by adjusting the positions of the components in the circuit board or the routing direction of the circuit board traces. For example: The length of the circuit board traces in the first main board 1 can be adjusted by adjusting the position of the first controller and / or the first connector 10, or adjusting the routing direction of the circuit board clock line 15, or adjusting the routing direction of the circuit board bus 14; For example: The length of the circuit board traces in the second main board 2 can be adjusted by adjusting the position of the second controller and / or the second connector 11, or adjusting the routing direction of the circuit board clock line 15, or adjusting the routing direction of the circuit board bus 14; For example: The length of the circuit board traces in the clock synchronization backplane 5 can be adjusted by adjusting the position of the clock buffer 7 and / or the third connector 12 and / or the fourth connector 13, or adjusting the routing direction of the circuit board clock line 15, or adjusting the routing direction of the circuit board bus 14.

[0086] Optionally, according to the above description of the transmission delay increment per unit length when the clock signal or data signal is transmitted on different types of connection lines, for the same type of connection line, when the raw materials of the connection line are different, the transmission delay increment per unit length is also different. Optionally, according to the above description of the calculation process of the transmission delay increment of the data signal received by the data receiving end, the transmission delay increment of the data signal received by the data receiving end can be reduced by adjusting the raw materials of the connection lines in the data transmission system 100, for example: adjusting the raw materials of the circuit board or cable, thereby improving the signal quality of data transmission.

[0087] Optionally, according to the above description of the calculation process of the transmission delay increment of the data signal received by the data receiving end, the lengths and raw materials of the connecting lines in the data transmission system 100 can be adjusted to reduce the transmission delay increment of the data signal received by the data receiving end, thereby improving the signal quality of data transmission.

[0088] The data transmission system provided in this embodiment, on the basis of the embodiment shown in Figure 1 further elaborates on the specific compositions of the first main board, the second main board, and the clock synchronization backplane, and improves the signal quality of data transmission by setting the lengths and / or materials of the connecting lines, the first cable, and the second cable in the elaborated specific compositions.

[0089] In a possible embodiment, at least one of the first main board 1 and the second main board 2 is a server main board. Specifically, based on the description in the embodiment shown in Figure 1 there is a main control device main board and a slave control device main board among the first main board 1 and the second main board 2, where the main control device main board is used to control the data transmission direction. Therefore, at least one of the first main board 1 and the second main board 2 is a server main board. Specifically, if there is a server main board among the first main board 1 and the second main board 2, it is determined as the main controller's main board; if both the first main board 1 and the second main board 2 are server main boards, one of the server main boards is determined as the main controller's main board, and the other server main board is determined as the slave server's main board.

[0090] In a possible embodiment, on the basis of the embodiment shown in Figure 1 or Figure 2 the system further includes at least one third main board and at least one third cable; where the third main board and the third cable correspond one by one; each third cable is respectively connected to the corresponding third main board and the clock synchronization backplane 5 for transmitting the third clock signal and the data signal.

[0091] Specifically, the description of the third main board and the third cable can refer to the description of the first main board 1, the second main board 2, the first cable 3, and the second cable 4 in the embodiment shown in Figure 1 or Figure 2 and will not be elaborated here. If the data transmission system 100 includes a third main board and a third cable, the data signal in the data transmission system 100 is transmitted among the first main board 1, the second main board 2, and at least one third main board.

[0092] If the data transmission system 100 includes a third main board and a third cable, the flexibility of the architecture of the data transmission system 100 can be improved in the case of including at least three data transmission terminals.

[0093] In a possible embodiment, optionally, each third main board includes a third main board controller and a fifth connector; wherein, the fifth connector is connected to the third main board controller through the circuit board clock line 15 for transmitting a third clock signal; the fifth connector is connected to the third main board controller through the circuit board bus 14 for transmitting data signals; the fifth connector is connected to the clock synchronization backplane 5 through the corresponding third cable for transmitting the third clock signal and data signals.

[0094] Specifically, for the description of the fifth connector, reference can be made to Figure 1 or Figure 2 the description of the first connector 10 and the second connector 11 in the illustrated embodiment, which will not be elaborated here. For the description of the third clock signal, reference can be made to Figure 1 or Figure 2 the description of the first clock signal and the second clock signal in the illustrated embodiment, which will not be elaborated here. Wherein, if the data transmission system 100 includes a third main board and a third cable, the clock synchronization backplane 5 of the data transmission system 100 further includes at least one sixth connector, wherein the sixth connector corresponds to the third cable and the third main board one by one, and the sixth connector is used to connect to the fifth connector of the corresponding third main board through the corresponding third cable; the sixth connector is further used to connect to the clock buffer 7 through the circuit board clock line 15 for transmitting the third clock signal transmitted by the clock buffer 7; the sixth connector is further used to connect to each of the first connector 10, the second connector 11 and other sixth connectors in the clock synchronization backplane 5 through the circuit board bus 14 for transmitting and / or receiving the data signals sent by it. Wherein, the third clock signal is obtained by the clock buffer 7 after expanding and processing the initial clock signal, and the third clock signal corresponds to the number of sixth connectors one by one.

[0095] Wherein, as described in the above embodiment, the lengths and / or materials of the circuit board clock line 15 and the circuit board bus 14 included in the first cable 3, the second cable 4, the first main board 1, the circuit board clock line 15 and the circuit board bus 14 included in the second main board 2, and the circuit board clock line 15 and the circuit board bus 14 included in the clock synchronization backplane 5 are set such that the transmission delay increment of the transmitted data signal is less than a preset transmission delay increment threshold. On this basis, the lengths and / or materials of at least one third cable and the circuit board clock line 15 and the circuit board bus 14 included in at least one third main board can also be set such that the transmission delay increment of the transmitted data signal is less than the preset transmission delay increment threshold to improve the signal quality of the data transmission system 100.

[0096] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0097] In the description of this specification, the description with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present utility model. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present utility model, rather than to limit them; although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present utility model.

Claims

1. A data transmission system, characterized in that: include: A first mainboard, a second mainboard, a first cable, a second cable, and a clock synchronization backplane; The first cable is connected to the first mainboard and the clock synchronization backplane respectively, and is used to transmit a first clock signal and a data signal; The second cable is connected to the second mainboard and the clock synchronization backplane respectively, and is used for transmitting a second clock signal and the data signal.

2. The system according to claim 1, characterized in that The clock synchronization backplane includes a clock generator and a clock buffer; Wherein, the clock buffer is connected to the clock generator and is used to receive the initial clock signal sent by the clock generator; The clock buffer is connected to the first mainboard via the first cable, and is used to send the first clock signal to the first mainboard via the first cable; The clock buffer is connected to the second mainboard via the second cable, and is used for sending the second clock signal to the second mainboard via the second cable.

3. The system according to claim 2, characterized in that The first mainboard includes a first mainboard controller, and the second mainboard includes a second mainboard controller; Wherein, the first mainboard controller is connected to the clock buffer via the first cable, and is used to receive the first clock signal, and receive and / or send the data signal via the first cable; The second mainboard controller is connected to the clock buffer via the second cable, and is used for receiving the second clock signal and receiving and / or sending the data signal via the second cable.

4. The system according to claim 3, characterized in that The first mainboard also includes a first connector; The first connector is connected to the first mainboard controller via a circuit board clock line, and is used to transmit the first clock signal; The first connector is connected to the first mainboard controller via a circuit board bus and is used to transmit the data signal; The first connector is connected to the clock buffer through the first cable, and is used for transmitting the first clock signal and the data signal.

5. The system according to claim 3, characterized in that The second mainboard also includes a second connector; The second connector is connected to the second mainboard controller via a circuit board clock line, and is used to transmit the second clock signal; The second connector is connected to the second mainboard controller via a circuit board bus and is used to transmit the data signal; The second connector is connected to the clock buffer through the second cable and is used for transmitting the second clock signal and the data signal.

6. The system according to claim 3, characterized in that The clock synchronization backplane also includes a third connector; The third connector is connected to the clock buffer via a circuit board clock line and is used to transmit the first clock signal; The third connector is connected to the first mainboard controller through the first cable, and is used for transmitting the first clock signal and the data signal.

7. The system according to claim 6, characterized in that The clock synchronization backplane also includes a fourth connector; The fourth connector is connected to the clock buffer via a circuit board clock line and is used to transmit the first clock signal; The fourth connector is connected to the second mainboard controller through the second cable, and is used to transmit the second clock signal and the data signal; The fourth connector is connected to the third connector via a circuit board bus and is used to transmit the data signal.

8. The system according to any one of claims 1 to 7, characterized in that: The length and / or material of the first cable, the second cable, the circuit board clock line and circuit board bus included in the first main board, the circuit board clock line and circuit board bus included in the second main board, and the circuit board clock line and circuit board bus included in the clock synchronization backplane are set so that the transmission delay increment of transmitting the data signal is less than a preset transmission delay increment threshold.

9. The system according to claim 8, characterized in that At least one of the first mainboard and the second mainboard is a server mainboard.

10. The system according to claim 9, characterized in that The system further comprises at least one third mainboard and at least one third cable; wherein the third mainboard and the third cable correspond one to one; Each of the third cables is respectively connected to the corresponding third mainboard and the clock synchronization backplane for transmitting a third clock signal and the data signal; Wherein, each of the third mainboards comprises a third mainboard controller and a fifth connector; The fifth connector is connected to the third mainboard controller via a circuit board clock line, and is used to transmit the third clock signal; The fifth connector is connected to the third mainboard controller via a circuit board bus and is used to transmit the data signal; The fifth connector is connected to the clock synchronization backplane through the corresponding third cable, and is used for transmitting the third clock signal and the data signal.

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