Display substrate, display panel and display device

Abstract

The embodiment of the utility model provides a display substrate, a display panel and a display device. The display substrate comprises a first conducting layer, a first insulating layer, a second conducting layer, a second insulating layer and a third conducting layer which are sequentially arranged on one side of a substrate in a stacked mode, the first conducting layer comprises at least one conducting block, the second conducting layer comprises a first conducting wire, the first conducting wire comprises a lap joint boundary, and the third conducting layer comprises at least one second conducting block. The first via hole comprises a middle sub-hole and end sub-holes located on the two sides of the middle sub-hole, and the lap joint boundary penetrates through the middle sub-hole; the third conducting layer comprises a first connecting part, the first connecting part is connected with the exposed surface of the first conducting wire through a first via hole and connected with the exposed surface of the conducting block, and the first distance corresponding to the middle sub-hole is larger than the second distance corresponding to the end sub-hole. According to the display substrate, the connecting area of the parts, located on the two sides of the lap joint boundary, of the first connecting part is increased, and poor electric conduction of the first connecting part is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a display panel, and a display device. Background Art

[0002] TDDI (Touch and Display Driver Integration) technology integrates touch sensing and display driving functions in a single chip. In TDDI technology, self-capacitance mode is generally adopted for touch sensing, and touch electrode blocks are connected to touch signal lines. Since the touch electrode blocks and the touch signal lines are located on different layers, usually, the touch electrode blocks and the touch signal lines are connected by a connection portion that straddles and is located on different layers from both the touch electrode blocks and the touch signal lines. In such a connection manner, poor connection between the touch electrode blocks and the touch signal lines often occurs, reducing touch performance. Summary of the Utility Model

[0003] Embodiments of the present disclosure provide a display substrate, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display substrate, including:

[0005] A substrate;

[0006] A first conductive layer located on one side of the substrate, the first conductive layer including at least one conductive block;

[0007] A first insulating layer located on the side of the first conductive layer facing away from the substrate;

[0008] A second conductive layer located on the side of the first insulating layer facing away from the substrate, the second conductive layer including a first conductive trace, the first conductive trace including a lapping boundary, and a projection edge of the lapping boundary on the substrate is located within the projection of the conductive block on the substrate;

[0009] A second insulating layer located on the side of the second conductive layer facing away from the substrate, the display substrate being provided with a first via hole, the first via hole including an intermediate sub-hole and end sub-holes located on both sides of the intermediate sub-hole in a direction perpendicular to the lapping boundary, the projection edge of the lapping boundary on the substrate passes through the projection of the intermediate sub-hole on the substrate, a part of the first via hole on one side of the lapping boundary penetrates through the second insulating layer to expose a part of the surface of the first conductive trace, and a part of the first via hole on the other side of the lapping boundary penetrates through the second insulating layer and the first insulating layer to expose a part of the surface of the conductive block;

[0010] The third conductive layer is located on the side of the second insulating layer away from the substrate. The third conductive layer includes a first connection portion. The orthographic projection of the first via hole on the substrate is located inside the orthographic projection of the first connection portion on the substrate. The first connection portion is connected to the exposed surface of the first conductive trace through the first via hole and is also connected to the exposed surface of the conductive block. The first distance corresponding to the middle sub-hole is greater than the second distance corresponding to the end sub-hole. The first distance is the distance between the outer boundary of the middle sub-hole and the corresponding outer boundary of the first connection portion, and the second distance is the distance between the outer boundary of the end sub-hole and the corresponding outer boundary of the first connection portion.

[0011] In some embodiments, the shape of the first via hole is a long strip extending in the second direction. The first distance is the distance between the outer boundary of the middle sub-hole parallel to the second direction and the corresponding outer boundary of the first connection portion, and the second distance is the distance between the outer boundary of the end sub-hole parallel to the second direction and the corresponding outer boundary of the first connection portion. The second direction is perpendicular to the overlapping boundary.

[0012] In some embodiments, the first via hole has a first axis, and the first axis is perpendicular to the direction of the overlapping boundary. The outer boundary of the middle sub-hole is the outer boundary of the middle sub-hole on both sides of the first axis, and the outer boundary of the end sub-hole is the outer boundary of the end sub-hole on both sides of the first axis. The outer boundary of the middle sub-hole is closer to the first axis than the outer boundary of the end sub-hole.

[0013] In some embodiments, the first via hole satisfies at least one of the following:

[0014] The distance between the outer boundary of the middle sub-hole and the outer boundary of the end sub-hole is greater than or equal to 0.5 μm;

[0015] The dimension of the middle sub-hole in the direction parallel to the first axis is greater than or equal to 3.2 μm;

[0016] The dimension of the middle sub-hole in the direction parallel to the overlapping boundary is greater than or equal to 3 μm;

[0017] The dimension of the end sub-hole in the direction parallel to the first axis is greater than or equal to 3 μm.

[0018] In some embodiments, the first connection portion includes a connection portion body and lugs located on both sides of the connection portion body. The lugs correspond to the middle sub-holes, and the first distance is the distance between the outer boundary of the middle sub-hole and the outer boundary of the corresponding lug.

[0019] In some embodiments, the lugs satisfy at least one of the following:

[0020] The dimension of the lug in the direction parallel to the overlapping boundary is greater than or equal to 0.5 μm;

[0021] The dimension of the lug in a direction perpendicular to the overlapping boundary is greater than or equal to 3.2 μm.

[0022] In some embodiments, the intermediate sub-hole includes a concave portion, and the concave portion is formed by removing a part of the material of the first insulating layer sandwiched between the first conductive trace and the conductive block along the overlapping boundary.

[0023] In some embodiments, the substrate includes a plurality of sub-pixel regions arranged in an array, the conductive block includes a plurality of connected sub-electrode blocks, the sub-electrode blocks are located in the sub-pixel regions, the conductive block further includes a second connecting portion connected to the sub-electrode blocks, and the orthographic projection edge line of the overlapping boundary on the substrate is located within the orthographic projection of the second connecting portion on the substrate;

[0024] The substrate includes a thin film transistor, and the third conductive layer further includes a pixel electrode located in the sub-pixel region, and the pixel electrode is connected to the thin film transistor through a second via hole.

[0025] In some embodiments, the first conductive trace extends along a first direction and is located between two adjacent columns of sub-pixel regions, and the first via hole is located between two adjacent rows of sub-pixel regions.

[0026] In some embodiments, the substrate includes a plurality of signal lines extending along a first direction and a plurality of gate lines extending along a second direction, the plurality of signal lines and the plurality of gate lines intersect with each other to define a plurality of sub-pixel regions, and the orthographic projection of the first conductive trace and the corresponding signal line on the substrate has an overlap.

[0027] In some embodiments, the material of the first conductive layer is a transparent conductive material, the material of the third conductive layer is a transparent conductive material, and the material of the second conductive layer is a metal material;

[0028] The substrate includes a substrate, a thin film transistor structure layer on one side of the substrate, a buffer layer on the side of the thin film transistor structure layer away from the substrate, an organic planarization layer on the side of the buffer layer away from the substrate, and the first conductive layer is located on the side of the organic planarization layer away from the substrate.

[0029] In some embodiments, the display substrate is applied to a display panel, a common voltage signal is applied to the conductive block during the display of a frame image of the display panel, and a touch signal is applied to the conductive block between two frame images of the display panel.

[0030] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel, including the display substrate of the present disclosure, further including a counter substrate disposed opposite to the display substrate, and the display panel further includes liquid crystal located between the display substrate and the counter substrate.

[0031] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including the display substrate of the present disclosure, or including the display panel of the present disclosure.

[0032] In the technical solution of the embodiments of the present disclosure, the first via hole includes an intermediate sub-hole and end sub-holes located on both sides of the intermediate sub-hole in a direction perpendicular to the overlapping boundary. The orthographic projection edge line of the overlapping boundary on the substrate passes through the orthographic projection of the intermediate sub-hole on the substrate. By setting the first distance corresponding to the intermediate sub-hole to be greater than the second distance corresponding to the end sub-holes, the connection width of the first connection portion in the extending direction of the overlapping boundary is increased. Thus, even if there is a concave portion along the overlapping boundary in the intermediate sub-hole, compared with the related art, the technical solution of the present disclosure still increases the connection area of the portions of the first connection portion located on both sides of the overlapping boundary, reduces the overlapping defect of the first connection portion, improves the conductive performance of the conductive block and the first conductive trace connected through the first connection portion, reduces the connection defect, and improves the performance of the display substrate.

[0033] The above summary is only for the purpose of the specification and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0035] Figure 1 It is a schematic plan view of a TDDI product;

[0036] Figure 2 It is a schematic cross-sectional view of another TDDI display substrate at the first via hole;

[0037] Figure 3A For Figure 2 It is a schematic plan view of the position of the first via hole in the shown display substrate;

[0038] Figure 3B For Figure 3A It is a schematic view in an actual product;

[0039] Figure 4 It is a schematic process view of forming the first via hole;

[0040] Figure 5 It is a schematic cross-sectional view of the display substrate at the position of the first via hole in an embodiment of the present disclosure;

[0041] Figure 6 is Figure 5 a schematic plan view showing the position of the first via hole on the substrate in one embodiment;

[0042] Figure 7 is Figure 5 a schematic plan view showing the position of the first via hole on the substrate in another embodiment;

[0043] Figure 8 a partial schematic plan view showing the substrate in another embodiment of the present disclosure;

[0044] Figure 9 is Figure 8 the schematic cross-sectional view taken along line B-B in

[0045] Figure 10 a schematic cross-sectional view showing the substrate after forming a substrate substrate in one embodiment of the present disclosure;

[0046] Figure 11A a schematic cross-sectional view showing the substrate after forming a first via hole pattern and a second via hole pattern in one embodiment of the present disclosure;

[0047] Figure 11B a schematic cross-sectional view showing the substrate after forming a first via hole and a second via hole in one embodiment of the present disclosure.

[0048] Explanation of reference numerals:

[0049] 10. Substrate substrate; 21. First conductive layer; 210. Conductive block / touch electrode block; 211. Sub-electrode block; 212. Second connection part; 213. Third connection part; 22. First insulating layer; 23. Second conductive layer; 231. First conductive trace; 24. Second insulating layer; 25. Third conductive layer; 251. First connection part; 252. Pixel electrode. Detailed Description of the Invention

[0050] In the following, only some exemplary embodiments are briefly described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure, and different embodiments can be arbitrarily combined without conflict. Therefore, the drawings and the description are considered to be exemplary in nature rather than restrictive.

[0051] Figure 1 is a schematic plan view of a TDDI product. As Figure 1As shown in FIG. 1 , in a TDDI product, the common electrode layer is divided into different touch electrode blocks 210, and each touch electrode block 210 is connected to the control module COF through a touch signal line Tx. When a finger touches, the capacitance of the touch electrode block 210 changes, and the capacitance change is transmitted to the control module COF through the touch signal line. The control module COF accurately determines the position of the touched touch electrode block through the received signal, and then responds accordingly.

[0052] In one TDDI display substrate, the touch signal line Tx is arranged on the same layer as the data line. However, as the demand for narrow borders from end customers continues to increase, the solution of arranging the touch signal line Tx and the data line on the same layer can no longer meet customer needs due to the large space occupied. In another TDDI display substrate, the touch signal line Tx is arranged on a separate layer, and the touch signal line Tx is connected to the touch electrode block 210 through a first connection portion arranged across the first via position.

[0053] Figure 2 is a cross-sectional schematic diagram of another TDDI display substrate at the first via hole, Figure 3A for Figure 2 The schematic plan view showing the position of the first via hole in the display substrate is shown. Figure 3B for Figure 3A Schematic diagram of the actual product. It should be noted that in this article, in order to more clearly illustrate each film layer, the filling form of each film layer in the plan view is different from the filling form in the cross-sectional view, and the label of each feature shall prevail. Figure 2 As shown, the display substrate includes a base substrate 10 , and the display substrate also includes a first conductive layer 21 , a first insulating layer 22 , a second conductive layer 23 , and a second insulating layer 24 .

[0054] The first conductive layer 21 may be a common electrode layer, the first conductive layer 21 is located on one side of the base substrate 10, and the first conductive layer 21 includes a touch electrode block. The first insulating layer 22 is located on the side of the common electrode layer away from the base substrate 10. The material of the second conductive layer 23 may be a metal material, and the second conductive layer 23 is located on the side of the first insulating layer 22 away from the base substrate 10. The second conductive layer 23 may include a touch signal line Tx. The orthographic projection of the touch signal line Tx on the base substrate 10 and the orthographic projection of the touch electrode block 210 on the base substrate 10 have an overlapping area. The second insulating layer 24 is located on the side of the second conductive layer 23 away from the base substrate 10.

[0055] like Figure 2 and Figure 3AAs shown, the display substrate is provided with a first via K1. A part of the orthographic projection of the first via K1 on the substrate 10 is located within the orthographic projection of the touch signal line Tx on the substrate 10, and another part of the orthographic projection of the first via K1 on the substrate 10 is located within the orthographic projection of the touch electrode block on the substrate 10. The first via K1 is formed by etching the second insulating layer 24 and the first insulating layer 22. Thus, the part of the first via K1 located on the touch signal line Tx exposes a part of the surface of the touch signal line Tx, and the part of the first via K1 located on the touch electrode block 210 exposes a part of the surface of the touch electrode block 210.

[0056] Exemplarily, as Figure 3A shown, the shape of the first via K1 can be rectangular. The width (horizontal dimension) of the first via K1 is about 4 μm, and the length (vertical dimension) of the first via K1 is about 6 μm.

[0057] Figure 4 is a schematic diagram of the process for forming the first via. As Figure 4 shown, Figure 4 (a) in is a schematic diagram before etching. There is photoresist 00 above the second insulating layer 2424, and the photoresist has a first via K1 pattern K1'. When forming the first via K1 using an etching process, the second insulating layer 24 within the first via K1 is first etched away to form Figure 4 (b) in. In (b), a part of the surface of the touch signal line Tx is exposed through the first via K1. Continuing the etching, the first insulating layer 22 within the first via K1 above the touch electrode block 210 is etched away to form Figure 4 (c) in. In (c), a part of the surface of the touch electrode block is exposed through the first via K1. When etching the first insulating layer 22, due to the isotropic nature of chemical etching, the first insulating layer 22 located below the touch signal line 141 is etched inward to form the concave portion K10 of the first via K1.

[0058] As Figure 2 shown, the display substrate further includes a third conductive layer 25, and the third conductive layer 25 can be a pixel electrode layer. The third conductive layer 25 includes pixel electrodes 252 and may further include a first connection portion 251. The orthographic projection of the first via K1 on the substrate 10 is located within the orthographic projection of the first connection portion 251 on the substrate 10. Thus, the third part 251a of the first connection portion 251 is connected to the touch signal line Tx through the first via K1, and the fourth part 251b of the first connection portion 251 is connected to the touch electrode block 210 through the first via K1. Therefore, the touch signal line Tx and the touch electrode block 210 are connected through the first connection portion 251.

[0059] As Figure 2 andFigure 3B As shown, due to the existence of the concave portion K10, when forming the first connection portion 251, poor lap joint of the first connection portion 251 often occurs, resulting in fracture at the position of the first connection portion 251 corresponding to the concave portion K10. Figure 3B The corresponding fracture opening DL is shown in FIG. The existence of the fracture opening DL reduces the connection area between the third portion 251a and the fourth portion 251b of the first connection portion 251, resulting in poor connection between the touch electrode block and the touch signal line 141, and reducing the performance of the display substrate.

[0060] Figure 5 FIG. is a cross-sectional schematic view of the display substrate at the first via position in an embodiment of the present disclosure. Figure 6 is Figure 5 a plan view of the display substrate at the first via position in one embodiment of FIG. Figure 7 is Figure 5 a plan view of the display substrate at the first via position in another embodiment of FIG. Figure 5 may be Figure 6 or Figure 7 the A-A cross-sectional schematic view in FIG. Figure 6 and Figure 7 The lap joint boundary 231a is schematically shown by a thick dashed line in FIG. As shown in FIG. Figure 5 The display substrate may include a substrate substrate 10, a first conductive layer 21, a first insulating layer 22, a second conductive layer 23, a second insulating layer 24, and a third conductive layer 25. Exemplarily, the substrate substrate 10 may be a substrate including a multi-layer structure or a single-layer structure. For example, the substrate substrate 10 may be a substrate 11.

[0061] Among them, the first conductive layer 21 is located on one side of the substrate substrate 10, and the first conductive layer 21 includes at least one conductive block 210. Exemplarily, the first conductive layer 21 may include a plurality of conductive blocks 210. The first insulating layer 22 is located on the side of the first conductive layer 21 facing away from the substrate substrate 10.

[0062] The second conductive layer 23 is located on the side of the first insulating layer 22 facing away from the substrate substrate 10. The second conductive layer 23 includes a first conductive trace 231, and the first conductive trace 231 includes a lap joint boundary 231a. The projection edge line of the lap joint boundary 231a on the substrate substrate 10 is located within the projection of the conductive block 210 on the substrate substrate 10. Exemplarily, the lap joint boundary 231a is a part of the boundary of the first conductive trace 231, and the lap joint boundary 231a may be the part of the first conductive trace boundary within the range of the conductive block 210. Thus, the projection edge line of the lap joint boundary 231a on the substrate substrate 10 is located within the projection of the conductive block 210 on the substrate substrate 10.

[0063] The second insulating layer 24 is located on the side of the second conductive layer 23 away from the substrate 10. As Figures 5 - 7 shown, the display substrate is provided with a first via K1. The first via K1 includes an intermediate sub-via K11 and end sub-vias K12 located on both sides of the intermediate sub-via K11 in a direction perpendicular to the overlapping boundary 231a. For example, in Figure 6 and Figure 7 , the number of end sub-vias K12 is two, namely a first end sub-via K12a and a second end sub-via K12b. The first end sub-via K12a and the second end sub-via K12b are respectively located on opposite sides of the intermediate sub-via K11 in the second direction Y. In this article, the direction where the overlapping boundary 231a is located is referred to as the first direction X, and the direction perpendicular to the overlapping boundary 231a is referred to as the second direction Y.

[0064] As Figure 6 and Figure 7 shown, the orthographic projection edge line of the overlapping boundary 231a on the substrate 10 passes through the orthographic projection of the intermediate sub-via K11 on the substrate 10. Thus, the first via K1 is divided into two parts by the overlapping boundary 231a, namely a first part and a second part located on opposite sides of the overlapping boundary 231a. The first part includes the first end sub-via K12a and the part of the intermediate sub-via K11 between the overlapping boundary 231a and the first end sub-via K12a. The second part includes the second end sub-via K12b and the part of the intermediate sub-via K11 between the overlapping boundary 231a and the second end sub-via K12b. It can be seen from Figure 5 that the first part is located above the first conductive trace 231, and the second part is located above the conductive block 210. The orthographic projection of the first part on the substrate 10 is located within the orthographic projection of the first conductive trace 231 on the substrate 10, and the orthographic projection of the second part on the substrate 10 is located within the orthographic projection of the conductive block 210 on the substrate 10.

[0065] The part of the first via K1 on one side of the overlapping boundary 231a, that is, the first part, penetrates through the second insulating layer 24 to expose a part of the surface of the first conductive trace 231. The part of the first via K1 on the other side of the overlapping boundary 231a, that is, the second part, penetrates through the second insulating layer 24 and the first insulating layer 22 to expose a part of the surface of the conductive block 210.

[0066] The third conductive layer 25 is located on a side of the second insulating layer 24 facing away from the substrate 10. The third conductive layer 25 includes a first connection portion 251. A positive projection of the first via K1 on the substrate 10 is located inside a positive projection of the first connection portion 251 on the substrate 10. The first connection portion 251 is connected to an exposed surface of the first conductive trace 231 through the first via K1 and is connected to an exposed surface of the conductive block 210. A first distance D1 corresponding to the intermediate sub-via K11 is greater than a second distance D2 corresponding to the end sub-via K12. The first distance is a distance between an outer boundary of the intermediate sub-via K11 and a corresponding outer boundary of the first connection portion 251, and the second distance is a distance between an outer boundary of the end sub-via K12 and a corresponding outer boundary of the first connection portion 251.

[0067] Exemplarily, as Figure 6 and Figure 7 shown, outer boundaries of the intermediate sub-via K11 are boundary a1 and boundary b1 respectively, outer boundaries of the first connection portion 251 corresponding to the intermediate sub-via K11 are boundary a2 and boundary b2 respectively, the first distance is a distance between boundary a1 and boundary a2, and / or, the first distance is a distance between boundary b1 and boundary b2. Outer boundaries of the end sub-via K12 are boundary c1 and boundary d1 respectively, outer boundaries of the first connection portion 251 corresponding to the end sub-via K12 are boundary c2 and boundary d2 respectively, the second distance is a distance between boundary c1 and boundary c2, and / or, the second distance is a distance between boundary d1 and boundary d2.

[0068] In related technologies, as Figure 2 and Figure 3B shown, due to the existence of the concave portion K10, when forming the first connection portion 251, poor lap of the first connection portion 251 often occurs, resulting in a fracture opening DL at a position of the first connection portion 251 corresponding to the concave portion K10. The existence of the fracture opening DL reduces the connection area of the first connection portion 251, causes poor connection between the conductive block 210 (touch control electrode block) and the first conductive trace 231 (touch control signal line 141), and degrades the performance of the display substrate.

[0069] In the technical solution of the embodiment of the present disclosure, the first via K1 includes an intermediate sub-via K11 and end sub-vias K12 located on both sides of the intermediate sub-via K11 in a direction perpendicular to the overlapping boundary 231a. The orthographic projection edge line of the overlapping boundary 231a on the substrate 10 passes through the orthographic projection of the intermediate sub-via K11 on the substrate 10. By setting the first distance D1 corresponding to the intermediate sub-via K11 to be greater than the second distance D2 corresponding to the end sub-vias K12, the connection width of the first connection portion 251 in the extending direction of the overlapping boundary 231a is increased. Thus, even if there is a concave portion K10 extending along the overlapping boundary 231a in the intermediate sub-via K11, compared with the related art, the technical solution of the present disclosure still increases the connection area of the portions of the first connection portion 251 located on both sides of the overlapping boundary 231a, reduces the poor overlap of the first connection portion 251, improves the conductive performance of the conductive block 210 and the first conductive trace 231 connected through the first connection portion 251, reduces the connection failure, and improves the performance of the display substrate.

[0070] For example, the first connection portion 251 is divided into a third portion 251a and a fourth portion 251b by the overlapping boundary 231a. The third portion 251a is lap-connected to the first conductive trace 231 through the first part of the first via K1, and the fourth portion 251b is lap-connected to the conductive block 210 through the second part of the first via K1. When there is a concave portion K10 extending along the overlapping boundary 231a in the intermediate sub-via K11, there may be a fracture corresponding to the concave portion K10 between the third portion 251a and the fourth portion 251b. By setting the first distance D1 corresponding to the intermediate sub-via K11 to be greater than the second distance D2 corresponding to the end sub-vias K12, the connection width of the third portion 251a and the fourth portion 251b of the first connection portion 251 in the direction of the overlapping boundary 231a is increased. Thus, the connection area of the third portion 251a and the fourth portion 251b of the first connection portion 251 is increased, the poor overlap of the first connection portion 251 is reduced, the conductive performance of the conductive block 210 and the first conductive trace 231 connected through the first connection portion 251 is improved, the connection failure is reduced, and the performance of the display substrate is improved.

[0071] Exemplarily, the materials of the first conductive layer 21 and the third conductive layer 25 are both conductive materials, and their materials may be the same or different. The material of the second conductive layer 23 is a conductive material, and the material of the second conductive layer 23 may be the same or different from the material of the first conductive layer 21 or the second conductive layer 23.

[0072] In one embodiment, as Figure 6 and Figure 7As shown, the shape of the first via K1 can be a long strip extending along the second direction Y. The first distance D1 can be the distance between the outer boundary of the middle sub-via K11 parallel to the second direction Y and the corresponding outer boundary of the first connecting portion 251. The second distance D2 can be the distance between the outer boundary of the end sub-via K12 parallel to the second direction Y and the corresponding outer boundary of the first connecting portion 251. In Figure 6 and Figure 7 In the embodiments, the outer boundary of the middle sub-via K11 can be the outer boundary of the middle sub-via K11 parallel to the second direction Y, and the outer boundary of the end sub-via K12 can be the outer boundary of the end sub-via K12 parallel to the second direction Y. Exemplarily, the outer boundaries of the first connecting portion 251 on both sides of the first via K1 along the overlapping boundary 231a can be parallel to the second direction Y.

[0073] Figure 6 and Figure 7 show that the outer boundaries of the middle sub-via K11 are the boundaries a1 and b1 respectively, and the corresponding outer boundaries of the first connecting portion 251 with the middle sub-via K11 are the boundaries a2 and b2. The outer boundaries of the end sub-via K12 are the boundaries c1 and d1 respectively, and the corresponding outer boundaries of the first connecting portion 251 with the end sub-via K12 are the boundaries c2 and d2.

[0074] In other embodiments, the shape of the first via K1 can also be other shapes. For example, the shape of the first via K1 can be an ellipse with the major axis along the second direction Y; the shape of the first via K1 can also be a circular shape or the like.

[0075] The first via K1 can have a first axis Z1, and the first axis is perpendicular to the direction of the overlapping boundary 231a, that is, the first axis Z1 extends along the second direction Y. The outer boundary of the middle sub-via K11 can be the outer boundary of the middle sub-via K11 on both sides of the first axis Z1. The outer boundary of the middle sub-via K11 can be parallel to the first axis Z1. The outer boundary of the end sub-via K12 can be the outer boundary of the end sub-via K12 on both sides of the first axis Z1. The outer boundary of the end sub-via K12 can be parallel to the first axis Z1. As Figure 6 shown, the outer boundary of the middle sub-via K11 can be closer to the first axis Z1 relative to the outer boundary of the end sub-via K12. In this way, the length of the overlapping boundary 231a in the first via K1 can be shortened, thereby reducing the length of the concave portion K10 in the first direction X, relatively increasing the connection width of the third portion 251a and the fourth portion 251b of the first connecting portion 251 in the first direction X, and increasing the connection area of the third portion 251a and the fourth portion 251b of the first connecting portion 251.

[0076] In one embodiment, the distance between the outer boundary of the intermediate sub-hole K11 and the outer boundary of the end sub-hole K12 is greater than or equal to 0.5 μm. For example, in Figure 6 the distance between the outer boundary a1 of the intermediate sub-hole K11 and the outer boundary c1 of the end sub-hole K12 is greater than or equal to 0.5 μm, and the distance between the outer boundary b1 of the intermediate sub-hole K11 and the outer boundary d1 of the end sub-hole K12 is greater than or equal to 0.5 μm. Correspondingly, the connection width of the third part 251a and the fourth part 251b of the first connecting portion 251 increases by at least 0.5 μm on one side in the first direction X, which is sufficient to eliminate the poor connection of the third part 251a and the fourth part 251b, and ensure the conductive performance of the connection between the conductive block 210 and the first conductive trace 231 through the first connecting portion 251.

[0077] In one embodiment, the dimension L1 of the intermediate sub-hole K11 in the direction parallel to the first axis Z1 is greater than or equal to 3.2 μm. It can be understood that the part of the first connecting portion 251 corresponding to the intermediate sub-hole K11 corresponds to the intermediate sub-hole K11. Setting L1 to be greater than or equal to 3.2 μm makes the dimension of the part of the first connecting portion 251 corresponding to the intermediate sub-hole K11 in the second direction Y greater than or equal to 3.2 μm, thereby further increasing the connection area of the third part 251a and the fourth part 251b of the first connecting portion 251, further improving the conductive performance of the connection between the conductive block 210 and the first conductive trace 231 through the first connecting portion 251, reducing the poor connection, and improving the performance of the display substrate.

[0078] In one embodiment, the dimension w of the intermediate sub-hole K11 in the direction parallel to the overlapping boundary 231a is greater than or equal to 3 μm.

[0079] In one embodiment, the dimension L2 of the end sub-hole K12 in the direction parallel to the first axis Z1 is greater than or equal to 3 μm.

[0080] Exemplarily, as Figure 6 shown, the first via hole K1 can be symmetrically arranged with respect to the first axis Z1.

[0081] As Figure 7As shown, the first connecting portion 251 includes a connecting portion body and lugs 2512 located on both sides of the connecting portion body. The lugs 2512 correspond to the intermediate sub-hole K11, and the number of the lugs 2512 is two. The two lugs 2512 are located on opposite sides of the intermediate sub-hole K11 along the direction of the overlapping boundary 231a. The first distance is the distance between the outer boundary of the intermediate sub-hole K11 and the outer boundary of the corresponding lug 2512. For example, the outer boundary of the upper lug 2512 is a3, the outer boundary of the lower lug 2512 is b3, and the first distance D1 can be the distance between the boundary a1 and a3, and / or the first distance D1 is the distance between the boundary b1 and the boundary b3.

[0082] In one embodiment, the dimension of the lug 2512 in the direction parallel to the overlapping boundary 231a (i.e., the first direction X) is greater than or equal to 0.5 μm. Correspondingly, the connection width of the third portion 251a and the fourth portion 251b of the first connecting portion 251 on one side in the first direction X increases by at least 0.5 μm, which is sufficient to eliminate the poor connection of the third portion 251a and the fourth portion 251b and ensure the conductive performance of the connection between the conductive block 210 and the first conductive trace 231 through the first connecting portion 251.

[0083] The dimension L3 of the lug 2512 in the direction perpendicular to the overlapping boundary 231a (i.e., the second direction Y) is greater than or equal to 3.2 μm. Setting L3 to be greater than or equal to 3.2 μm further increases the connection area of the third portion 251a and the fourth portion 251b of the first connecting portion 251.

[0084] In one embodiment, the intermediate sub-hole K11 includes a concave portion K10, and the concave portion K10 is formed by removing a part of the material of the first insulating layer 22 clamped between the first conductive trace 231 and the conductive block 210 along the overlapping boundary 231a.

[0085] Exemplarily, the dimension of the first via K1 in the first direction X can be 3.5 μm to 4.5 μm. For example, the dimension of the first via K1 in the first direction X can be 4 μm. The dimension of the first via K1 in the second direction Y can be 5.5 μm to 6.5 μm. For example, the dimension of the first via K1 in the second direction Y can be 6 μm.

[0086] Figure 8 It is a partial plan schematic diagram of a display substrate in another embodiment of the present disclosure. Figure 9 is Figure 8 the schematic cross-sectional view taken along line B-B in Figure 8 The plan schematic diagram of the position of the first via in Figure 6 and Figure 7 can be referred to. In another embodiment, as shown in Figure 8 and Figure 9As shown, the substrate 10 may include a plurality of sub-pixel regions arranged in an array. The conductive block 210 includes a plurality of connected sub-electrode blocks 211, and the sub-electrode blocks 211 are located within the sub-pixel regions. Exemplarily, a sub-electrode block 211 is disposed within each sub-pixel region. According to product requirements, the conductive block 210 may include M rows and N columns of connected sub-electrode blocks 211. For example, the conductive block 210 may further include a third connection portion 213, and two adjacent sub-electrode blocks 211 in the same row may be connected through the third connection portion 213. The conductive block 210 may further include a second connection portion 212, and two adjacent sub-electrode blocks 211 in the same column are connected through the second connection portion 212. The conductive block 210 may further include a fourth connection portion 214, and the fourth connection portion 214 is used to connect sub-electrode blocks 211 in different columns and different rows. It can be understood that in the conductive block, in order to connect different sub-electrode blocks 211 into one body, other connection portions may also be provided as needed, which will not be enumerated one by one here.

[0087] The orthographic projection edge line of the overlapping boundary 231a on the substrate 10 is located within the orthographic projection of the second connection portion 212 on the substrate 10. Correspondingly, the second part of the first via K1 is located above the second connection portion 212, and the orthographic projection of the second part on the substrate 10 is located within the orthographic projection of the second connection portion 212 on the substrate 10. The part of the first via K1 located on the other side of the overlapping boundary 231a penetrates through the second insulating layer 24 and the first insulating layer 22 to expose a part of the surface of the second connection portion 212. The first connection portion 251 is connected to the exposed surface of the second connection portion 212 through the first via K1, realizing the connection of the first connection portion 251 to the conductive block 210 through the first via K1.

[0088] The substrate 10 may include thin-film transistors, and the third conductive layer 25 may further include a pixel electrode 252 located in the sub-pixel region, and the pixel electrode 252 is connected to the thin-film transistor through a second via K2.

[0089] In this way, the first conductive layer 21 may be a common electrode layer, the third conductive layer 25 may be a pixel electrode 252 layer, and the conductive block 210 may be called a touch control electrode block. The sub-electrode block 211 may be used as a common electrode, and the sub-electrode block 211 and the pixel electrode 252 may form an electric field for driving liquid crystal.

[0090] Exemplarily, the material of the first conductive layer 21 is a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), etc. The material of the third conductive layer 25 is a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), etc. The material of the third conductive layer 25 may be the same as or different from the material of the first conductive layer 21.

[0091] In one embodiment, asFigure 8 As shown, the first conductive trace 231 extends along the first direction X and is located between two adjacent columns of sub-pixel regions. The first via K1 is located between two adjacent rows of sub-pixel regions. In this article, a plurality of sub-pixel regions arranged along the first direction X are referred to as a column of sub-pixel regions, and a plurality of sub-pixel regions arranged along the second direction Y are referred to as a row of sub-pixel regions. With such an arrangement, the first conductive trace 231 is located outside the sub-pixel regions and does not affect the aperture ratio of the display substrate; the first via K1 is located between two adjacent rows of sub-pixel regions, and the first via K1 is also located outside the sub-pixel regions and does not affect the aperture ratio of the display substrate.

[0092] As Figure 8 As shown, the substrate 10 further includes a plurality of signal lines 141 extending along the first direction X and a plurality of gate lines 121 extending along the second direction Y. The plurality of signal lines 141 and the plurality of gate lines 121 intersect with each other to define a plurality of sub-pixel regions. The first conductive trace 231 is located between two adjacent columns of sub-pixel regions, and the signal line 141 is also located between two adjacent columns of sub-pixel regions. Thus, there is an overlap between the orthographic projection of the first conductive trace 231 and the corresponding signal line 141 on the substrate 10. The first conductive trace 231 and the signal line 141 located between the same two columns of sub-pixel regions correspond to each other. With such a structure, the first conductive trace 231 and the signal line 141 are located on different layers, and the first conductive trace 231 and a signal line 141 are arranged in a stacked manner, reducing the extra space occupied by the first conductive trace 231, saving the wiring space, and being beneficial to realizing the narrow bezel design of the product.

[0093] Exemplarily, the signal line 141 may include a first signal line 141a and a second signal line 141b. The first signal line 141a is used as a data line, and the second signal line 141b can be used to transmit the gate signal output by the gate driving module to the gate line 121. Exemplarily, the signal line 141 located between the same two columns of sub-pixel regions as the first conductive trace 231 is the second signal line 141b. The second signal line 141b and the first signal line 141a can be arranged at intervals.

[0094] Exemplarily, in the second direction Y, that is, in the width direction of the first conductive trace 231 and the signal line 141, the orthographic projection of the first conductive trace 231 on the substrate 10 is located within the orthographic projection of the corresponding signal line 141 on the substrate 10, or the orthographic projection of the signal line 141 on the substrate 10 is located within the orthographic projection of the corresponding first conductive trace 231 on the substrate 10. With such an arrangement, the occupied space of the first conductive trace 231 is minimized, the wiring space is saved, and it is beneficial to realizing the narrow bezel design of the product.

[0095] Exemplarily, as Figure 8As shown, a first conductive trace 231 can be provided every two columns of sub-pixel regions. The material of the first conductive trace 231 can be a metallic material. The thickness of the first conductive trace 231 can be set as required.

[0096] Exemplarily, as Figure 8 shown, two gate lines 121 are provided between adjacent rows of sub-pixel regions. One gate line 121 is connected to some pixel electrodes 252 in the upper row through a thin-film transistor, and the other gate line 121 is connected to some pixel electrodes 252 in the lower row through a thin-film transistor. In other embodiments, one gate line 121 can be provided between adjacent rows of sub-pixel regions, and each gate line 121 is connected to a row of pixel electrodes 252 through a thin-film transistor.

[0097] As Figure 8 shown, the substrate 10 can include a base 11 and a thin-film transistor structure layer on one side of the base 11. The thin-film transistor structure layer includes thin-film transistors. The gate line 121 is provided on the same layer as the gate in the thin-film transistor, and the data line is provided on the same layer as the source and drain in the thin-film transistor. The substrate 10 can further include a buffer layer 15 and an organic planarization layer 16. The buffer layer 15 is located on the side of the thin-film transistor structure layer away from the base 11, and the organic planarization layer 16 is located on the side of the buffer layer 15 away from the base 11. The material of the organic planarization layer 16 can be an organic material. The first conductive layer 21 is located on the side of the organic planarization layer 16 away from the base 11.

[0098] As Figure 9As shown, the organic planarization layer 16 may include a third via hole K3. There is no first conductive layer 21 in the area where the third via hole K3 is located. The orthographic projection of the second via hole K2 on the substrate 11 is located inside the orthographic projection of the third via hole K3 on the substrate 11. The second via hole K2 penetrates through the second insulating layer 24, the first insulating layer 22, the third via hole K3, and the buffer layer 15 to expose the second pole 142 of the thin film transistor. The pixel electrode 252 is lap-connected to the second pole 142 of the thin film transistor through the second via hole K2. The first pole of the thin film transistor is connected to the data line. One of the first pole and the second pole of the thin film transistor may be the source electrode, and the other may be the drain electrode. Therefore, the second via hole K2 is formed during the formation of the second insulating layer 24, that is to say, the etching of the buffer layer 15 occurs during the formation of the second via hole K2. Thus, before the formation of the second via hole K2, the buffer layer 15 is not etched, and the buffer layer 15 completely covers the thin film transistor structure layer. And in the bonding area of the display substrate, the organic planarization layer 16 is removed, that is to say, during the formation of the organic planarization layer 16, the organic material in the bonding area is removed. Thus, the buffer layer 15 remains in the bonding area, and the buffer layer 15 in the bonding area is not etched before the formation of the second via hole K2. Therefore, by disposing the pixel electrode 252 layer above the common electrode layer, the buffer layer 15 will not be etched before the formation of the second via hole K2. The buffer layer 15 can isolate moisture and prevent metal corrosion in a high-temperature and high-humidity environment, improving the reliability of the product.

[0099] The display substrate of the embodiment of the present disclosure can be applied to a display panel. A common voltage signal is applied to the conductive block 210 during the display of a frame image of the display panel, and a touch signal is applied to the conductive block 210 between two frame images of the display panel.

[0100] It should be noted that during the display of the display panel, the image is refreshed frame by frame. During the display of a frame image, a gate signal is sequentially provided to a plurality of gate lines 121 from top to bottom. During the frame image process, a common voltage signal is applied to the conductive block 210 to realize the display of the frame image. Between two frame images, a touch signal is applied to the conductive block 210 to detect the touch position. Thus, the common voltage signal and the touch signal share the conductive block 210, realizing a display panel of touch and display driver integration (TDDI) technology.

[0101] Next, through Figure 8 and Figure 9The preparation process of the shown display substrate further illustrates the technical solution of the embodiments of the present disclosure. It can be understood that, in this article, when the patterned material is an inorganic material or a metal, "patterning" includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping. When the patterned material is an organic material, "patterning" includes processes such as mask exposure and development. Evaporation, deposition, coating, etc. mentioned in this article are all mature preparation processes in related technologies.

[0102] Form a substrate substrate 10. The process of forming the substrate substrate 10 may include: forming a thin-film transistor structure layer on one side of the substrate 11; forming a buffer layer 15 on the side of the thin-film transistor structure layer away from the substrate 11 by a deposition process; forming an organic planarization layer 16 on the side of the buffer layer 15 away from the substrate 11. Among them, during the process of forming the organic planarization layer 16, the material of the organic planarization layer 16 in the bonding area is removed, and the material of the organic planarization layer 16 at the position of the third via K3 is removed to form the third via K3, as Figure 10 , Figure 10 is a cross-sectional schematic diagram of the substrate substrate after being formed in a display substrate according to an embodiment of the present disclosure. Exemplarily, the thin-film transistor structure layer may include film layers such as a first metal layer, a gate insulating layer 13, an active layer, and a second metal layer. The first metal layer includes a gate line 121 and the gate of the thin-film transistor. The second metal layer includes a signal line 141 and the source and drain of the thin-film transistor.

[0103] Deposit a first conductive thin film on the side of the organic planarization layer 16 away from the substrate 11. After patterning the first conductive thin film, a first conductive layer 21 is formed. The first conductive layer 21 includes conductive blocks 210. The conductive blocks 210 include sub-electrode blocks 211 located in a plurality of sub-pixel regions, a third connection portion 213, and a second connection portion 212. The third connection portion 213 connects adjacent sub-electrode blocks 211 in the same row in the conductive block 210, and the second connection portion 212 connects adjacent sub-electrode blocks 211 in the same column in the conductive block 210.

[0104] Form a first insulating layer 22 on the side of the first conductive layer 21 away from the substrate 11.

[0105] Deposit a second conductive thin film on the side of the first insulating layer 22 away from the substrate 11. After patterning the second conductive thin film, a second conductive layer 23 is formed. The second conductive layer 23 includes a first conductive trace 231. The first conductive trace 231 includes a lap boundary 231a. The projection edge of the lap boundary 231a on the substrate substrate 10 is located within the projection of the conductive block 210 on the substrate substrate 10.

[0106] A second insulating layer 24 is formed on the side of the second conductive layer 23 facing away from the substrate 11 by a deposition process; a photoresist is coated on the second insulating layer 24, and after exposure and development of the photoresist, a first via pattern K1' and a second via pattern K2' are formed, as Figure 11A shown, Figure 11A FIG. 0000305 is a cross-sectional schematic view of a display substrate in an embodiment of the present disclosure after forming the first via pattern and the second via pattern. When exposing the photoresist, the first conductive trace 231 can be used for alignment to improve the accuracy of the first via K1 pattern; a dry etching process is used to etch the inorganic insulating material at the positions of the first via pattern K1' and the second via pattern K2' to form a first via K1 and a second via K2 respectively, as Figure 11B shown, Figure 11B FIG. 0000307 is a cross-sectional schematic view of a display substrate in an embodiment of the present disclosure after forming the first via and the second via.

[0107] Among them, as Figure 11B shown, a first part of the first via K1 located on the right side of the overlapping boundary 231a exposes a part of the surface of the first conductive trace 231, and a second part of the first via K1 located on the left side of the overlapping boundary 231a exposes a part of the surface of the second connection part 212. And due to the isotropic nature of chemical etching, the first via K1 further includes a concave portion K10 located below the overlapping boundary 231a. The second via K2 exposes a part of the surface of the second pole of the thin film transistor.

[0108] A third conductive thin film is deposited on the side of the second insulating layer 24 facing away from the substrate 11, and after patterning the third conductive thin film, a third conductive layer 25 is formed. The third conductive layer 25 includes a first connection part 251 and a pixel electrode 252 located in the sub-pixel region, as Figure 9 shown. The first connection part 251 is connected to the first conductive trace 231 through the first part of the first via K1 and is connected to the second connection part 212 through the second part of the first via K1. Thus, the first conductive trace 231 is connected to the conductive block 210 through the first connection part 251. The pixel electrode 252 is connected to the second pole of the thin film transistor through the second via K2. During the formation of the third conductive layer 25, alignment can be performed using alignment marks located on the first metal layer, alignment marks located on the second metal layer, or alignment marks located on the second conductive layer 23. During the patterning process of forming the third conductive layer 25, a wet etching process can be used to etch the third conductive thin film.

[0109] Due to the existence of the concave portion K10 in the first via K1, the formed first connection portion 251 may have poor connection at the position corresponding to the concave portion K10, resulting in a fracture at the position corresponding to the concave portion K10 of the first connection portion 251. In the embodiment of the present disclosure, the first via K1 includes an intermediate sub-via K11 and end sub-vias K12 located on both sides of the intermediate sub-via K11 in a direction perpendicular to the overlapping boundary 231a. The orthographic projection edge of the overlapping boundary 231a on the substrate 10 passes through the orthographic projection of the intermediate sub-via K11 on the substrate 10. The first distance corresponding to the intermediate sub-via K11 is greater than the second distance corresponding to the end sub-vias K12. In this way, the connection width of the first connection portion 251 in the extending direction of the overlapping boundary 231a is increased. Thus, even if there is a fracture in the first connection portion 251, compared with the related art, the technical solution of the present disclosure still increases the connection area of the portions of the first connection portion 251 located on both sides of the overlapping boundary 231a, reduces the overlapping defect of the first connection portion 251, improves the conductive performance of the conductive block 210 and the first conductive trace 231 connected through the first connection portion 251, reduces the connection defect, and improves the performance of the display substrate.

[0110] In an exemplary embodiment, the first insulating layer 22, the second insulating layer 24, the gate insulating layer, and the buffer layer 15 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The metal layer and the second conductive layer 23 can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc.

[0111] The embodiment of the present disclosure also provides a display panel, which includes the display substrate of the embodiment of the present disclosure. Exemplarily, the display panel further includes a counter substrate disposed opposite to the display substrate, and liquid crystal located between the display substrate and the counter substrate.

[0112] Based on the inventive concept of the foregoing embodiments, the embodiment of the present disclosure also provides a display device, which includes the display substrate or the display panel of the embodiment of the present disclosure. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function.

[0113] In the description of this specification, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationships shown in the drawings. These are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0114] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0115] In the present disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled", "fixed", etc. shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or a communication connection; it may be directly connected, or indirectly connected through an intermediate medium, and may be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0116] In the present disclosure, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0117] The foregoing disclosure provides many different embodiments or examples for implementing the different structures of the present disclosure. To simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0118] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of various changes or substitutions thereof. The different parts in different embodiments can be combined with each other without conflict, and all of these should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: substrate substrate; A first conductive layer, located on one side of the substrate, the first conductive layer comprising at least one conductive block; A first insulating layer, located on a side of the first conductive layer away from the substrate; A second conductive layer is located on a side of the first insulating layer away from the substrate, the second conductive layer includes a first conductive trace, the first conductive trace includes an overlapped boundary, and an orthographic projection edge line of the overlapped boundary on the substrate is located within an orthographic projection of the conductive block on the substrate; a second insulating layer, located on a side of the second conductive layer away from the base substrate, the display substrate being provided with a first via hole, the first via hole including a middle sub-hole and end sub-holes located on both sides of the middle sub-hole in a direction perpendicular to the overlap boundary, the orthographic projection edge line of the overlap boundary on the base substrate passing through the orthographic projection of the middle sub-hole on the base substrate, a portion of the first via hole located on one side of the overlap boundary penetrating the second insulating layer to expose a portion of the surface of the first conductive trace, and a portion of the first via hole located on the other side of the overlap boundary penetrating the second insulating layer and the first insulating layer to expose a portion of the surface of the conductive block; A third conductive layer is located on a side of the second insulating layer away from the substrate substrate, the third conductive layer includes a first connecting portion, the orthographic projection of the first via hole on the substrate substrate is located on the inner side of the orthographic projection of the first connecting portion on the substrate substrate, the first connecting portion is connected to the exposed surface of the first conductive trace through the first via hole, and is connected to the exposed surface of the conductive block, the first distance corresponding to the middle sub-hole is greater than the second distance corresponding to the end sub-hole, the first distance is the distance between the outer boundary of the middle sub-hole and the outer boundary corresponding to the first connecting portion, and the second distance is the distance between the outer boundary of the end sub-hole and the outer boundary corresponding to the first connecting portion.

2. The display substrate according to claim 1, characterized in that: The shape of the first via hole is a long strip extending along the second direction, the first distance is the distance between the outer boundary of the middle sub-hole parallel to the second direction and the outer boundary corresponding to the first connecting part, the second distance is the distance between the outer boundary of the end sub-hole parallel to the second direction and the outer boundary corresponding to the first connecting part, and the second direction is a direction perpendicular to the overlapping boundary.

3. The display substrate according to claim 1, characterized in that: The first via hole has a first axis, and the first axis is perpendicular to the direction of the overlapping boundary. The outer boundary of the middle sub-hole is the outer boundary of the middle sub-hole located on both sides of the first axis, and the outer boundary of the end sub-hole is the outer boundary of the end sub-hole located on both sides of the first axis. The outer boundary of the middle sub-hole is closer to the first axis than the outer boundary of the end sub-hole.

4. The display substrate according to claim 3, characterized in that: The first via meets at least one of the following conditions: The distance between the outer boundary of the middle sub-hole and the outer boundary of the end sub-hole is greater than or equal to 0.5 μm; The size of the middle sub-pore in a direction parallel to the first axis is greater than or equal to 3.2 μm; The size of the middle sub-hole in the direction parallel to the overlap boundary is greater than or equal to 3 μm; The dimension of the end sub-hole in a direction parallel to the first axis is greater than or equal to 3 μm.

5. The display substrate according to claim 1, characterized in that: The first connection part includes a connection part body and lugs located on both sides of the connection part body, the lugs correspond to the middle sub-hole, and the first distance is the distance between the outer boundary of the middle sub-hole and the outer boundary of the corresponding lug.

6. The display substrate according to claim 5, characterized in that: The lug satisfies at least one of the following: The dimension of the lug in a direction parallel to the overlap boundary is greater than or equal to 0.5 μm; The dimension of the lug in a direction perpendicular to the overlap boundary is greater than or equal to 3.2 μm.

7. The display substrate according to claim 1, characterized in that: The middle sub-hole includes an inner concave portion, which is formed by removing part of the material of the first insulating layer sandwiched between the first conductive trace and the conductive block along the overlapping boundary.

8. The display substrate according to any one of claims 1 to 7, characterized in that: The base substrate includes a plurality of sub-pixel regions arranged in an array, the conductive block includes a plurality of connected sub-electrode blocks, the sub-electrode blocks are located in the sub-pixel regions, the conductive block also includes a second connecting portion connected to the sub-electrode block, and the orthographic projection edge line of the overlap boundary on the base substrate is located within the orthographic projection of the second connecting portion on the base substrate; The base substrate includes a thin film transistor, and the third conductive layer also includes a pixel electrode located in the sub-pixel area, and the pixel electrode is connected to the thin film transistor through a second via hole.

9. The display substrate according to claim 8, characterized in that: The first conductive trace extends along a first direction and is located between two adjacent columns of sub-pixel regions, and the first via hole is located between two adjacent rows of sub-pixel regions.

10. The display substrate according to claim 9, characterized in that: The base substrate includes a plurality of signal lines extending along the first direction and a plurality of gate lines extending along the second direction. The plurality of signal lines and the plurality of gate lines intersect with each other to define the plurality of sub-pixel areas. The first conductive trace overlaps with the orthographic projection of the corresponding signal line on the base substrate.

11. The display substrate according to claim 8, characterized in that: The material of the first conductive layer is a transparent conductive material, the material of the third conductive layer is a transparent conductive material, and the material of the second conductive layer is a metal material; The substrate includes a base, a thin film transistor structure layer located on one side of the base, a buffer layer located on a side of the thin film transistor structure layer away from the base, and an organic planar layer located on a side of the buffer layer away from the base, and the first conductive layer is located on a side of the organic planar layer away from the base.

12. The display substrate according to claim 8, characterized in that: The display substrate is applied to a display panel, a common voltage signal is applied to the conductive block during the process of the display panel displaying a frame image, and a touch signal is applied to the conductive block between two frame images of the display panel.

13. A display panel, characterized in that: The display panel comprises the display substrate according to any one of claims 1 to 12, and further comprises an opposing substrate arranged opposite to the display substrate, and the display panel further comprises liquid crystal located between the display substrate and the opposing substrate.

14. A display device, characterized in that: A display substrate comprising any one of claims 1 to 12, or a display panel comprising claim 13.

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