Display device

Abstract

A display device includes: a display substrate including a display area and a pad area adjacent to one side of the display area; the driving chip is arranged on the bonding pad area of the display substrate; a first circuit board disposed under the display substrate and electrically connected to the pad area; and a cover tape covering each of the driving chip and the first circuit board, and including a cutout portion.

Description

Technical Field

[0001] The present disclosure generally relates to a display device. More specifically, the present disclosure relates to a display device that provides visual information. Background Art

[0002] With the development of information technology, the importance of a display device, which is a connection medium between a user and information, has been highlighted. For example, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), plasma display devices (PDPs), or quantum dot display devices is increasing.

[0003] The display device is driven by various voltages and signals, and accordingly, electromagnetic interference noise (EMI noise) may be generated in the display device. To enable the display device to perform various functions, various electronic devices (e.g., antennas, GPS, etc.) are integrated into the display device, and these electronic devices operate by forming a network with each other. Due to the electromagnetic interference noise generated in the display device, the problem of malfunction of the display device and / or the electronic devices is increasing. Summary of the Utility Model

[0004] Embodiments provide a display device having improved adhesion performance of a cover tape that shields electromagnetic interference noise.

[0005] A display device according to an embodiment of the present disclosure includes: a display substrate including a display area and a pad area adjacent to one side of the display area; a driving chip disposed on the pad area of the display substrate; a first circuit board disposed under the display substrate and electrically connected to the pad area; and a cover tape covering each of the driving chip and the first circuit board and including a cutout portion.

[0006] In an embodiment, the cover tape may include: a first portion covering the driving chip; a second portion extending from the first portion and bent with a predetermined curvature; and a third portion extending from the second portion and covering the first circuit board. The second portion of the cover tape may include a cutout portion.

[0007] In an embodiment, a plurality of openings may be defined in the cutout portion. In a plan view, the plurality of openings may be arranged in a row along one direction.

[0008] In an embodiment, a plurality of openings may be defined in the cutout portion. In a plan view, the plurality of openings may be arranged in a zigzag shape.

[0009] A display device according to another embodiment of the present disclosure includes: a display substrate, including a display area and a pad area adjacent to one side of the display area; a driving chip, disposed on the pad area of ​​the display substrate; a first circuit board, disposed under the display substrate and electrically connected to the pad area; and a cover tape, covering each of the driving chip and the first circuit board, including a conductive layer and an insulating layer disposed on the conductive layer, and including a cutout portion bent with a predetermined curvature.

[0010] In an embodiment, the insulating layer may include an inorganic material having a black color or an organic material having a black color.

[0011] In an embodiment, the cover tape may further include an adhesive layer disposed below the conductive layer. The adhesive layer may include a conductive material.

[0012] In an embodiment, in the cutout portion, a portion of the insulating layer may be cut.

[0013] In an embodiment, in the cut portion, a portion of the conductive layer and a portion of the insulating layer may be cut.

[0014] In an embodiment, a plurality of openings may be defined in the cutout portion.

[0015] The display device according to an embodiment of the present disclosure may include a cover tape covering a driving chip and a circuit board, and a portion of the cover tape bent at a predetermined curvature may include a cutout portion.

[0016] Accordingly, when the cover tape is bent, the repulsive force acting on the portion of the cover tape bent with a predetermined curvature can be reduced. As a result, the cover tape can be smoothly attached to the driver chip. In other words, the phenomenon of partial warping of the cover tape caused by the cover tape not being attached to the driver chip can be effectively suppressed.

[0017] A display device according to another embodiment of the present disclosure may include a cover tape covering a driving chip and a circuit board, wherein the cover tape may include a conductive layer and an insulating layer disposed on the conductive layer, and may include a cutout portion bent at a predetermined curvature.

[0018] Since the cover tape includes the insulating layer disposed on the conductive layer, the problem that the cover tape is torn during the rework process can be effectively suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0020] Figure 1 is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0021] Figure 2 It is along Figure 1Cross-sectional view taken along line I-I'.

[0022] Figure 3 is shown Figure 1 Cross-sectional view of the display device shown.

[0023] Figure 4 is shown Figure 3 Plan view of the first cover tape shown.

[0024] Figure 5 Cross-sectional view of a display device according to another embodiment of the present disclosure is shown.

[0025] Figure 6 is shown Figure 5 Plan view of the second cover tape shown.

[0026] Figure 7 Cross-sectional view of a display device according to yet another embodiment of the present disclosure is shown.

[0027] Figure 8 is shown Figure 7 Cross-sectional view of the third cover tape shown.

[0028] Figure 9 Cross-sectional view of a display device according to yet another embodiment of the present disclosure is shown.

[0029] Figure 10 is shown Figure 9 Cross-sectional view of the fourth cover tape shown. Detailed Description

[0030] It will be understood that when an element is referred to as being "on" or "connected to" another element, it can be directly on or directly connected to the other element, or intervening elements may be present between them. In contrast, when an element is referred to as being "directly" on another element, no intervening elements are present.

[0031] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another illustrated in the figures. It will be understood that the relative terms are intended to cover different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as being on the "lower" side of other elements will then be oriented on the "upper" side of the other elements. Thus, depending on the particular orientation of the figure, the term "lower" can cover both the "lower" and "upper" orientations. Similarly, if the device in one of the figures is flipped, an element described as being "beneath" or "below" other elements will then be oriented "above" the other elements. Thus, the terms "beneath" or "below" can cover both the above and below orientations.

[0032] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the teachings herein, the "first element", "component", "region", "layer", or "section" discussed below may be referred to as a second element, component, region, layer, or section.

[0033] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, "a", "the", and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural, unless the context clearly dictates otherwise. For example, "element" has the same meaning as "at least one element" unless the context clearly dictates otherwise. "At least one" should not be construed as limiting "a". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when used in this specification, the terms "comprises" or "comprising" and their variants specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0034] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0035] Figure 1 is a plan view of a display device according to an embodiment of the present disclosure.

[0036] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 that intersects the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. A third direction DR3 perpendicular to the plane defined by the first direction DR1 and the second direction DR2 may be parallel to the thickness direction of the display substrate DP. As used herein, a "plan view" is a view in the third direction DR3.

[0037] Reference Figure 1 , a display device DD according to an embodiment of the present disclosure may include a display substrate DP, a driving chip D-IC, a first circuit board (e.g., Figure 3 the first circuit board PCB), a second circuit board FPCB, and a first cover tape CT.

[0038] The display substrate DP may include a display area DA and a non-display area NDA. A plurality of pixels PX for generating an image may be provided in the display area DA. The image may be generated by combining light emitted from each of the pixels PX. For example, the pixels PX may be arranged in a matrix form along a first direction DR1 and a second direction DR2.

[0039] The non-display area NDA may be located around the display area DA. For example, in a plan view, the non-display area NDA may surround the display area DA.

[0040] The non-display area NDA may include a pad area PA. The pad area PA may be located at one side of the display area DA. In an embodiment, for example, the pad area PA may be positioned to be spaced apart from the display area DA in the second direction DR2. The pad area PA may extend in the first direction DR1. A plurality of pads may be provided in the pad area PA.

[0041] The display substrate DP may include a plurality of transmission lines TL connecting the display area DA and the pad area PA. The transmission lines TL may be located between the display area DA and the pad area PA. Each of the transmission lines TL may include a first end adjacent to the pad area PA and a second end adjacent to the display area DA, wherein the first end and the second end are opposite to each other. The first end of each of the transmission lines TL may be connected to a corresponding one of the pads. The second end of each of the transmission lines TL may be connected to a corresponding one of a plurality of lines (such as gate lines, data lines, driving voltage lines, etc.) provided in the display area DA. The pads and the pixels PX may be electrically connected through the transmission lines TL.

[0042] A driving chip D-IC may be provided on the pad area PA of the display substrate DP. The driving chip D-IC may include a plurality of bumps connected to the pads.

[0043] A part of a second circuit board FPCB may be provided on the pad area PA of the display substrate DP. Specifically, a first end of the second circuit board FPCB may be attached to the display substrate DP so as to overlap a part of the pad area PA in a plan view. Accordingly, the second circuit board FPCB may be electrically connected to the pad area PA. In an embodiment, for example, the second circuit board FPCB may be a flexible printed circuit board.

[0044] A first circuit board (for example, Figure 3 the first circuit board PCB) may be provided under the display substrate DP. The first circuit board may be attached to a second end of the second circuit board FPCB opposite to the first end of the second circuit board FPCB. Accordingly, the first circuit board may be electrically connected to the second circuit board FPCB. In addition, the first circuit board may be electrically connected to the pad area PA through the second circuit board FPCB. In an embodiment, for example, the first circuit board may be a printed circuit board.

[0045] When the second circuit board FPCB is bent, the second circuit board FPCB can be connected to the first circuit board disposed under the display substrate DP. A detailed description thereof will be provided later with reference to Figure 3 and

[0046] The driving chip D-IC, the first circuit board, and the second circuit board FPCB can provide driving signals to the display substrate DP. The driving signals can refer to various signals such as driving voltages, control signals, data signals, etc. for driving the display substrate DP. The driving signals can be transmitted to the pixels PX disposed in the display area DA through pads and transmission lines TL.

[0047] The first cover tape CT can cover each of the driving chip D-IC, the first circuit board PCB, and the second circuit board FPCB. Accordingly, the first cover tape CT can protect the driving chip D-IC, the first circuit board PCB, and the second circuit board FPCB.

[0048] The first cover tape CT can include a cutout portion (e.g., Figure 4 the cutout portion RP) bent with a predetermined curvature. A detailed description thereof will be provided later with reference to Figure 3 and Figure 4 and

[0049] Figure 2 is a cross-sectional view taken along the line I-I’ of Figure 1 and

[0050] Referring to Figure 2 the display device DD can include a display substrate DP and a packaging layer TFE. The display substrate DP can include a base substrate SUB, thin film transistors TR, a first insulating layer ILD1, a second insulating layer ILD2, a via insulating layer VIA, a light emitting element LD, and a pixel defining layer PDL. The thin film transistors TR can include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The light emitting element LD can include a lower electrode AE, a light emitting layer EML, and an upper electrode CE.

[0051] The base substrate SUB can include a transparent material or an opaque material. The base substrate SUB can be formed of a transparent resin substrate or include a transparent resin substrate. A polyimide substrate can be an example of the transparent resin substrate. In this case, the polyimide substrate can include a first organic layer, a first barrier layer, a second organic layer, etc. Alternatively, the base substrate SUB can include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, a non-alkali glass substrate, etc. These can be used alone or in combination with each other.

[0052] A buffer layer may be provided on the base substrate SUB. The buffer layer can prevent metal atoms or impurities from diffusing from the base substrate SUB into the upper structure (e.g., thin film transistor TR, light emitting element LD, etc.). Additionally, the buffer layer can obtain a substantially uniform active layer ACT by controlling the heat transfer rate during the crystallization process for forming the active layer ACT. In an embodiment, for example, the buffer layer may include an organic insulating material or an inorganic insulating material. Alternatively, the buffer layer may be omitted.

[0053] The active layer ACT may be provided on the base substrate SUB. The active layer ACT may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, etc. In an embodiment, for example, the oxide semiconductor may include indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), zinc (Zn), etc. These may be used alone or in combination with each other. The silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. The active layer ACT may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0054] The first insulating layer ILD1 may be provided on the active layer ACT and the base substrate SUB. The first insulating layer ILD1 may cover the active layer ACT on the base substrate SUB and may be provided along the contour of the active layer ACT with a substantially uniform thickness. Alternatively, the first insulating layer ILD1 may sufficiently cover the active layer ACT on the base substrate SUB and may have a substantially flat upper surface without generating a step difference around the active layer ACT. Contact holes may be defined in the first insulating layer ILD1. The contact holes may expose a part of the active layer ACT. The first insulating layer ILD1 may include a silicon compound, a metal oxide, etc. Examples of the silicon compound may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc. These may be used alone or in combination with each other. The first insulating layer ILD1 may electrically insulate the active layer ACT and the gate electrode GE.

[0055] The gate electrode GE can be disposed on the first insulating layer ILD1. In a plan view, the gate electrode GE can overlap with the active layer ACT. The gate electrode GE can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. Examples of materials that can be used as the gate electrode GE can include silver (Ag), alloys including silver, molybdenum (Mo), alloys including molybdenum, aluminum (Al), alloys including aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc. These can be used alone or in combination with each other.

[0056] The second insulating layer ILD2 can be disposed on the gate electrode GE and the first insulating layer ILD1. The second insulating layer ILD2 can cover the gate electrode GE on the first insulating layer ILD1 and can be disposed along the contour of the gate electrode GE with a substantially uniform thickness. Alternatively, the second insulating layer ILD2 can sufficiently cover the gate electrode GE on the first insulating layer ILD1 and can have a substantially flat upper surface without creating a step difference around the gate electrode GE. Contact holes can be defined in the second insulating layer ILD2. The contact holes can expose a part of the active layer ACT. The second insulating layer ILD2 can include silicon compounds, metal oxides, etc. The second insulating layer ILD2 can electrically insulate the gate electrode GE from the source electrode SE. Additionally, the second insulating layer ILD2 can electrically insulate the gate electrode GE from the drain electrode DE.

[0057] The source electrode SE and the drain electrode DE can be disposed on the second insulating layer ILD2. Each of the source electrode SE and the drain electrode DE can be electrically connected to the active layer ACT through contact holes formed by passing through the first insulating layer ILD1 and the second insulating layer ILD2. Each of the source electrode SE and the drain electrode DE can include metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, etc. These can be used alone or in combination with each other.

[0058] Accordingly, a thin-film transistor TR including the active layer ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE can be formed.

[0059] The via insulating layer VIA can be disposed on the second insulating layer ILD2. In an embodiment, for example, the via insulating layer VIA can be disposed on the second insulating layer ILD2 with a relatively thick thickness to sufficiently cover the source electrode SE and the drain electrode DE. Contact holes can be defined in the via insulating layer VIA. The contact holes can expose a part of the drain electrode DE. The via insulating layer VIA can include an organic insulating material or an inorganic insulating material. Examples of the organic insulating material that can be used as the via insulating layer VIA can include photoresist, polyacrylic acid resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, epoxy resin, etc. These can be used alone or in combination with each other.

[0060] The lower electrode AE can be disposed on the via insulating layer VIA. The lower electrode AE can be electrically connected to the drain electrode DE through the contact holes formed through the via insulating layer VIA. Accordingly, the lower electrode AE can be electrically connected to the thin film transistor TR. In an embodiment, for example, the lower electrode AE can be a transmissive (or semi-transmissive) electrode or a reflective electrode. The lower electrode AE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In an embodiment, for example, the lower electrode AE can serve as an anode electrode.

[0061] The pixel defining layer PDL can be disposed on the via insulating layer VIA. The pixel defining layer PDL can cover the edge of the lower electrode AE and can expose a part of the upper surface of the lower electrode AE. The pixel defining layer PDL can include an organic insulating material or an inorganic insulating material. Examples of the organic insulating material that can be used as the pixel defining layer PDL can include photoresist, polyacrylic acid resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, epoxy resin, etc. These can be used alone or in combination with each other. In an embodiment, the pixel defining layer PDL can further include an inorganic material or an organic material containing a light-shielding material having black.

[0062] The light emitting layer EML can be disposed on the lower electrode AE. The light emitting layer EML can emit light having a specific color (e.g., red, green, and / or blue). In an embodiment, the light emitting layer EML can include one or both of an organic light emitting material and a quantum dot. In an embodiment, for example, the light emitting layer EML can include an organic material containing a fluorescent or phosphorescent material that emits red light, green light, blue light, or white light. The quantum dot can be a particle having a crystal structure with a size of several nanometers to several tens of nanometers and can include several hundred to several thousand atoms. The quantum dot can include a fluorescent material or a phosphorescent material and can produce monochromatic red light, green light, and blue light.

[0063] The upper electrode CE can be disposed on the pixel defining layer PDL and the light emitting layer EML. Specifically, the upper electrode CE can be disposed along the contours of the pixel defining layer PDL and the light emitting layer EML with a substantially uniform thickness. In an embodiment, for example, the upper electrode CE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These can be used alone or in combination with each other. In an embodiment, for example, the upper electrode CE can act as a cathode electrode.

[0064] Accordingly, a light emitting element LD including a lower electrode AE, a light emitting layer EML, and an upper electrode CE can be formed.

[0065] The encapsulation layer TFE can be disposed on the upper electrode CE. The encapsulation layer TFE can prevent impurities, moisture, etc. from penetrating into the light emitting element LD from the outside. The encapsulation layer TFE can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, for example, the inorganic encapsulation layer can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), etc., and the organic encapsulation layer can include a cured polymer such as polyacrylate. In an embodiment, the encapsulation layer TFE can include a first inorganic encapsulation layer disposed on the upper electrode CE, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer.

[0066] Although the display device DD of the present disclosure is described by limiting an organic light emitting display device (OLED), the configuration of the present disclosure is not limited thereto. In other embodiments, the display device DD can include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP), an electrophoretic image display device (EPD), an inorganic light emitting display device (ILED), or a quantum dot display device.

[0067] Figure 3 is a cross-sectional view of the illustrated Figure 1 display device. Figure 4 is a plan view of the first cover tape illustrated Figure 3 . For example, Figure 4 is a plan view of the shape of the first cover tape CT before being bent.

[0068] Referring to Figure 1 , Figure 3 and Figure 4 , the display device DD according to an embodiment of the present disclosure can include a display substrate DP, an encapsulation layer TFE, an antireflection layer ARL, a cover window CW, a cover panel CP, a driving chip D-IC, a first circuit board PCB, a second circuit board FPCB, and a first cover tape CT.

[0069] The encapsulation layer TFE can be disposed on the display substrate DP. The encapsulation layer TFE can include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0070] The anti-reflection layer ARL can be disposed on the encapsulation layer TFE. External light may enter the display device DD, and the external light may be reflected by various electrodes or lines included in the display substrate DP. The anti-reflection layer ARL can prevent the reflected external light from being visible to the user.

[0071] The anti-reflection layer ARL can include a polarizer and a phase retarder. In an embodiment, for example, the anti-reflection layer ARL can include a stretched film type polarizer and / or phase retarder. The number of phase retarders and the phase retardation length (λ / 4 or λ / 2) of the phase retarder can be determined according to the operating principle of the anti-reflection layer ARL. Alternatively, the anti-reflection layer ARL can include a color filter and a black matrix disposed between the color filters. The color filters can have a predetermined arrangement. The color filters can be arranged in consideration of the emission color of the pixels included in the display substrate DP.

[0072] The cover window CW can be disposed on the anti-reflection layer ARL. The cover window CW can be used to cover and protect the display substrate DP. The cover window CW can be attached to one surface of the display substrate DP through an adhesive member. When the display device DD includes the anti-reflection layer ARL, the cover window CW can be attached to the upper surface of the anti-reflection layer ARL. In an embodiment, for example, the adhesive member can include a pressure sensitive adhesive (PSA) film, an optically clear adhesive (OCA) film, an optically clear resin (OCR), etc.

[0073] The cover window CW can include a window substrate and a printed layer. The window substrate can include a transparent material. In an embodiment, for example, the window substrate can include glass or plastic. The printed layer can be disposed on the window substrate. The printed layer can be disposed on the edge of the window substrate and can be disposed in the non-display area NDA. The printed layer can include an inorganic material and / or an organic material containing a light-shielding material having black. In an embodiment, for example, the light-shielding material can include black pigments, black dyes, carbon black, etc. These can be used alone or in combination with each other.

[0074] The cover panel CP can be disposed under the display substrate DP. The cover panel CP can protect the display substrate DP from external impacts. Additionally, the cover panel CP can include a metal material for heat dissipation. In an embodiment, for example, the cover panel CP can include aluminum (Al), copper (Cu), etc. These can be used alone or in combination with each other.

[0075] The driving chip D-IC can be disposed on the pad region PA of the display substrate DP. The driving chip D-IC can supply driving signals to the display substrate DP. The driving signals can refer to various signals such as driving voltages, control signals, data signals, etc., for driving the display substrate DP.

[0076] The second circuit board FPCB can be disposed on the display substrate DP. Specifically, the second circuit board FPCB can be disposed on the display substrate DP so as to overlap a part of the pad region PA in a plan view. Accordingly, the second circuit board FPCB can be electrically connected to the pad region PA. Specifically, the second circuit board FPCB can include at least one insulating layer and at least one conductive layer. The conductive layer of the second circuit board FPCB can be connected to the pads disposed on the pad region PA of the display substrate DP through an anisotropic conductive film (ACF). Accordingly, the second circuit board FPCB can be electrically connected to the pads.

[0077] In an embodiment, for example, the second circuit board FPCB can be a flexible printed circuit board. In other words, the second circuit board FPCB can be bent downward toward the display substrate DP to be connected to the first circuit board PCB disposed under the display substrate DP. Specifically, the second circuit board FPCB can include a first portion disposed on a part of the pad region PA in a plan view, a second portion extending from the first portion and bent with a predetermined curvature, and a third portion extending from the second portion and disposed under the cover panel CP.

[0078] The first circuit board PCB can be disposed under the display substrate DP. Specifically, the first circuit board PCB can be disposed under the cover panel CP. The first circuit board PCB can include at least one insulating layer and at least one conductive layer. The conductive layer of the first circuit board PCB can be connected to the conductive layer of the second circuit board FPCB through an anisotropic conductive film. Accordingly, the first circuit board PCB can be electrically connected to the second circuit board FPCB. In addition, the first circuit board PCB can be electrically connected to the pad region PA through the second circuit board FPCB.

[0079] The first cover tape CT can cover each of the driving chip D-IC, the first circuit board PCB, and the second circuit board FPCB. The first cover tape CT can protect the driving chip D-IC, the first circuit board PCB, and the second circuit board FPCB from external impacts. In addition, the first cover tape CT can prevent electrostatic discharge (ESD) of the driving chip D-IC.

[0080] In an embodiment, the first cover tape CT can be bent to be disposed under the display substrate DP. Specifically, the first cover tape CT can be bent such that a portion of the first cover tape CT can be disposed under the display substrate DP, and the first cover tape CT can cover the driving chip D-IC disposed on the display substrate DP, the first circuit board PCB disposed under the display substrate DP, and the second circuit board FPCB disposed under the display substrate DP. In an embodiment, for example, the first cover tape CT can include a first portion CT-P1 disposed on the display substrate DP, a second portion CT-P2 extending from the first portion CT-P1 and bent with a predetermined curvature, and a third portion CT-P3 extending from the second portion CT-P2 and disposed under the display substrate DP. In this case, the first portion CT-P1 can cover the driving chip D-IC. The second portion CT-P2 can cover the second circuit board FPCB. The third portion CT-P3 can cover the first circuit board PCB.

[0081] In an embodiment, the first cover tape CT can extend from under the display substrate DP to at least a portion of the encapsulation layer TFE. In other words, a portion of the first cover tape CT disposed on the display substrate DP (e.g., the first portion CT-P1) can cover the driving chip D-IC. A part of this portion of the first cover tape CT disposed on the display substrate DP can be disposed on the encapsulation layer TFE.

[0082] In an embodiment, the first cover tape CT can include an adhesive layer and a conductive layer disposed on the adhesive layer. In other words, the adhesive layer can be disposed under the conductive layer. The adhesive layer can include an adhesive material. In an embodiment, for example, the adhesive layer can include a pressure-sensitive adhesive (PSA) film, an optically clear adhesive (OCA) film, an optically clear adhesive resin (OCR), etc. Accordingly, the first cover tape CT can be attached to the driving chip D-IC, the first circuit board PCB, the second circuit board FPCB, the cover panel CP, and the encapsulation layer TFE through the adhesive layer.

[0083] The conductive layer of the first cover tape CT can include an elastic material and a conductive material having magnetism. In an embodiment, for example, the conductive layer can include aluminum (Al). However, the materials included in the conductive layer are not limited thereto. Accordingly, the first cover tape CT can shield electromagnetic interference noise (EMI noise) generated from the first circuit board PCB and the second circuit board FPCB.

[0084] In an embodiment, the first cover tape CT may include a cutout portion RP bent with a predetermined curvature. That is, the second portion CT-P2 of the first cover tape CT may include a cutout portion RP. A plurality of openings OP may be defined in the cutout portion RP. In an embodiment, for example, in a plan view, each of the openings OP may have a square plan shape, a circular plan shape, or an elliptical plan shape. However, the present disclosure is not limited thereto, and each of the openings OP may have various plan shapes.

[0085] Since the first cover tape CT includes the cutout portion RP, the elastic modulus of the first cover tape CT can be reduced. Accordingly, when the first cover tape CT is bent, the repulsive force (e.g., elastic restoring force) acting on the second portion CT-P2 of the first cover tape CT can be reduced. As a result, the first cover tape CT can be smoothly attached to the driver chip D-IC and the encapsulation layer TFE. In other words, the phenomenon of partial warping of the first cover tape CT caused by the first cover tape CT not being attached to the driver chip D-IC and the encapsulation layer TFE can be effectively suppressed.

[0086] In an embodiment, Figure 4 As illustrated in , in a plan view, the openings OP may be arranged in a row along one direction. That is, in a plan view, the openings OP may be arranged in a row along a first direction DR1. In an embodiment, for example, in a plan view, the openings OP may include a plurality of groups each arranged in a row along the first direction DR1, and the plurality of groups may be arranged along a second direction DR2.

[0087] Figure 5 is a cross-sectional view illustrating a display device according to another embodiment of the present disclosure. Figure 6 It is a graphic Figure 5 A plan view of the second cover tape. For example, Figure 6 It is a plan view showing the shape of the second cover tape CT2 before being folded.

[0088] refer to Figure 5 and Figure 6 According to another embodiment of the present disclosure, a display device DD2 may include a display substrate DP, an encapsulation layer TFE, an anti-reflection layer ARL, a cover window CW, a cover panel CP, a driving chip D-IC, a first circuit board PCB, a second circuit board FPCB and a second cover tape CT2.

[0089] In addition to the second cover tape CT2, the display device DD2 can be connected with the reference Figure 3 and Figure 4 The display device DD described in the embodiment is substantially the same. In addition, except for the shape in which the opening OP is arranged in a plan view, the second cover tape CT2 may be the same as the reference Figure 3 and Figure 4The first cover tape CT described is substantially the same. Figure 3 and Figure 4 The description of the display device DD described is repeated.

[0090] The second cover tape CT2 may cover each of the driver chip D-IC, the first circuit board PCB, and the second circuit board FPCB. The second cover tape CT2 may be bent so that a portion of the second cover tape CT2 may be disposed under the display substrate DP. In an embodiment, for example, the second cover tape CT2 may include a first portion CT2-P1 disposed on the display substrate DP, a second portion CT2-P2 extending from the first portion CT2-P1 and bent with a predetermined curvature, and a third portion CT2-P3 extending from the second portion CT2-P2 and disposed under the display substrate DP. In this case, the first portion CT2-P1 may cover the driver chip D-IC. The second portion CT2-P2 may cover the second circuit board FPCB. The third portion CT2-P3 may cover the first circuit board PCB.

[0091] The second cover tape CT2 may include a cutout portion RP bent at a predetermined curvature. That is, the second portion CT2 - P2 of the second cover tape CT2 may include the cutout portion RP. A plurality of openings OP may be defined in the cutout portion RP.

[0092] In an embodiment, Figure 6 As shown in the figure, in the plan view, the opening OP can be arranged in a zigzag shape. That is, in the plan view, the opening OP can be arranged in a zigzag shape relative to the imaginary line extending along the first direction DR1. In this case, when the second cover tape CT2 is bent, the repulsive force acting on the second part CT2-P2 of the second cover tape CT2 can be relatively reduced. As a result, the second cover tape CT2 can be more smoothly attached to the driver chip D-IC and the packaging layer TFE. In other words, the phenomenon of partial warping of the second cover tape CT2 caused by the second cover tape CT2 not being attached to the driver chip D-IC and the packaging layer TFE can be further suppressed.

[0093] Figure 7 is a cross-sectional view illustrating a display device according to still another embodiment of the present disclosure. Figure 8 It is a graphic Figure 7 For example, Figure 8 : is a cross-sectional view showing the shape of the cut of the third cover tape CT3.

[0094] refer to Figure 7 and Figure 8, a display device DD3 according to another embodiment of the present disclosure may include a display substrate DP, a packaging layer TFE, an anti-reflection layer ARL, a cover window CW, a cover panel CP, a driving chip D-IC, a first circuit board PCB, a second circuit board FPCB, and a third cover tape CT3.

[0095] Except for the third cover tape CT3, the display device DD3 may be substantially the same as the display device DD described in the reference Figure 3 and Figure 4 In addition, except that the third cover tape CT3 further includes an insulating layer ISL on the conductive layer CDL, the third cover tape CT3 may be substantially the same as the first cover tape CT described in the reference Figure 3 and Figure 4 Descriptions that are repetitive of the description of the display device DD described in the reference Figure 3 and Figure 4 will be omitted or simplified hereinafter.

[0096] The third cover tape CT3 may cover each of the driving chip D-IC, the first circuit board PCB, and the second circuit board FPCB. The third cover tape CT3 may be bent such that a portion of the third cover tape CT3 may be disposed under the display substrate DP. In an embodiment, for example, the third cover tape CT3 may include a first portion CT3-P1 disposed on the display substrate DP, a second portion CT3-P2 extending from the first portion CT3-P1 and curved with a predetermined curvature, and a third portion CT3-P3 extending from the second portion CT3-P2 and disposed under the display substrate DP. In this case, the first portion CT3-P1 may cover the driving chip D-IC. The second portion CT3-P2 may cover the second circuit board FPCB. The third portion CT3-P3 may cover the first circuit board PCB.

[0097] In an embodiment, as illustrated in Figure 8 , the third cover tape CT3 may include an adhesive layer ADL, a conductive layer CDL, and an insulating layer ISL.

[0098] The adhesive layer ADL may be disposed under the conductive layer CDL. The adhesive layer ADL may include an adhesive material. Accordingly, the third cover tape CT3 may be attached to the driving chip D-IC, the first circuit board PCB, the second circuit board FPCB, the cover panel CP, and the packaging layer TFE. In an embodiment, the adhesive layer ADL may further include a conductive material. In other words, the adhesive layer ADL may be an adhesive layer in which an electromagnetic absorption material is embedded.

[0099] The conductive layer CDL may be disposed on the adhesive layer ADL. The conductive layer CDL may include an elastic material and a conductive material having magnetism. In an embodiment, for example, the conductive layer CDL may include aluminum (Al). Accordingly, the third cover tape CT3 may shield electromagnetic interference noise (EMI noise) generated from the first circuit board PCB and the second flexible circuit board FPCB.

[0100] The insulating layer ISL may be disposed on the conductive layer CDL. The insulating layer ISL may include an organic insulating material. In an embodiment, for example, the insulating layer ISL may include polyethylene terephthalate (PET). Since the third cover tape CT3 includes the insulating layer ISL, the problem that the third cover tape CT3 is torn during the rework process can be effectively suppressed. In addition, since the third cover tape CT3 includes the insulating layer ISL, the third cover tape CT3 can effectively shield electromagnetic interference noise (EMI noise) generated from the first circuit board PCB and the second flexible circuit board FPCB.

[0101] In an embodiment, the insulating layer ISL may further include an inorganic material having black or an organic material having black. Accordingly, the third cover tape CT3 can prevent external light reflected by electrodes or wires included in the display substrate DP from being visible to the user.

[0102] The third cover tape CT3 may include a cutout portion RP curved with a predetermined curvature. That is, the second portion CT3-P2 of the third cover tape CT3 may include the cutout portion RP. A plurality of openings OP may be defined in the cutout portion RP. In an embodiment, in a plan view, the openings OP may be arranged in a row along one direction. In another embodiment, in a plan view, the openings OP may be arranged in a zigzag shape.

[0103] In an embodiment, as Figure 8 illustrated, the cutout portion RP may be defined as a part where a portion of the conductive layer CDL and a portion of the insulating layer ISL of the third cover tape CT3 are cut.

[0104] Figure 9 is a cross-sectional view of a display device according to another embodiment of the present disclosure. Figure 10 is illustrated Figure 9 of the fourth cover tape. For example, Figure 10 is a cross-sectional view of the cut shape of the fourth cover tape CT4.

[0105] Refer to Figure 9 and Figure 10 , a display device DD4 according to another embodiment of the present disclosure may include a display substrate DP, a packaging layer TFE, an antireflection layer ARL, a cover window CW, a cover panel CP, a driving chip D-IC, a first circuit board PCB, a second flexible circuit board FPCB, and a fourth cover tape CT4.

[0106] Except for the fourth cover tape CT4, the display device DD4 can be substantially the same as the reference Figure 7 and Figure 8 described display device DD3. Additionally, except for the shape of the cutout portion RP in the cross-section, the fourth cover tape CT4 can be substantially the same as the reference Figure 7 and Figure 8 described third cover tape CT3. Hereinafter, descriptions that are repetitive of those of the display device DD3 described with reference to Figure 7 and Figure 8 will be omitted or simplified.

[0107] The fourth cover tape CT4 can cover each of the driving chip D-IC, the first circuit board PCB, and the second flexible printed circuit board FPCB. The fourth cover tape CT4 can be bent such that a part of the fourth cover tape CT4 can be disposed under the display substrate DP. In an embodiment, for example, the fourth cover tape CT4 can include a first portion CT4-P1 disposed on the display substrate DP, a second portion CT4-P2 extending from the first portion CT4-P1 and bent with a predetermined curvature, and a third portion CT4-P3 extending from the second portion CT4-P2 and disposed under the display substrate DP. In this case, the first portion CT4-P1 can cover the driving chip D-IC. The second portion CT4-P2 can cover the second flexible printed circuit board FPCB. The third portion CT4-P3 can cover the first circuit board PCB.

[0108] As Figure 10 illustrated, the fourth cover tape CT4 can include an adhesive layer ADL, a conductive layer CDL disposed on the adhesive layer ADL, and an insulating layer ISL disposed on the conductive layer CDL.

[0109] The fourth cover tape CT4 can include a cutout portion RP bent with a predetermined curvature. That is, the second portion CT4-P2 of the fourth cover tape CT4 can include the cutout portion RP. A plurality of openings OP can be defined in the cutout portion RP. In an embodiment, the cutout portion RP can be defined as a part where a portion of the insulating layer ISL of the fourth cover tape CT4 is cut. In other words, compared with the cutout portion RP of the third cover tape CT3 of Figure 8 , the conductive layer CDL can not be cut and can have a substantially flat upper surface.

[0110] The present disclosure can be applied to various display devices. For example, the present disclosure is applicable to various display devices such as display devices for vehicles, ships, and airplanes, portable communication devices, display devices for exhibitions or information transmission, and medical display devices.

[0111] The foregoing is a description of embodiments of the present disclosure and should not be construed as a limitation thereof. Although some embodiments have been described with reference to the figures, those skilled in the art will readily understand that many changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as defined in the claims.

Claims

1. A display device, comprising: A display substrate, comprising a display area and a pad area adjacent to one side of the display area; A driving chip, disposed on the pad area of ​​the display substrate; A first circuit board is disposed under the display substrate and is electrically connected to the pad area; as well as A cover tape covers each of the driving chip and the first circuit board and includes a cutout portion.

2. The display device according to claim 1, wherein: The cover tape comprises: The first part covers the driver chip; a second portion extending from the first portion and bent with a predetermined curvature; and a third portion extending from the second portion and covering the first circuit board, and Wherein, the second portion of the cover tape includes the cutout portion.

3. The display device according to claim 1 or 2, wherein: a plurality of openings are defined in the cutout portion, and The plurality of openings are arranged in a row along one direction in a plan view.

4. The display device according to claim 1 or 2, wherein: a plurality of openings are defined in the cutout portion, and In a plan view, the plurality of openings are arranged in a zigzag shape.

5. A display device, comprising: A display substrate, comprising a display area and a pad area adjacent to one side of the display area; A driving chip, disposed on the pad area of ​​the display substrate; A first circuit board is disposed under the display substrate and is electrically connected to the pad area; as well as A cover tape covers each of the driving chip and the first circuit board, includes a conductive layer and an insulating layer disposed on the conductive layer, and includes a cutout portion bent with a predetermined curvature.

6. The display device according to claim 5, wherein: The insulating layer is an insulating layer having a black color.

7. The display device according to claim 5, wherein: The cover tape further includes an adhesive layer disposed below the conductive layer.

8. The display device according to claim 5, wherein: In the cutout portion, a portion of the insulating layer is cut.

9. The display device according to claim 5, wherein: In the cutout portion, a portion of the conductive layer and a portion of the insulating layer are cut.

10. The display device according to any one of claims 5 to 9, wherein: A plurality of openings are defined in the cutout portion.

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