Array substrate, display panel and display device

Abstract

The utility model discloses an array substrate, a display panel and a display device. The array substrate comprises a plurality of grid lines; a plurality of data lines; a plurality of pixel electrode rows, wherein the plurality of pixel electrode rows extend along the first direction and are arranged along the second direction; at least one pixel electrode row in the plurality of pixel electrode rows comprises a plurality of pixel electrodes with different light emitting colors; the pixel electrode is positioned in an area formed by crossing the grid line and the data line; the pixel electrodes are electrically connected to the grid lines and the data lines through the transistors, and the multiple pixel electrodes which are electrically connected to the same data line through the transistors are alternately located on different sides of the data lines; wherein two pixel electrodes which are located in at least part of adjacent pixel electrode rows and are electrically connected to the same data line through the transistors have the same light emitting color.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly to an array substrate, a display panel and a display device. Background Art

[0002] The liquid crystal display panel is a high and new technology that has developed rapidly in recent years. Due to its advantages of being thinner and lighter, low radiation, high contrast, fast response speed and low energy consumption, it has been widely used in flat panel display devices. Summary of the Utility Model

[0003] The utility model provides an array substrate, a display panel and a driving method of a display device. The array substrate includes:

[0004] A substrate;

[0005] A plurality of gate lines extending along a first direction;

[0006] A plurality of data lines extending along a second direction;

[0007] A plurality of pixel electrode rows extending along the first direction and arranged along the second direction; at least one pixel electrode row in the plurality of pixel electrode rows includes: a plurality of pixel electrodes with different light emitting colors; the pixel electrodes are located in an area formed by the intersection of the gate lines and the data lines;

[0008] A plurality of transistors, the pixel electrodes are electrically connected to the gate lines and the data lines through the transistors, and the plurality of pixel electrodes electrically connected to the same data line are alternately located on different sides of the data line;

[0009] Wherein, the light emitting colors of two pixel electrodes located in at least part of adjacent pixel electrode rows and electrically connected to the same data line through the transistors are the same.

[0010] In a possible implementation manner, among adjacent pixel electrode rows, the pixel electrodes with the same light emitting color are staggeredly distributed.

[0011] In a possible implementation manner, among adjacent pixel electrode rows, the minimum stagger width of the pixel electrodes with the same light emitting color is the same as the distance between two adjacent pixel electrodes in the same pixel electrode row.

[0012] In a possible implementation manner, the light emitting colors of any two pixel electrodes electrically connected to the same data line are the same.

[0013] In a possible implementation, the array substrate includes: a plurality of first pixel electrode repeating units; the first pixel electrode repeating unit includes: a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode, and a sixth pixel electrode;

[0014] Wherein, the first pixel electrode is electrically connected to the Nth gate line and the Mth data line through the transistor; the second pixel electrode is electrically connected to the Nth gate line and the (M + 1)th data line through the transistor; the third pixel electrode is electrically connected to the Nth gate line and the (M + 2)th data line through the transistor; the fourth pixel electrode is electrically connected to the (N + 1)th gate line and the (M + 1)th data line through the transistor; the fifth pixel electrode is electrically connected to the (N + 1)th gate line and the (M + 2)th data line through the transistor; the sixth pixel electrode is electrically connected to the (N + 1)th gate line and the (M + 3)th data line through the transistor; wherein, N and M represent positive integers;

[0015] The first pixel electrode and the sixth pixel electrode have the same light-emitting color; the second pixel electrode and the fourth pixel electrode have the same light-emitting color; the third pixel electrode and the fifth pixel electrode have the same light-emitting color.

[0016] In a possible implementation, the array substrate includes: a plurality of pixel electrode row groups extending along the first direction and arranged along the second direction; at least one pixel electrode row group among the plurality of pixel electrode row groups includes: two pixel electrode rows;

[0017] Two pixel electrodes that are electrically connected to the same data line through the transistor and are located in the same pixel electrode row group have the same light-emitting color.

[0018] In a possible implementation, two pixel electrodes that are electrically connected to the same data line through the transistor and are located in adjacent pixel electrode row groups have different light-emitting colors.

[0019] In a possible implementation, the array substrate includes: a plurality of second pixel electrode repeating units; the second pixel electrode repeating unit includes: a seventh pixel electrode, an eighth pixel electrode, a ninth pixel electrode, a tenth pixel electrode, an eleventh pixel electrode, a twelfth pixel electrode, a thirteenth pixel electrode, a fourteenth pixel electrode, a fifteenth pixel electrode, a sixteenth pixel electrode, a seventeenth pixel electrode, an eighteenth pixel electrode, a nineteenth pixel electrode, a twentieth pixel electrode, a twenty-first pixel electrode, a twenty-second pixel electrode, a twenty-third pixel electrode, a twenty-fourth pixel electrode, and a twenty-fifth pixel electrode;

[0020] Among them, the seventh pixel electrode is electrically connected to the J-th gate line and the K-th data line through the transistor; the eighth pixel electrode is electrically connected to the J-th gate line and the (K + 1)-th data line through the transistor; the ninth pixel electrode is electrically connected to the J-th gate line and the (K + 2)-th data line through the transistor; the tenth pixel electrode is electrically connected to the (J + 1)-th gate line and the (K + 1)-th data line through the transistor; the eleventh pixel electrode is electrically connected to the (J + 1)-th gate line and the (K + 2)-th data line through the transistor; the twelfth pixel electrode is electrically connected to the (J + 1)-th gate line and the (K + 3)-th data line through the transistor; the thirteenth pixel electrode is electrically connected to the (J + 2)-th gate line and the K-th data line through the transistor; the fourteenth pixel electrode is electrically connected to the (J + 2)-th gate line and the (K + 1)-th data line through the transistor; the fifteenth pixel electrode is electrically connected to the (J + 2)-th gate line and the (K + 2)-th data line through the transistor; the sixteenth pixel electrode is electrically connected to the (J + 3)-th gate line and the (K + 1)-th data line through the transistor; the seventeenth pixel electrode is electrically connected to the (J + 3)-th gate line and the (K + 2)-th data line through the transistor; the eighteenth pixel electrode is electrically connected to the (J + 3)-th gate line and the (K + 3)-th data line through the transistor; the nineteenth pixel electrode is electrically connected to the (J + 4)-th gate line and the K-th data line through the transistor; the twentieth pixel electrode is electrically connected to the (J + 4)-th gate line and the (K + 1)-th data line through the transistor; the twenty-first pixel electrode is electrically connected to the (J + 4)-th gate line and the (K + 2)-th data line through the transistor; the twenty-second pixel electrode is electrically connected to the (J + 5)-th gate line and the (K + 1)-th data line through the transistor; the twenty-third pixel electrode is electrically connected to the (J + 5)-th gate line and the (K + 2)-th data line through the transistor; the twenty-fourth pixel electrode is electrically connected to the (J + 5)-th gate line and the (K + 3)-th data line through the transistor; where J and K represent positive integers;

[0021] The light-emitting colors of the seventh pixel electrode, the twelfth pixel electrode, the fourteenth pixel electrode, the sixteenth pixel electrode, the twenty-first pixel electrode, and the twenty-third pixel electrode are the same; the light-emitting colors of the eighth pixel electrode, the tenth pixel electrode, the fifteenth pixel electrode, the seventeenth pixel electrode, the nineteenth pixel electrode, and the twenty-fourth pixel electrode are the same; the light-emitting colors of the ninth pixel electrode, the eleventh pixel electrode, the thirteenth pixel electrode, the eighteenth pixel electrode, the twentieth pixel electrode, and the twenty-second pixel electrode are the same.

[0022] In a possible implementation, the length of the pixel electrode in the first direction is greater than the length in the second direction.

[0023] In a possible implementation, the length of the pixel electrode in the first direction is less than the length in the second direction.

[0024] Based on the same inventive concept of the utility model, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure, and further includes an opposing substrate disposed opposite to the array substrate.

[0025] Based on the same inventive concept of the utility model, an embodiment of the present disclosure further provides a display device, which includes the display panel provided in the embodiment of the present disclosure. Description of the Drawings

[0026] Figure 1A One of the schematic diagrams of the pixel architecture provided by the embodiment of the present utility model;

[0027] Figure 1B Two of the schematic diagrams of the pixel architecture provided by the embodiment of the present utility model;

[0028] Figure 2A is Figure 1A The schematic layout diagram of the array substrate corresponding to the pixel architecture shown;

[0029] Figure 2B is Figure 2A The film layer diagram of the layer where the common electrode is located in;

[0030] Figure 2C is Figure 2A The film layer diagram of the layer where the gate line is located in;

[0031] Figure 2D is Figure 2A The film layer diagram of the layer where the active layer is located in;

[0032] Figure 2E is Figure 2A The film layer diagram of the data line in;

[0033] Figure 2F is Figure 2A The film layer diagram of the pixel electrode in;

[0034] Figure 3 Three of the schematic diagrams of the pixel architecture provided by the embodiment of the present utility model;

[0035] Figure 4 Four of the schematic diagrams of the pixel architecture provided by the embodiment of the present utility model;

[0036] Figure 5ASchematic diagram of sub-pixel arrangement corresponding to the triple-gate pixel architecture provided by an embodiment of the present utility model;

[0037] Figure 5B is Figure 5A an enlarged schematic diagram of one pixel in;

[0038] Figure 6A Schematic diagram of sub-pixel arrangement corresponding to the single-gate pixel architecture provided by an embodiment of the present utility model;

[0039] Figure 6B is Figure 6A an enlarged schematic diagram of one pixel in;

[0040] Figure 7 Timing diagram of the HSR mode provided by an embodiment of the present utility model;

[0041] Figure 8 Timing diagram of the DLG mode provided by an embodiment of the present utility model;

[0042] Figure 9 Schematic diagram of the driving method flow of the array substrate provided by an embodiment of the present utility model. Detailed implementation manners

[0043] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0045] As used herein, "about" or "substantially the same" includes the stated value and means within an acceptable deviation range for a particular value as determined by one of ordinary skill in the art in view of the measurement being discussed and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" can mean within one or more standard deviation ranges of the stated value, or within ±30%, 20%, 10%, 5%.

[0046] In the drawings, for clarity, the thickness of layers, films, panels, regions, etc. is exaggerated. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, deviations from the shape of the figures as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments described herein should not be construed as limited to the particular shapes of regions shown herein, but rather include deviations in shape resulting from, for example, manufacturing. For example, regions illustrated or described as flat may typically have rough and / or non-linear features. Additionally, sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of the regions and are not intended to limit the scope of the claims.

[0047] To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components are omitted from the present disclosure.

[0048] See Figure 1A 、 Figure 1B 、 Figure 2A - Figure 2F 、 Figure 3 and Figure 4 as shown, wherein Figure 1A is Figure 2A the equivalent pixel architecture diagram of Figure 2B is Figure 2A the film layer diagram of the layer where the common electrode is located in Figure 2C is Figure 2A the film layer diagram of the layer where the gate line is located in Figure 2D is Figure 2A the film layer diagram of the layer where the active layer is located in Figure 2E is Figure 2A the film layer diagram of the data line in Figure 2F is Figure 2A the film layer diagram of the pixel electrode in; An embodiment of the present invention provides an array substrate, which includes:

[0049] a substrate;

[0050] a plurality of gate lines G extending along a first direction X;

[0051] a plurality of data lines D extending along a second direction Y;

[0052] A plurality of pixel electrode rows P00 extend along a first direction X and are arranged along a second direction Y; at least one pixel electrode row P00 in the plurality of pixel electrode rows P00 includes: a plurality of pixel electrodes P with different light-emitting colors; the pixel electrodes P are located in an area formed by the intersection of the gate lines G and the data lines D;

[0053] A plurality of transistors T, the pixel electrodes P are electrically connected to the gate lines G and the data lines D through the transistors T, and the plurality of pixel electrodes P electrically connected to the same data line D are alternately located on different sides of the data line D; for example, referring to Figure 1A As shown, for the second data line D(M + 1) in the left-to-right direction, the plurality of pixel electrodes P electrically connected to the second data line D(M + 1) are respectively electrically connected to the second data line D(M + 1) alternately on the left and right. Specifically, as Figure 1A shown, in the up-and-down direction, the first pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the right side of the second data line D(M + 1), the second pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the left side of the second data line D(M + 1), the third pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the right side of the second data line D(M + 1), the fourth pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the left side of the second data line D(M + 1), the fifth pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the right side of the second data line D(M + 1), and the sixth pixel electrode P (i.e., the green pixel electrode G that emits green light) is electrically connected to the left side of the second data line D(M + 1);

[0054] Among them, the two pixel electrodes P that are located in at least some adjacent pixel electrode rows P00 and are electrically connected to the same data line D through the transistors T have the same light-emitting color. The light-emitting color of the pixel electrode P can be understood as the light-emitting color of the area where the pixel electrode P is located when the display panel is powered on for display. Specifically, for example, when the display panel is a liquid crystal display panel, the light-emitting color of the pixel electrode P can be the color emitted by the backlight through the color filter in the area where the pixel electrode P is located.

[0055] In the embodiments of the present disclosure, multiple pixel electrodes P electrically connected to the same data line D through a transistor T are alternately located on different sides of the data line D. Moreover, the light-emitting colors of two pixel electrodes P located in at least some adjacent pixel electrode rows P00 and electrically connected to the same data line D through a transistor T are the same. Furthermore, when performing display driving, data signals of the same data line D can be loaded onto two pixel electrodes P in adjacent pixel electrode rows P00, that is, data signals of the data line D can be shared by adjacent two rows of gate lines G. The double-frequency driving can be applied to increase the scanning frequency of the display panel, making the picture smoother and delay-free during the display process of the display panel, improving the specifications of the display device (for example, 60Hz → 120Hz), and enhancing the product competitiveness.

[0056] In the embodiments of the present disclosure, multiple pixel electrodes P electrically connected to the same data line D through a transistor T are alternately located on different sides of the data line D, that is, the display panel provided in the embodiments of the present disclosure has a Z-shaped architecture. For this pixel architecture, pixel-level dot flipping can be achieved by frame flipping of the data line, which can make the panel brightness uniformity better. Moreover, in frame flipping, within one frame, the same data line is either all positive-polarity signals or all negative-polarity signals. Compared with the dot flipping method, the frame flipping method has the advantages of low power consumption and less heat generation in the integrated circuit chip (IC). And the embodiments of the present utility model can achieve the effect of dot flipping through frame flipping, and while making the display panel brightness uniformity better, the display panel can also have the advantages of low power consumption and less heat generation in the integrated circuit chip (IC).

[0057] The display panel provided in the embodiments of the present disclosure can adopt the hardware super-resolution (HSR) technology and / or the dual line gate (DLG) mode of double-frequency driving with two adjacent rows of gate lines G turned on simultaneously. Without changing the original hardware and chip computing power, the refresh rate of the display panel can be increased by doubling the signal of the gate driving circuit. For example, the product specification of 60Hz FHD is 1920*1080*60Hz, which can be increased to 1920*540*120Hz; the product specification of 120Hz 4K is 3840*2160*120Hz, which can be increased to 3840*1080*240Hz.

[0058] The HSR driving mode can share the output mode of multiple scanning signals for data output. In order to enable adjacent two rows of scanning lines (gate lines G) to share the data of the data line D, the pixel architecture requires that one data line in adjacent two rows be connected to sub-pixels of the same color, so as to correctly display the R, G, B monochromatic pictures and the function of correctly displaying the picture. The DLG mode is that the timing of two rows of gate lines G scanning lines is the same and they are turned on simultaneously to share the data line signal. Therefore, one data line in every two rows needs to be connected to sub-pixels of the same color.

[0059] As Figure 7 shown, the data signal of "1" will be loaded onto the nth gate line and the (n + 1)th gate line; taking the pixel architecture shown in Figure 1B as an example, HSR driving can be implemented through the timing shown in Figure 7 . For example, when N = n and M = m, the nth gate line is controlled to be turned on. Among them, the effective period of the nth gate line sequentially includes: a starting period t0, and a first period t1; where the starting period t0 can be the pre-charging duration. For example, taking G(n + 4) as an example, the starting period t0 can pre-charge "1", "2", "2". The liquid crystal will also deflect during this starting period t0, but this stage is not the required data, so it can be called the pre-charging period, which can make the liquid crystal deflect in advance. When it comes to the first period t1, the pixel electrode will be charged to the required data "3", that is, the data pre-charged in the starting period t0 can be covered by the data in the first period t1; within the first period t1, a data signal with content such as "1" can be loaded onto the pixel electrode P through the data line D; due to the doubling of the scanning frequency of the gate line, when the data line still loads the data signal with content "1", the (n + 1)th gate line has also been turned on. Therefore, the data signal with content "1" can also be loaded onto the pixel electrode controlled by the (n + 1)th gate line.

[0060] What is different between the DLG mode and the HSR mode is that two adjacent gate lines are turned on simultaneously in pairs. Therefore, the same data signal can be loaded onto the pixel electrodes controlled by two gate lines at the same time.

[0061] In a possible implementation manner, referring to Figure 1B , Figure 2A , Figure 3 and Figure 5A shown, the length b1 of the pixel electrode P in the first direction X is greater than the length b2 in the second direction Y, that is, in the embodiments of the present disclosure, the display panel can be a display panel with a triple gate pixel architecture, which can reduce the number of chip on film (COF) used and lower the cost of the display panel; moreover, in the conventional triple gate pixel architecture, the light-emitting colors of the pixel electrodes located in two adjacent pixel electrode rows and electrically connected to the same data line are different, and frequency doubling driving cannot be achieved. However, in the embodiments of the present disclosure, for the display panel with a triple gate pixel architecture, for each data line D, every two adjacent pixel electrode rows are connected to the same color sub-pixels, and frequency doubling driving modes (HSR mode and / or DLG mode) can be achieved. Furthermore, while the display panel with a triple gate pixel architecture has the advantage of low cost, the picture can also be smoother and without delay during the display process, further enhancing the competitiveness of the display product.

[0062] In a possible implementation, refer to Figure 4 and Figure 6A As shown, the length b1 of the pixel electrode P in the first direction X is less than the length b2 in the second direction Y. That is, in the embodiments of the present disclosure, the display panel can also be a display panel with a single-gate pixel architecture. In a conventional single-gate pixel architecture, the light-emitting colors of the pixel electrodes located in two adjacent pixel electrode rows and electrically connected to the same data line are different, and frequency doubling driving cannot be achieved. However, in the embodiments of the present disclosure, for a display panel with a single-gate pixel architecture, for each data line D, every two adjacent pixel electrode rows are connected to the same color sub-pixels, and a frequency doubling driving mode (HSR mode and / or DLG mode) can be achieved, which can make the picture smoother and without delay during display, and further enhance the competitiveness of display products.

[0063] It should be noted that Figure 3 and Figure 4 , or Figure 5A and Figure 6A are mainly the differences between the Triple Gate and Single Gate architectures. Although Figure 3 and Figure 4 the pixel architectures shown are the same in terms of pixel connection sorting, but combined with different display panel architectures, they will be different pixel designs. That is, the total area and resolution of the display area AA are the same, but the number of gate lines and data lines and the COF usage are all different. Figure 3 or Figure 5A In the Triple Gate architecture shown in Figure 3 or Figure 5A , B-G-R in the second direction Y (i.e., the vertical direction) is one pixel (Pixel). The number of gate lines G (and the sub-pixels in the second direction Y) is 1080 * 3, and the number of data lines D (and the sub-pixels in the first direction X) is 1920. Therefore, the single-machine COF usage is 1920 / 960 = 2 pieces; the total width of the display area AA in the first direction X = b1 * 1920, and the total width of the display area AA in the second direction Y = b2 * 1080 * 3; Figure 4 or Figure 6A In the Single Gate architecture shown in Figure 4 or Figure 6A : B-G-R in the first direction X (i.e., the horizontal direction) is one Pixel. The number of data lines D (and the sub-pixels in the first direction X) is 1920 * 3, and the number of gate lines G (and the sub-pixels in the second direction Y) is 1080; so the single-machine COF usage is 1920 * 3 / 960 = 6 pieces, the total width of the display area AA in the first direction X = b1 * 1920 * 3, and the total width of the display area AA in the second direction Y = b2 * 1080.

[0064] In a possible implementation, refer to Figure 5B As shown, wherein Figure 5B is Figure 5ASchematic diagram of the magnification of a pixel, b1 = 3b2, and three sub-pixels can form a square pixel; in a possible implementation, refer to Figure 6B as shown, where Figure 6B is Figure 6A a schematic diagram of the magnification of a pixel in

[0065] In a possible implementation, refer to Figure 1A 、 Figure 3 and Figure 4 as shown, in adjacent pixel electrode rows P00, the pixel electrodes P with the same light-emitting color are misaligned. For example, as Figure 1A in, in the first pixel electrode row P100 and the second pixel electrode row P00 in the up-down direction, the green pixel electrodes G emitting green light are misaligned and do not lie in the same column. That is, the green pixel electrode G emitting green light in the first pixel electrode row P100 and the red pixel electrode R adjacent to the green pixel electrode G and emitting red light in the second pixel electrode row P00 lie in the same column.

[0066] In a possible implementation, refer to Figure 1B as shown, in adjacent pixel electrode rows P00, the minimum misalignment width a1 of the pixel electrodes P with the same light-emitting color is the same as the pitch a2 between two adjacent pixel electrodes P in the same pixel electrode row P00. Compared with the conventional technology, in the horizontal direction of each pixel electrode row in the embodiments of the present disclosure, the sub-pixels of the same color are displaced by one sub-pixel relative to the previous sub-pixel row to form a new pixel arrangement. In each pixel, the sub-pixels of the three primary colors R, G, and B are still retained, and the sub-pixel ratio in the pixel can be 1:1:1, maintaining the same resolution as the conventional structure, but the HSR frequency doubling mode can be applied, thereby increasing the refresh rate of the display panel.

[0067] In a possible implementation, refer to Figure 1B as shown, the array substrate includes: a plurality of first pixel electrode repeating units PA; the first pixel electrode repeating unit PA includes: a first pixel electrode P1, a second pixel electrode P2, a third pixel electrode P3, a fourth pixel electrode P4, a fifth pixel electrode P5, and a sixth pixel electrode P6;

[0068] Among them, the first pixel electrode P1 is electrically connected to the Nth gate line G and the Mth data line G through the transistor T; the second pixel electrode P2 is electrically connected to the Nth gate line G and the (M + 1)th data line D through the transistor T; the third pixel electrode P3 is electrically connected to the Nth gate line G and the (M + 2)th data line D through the transistor T; the fourth pixel electrode P4 is electrically connected to the (N + 1)th gate line G and the (M + 1)th data line D through the transistor T; the fifth pixel electrode P5 is electrically connected to the (N + 1)th gate line G and the (M + 2)th data line D through the transistor T; the sixth pixel electrode P6 is electrically connected to the (N + 1)th gate line G and the (M + 3)th data line D through the transistor T; where N and M represent positive integers.

[0069] The light-emitting colors of the first pixel electrode P1 and the sixth pixel electrode P6 are the same; the light-emitting colors of the second pixel electrode P2 and the fourth pixel electrode P4 are the same; the light-emitting colors of the third pixel electrode P3 and the fifth pixel electrode P5 are the same.

[0070] In the embodiments of the present disclosure, by adjusting the positions of different sub-pixels, a pixel arrangement manner with a 2-row * 3-column sub-pixel as the minimum cycle unit is formed to enable the display panel of the Triple Gate pixel architecture to apply the HSR frequency doubling mode, thereby further improving the specifications of the display device (for example, 60Hz → 120Hz) and enhancing the product competitiveness; moreover, compared with the prior art, in the embodiments of the present disclosure, a pixel arrangement manner with a 2-row * 3-column sub-pixel as the minimum cycle unit is formed, and the sub-pixels of the three primary colors RGB are still retained in each pixel, which can achieve a sub-pixel ratio of 1:1:1 in the pixel, maintain the same resolution, and at the same time can have one more application of the HSR frequency doubling mode to provide the refresh rate of the display panel.

[0071] In a possible implementation manner, as shown in Figure 1B the first pixel electrode P1 and the sixth pixel electrode P6 both emit blue light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit green light; the third pixel electrode P3 and the fifth pixel electrode P5 both emit red light.

[0072] In another possible implementation manner, the first pixel electrode P1 and the sixth pixel electrode P6 may also both emit blue light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit red light; the third pixel electrode P3 and the fifth pixel electrode P5 both emit green light.

[0073] In another possible implementation manner, the first pixel electrode P1 and the sixth pixel electrode P6 both emit green light; the second pixel electrode P2 and the fourth pixel electrode P4 both emit blue light; the third pixel electrode P3 and the fifth pixel electrode P5 both emit red light.

[0074] In another possible implementation, both the first pixel electrode P1 and the sixth pixel electrode P6 emit green light; both the second pixel electrode P2 and the fourth pixel electrode P4 emit red light; both the third pixel electrode P3 and the fifth pixel electrode P5 emit blue light.

[0075] In another possible implementation, both the first pixel electrode P1 and the sixth pixel electrode P6 emit red light; both the second pixel electrode P2 and the fourth pixel electrode P4 emit green light; both the third pixel electrode P3 and the fifth pixel electrode P5 emit blue light.

[0076] In another possible implementation, both the first pixel electrode P1 and the sixth pixel electrode P6 emit red light; both the second pixel electrode P2 and the fourth pixel electrode P4 emit blue light; both the third pixel electrode P3 and the fifth pixel electrode P5 emit green light.

[0077] For two pixel electrodes P that are located in at least partially adjacent pixel electrode rows P00 and are electrically connected to the same data line D through a transistor T, the light-emitting colors are the same. In one possible implementation, it can be that the light-emitting colors of any two pixel electrodes P electrically connected to the same data line D are the same. For example, Figure 1A in, for any one data line D, the light-emitting colors of multiple pixel electrodes P electrically connected to this data line D are the same. For example, for the second data line D in the left-to-right direction, the pixel electrodes P electrically connected to this second data line D are all green pixel electrodes G that emit green light; for another example, for the third data line D in the left-to-right direction, the pixel electrodes P electrically connected to this third data line D are all red pixel electrodes R that emit red light; for another example, for the fourth data line D in the left-to-right direction, the pixel electrodes P electrically connected to this fourth data line D are all blue pixel electrodes B that emit blue light.

[0078] In the embodiments of the present disclosure, the light-emitting colors of any two pixel electrodes P electrically connected to the same data line D are the same, which can simultaneously support the implementation of the HSR mode and the DLG mode.

[0079] For two pixel electrodes P that are located in at least partially adjacent pixel electrode rows P00 and are electrically connected to the same data line D through a transistor T, the light-emitting colors are the same. In one possible implementation, it can also be that every two adjacent pixel electrode rows form a group, and the light-emitting colors of the two pixel electrodes P located in the two pixel electrode rows of this group and electrically connected to the same data line D are the same. Specifically, in combination with Figure 3 or Figure 4As shown, the array substrate includes: a plurality of pixel electrode row groups PZ extending along a first direction X and arranged along a second direction Y; at least one pixel electrode row group PZ among the plurality of pixel electrode row groups PZ includes: two pixel electrode rows P00; two pixel electrodes P that are electrically connected to the same data line D through a transistor T and are located in the same pixel electrode row group PZ have the same light-emitting color.

[0080] In an embodiment of the present disclosure, any two pixel electrodes P electrically connected to the same data line D have the same light-emitting color, and a DLG mode can be realized.

[0081] In a possible implementation manner, in combination with Figure 3 or Figure 4 As shown, two pixel electrodes P that are electrically connected to the same data line D through a transistor T and are located in adjacent pixel electrode row groups PZ have different light-emitting colors. For example, as Figure 3 In, for the second data line D in the left-to-right direction, among the plurality of pixel electrodes P electrically connected to the second data line D, in the up-to-down direction, there are successively two green pixel electrodes G that emit green light, two blue pixel electrodes B that emit blue light, and two red pixel electrodes R that emit red light.

[0082] In a possible implementation manner, referring to Figure 3 or Figure 4 As shown, the array substrate includes: a plurality of second pixel electrode repeating units PB; the second pixel electrode repeating unit PB includes: a seventh pixel electrode P7, an eighth pixel electrode P8, a ninth pixel electrode P9, a tenth pixel electrode P10, an eleventh pixel electrode P11, a twelfth pixel electrode P12, a thirteenth pixel electrode P13, a fourteenth pixel electrode P14, a fifteenth pixel electrode P15, a sixteenth pixel electrode P16, a seventeenth pixel electrode P17, an eighteenth pixel electrode P18, a nineteenth pixel electrode P19, a twentieth pixel electrode P20, a twenty-first pixel electrode P21, a twenty-second pixel electrode P22, a twenty-third pixel electrode P23, a twenty-fourth pixel electrode P24, and a twenty-fifth pixel electrode P25;

[0083] Among them, the seventh pixel electrode P7 is electrically connected to the J-th gate line G and the K-th data line D through the transistor T; the eighth pixel electrode P8 is electrically connected to the J-th gate line G and the (K + 1)-th data line D through the transistor T; the ninth pixel electrode P9 is electrically connected to the J-th gate line G and the (K + 2)-th data line D through the transistor T; the tenth pixel electrode P10 is electrically connected to the (J + 1)-th gate line G and the (K + 1)-th data line D through the transistor T; the eleventh pixel electrode P11 is electrically connected to the (J + 1)-th gate line G and the (K + 2)-th data line D through the transistor T; the twelfth pixel electrode P12 is electrically connected to the (J + 1)-th gate line G and the (K + 3)-th data line D through the transistor T; the thirteenth pixel electrode P13 is electrically connected to the (J + 2)-th gate line G and the K-th data line D through the transistor T; the fourteenth pixel electrode P14 is electrically connected to the (J + 2)-th gate line G and the (K + 1)-th data line D through the transistor T; the fifteenth pixel electrode P15 is electrically connected to the (J + 2)-th gate line G and the (K + 2)-th data line D through the transistor T; the sixteenth pixel electrode P16 is electrically connected to the (J + 3)-th gate line G and the (K + 1)-th data line D through the transistor T; the seventeenth pixel electrode P17 is electrically connected to the (J + 3)-th gate line G and the (K + 2)-th data line D through the transistor T; the eighteenth pixel electrode P18 is electrically connected to the (J + 3)-th gate line G and the (K + 3)-th data line D through the transistor T; the nineteenth pixel electrode P19 is electrically connected to the (J + 4)-th gate line G and the K-th data line D through the transistor T; the twentieth pixel electrode P20 is electrically connected to the (J + 4)-th gate line G and the (K + 1)-th data line D through the transistor T; the twenty-first pixel electrode P21 is electrically connected to the (J + 4)-th gate line G and the (K + 2)-th data line D through the transistor T; the twenty-second pixel electrode P22 is electrically connected to the (J + 5)-th gate line G and the (K + 1)-th data line D through the transistor T; the twenty-third pixel electrode P23 is electrically connected to the (J + 5)-th gate line G and the (K + 2)-th data line D through the transistor T; the twenty-fourth pixel electrode P24 is electrically connected to the (J + 5)-th gate line G and the (K + 3)-th data line D through the transistor T; where J and K represent positive integers;

[0084] The light-emitting colors of the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 are the same; the light-emitting colors of the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 are the same; the light-emitting colors of the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 are the same.

[0085] In the embodiments of the present disclosure, by adjusting the positions of different sub-pixels, a pixel arrangement manner with a minimum repeating unit of 6 rows * 3 columns of sub-pixels is formed to enable a display panel with a Triple Gate pixel structure or a single-gate pixel structure to apply the HSR frequency doubling mode, thereby further improving the specifications of the display device (for example, 60Hz → 120Hz) and enhancing the product competitiveness.

[0086] In a possible implementation manner, referring to Figure 3 or Figure 4 as shown, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 may all emit blue light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 may all emit green light; the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 may all emit red light.

[0087] In another possible implementation manner, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 may all emit blue light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 may all emit red light; the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 may all emit green light.

[0088] In another possible implementation manner, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 may all emit green light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 may all emit blue light; the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 may all emit red light.

[0089] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 may all emit green light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 may all emit red light; the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 may all emit blue light.

[0090] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 may all emit red light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 may all emit green light; the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 may all emit blue light.

[0091] In another possible implementation, the seventh pixel electrode P7, the twelfth pixel electrode P12, the fourteenth pixel electrode P14, the sixteenth pixel electrode P16, the twenty-first pixel electrode P21, and the twenty-third pixel electrode P23 may all emit red light; the eighth pixel electrode P8, the tenth pixel electrode P10, the fifteenth pixel electrode P15, the seventeenth pixel electrode P17, the nineteenth pixel electrode P19, and the twenty-fourth pixel electrode P24 may all emit blue light; the ninth pixel electrode P9, the eleventh pixel electrode P11, the thirteenth pixel electrode P13, the eighteenth pixel electrode P18, the twentieth pixel electrode P20, and the twenty-second pixel electrode P22 may all emit green light.

[0092] In a possible implementation, Figure 2B - Figure 2FIt can be a single-layer schematic diagram of each film layer sequentially disposed on the substrate. That is, on the substrate of the array substrate, a common electrode layer, a gate line layer, an active layer, a data line layer, and a pixel electrode layer can be sequentially disposed. Among them, the common electrode layer can include a plurality of common electrode blocks Z arranged in an array. There may be no insulating layer between the common electrode layer and the layer where the gate line G is located. There is a gap between the common electrode block Z and the gate line G, and they are insulated from each other. The layer where the gate line G is located can also include a plurality of first common connection lines G0 extending along the first direction X. A plurality of common electrode blocks Z in the first direction X can be directly lapped with the first common connection line G0 to connect the plurality of common electrode blocks Z in the first direction X to each other. The layer where the pixel electrode P is located can also include a plurality of lapping portions P0. As shown in Figure 2A FIG. [Reference numeral not provided], a plurality of common electrode blocks Z in the second direction Y can be electrically connected to each other through the lapping portion P0, so that the plurality of common electrode blocks Z are connected to each other in the second direction Y, and further the common electrode layer forms a structure of horizontal and vertical electrical connection. Optionally, the common electrode block Z and the lapping portion P0 can be electrically connected through a via K2. Optionally, the active layer can include a plurality of active patterns F. The pixel electrode P can be electrically connected to the drain of the transistor T through a first via K1. Optionally, the common electrode block Z can be a block electrode, and the pixel electrode P can have a plurality of slits.

[0093] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the array substrate provided by the embodiment of the present disclosure.

[0094] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes the above-mentioned display panel provided by the embodiment of the present disclosure. For the implementation of this display device, reference can be made to the embodiment of the above-mentioned display panel, and the repeated parts will not be described again.

[0095] In specific implementation, in the embodiment of the present disclosure, the display device can be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of this display device are understood by those of ordinary skill in the art and will not be described here, nor should it be regarded as a limitation to the present disclosure.

[0096] Based on the same inventive concept, an embodiment of the present disclosure further provides a driving method for driving the array substrate provided by the embodiment of the present disclosure. As shown in Figure 9 FIG. [Reference numeral not provided], the driving method includes:

[0097] Step S100, controlling the data lines to sequentially load data signals;

[0098] Step S200: During the period when the same data signal is loaded on the data line, control at least two adjacent gate lines to be turned on, so that two pixel electrodes that are electrically connected to the same data line through transistors and are located in adjacent pixel electrode rows load the same data signal.

[0099] In a possible implementation manner, as shown in Figure 7 for Step S200: During the period when the same data signal is loaded on the data line, controlling at least two adjacent gate lines to be turned on includes:

[0100] Control the nth gate line to be turned on, and control the (n + 1)th gate line to be turned on, where the (n + 1)th gate line has a first period t1 that is turned on simultaneously with the nth gate line, and a second period t2 that is turned off after the nth gate line;

[0101] Load the first data signal on the mth data line during the first period t1 and the second period t2, so that two pixel electrodes electrically connected to the nth, (n + 1)th gate lines, and the mth data line both load the first data signal, where n and m represent positive integers.

[0102] In a possible implementation manner, as shown in Figure 8 for Step S200: During the period when the same data signal is loaded on the data line, controlling at least two adjacent gate lines to be turned on includes:

[0103] Control the jth and (j + 1)th gate lines to be turned on simultaneously, where the (j + 1)th gate line has a third period t3 that is turned on simultaneously with the jth gate line;

[0104] Load the second data signal on the kth data line during the third period t4, so that two pixel electrodes electrically connected to the jth, (j + 1)th gate lines, and the kth data line both load the second data signal, where j represents an odd or even number, and k represents a positive integer.

[0105] In a possible implementation manner, in the current frame, the polarities of the valid signals loaded on adjacent data lines can be opposite. For example, one data line loads a positive-polarity data signal, and the adjacent data line loads a negative-polarity data signal; in the next frame, the valid signal loaded on each data line can be opposite to the polarity of the valid data signal loaded on this data line in the previous frame. For example, in the current frame, one data line loads a positive-polarity data signal, and in the next frame, this data line loads a negative-polarity data signal.

[0106] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present disclosure.

[0107] Obviously, those skilled in the art can make various changes and modifications to the present utility model without departing from the spirit and scope of the present utility model. Thus, if these modifications and variations of the present utility model fall within the scope of the claims of the present utility model and their equivalent technologies, the present utility model is also intended to include these changes and modifications.

Claims

1. An array substrate, wherein: include: substrate; A plurality of grid lines extending along a first direction; a plurality of data lines extending along a second direction; a plurality of pixel electrode rows extending along the first direction and arranged along the second direction; At least one pixel electrode row among the plurality of pixel electrode rows comprises: a plurality of pixel electrodes with different light emitting colors; the pixel electrode is located in a region formed by the intersection of the gate line and the data line; A plurality of transistors, the pixel electrodes are electrically connected to the gate line and the data line through the transistors, and the plurality of pixel electrodes electrically connected to the same data line through the transistors are alternately located on different sides of the data line; Wherein, the light emitting colors of two pixel electrodes located in at least partially adjacent pixel electrode rows and electrically connected to the same data line through the transistor are the same.

2. The array substrate according to claim 1, wherein: In adjacent rows of pixel electrodes, the pixel electrodes with the same light output color are staggered.

3. The array substrate according to claim 2, wherein: In adjacent rows of pixel electrodes, the minimum offset width of the pixel electrodes with the same light output color is the same as the spacing between two adjacent pixel electrodes in the same row of pixel electrodes.

4. The array substrate according to any one of claims 1 to 3, wherein: Any two pixel electrodes electrically connected to the same data line have the same light output color.

5. The array substrate according to claim 4, wherein: The array substrate comprises: a plurality of first pixel electrode repeating units; the first pixel electrode repeating unit comprises: a first pixel electrode, a second pixel electrode, a third pixel electrode, a fourth pixel electrode, a fifth pixel electrode and a sixth pixel electrode; wherein the first pixel electrode is electrically connected to the Nth gate line and the Mth data line through the transistor; the second pixel electrode is electrically connected to the Nth gate line and the M+1th data line through the transistor; the third pixel electrode is electrically connected to the Nth gate line and the M+2th data line through the transistor; the fourth pixel electrode is electrically connected to the N+1th gate line and the M+1th data line through the transistor; the fifth pixel electrode is electrically connected to the N+1th gate line and the M+2th data line through the transistor; the sixth pixel electrode is electrically connected to the N+1th gate line and the M+3th data line through the transistor; wherein N and M represent positive integers; The first pixel electrode and the sixth pixel electrode have the same light output color; the second pixel electrode and the fourth pixel electrode have the same light output color; and the third pixel electrode and the fifth pixel electrode have the same light output color.

6. The array substrate according to any one of claims 1 to 3, wherein: The array substrate comprises: a plurality of pixel electrode row groups extending along the first direction and arranged along the second direction; at least one pixel electrode row group among the plurality of pixel electrode row groups comprises: two pixel electrode rows; The two pixel electrodes electrically connected to the same data line through the transistor and located in the same pixel electrode row group have the same light output color.

7. The array substrate according to claim 6, wherein: The two pixel electrodes electrically connected to the same data line through the transistor and located in adjacent pixel electrode row groups have different light emission colors.

8. The array substrate according to claim 6 or 7, wherein: The array substrate comprises: a plurality of second pixel electrode repeating units; the second pixel electrode repeating units comprise: a seventh pixel electrode, an eighth pixel electrode, a ninth pixel electrode, a tenth pixel electrode, an eleventh pixel electrode, a twelfth pixel electrode, a thirteenth pixel electrode, a fourteenth pixel electrode, a fifteenth pixel electrode, a sixteenth pixel electrode, a seventeenth pixel electrode, an eighteenth pixel electrode, a nineteenth pixel electrode, a twentieth pixel electrode, a twenty-first pixel electrode, a twenty-second pixel electrode, a twenty-third pixel electrode, a twenty-fourth pixel electrode and a twenty-fifth pixel electrode; wherein the seventh pixel electrode is electrically connected to the J-th gate line and the K-th data line through the transistor; the eighth pixel electrode is electrically connected to the J-th gate line and the K+1-th data line through the transistor; the ninth pixel electrode is electrically connected to the J-th gate line and the K+2-th data line through the transistor; the tenth pixel electrode is electrically connected to the J+1-th gate line and the K+1-th data line through the transistor; the eleventh pixel electrode is electrically connected to the J+1-th gate line and the K+1-th data line through the transistor the K+2th data line; the twelfth pixel electrode is electrically connected to the J+1th gate line and the K+3th data line through the transistor; the thirteenth pixel electrode is electrically connected to the J+2th gate line and the Kth data line through the transistor; the fourteenth pixel electrode is electrically connected to the J+2th gate line and the K+1th data line through the transistor; the fifteenth pixel electrode is electrically connected to the J+2th gate line and the K+2th data line through the transistor; the sixteenth pixel electrode is electrically connected to the J+2th gate line and the K+2th data line through the transistor The transistor is electrically connected to the J+3th gate line and the K+1th data line; the seventeenth pixel electrode is electrically connected to the J+3th gate line and the K+2th data line through the transistor; the eighteenth pixel electrode is electrically connected to the J+3th gate line and the K+3th data line through the transistor; the nineteenth pixel electrode is electrically connected to the J+4th gate line and the Kth data line through the transistor; the twentieth pixel electrode is electrically connected to the J+4th gate line and the K+1th data line through the transistor the data line; the twenty-first pixel electrode is electrically connected to the J+4th gate line and the K+2th data line through the transistor; the twenty-second pixel electrode is electrically connected to the J+5th gate line and the K+1th data line through the transistor; the twenty-third pixel electrode is electrically connected to the J+5th gate line and the K+2th data line through the transistor; the twenty-fourth pixel electrode is electrically connected to the J+5th gate line and the K+3th data line through the transistor; wherein J and K represent positive integers; The seventh pixel electrode, the twelfth pixel electrode, the fourteenth pixel electrode, the sixteenth pixel electrode, the twenty-first pixel electrode, and the twenty-third pixel electrode have the same light emitting color; the eighth pixel electrode, the tenth pixel electrode, the fifteenth pixel electrode, the seventeenth pixel electrode, the nineteenth pixel electrode, and the twenty-fourth pixel electrode have the same light emitting color; the ninth pixel electrode, the eleventh pixel electrode, the thirteenth pixel electrode, the eighteenth pixel electrode, the twentieth pixel electrode, and the twenty-second pixel electrode have the same light emitting color.

9. The array substrate according to any one of claims 1 to 8, wherein: The length of the pixel electrode in the first direction is greater than the length in the second direction.

10. The array substrate according to any one of claims 1 to 3 and 6 to 8, wherein: The length of the pixel electrode in the first direction is smaller than the length of the pixel electrode in the second direction.

11. A display panel, wherein: It comprises the array substrate as claimed in any one of claims 1 to 10, and also comprises an opposite substrate arranged opposite to the array substrate.

12. A display device, wherein: Comprising the display panel as claimed in claim 11.

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