Display device

Abstract

The utility model relates to a display device. The display device includes: a bank including a first bank layer and a second bank layer each having side surfaces defining bank openings corresponding to light emitting regions, respectively, the second bank layer protruding much than the side surfaces of the first bank layer to define a tip of the second bank layer; an inorganic encapsulation layer on the bank and including a first pattern and a second pattern each having a body corresponding to the light emitting region and a wing portion extending from the body, the wing portions overlapping each other and spaced apart from an upper surface of the second bank layer at a tip, the second pattern further including a connecting portion, the connecting portion is connected to the body of the second pattern and the first wing portion, and between the first wing portion of the first pattern and the second bank layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of, and all rights arising from, Korean Patent Application No. 10 - 2023 - 0097311, filed on July 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a display device and a method of providing the same. Background art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. For example, display devices are applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and an organic light - emitting display device. Among these flat panel display devices, a light - emitting display device includes light - emitting elements that enable each pixel of the display panel to emit light by itself. Therefore, the light - emitting display device can display an image without a backlight unit that provides light to the display panel.

[0005] Display devices have been applied to glasses - like devices for providing virtual reality and augmented reality. To be applied to glasses - like devices, the display device is implemented in a very small size of two inches or less. Summary of the utility model

[0006] In the case of applying a relatively small display device to an electronic device, the display device has a high pixel density to have a high resolution. For example, a display device applied to a glasses - like device may have a high pixel density of 400 pixels per inch (PPI) or more. When the display device is implemented in a very small size as described above but has a high pixel density, it may be difficult to implement individual light - emitting elements in each light - emitting area of the display device through a mask process because the planar area of the light - emitting area in which the light - emitting elements are disposed is reduced.

[0007] Aspects of the present disclosure provide a display device capable of forming individual light - emitting elements in each emission area without a mask process.

[0008] Aspects of the present disclosure also provide a display device having improved encapsulation reliability at the tip of a second bank layer.

[0009] However, aspects of the present disclosure are not limited to the aspects set forth herein. Through reference to the detailed description of the present disclosure given below, the above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0010] According to an embodiment of the present disclosure, a display device includes: a first pixel electrode and a second pixel electrode spaced apart from each other on a substrate; a pixel defining layer disposed on the substrate and exposing the first pixel electrode and the second pixel electrode; a first light-emitting layer and a first common electrode, the first light-emitting layer being on the first pixel electrode and the first common electrode being on the first light-emitting layer; a second light-emitting layer and a second common electrode, the second light-emitting layer being on the second pixel electrode and the second common electrode being on the second light-emitting layer; a first bank layer disposed on the pixel defining layer; a second bank layer disposed on the first bank layer and including side surfaces protruding much more than the side surfaces of the first bank layer; a first inorganic layer including a main body portion disposed on the first common electrode and a first wing portion disposed on the second bank layer but spaced apart from the upper surface of the second bank layer; and a second inorganic layer including a main body portion disposed on the second common electrode, a first connecting portion disposed between the first wing portion of the first inorganic layer and the second bank layer, and a first wing portion disposed on the first wing portion of the first inorganic layer.

[0011] The first inorganic layer may further include a second wing portion connecting the main body portion of the first inorganic layer and the first wing portion of the first inorganic layer and spaced apart from the upper surface of the second bank layer, wherein the first wing portion of the first inorganic layer may include a first side surface overlapping with the first light-emitting layer and a second side surface opposite to the first side surface, the second wing portion of the first inorganic layer may include a first side surface overlapping with the first light-emitting layer and a second side surface opposite to the first side surface of the second wing portion, and the second side surface of the first wing portion of the first inorganic layer may protrude much more than the second side surface of the second wing portion of the first inorganic layer.

[0012] The first wing portion of the second inorganic layer may be spaced apart from the first wing portion of the first inorganic layer.

[0013] The second inorganic layer may further include a third wing portion protruding in the thickness direction of the substrate from the first connecting portion of the second inorganic layer and a second wing portion connecting the third wing portion of the second inorganic layer and the first wing portion of the second inorganic layer, wherein the first wing portion of the second inorganic layer may include a first side surface adjacent to the second light-emitting layer and a second side surface opposite to the first side surface of the first wing portion of the second inorganic layer, the second wing portion of the second inorganic layer may include a first side surface adjacent to the second light-emitting layer and a second side surface opposite to the first side surface of the second wing portion of the second inorganic layer, and the second side surface of the first wing portion of the second inorganic layer may protrude much more than the second side surface of the second wing portion of the second inorganic layer.

[0014] The display device may further include a first void space between the second wing portion of the first inorganic layer and the second bank layer.

[0015] The second inorganic layer may further include a second connection portion connected to the first connection portion of the second inorganic layer and disposed on the second side surface of the second wing portion of the first inorganic layer, and a third connection portion connecting the second connection portion of the second inorganic layer and the main body portion of the second inorganic layer.

[0016] The display device may further include a second organic pattern disposed on the second bank layer and including the same material as the second light-emitting layer, wherein a part of the second bank layer may contact the third connection portion of the second inorganic layer, and another part of the second bank layer may contact the second organic pattern.

[0017] The first connection portion of the second inorganic layer may contact the lower surface of the first wing portion of the first inorganic layer, and the second connection portion of the second inorganic layer may contact the second side surface of the second wing portion of the first inorganic layer.

[0018] The thickness of the first wing portion of the first inorganic layer may be less than the thickness of the second wing portion of the first inorganic layer.

[0019] The distance between the first wing portion of the first inorganic layer and the first wing portion of the second inorganic layer may be greater than the distance between the second pixel electrode and the main body portion of the second inorganic layer.

[0020] The distance between the second bank layer and the second wing portion of the first inorganic layer may be equal to the distance between the first pixel electrode and the main body portion of the first inorganic layer.

[0021] The display device may further include an organic encapsulation layer disposed between the first wing portion of the first inorganic layer and the first wing portion of the second inorganic layer.

[0022] The main body portion of the first inorganic layer may include silicon (Si), oxygen (O), and nitrogen (N), and the first wing portion of the first inorganic layer may include silicon (Si) and oxygen (O).

[0023] The first wing portion of the first inorganic layer may include silicon (Si) and oxygen (O), and the first connection portion of the second inorganic layer may include silicon (Si) and nitrogen (N).

[0024] The first common electrode and the second common electrode may be spaced apart from each other and contact the side surface of the first bank layer.

[0025] The display device may further include a residual pattern disposed between the pixel defining layer and the first pixel electrode and between the pixel defining layer and the second pixel electrode.

[0026] According to an embodiment of the present disclosure, a method of manufacturing (or providing) a display device includes: forming (or disposing) pixel electrodes spaced apart from each other on a substrate; forming a sacrificial layer on each of the pixel electrodes; forming a pixel defining material layer on the sacrificial layer; forming a first bank material layer on the pixel defining material layer, and forming a second bank material layer on the first bank material layer; exposing the pixel defining material layer by etching the first bank material layer and the second bank material layer in a region overlapping with the pixel electrodes; etching side surfaces of the first bank material layer to partially expose a lower surface of the second bank material layer; exposing the pixel electrodes by etching the exposed pixel defining material layer and the sacrificial layer; forming a first light emitting layer on a first pixel electrode among the pixel electrodes, and forming a first light emitting material layer on the second bank material layer; forming a first common electrode on the first light emitting layer, and forming a first electrode material layer on the first light emitting material layer; forming a first inorganic material layer on the first common electrode and the first electrode material layer; forming a mask pattern on the first inorganic material layer overlapping with the first pixel electrode; and removing the first inorganic material layer not covered by the mask pattern and a part of the first inorganic material layer covered by the mask pattern.

[0027] When forming a mask pattern on the first inorganic material layer overlapping with the first pixel electrode and removing the first inorganic material layer not covered by the mask pattern and a part of the first inorganic material layer covered by the mask pattern, an isotropic etching process can be used to remove silicon nitride or silicon oxynitride to form a protruding side surface of the first inorganic material layer.

[0028] The method of manufacturing a display device may further include: etching the first electrode material layer and the first light emitting material layer; forming a second light emitting layer on a second pixel electrode among the pixel electrodes, and forming a second light emitting material layer on the second bank material layer and the first inorganic material layer; forming a second common electrode on the second light emitting layer, and forming a second electrode material layer on the second light emitting material layer; and forming a second inorganic material layer on the second common electrode, the second electrode material layer, the second bank material layer and the first inorganic material layer.

[0029] Forming the second light emitting material layer on the second bank material layer and the first inorganic material layer may include: separating a light emitting material deposited on the substrate by the protruding side surface of the first inorganic material layer, and forming the second inorganic material layer on the second common electrode, the second electrode material layer, the second bank material layer and the first inorganic material layer may include: forming the second inorganic material layer between the second bank material layer and the first inorganic material layer.

[0030] According to a display device and a manufacturing method thereof according to an embodiment, the lower inorganic encapsulation layer includes wing portions on a second bank layer, and adjacent lower inorganic encapsulation layers may cover upper and lower portions of the wing portions. Since the sealing between the lower inorganic encapsulation layer and the light-emitting device is excellent, the reliability of the display device can be improved.

[0031] However, the effects according to the embodiments of the present disclosure are not limited to those of the above examples, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to an embodiment;

[0034] Figure 2 is a cross-sectional view of the Figure 1 display device viewed from the side;

[0035] Figure 3 is a plan view showing the arrangement of emission regions in a display device according to an embodiment;

[0036] Figure 4 is a perspective exploded view showing the Figure 3 laminated structure of the light-emitting element layer in region B with respect to the lower inorganic encapsulation layer;

[0037] Figure 5 is a cross-sectional view of a part of a display device according to an embodiment;

[0038] Figure 6 is a Figure 5 magnified cross-sectional view of region A1;

[0039] Figure 7 is a flowchart showing a process of providing (or manufacturing) a display device according to an embodiment; and

[0040] Figures 8 to 20 is a cross-sectional view showing a process in a method of providing (or manufacturing) a display device according to an embodiment. DETAILED DESCRIPTION

[0041] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0042] It will also be understood that when a layer is referred to as being related to another element, such as "on" another layer or substrate, it can be directly on the other layer or substrate, or there can also be intervening layers. Conversely, when a layer is referred to as being related to another element, such as "directly on" another layer or substrate, there are no other layers, substrates, or intervening layers between them.

[0043] Throughout the specification, like reference numerals indicate like elements.

[0044] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0045] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, "a", "an", "the", and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. Thus, the reference to "a" element followed by reference to "the" element in the claims includes one element and a plurality of elements. For example, "element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be construed as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms "comprise" and / or "comprising" or "include" and / or "including" are used in this specification, they specify the presence of the stated features, regions, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components, and / or groups thereof.

[0046] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another as shown in the figures. It will also be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is flipped, an element described as on the "lower" side of another element will then be oriented on the "upper" side of the other element. Thus, depending on the particular orientation of the figure, the term "lower" can include both the "lower" and "upper" orientations. Similarly, if the device in one of the figures is flipped, an element described as "below" or "beneath" another element will then be oriented "above" the other element. Thus, the terms "below" or "beneath" can include both the above and below orientations.

[0047] In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximate" includes the stated value and means within an acceptable deviation of the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] Embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, deviations from the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, the embodiments described herein are not to be construed as limited to the particular shapes of regions as shown herein, but will include, for example, shape deviations resulting from manufacturing. For example, regions shown or described as flat will generally have rough and / or non-linear features. Additionally, sharp corners shown may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the exact shape of the regions and are not intended to limit the scope of the claims.

[0050] Hereinafter, embodiments will be described with reference to the drawings.

[0051] Figure 1 is a perspective view of a display device 10 according to an embodiment.

[0052] Reference Figure 1, the display device 10 according to an embodiment may be included in an electronic device to provide a display screen where the electronic device displays an image. The electronic device may refer to any electronic device that provides a display screen. Examples of the electronic device may include a television, a laptop computer, a monitor, a billboard, an Internet of Things (IoT) device, a mobile phone, a smartphone, a tablet personal computer (PC), an electronic watch, smart glasses, a smartwatch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, a gaming device, a digital camera, and a camcorder, all of which provide a display screen.

[0053] The shape of the display device 10 may be variously modified. For example, the display device 10 may have a planar shape similar to a rectangle having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. Each corner at the intersection of the short side extending in the first direction DR1 and the long side extending in the second direction DR2 may be rounded to have a curvature in a plan view. However, the present disclosure is not limited thereto, and the corners may also be right angles. The planar shape of the display device 10 is not limited to a quadrilateral shape, but may also be similar to other polygonal shapes, circular shapes, or elliptical shapes.

[0054] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, and a touch driver 400 (see Figure 2 ).

[0055] The display panel 100 may include a main area MA and a sub-area SBA.

[0056] The main area MA may include a display area DA and a non-display area NDA adjacent to the display area DA, and the display area DA includes pixels for displaying an image. In an embodiment, in a plan view, the non-display area NDA is disposed around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas (e.g., a plurality of light-emitting areas including a plurality of light-emitting areas). For example, the display panel 100 may include a pixel circuit having a switching element, a pixel defining layer defining the emission area and / or the opening area, and a self-luminous element connected to the pixel circuit.

[0057] For example, each of the self-luminous elements as light-emitting elements may include, but is not limited to, at least one of an organic light-emitting diode including an organic light-emitting layer, a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, and a micro light-emitting diode.

[0058] Multiple pixels, multiple scan lines, multiple data lines, and multiple power lines may be provided in the display area DA. Each of the pixels may be defined as a minimum unit that emits light, displays an image, etc., and the self-emitting elements described above may be respectively in the pixels. The light-emitting elements may correspond to or define the pixels, however, it is not limited thereto. The scan line, which is a signal line, may provide a scan signal (which is an electrical signal received from the scan driver) to the pixels. The data line, which is a signal line, may provide a data voltage (which is an electrical signal received from the display driver 200) to the pixels. The power line, which is a signal line, may provide a power supply voltage (which is an electrical signal received from the display driver 200) to the pixels.

[0059] The non-display area NDA may be an area outside the display area DA (e.g., a planar area) so as to be closer to the outer edge of the display device 10 than the display area DA. The non-display area NDA may be defined as an edge area of the main area MA of the display panel 100. The non-display area NDA may include a scan driver that provides a scan signal to the scan lines and fan-out lines connecting the display driver 200 and the components in the display area DA.

[0060] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, curled, etc. For example, when the display device 10 is bent at the sub-area SBA, the sub-area SBA may overlap the main area MA in the thickness direction (e.g., the third direction DR3) (or along the thickness direction (e.g., the third direction DR3)). That is, the thickness of the display device 10 and its various components or layers may be defined along the third direction DR3, which intersects the plane defined by the first direction DR1 and the second direction DR2 that intersect each other. The sub-area SBA may include the display driver 200 and a pad unit connected to the circuit board 300. In an embodiment, the sub-area SBA may be omitted, and the display driver 200 and the pad unit may be provided in the non-display area NDA. In an embodiment, the sub-area SBA may be a part of the non-display area NDA.

[0061] The display driver 200 can output signals and voltages for driving the display panel 100. The display driver 200 can supply data voltages to data lines. The display driver 200 can supply a power supply voltage to a power line and supply a scan control signal to a scan driver. The display driver 200 can be formed (or set) as an integrated circuit and mounted on the display panel 100, such as by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method on the display panel 100. For example, the display driver 200 can be disposed in the sub-region SBA and can overlap with the main region MA in the thickness direction DR3 (third direction DR3) in the display device 10 that is bent at the sub-region SBA. For another example, the display driver 200 can be mounted on the circuit board 300.

[0062] The circuit board 300 can be attached to the pad unit of the display panel 100, such as by using an anisotropic conductive film (ACF). The leads of the circuit board 300 can be electrically connected to the display panel 100 at the pad unit of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0063] Figure 2 is a cross-sectional view of the display device 10 viewed from the side. Specifically, Figure 1 of the display device 10. Specifically, Figure 2 shows one side of the display device 10 in a folded state. The display device 10 and its various components or layers can be bendable, foldable, rollable, etc., so as to deform together with each other. Figure 1 of the display device 10 in a folded state. The display device 10 and its various components or layers can be bendable, foldable, rollable, etc., so as to deform together with each other.

[0064] Referring to Figure 2 , the display panel 100 can include a substrate SUB, a thin film transistor layer TFTL as a circuit layer, a light emitting element layer EML, a thin film encapsulation layer TFEL as a packaging layer, and a color filter layer CFL as a color control layer.

[0065] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a flexible substrate that can be bent, folded, rolled, etc. For example, the substrate SUB can include a polymer resin such as polyimide (PI), but the present disclosure is not limited thereto. In an embodiment, the substrate SUB can include a glass material or a metal material.

[0066] The thin film transistor layer TFTL may be disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors constituting a pixel circuit of a pixel. The thin film transistor layer TFTL may further include scan lines, data lines, power lines, scan control lines, fan-out lines connecting the display driver 200 and the data lines to each other, and leads connecting the display driver 200 and the pad unit to each other. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a scan driver is formed (or disposed) on one side of the non-display area NDA of the display panel 100 as a driver, the driver may include thin film transistors.

[0067] The thin film transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, scan lines, data lines, and power lines of the pixels of the thin film transistor layer TFTL may be disposed in the display area DA. The scan control lines and fan-out lines of the thin film transistor layer TFTL may be disposed in the non-display area NDA. The leads of the thin film transistor layer TFTL may be disposed in the sub-area SBA.

[0068] The light-emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light-emitting element layer EML may include a plurality of light-emitting elements and a pixel defining layer defining a pixel. Each light-emitting element includes a first electrode, a second electrode, and a light-emitting layer to emit light. The light-emitting elements of the light-emitting element layer EML may be disposed in the display area DA. The light-emitting element layer EML may be electrically connected to a circuit layer (e.g., the thin film transistor layer TFTL) to emit light, display an image with light, etc.

[0069] In an embodiment, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the first electrode receives a voltage through the thin film transistors of the thin film transistor layer TFTL and the second electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively. Then, the holes and electrons may recombine with each other in the organic light-emitting layer to emit light.

[0070] In an embodiment, each of the light-emitting elements may include: a quantum dot light-emitting diode including a quantum dot light-emitting layer; an inorganic light-emitting diode including an inorganic semiconductor; or a micro light-emitting diode.

[0071] The thin film encapsulation layer TFEL may cover the upper surface and the side surface of the light-emitting element layer EML, and may protect the light-emitting element layer EML from the influence of the environment outside the thin film transistor layer TFTL. The thin film encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer to encapsulate the light-emitting element layer EML.

[0072] The color filter layer CFL may be disposed on the thin film encapsulation layer TFEL. The color filter layer CFL may include a plurality of color filters respectively corresponding to a plurality of emission regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths, such as controlling the color of light. The color filter layer CFL may absorb a part of the external light from outside the display device 10, thereby reducing the reflected light caused by the external light. Therefore, the color filter layer CFL may prevent color distortion caused by the reflection of the external light to further control the light.

[0073] In an embodiment, since the color filter layer CFL is directly disposed on the thin film encapsulation layer TFEL, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the total thickness of the display device 10 may be relatively small.

[0074] In some embodiments, the display device 10 may further include an optical device that provides functions to the display device 10 as a functional component of the display device 10. The optical device may emit or receive light in the infrared, ultraviolet, and visible light bands to provide functions. For example, the optical device may be an optical sensor that senses the light incident on the display device 10 to provide a light sensing function, such as a proximity sensor that provides a proximity sensing function, an illuminance sensor that provides a light sensing function, a camera sensor that captures images, a fingerprint sensor that detects fingerprints, or an image sensor that detects images.

[0075] Figure 3 is a plan view of a part of the display device 10 according to an embodiment. Figure 3 is a plan view showing the arrangement of the emission regions EA1 to EA3 in the display region DA of the display device 10.

[0076] Reference Figure 3 , the display device 10 may include a plurality of emission regions EA1 to EA3 disposed in the display region DA. The emission regions EA1 to EA3 may include a first emission region EA1, a second emission region EA2, and a third emission region EA3 that emit light of different colors. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may emit red light, green light, or blue light, respectively. The color of the light respectively emitted from each of the emission regions EA1 to EA3 may vary according to the type of the light emitting elements ED1, ED2, or ED3 (see Figure 5 ) to be described later. For example, the first emission region EA1 may emit first light of red color, the second emission region EA2 may emit second light of green color, and the third emission region EA3 may emit third light of blue color. However, the present disclosure is not limited thereto.

[0077] The emission regions EA1 to EA3 may be arranged in a type, for example, diamond Type. For example, the first emission region EA1 and the third emission region EA3 may be spaced apart from each other in the first direction DR1 and may be alternately arranged with each other in the first direction DR1. The emission regions within the first emission region EA1 of a column or the third emission region EA3 of a column may be spaced apart from each other along the second direction DR2. The emission regions of adjacent columns (or adjacent rows) may be spaced apart from each other along the first direction DR1 (or the second direction DR2). Each of the second emission regions EA2 may be spaced apart from another adjacent second emission region EA2 in the first direction DR1 and the second direction DR2. The second emission region EA2 and the first emission region EA1 or the second emission region EA2 and the third emission region EA3 may be alternately arranged with each other along any single direction in a plane formed by the first direction DR1 and the second direction DR2 intersecting each other. In an embodiment, the order of the three emission regions of different colors may be arranged along a direction inclined with respect to the first direction DR1 and / or the second direction DR2.

[0078] Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be defined by a pixel defining layer PDL (see Figure 4 ).

[0079] In the display device 10, the first emission region EA1, the second emission region EA2, and the third emission region EA3 arranged adjacent to each other may form a pixel group. Referring to Figure 3 , region B represents a pixel group. Figure 4 is Figure 3 exploded perspective view of region B of

[0080] Referring to Figure 4 , the pixel defining layer PDL defines the first emission region EA1, the second emission region EA2, and the third emission region EA3. Here, the pixel defining layer PDL may define the planar size, planar shape, planar position, etc. of the first emission region EA1, the second emission region EA2, and the third emission region EA3. In Figure 4 , for ease of explanation, the light emitting elements, thin film transistor layers, etc. are omitted.

[0081] The first bank layer BN1, the second bank layer BN2, and the first inorganic layer TL1 to the third inorganic layer TL3 are sequentially stacked on the pixel defining layer PDL to define a stacked structure on the pixel defining layer PDL. In the stacked structure, exposed regions corresponding to the first emission region EA1, the second emission region EA2, and the third emission region EA3 are defined in each of the first bank layer BN1, the second bank layer BN2, and the first inorganic layer TL1 to the third inorganic layer TL3. As used herein, the exposed region may correspond to an opening or a hole in a layer or a material portion (solid portion) of the layer.

[0082] The exposed area of the first bank layer BN1 may overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3, but may have a planar size that is respectively larger than the planar sizes of the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0083] The exposed area of the second bank layer BN2 may overlap with the first emission area EA1, the second emission area EA2, and the third emission area EA3, but may have a planar size that is respectively smaller than the planar size of the exposed area of the first bank layer BN1.

[0084] The exposed area of the first inorganic layer TL1 may entirely overlap with the second emission area EA2 and the third emission area EA3. The exposed areas of the first inorganic layer TL1 corresponding to the second emission area EA2 and the third emission area EA3 may be connected to each other, such as being a single opening, to overlap with the entirety of the second emission area EA2 and the third emission area EA3 and the planar area directly surrounding the second emission area EA2 and the third emission area EA3.

[0085] The exposed area of the second inorganic layer TL2 may entirely overlap with the first emission area EA1 and the third emission area EA3. The exposed areas of the second inorganic layer TL2 corresponding to the first emission area EA1 and the third emission area EA3 may be disconnected from each other so as to respectively overlap with the entire planar areas of the first emission area EA1 and the third emission area EA3 and the planar area directly surrounding the first emission area EA1 and the third emission area EA3. In an embodiment, the exposed areas of the second inorganic layer TL2 corresponding to the first emission area EA1 and the third emission area EA3 may be connected to each other to provide a single opening.

[0086] The exposed area of the third inorganic layer TL3 may entirely overlap with the first emission area EA1 and the second emission area EA2.

[0087] Figure 5 is a cross-sectional view of a part of the display device 10 according to an embodiment. Figure 5 The horizontal direction in the view of may represent any one of a plurality of directions along a plane formed by a first direction DR1 and a second direction DR2 that intersect each other. Specifically, Figure 5 is Figure 3 and Figure 4 is a cross-sectional view taken along line I-I' of the portions within each of the layers of and. Figure 5 Further shows provided in Figure 4The organic encapsulation layer TFE2, the upper inorganic encapsulation layer TFE3, the color filters CF1 to CF3, the light blocking layer BM, and the outer coating OC on the third inorganic layer TL3, and the thin film transistor layer TFTL and the substrate SUB disposed below the pixel defining layer PDL. Refer to Figure 5 , the thin film transistor layer TFTL, the light emitting element layer EML, the thin film encapsulation layer TFEL, and the color filter layer CFL may be sequentially stacked on the substrate SUB, that is, arranged in one direction starting from the substrate SUB.

[0088] The thin film transistor layer TFTL may include a first buffer layer BF1, a bottom metal layer BML of a metal pattern that is a metal pattern layer, a second buffer layer BF2, a thin film transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first passivation layer PAS1, a second connection electrode CNE2, and a second passivation layer PAS2. One or more of the above-mentioned insulating layers may be regarded as "an insulating layer".

[0089] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer capable of preventing the penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers stacked alternately with each other.

[0090] The bottom metal layer BML may be disposed on the first buffer layer BF1. For example, each pattern among the bottom metal layers BML may be a single layer or a multi-layer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0091] The second buffer layer BF2 may cover the first buffer layer BF1 and the bottom metal layer BML. The second buffer layer BF2 may include an inorganic layer capable of preventing the penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic layers stacked alternately with each other.

[0092] The thin film transistor TFT may be disposed on the second buffer layer BF2. The thin film transistor TFT may constitute the corresponding pixel circuits of a plurality of pixels. For example, each of the thin film transistors TFT may be a driving transistor or a switching transistor of the pixel circuit. Each of the thin film transistors TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0093] The semiconductor layer ACT may be disposed on the second buffer layer BF2. The semiconductor layer ACT may overlap with the bottom metal layer BML and the gate electrode GE in the thickness direction DR3, and may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0094] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap with the semiconductor layer ACT in the thickness direction DR3, and the gate insulating layer GI is interposed therebetween.

[0095] The gate insulating layer GI may be disposed on the semiconductor layer ACT. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2, and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes. That is, a contact hole may be defined in the gate insulating layer GI. As used herein, the contact hole may completely penetrate the corresponding layer so as to open at both the upper surface and the lower surface opposite to the upper surface of the corresponding layer.

[0096] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include (or define) a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2 so as to form a single corresponding contact hole.

[0097] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap with the gate electrode GE in the thickness direction DR3. A capacitance may be formed between the capacitor electrode CPE and the gate electrode GE.

[0098] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0099] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may extend through the corresponding contact holes formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the thin film transistor TFT.

[0100] The first passivation layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first passivation layer PAS1 may protect the thin film transistor TFT. The first passivation layer PAS1 may include contact holes through which or into which the second connection electrode CNE2 passes or extends.

[0101] The second connection electrode CNE2 may be disposed on the first passivation layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1 to AE3 of the light-emitting element ED, respectively. The second connection electrode CNE2 may be inserted into (e.g., extend through) the contact holes formed in the first passivation layer PAS1 to contact the first connection electrode CNE1. The first connection electrode CNE1 in contact with the second connection electrode CNE2 may form a connection electrode together with the second connection electrode CNE2.

[0102] The second passivation layer PAS2 may cover the second connection electrode CNE2 and the first passivation layer PAS1. The second passivation layer PAS2 may include contact holes through which the pixel electrodes AE1 to AE3 of the light-emitting element ED pass.

[0103] The light-emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light-emitting element layer EML may include a light-emitting element ED, a pixel defining layer PDL, a capping layer CAP, and a bank structure BNS. The light-emitting element ED may include pixel electrodes AE1 to AE3, light-emitting layers EL1 to EL3, and common electrodes CE1 to CE3, respectively.

[0104] Figure 6 is Figure 5 an enlarged cross-sectional view of region A1 of

[0105] associated Figure 5 reference Figure 6 , the display device 10 may include a plurality of emission regions EA1 to EA3 disposed in the display area DA. The emission regions EA1 to EA3 may include or define a planar region in which light is emitted from the light-emitting elements ED1 to ED3 (which respectively include pixel electrodes AE1 to AE3, light-emitting layers EL1 to EL3, and common electrodes CE1 to CE3) and passes through the color filter layer CFL in the third direction DR3. The boundaries between adjacent emission regions among the emission regions EA1 to EA3 may be defined by the pixel defining layer PDL. The emission regions EA1 to EA3 may include a first emission region EA1, a second emission region EA2, and a third emission region EA3 that are spaced apart from each other and emit light of the same color or different colors from each other.

[0106] In an embodiment, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have the same planar area or planar dimension. For example, in the display device 10, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may have the same area. However, the present disclosure is not limited thereto. In the display device 10, the first emission region EA1, the second emission region EA2, and the third emission region EA3 may also have different areas or dimensions from each other. For example, the area (e.g., planar area) of the second emission region EA2 may be greater than the areas of the first emission region EA1 and the third emission region EA3, and the area of the third emission region EA3 may be greater than the area of the first emission region EA1. The intensity of light emitted from each of the emission regions EA1 to EA3 may vary according to the corresponding area of the emission regions EA1, EA2, or EA3, and the color of an image displayed on the display screen of the display device 10 may be controlled by adjusting the area of each of the emission regions EA1 to EA3. In Figure 4 the embodiment, for illustrative purposes, the emission regions EA1 to EA3 have the same area. However, the present disclosure is not limited thereto.

[0107] In the display device 10, one first emission region EA1, one second emission region EA2, and one third emission region EA3 adjacent to each other may form a pixel group. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may be sequentially arranged along the light-emitting element layer EML. A pixel group may include the emission regions EA1 to EA3 that emit light of different colors to present a white gray level. However, the present disclosure is not limited thereto, and the combination of the emission regions EA1 to EA3 constituting a pixel group may be differently modified according to the arrangement of the emission regions EA1 to EA3 and the colors of light emitted from the emission regions EA1 to EA3.

[0108] A plurality of openings formed or defined in the bank structure BNS of the light-emitting element layer EML are defined to extend along the boundary of the bank structure BNS. That is, the solid part (or material part) of the bank structure BNS may have sidewalls that define the openings, and the openings may extend around the periphery of the solid part in a plan view. The first bank layer BN1 and the second bank layer BN2 may together provide the bank structure BNS, and its solid part may surround the emission regions EA1 to EA3. The areas of the bank openings of the bank structure BNS may respectively include the areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3.

[0109] The display device 10 may include a plurality of light-emitting elements ED1 to ED3 disposed in different emission regions EA1 to EA3. The light-emitting elements ED1 to ED3 may include a first light-emitting element ED1 disposed in the first emission region EA1, a second light-emitting element ED2 disposed in the second emission region EA2, and a third light-emitting element ED3 disposed in the third emission region EA3.

[0110] The light-emitting elements ED1 to ED3 may respectively include pixel electrodes AE1 to AE3, light-emitting layers EL1 to EL3, and common electrodes CE1 to CE3.

[0111] The light-emitting elements ED1 to ED3 disposed in different emission regions EA1 to EA3 may emit light of different colors from each other according to the materials of the light-emitting layers EL1 to EL3. For example, the first light-emitting element ED1 disposed in the first emission region EA1 may emit first light of red having a peak wavelength of about 610 nanometers (nm) to about 650 nm, the second light-emitting element ED2 disposed in the second emission region EA2 may emit second light of green having a peak wavelength of about 510 nm to about 550 nm, and the third light-emitting element ED3 disposed in the third emission region EA3 may emit third light of blue having a peak wavelength of about 440 nm to about 480 nm.

[0112] The first emission region EA1, the second emission region EA2, and the third emission region EA3 constituting one pixel group may include the light-emitting elements ED1 to ED3 that emit light of different colors from each other to present a white gray level. Optionally, the light-emitting layers EL1 to EL3 may include two or more materials that emit light of different colors such that one light-emitting layer may emit mixed light. For example, the light-emitting layers EL1 to EL3 may include a red light-emitting material and a green light-emitting material to emit yellow light, or may include a red light-emitting material, a green light-emitting material, and a blue light-emitting material to emit white light.

[0113] The pixel electrodes AE1 to AE3 may be disposed on the second passivation layer PAS2. The pixel electrodes AE1 to AE3 may be respectively disposed in the emission regions EA1 to EA3. The pixel electrodes AE1 to AE3 may include a first pixel electrode AE1 disposed in the first emission region EA1, a second pixel electrode AE2 disposed in the second emission region EA2, and a third pixel electrode AE3 disposed in the third emission region EA3. The first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3 may be spaced apart from each other along the second passivation layer PAS2.

[0114] The pixel electrodes AE1 to AE3 can be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2, respectively. The first pixel electrode AE1 to the third pixel electrode AE3 can be insulated from each other through a material portion of the pixel defining layer PDL that covers the edges of the pixel electrodes AE1 to AE3 spaced apart from each other.

[0115] The pixel electrodes AE1 to AE3 can include a transparent electrode material or / and a conductive metal material. The metal material can be at least one of silver (Ag), copper (Cu), aluminum (Al), nickel (Ni), lanthanum (La), titanium (Ti), and titanium nitride (TiN). The transparent electrode material can be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The pixel electrodes AE1 to AE3 can have a multilayer structure including a transparent electrode material and a conductive metal material.

[0116] The pixel defining layer PDL can be disposed on the second passivation layer PAS2, the residual pattern RP, and the pixel electrodes AE1 to AE3. Except for the pixel openings corresponding to the light emitting regions (where the upper surfaces of the pixel electrodes AE1 to AE3 are exposed to the outside of the pixel defining layer PDL), the pixel defining layer PDL can be disposed over the entire second passivation layer PAS2 to cover the side surfaces of the pixel electrodes AE1 to AE3 and the residual pattern RP. For example, at the corresponding pixel openings, the pixel defining layer PDL can expose the first pixel electrode AE1 in the first emission region EA1, and the first light emitting layer EL1 can be directly disposed on the first pixel electrode AE1 exposed to the outside of the pixel defining layer PDL at the corresponding pixel openings.

[0117] The pixel defining layer PDL can include an inorganic insulating material. The pixel defining layer PDL can include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, tantalum oxide, hafnium oxide, zinc oxide, and an amorphous silicon layer.

[0118] According to an embodiment, the pixel defining layer PDL can be disposed on the pixel electrodes AE1 to AE3, but can be spaced apart from the upper surfaces of the pixel electrodes AE1 to AE3. For example, within the pixel opening, a portion of the pixel defining layer PDL can partially overlap with the upper surfaces of the pixel electrodes AE1 to AE3 in the thickness direction DR3 of the substrate SUB, but can not directly contact the upper surfaces of the pixel electrodes AE1 to AE3, such that the residual pattern RP can be disposed between the pixel defining layer PDL and the pixel electrodes AE1 to AE3 within the pixel opening. At the regions adjacent to the light emitting regions, the sidewalls of the pixel defining layer PDL can directly contact the side surfaces of the pixel electrodes AE1 to AE3.

[0119] The side surface of the pixel definition layer PDL defines a pixel opening, while the side surface of the bank structure BNS defines a bank opening. The opening may have a thickness portion (or a volume portion) arranged along the thickness direction DR3 and corresponding to various material layers (e.g., the pixel definition layer PDL, the first bank layer BN1, the second bank layer BN2, etc.). Refer to Figure 5 and Figure 6 , for example, the side surface of the pixel definition layer PDL at its upper thickness portion may protrude much more toward the emission regions EA1 to EA3 than the side surface at the upper thickness portion of the bank structure BNS defined by the second bank layer BN2.

[0120] The residual pattern RP may be provided on the outer edge of each of the pixel electrodes AE1 to AE3. In a region adjacent to the light-emitting region, within the pixel opening, the pixel definition layer PDL may not directly contact the upper surface of the pixel electrodes AE1 to AE3 due to the residual pattern RP provided therebetween.

[0121] In an embodiment, when the sacrificial layer SFL provided on the pixel electrodes AE1 to AE3 is partially removed during the process of manufacturing or providing the display device 10 (refer to Figure 9 ), the residual pattern RP may be formed or provided. The residual pattern RP, which is the remaining portion of the sacrificial layer SFL, may include a metal, an oxide semiconductor, or a transparent conductive oxide (TCO). In the drawings, the inner surface of the residual pattern RP facing the emission regions EA1 to EA3 (e.g., the inner surface closest to the light-emitting region) is recessed from the inner surface of the pixel definition layer PDL defined at its upper thickness portion. However, the present disclosure is not limited thereto. The inner surface of the residual pattern RP may also be aligned with the inner surface of the pixel definition layer PDL, or may protrude much more than the inner surface of the pixel definition layer PDL in the direction toward the emission regions EA1 to EA3.

[0122] The light-emitting layers EL1 to EL3 may be provided on the pixel electrodes AE1 to AE3. The light-emitting layers EL1 to EL3 may be organic light-emitting layers made of or including organic materials, and may be formed on the pixel electrodes AE1 to AE3 by a deposition process, for example. Each of the light-emitting layers EL1 to EL3 may have a multilayer structure and may include a hole injection material, a hole transport material, a light-emitting material, an electron transport material, and / or an electron injection material. When the thin-film transistor TFT applies a predetermined voltage to the pixel electrodes AE1 to AE3 of the light-emitting elements ED1 to ED3 and the common electrodes CE1 to CE3 of the light-emitting elements ED1 to ED3 receive a common voltage or a cathode voltage, holes and electrons may be injected and transported, respectively, and then may recombine with each other in the light-emitting layers EL1 to EL3 to emit light.

[0123] The light-emitting layers EL1 to EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3 respectively disposed in different emission regions EA1 to EA3. The first light-emitting layer EL1 may be disposed on the first pixel electrode AE1 in the first emission region EA1, the second light-emitting layer EL2 may be disposed on the second pixel electrode AE2 in the second emission region EA2, and the third light-emitting layer EL3 may be disposed on the third pixel electrode AE3 in the third emission region EA3. The light-emitting layers EL1 to EL3 may emit light of different colors, or one of the light-emitting layers EL1, EL2, or EL3 may emit a combination of light as mixed light. In an embodiment, the first light-emitting layer EL1 may emit red light, the second light-emitting layer EL2 may emit green light, and the third light-emitting layer EL3 may emit blue light. In an embodiment, the first light-emitting layer EL1 may emit yellow light, which is a mixture of red light and green light, and the second light-emitting layer EL2 may emit blue light. In an embodiment, the first light-emitting layer EL1 may emit white light, which is a mixture of red light, green light, and blue light.

[0124] The light-emitting layers EL1 to EL3 may extend beyond the corresponding pixel openings to be disposed on the upper surface of the pixel defining layer PDL. The light-emitting layers EL1 to EL3 may be disposed in a space or gap defined between the pixel electrodes AE1 to AE3 and the pixel defining layer PDL at the pixel openings. The light-emitting layers EL1 to EL3 may contact the pixel defining layer PDL, the residual pattern RP, and the pixel electrodes AE1 to AE3.

[0125] The common electrodes CE1 to CE3 may be disposed on the light-emitting layers EL1 to EL3. The common electrodes CE1 to CE3 may include a transparent conductive material to allow the light generated by the light-emitting layers EL1 to EL3 to pass therethrough. The common electrodes CE1 to CE3 may receive a common voltage or a low-potential voltage. When the pixel electrodes AE1 to AE3 receive voltages corresponding to data voltages and the common electrodes CE1 to CE3 receive a low-potential voltage, a potential difference may be formed between the pixel electrodes AE1 to AE3 and the common electrodes CE1 to CE3. Accordingly, the light-emitting layers EL1 to EL3 may emit light.

[0126] The common electrodes CE1 to CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 respectively disposed in different emission regions EA1 to EA3. The first common electrode CE1 may be disposed on the first light-emitting layer EL1 in the first emission region EA1, the second common electrode CE2 may be disposed on the second light-emitting layer EL2 in the second emission region EA2, and the third common electrode CE3 may be disposed on the third light-emitting layer EL3 in the third emission region EA3. The first common electrode CE1 to the third common electrode CE3 may be discrete patterns spaced apart from each other.

[0127] The capping layer CAP can be disposed on the common electrodes CE1 to CE3. The capping layer CAP can include an organic or inorganic insulating material to cover the patterns disposed on the light-emitting elements ED1 to ED3. The capping layer CAP can prevent the light-emitting elements ED1 to ED3 from being damaged by external air (e.g., the air outside the light-emitting elements ED1 to ED3). In an embodiment, the capping layer CAP can include an organic material such as α-NPD (2,2'-dimethyl-N,N'-bis[(1-naphthyl)-N,N'-diphenyl]-1,1'-biphenyl-4,4'-diamine), NPB (N,N'-bis(naphthalen-1-yl)-N,N'-diphenyl-benzidine), TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), m-MTDATA (4,4',4''-[tris(3-methylphenyl)phenylamino]triphenylamine), Alq3 (tris(8-hydroxyquinoline)aluminum), and / or CuPc (copper(II) phthalocyanine), or can include an inorganic material such as LiF, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0128] The display device 10 can include a bank structure BNS disposed on the pixel defining layer PDL. The bank structure BNS can have a structure in which bank layers BN1 and BN2 including different materials are sequentially stacked. The bank structure BNS can include a plurality of openings (e.g., bank openings) having an area larger than the areas of the emission regions EA1 to EA3, and a solid portion that can overlap with the light blocking layer BM (to be described later). The light-emitting elements ED1 to ED3 of the display device 10 can overlap with or be disposed in the bank openings of the bank structure BNS.

[0129] The bank structure BNS can include a first bank layer BN1 and a second bank layer BN2 sequentially stacked in one direction from the pixel defining layer PDL.

[0130] The first bank layer BN1 can be disposed on the pixel defining layer PDL and can be closer to the pixel defining layer PDL than the second bank layer BN2 along the thickness direction DR3. The side surface of the first bank layer BN1 can be recessed from the side surface of the pixel defining layer PDL in a direction opposite to the direction toward the emission regions EA1 to EA3 (e.g., in a direction away from each light-emitting region). The side surface of the first bank layer BN1 can be recessed from the side surface of the second bank layer BN2 (to be described later) in a direction opposite to the direction toward the emission regions EA1 to EA3.

[0131] According to an embodiment, the first bank layer BN1 can include a metal material. In an embodiment, the first bank layer BN1 can include aluminum (Al) or an alloy of aluminum (Al).

[0132] In an embodiment, the thickness of the first bank layer BN1 can be in the range of about 4000 angstroms to about . When the above range is satisfied, the light-emitting layers EL1 to EL3 and the common electrodes CE1 to CE3 that are separated from each other can be formed by a deposition and etching process instead of a mask process.

[0133] According to an embodiment, the common electrodes CE1 to CE3 can directly contact a part of the side surface of the first bank layer BN1 that defines the bank opening. The common electrodes CE1 to CE3 of different light-emitting elements ED1 to ED3 can directly contact the first bank layer BN1, such as directly contacting the first bank layer BN1 at its side surface, and the first bank layer BN1 can include a metal material. Therefore, the common electrodes CE1 to CE3 can be electrically connected to each other through the first bank layer BN1 that is a conductive layer.

[0134] The light-emitting layers EL1 to EL3 can directly contact the side surface of the first bank layer BN1. The area of contact between the common electrodes CE1 to CE3 and the side surface of the first bank layer BN1 can be larger than the area of contact between the light-emitting layers EL1 to EL3 and the side surface of the first bank layer BN1. Here, the area of contact can be separately defined as the plane or surface of the corresponding element. Compared with the light-emitting layers EL1 to EL3, the common electrodes CE1 to CE3 can be disposed on a larger area of the side surface of the first bank layer BN1, or can be disposed to a higher position along the side surface of the first bank layer BN1. The higher position can be a height or a distance from a reference (such as from the pixel defining layer PDL, the substrate SUB, etc.). Since the common electrodes CE1 to CE3 of different light-emitting elements ED1 to ED3 are electrically connected to each other through the first bank layer BN1, it may be advantageous for the common electrodes CE1 to CE3 to have a relatively large contact area with the first bank layer BN1.

[0135] The second bank layer BN2 can be disposed on the first bank layer BN1. The second bank layer BN2 can include a tip BN2_TP that defines an inner surface of the second bank layer BN2, and the inner surface is closest to the light-emitting region and protrudes from the corresponding inner surface of the first bank layer BN1 on the same side of the light-emitting region. The facing inner surfaces of the second bank layer BN2 at the same light-emitting region can protrude much more toward the emission regions EA1 to EA3 than the corresponding inner surfaces of the first bank layer BN1.

[0136] Since the side surface of the second bank layer BN2 protrudes much more in the direction toward the emission regions EA1 to EA3 than the side surface of the first bank layer BN1, an undercut structure of the bank structure BNS can be formed together with the first bank layer BN1 under each tip BN2_TP of the second bank layer BN2.

[0137] In the display device 10 according to the embodiment, since the bank structure BNS includes tips BN2_TP (e.g., bank tips) protruding toward the emission regions EA1 to EA3, the light-emitting layers EL1, EL2, and EL3 and the common electrodes CE1, CE2, and CE3 can be formed by a deposition and etching process instead of a mask process. In addition, even by a deposition process, different layers can be separately formed in the different emission regions EA1 to EA3 because the bank tips are used to disconnect the material layers and form patterns separated from each other. For example, even when the material layers for providing the light-emitting layers EL1 to EL3 of the light-emitting elements ED1 to ED3 and the material layers for providing the common electrodes CE1 to CE3 are formed by a deposition process without using a mask, the deposited material layers may not be connected to each other in the region between the emission regions EA1 to EA3, but may be separated from each other by the tips BN2_TP of the second bank layer BN2, and the bank structure BNS is interposed therebetween. After the material layer for forming a specific layer is formed on the entire underlying stacked structure of the display device 10, the material layer formed in an undesired region can be removed by etching. Through this process, separated patterns of different layers can be separately formed in the different emission regions EA1 to EA3. In the display device 10, different light-emitting elements ED1 to ED3 can be separately formed in the emission regions EA1 to EA3 by a deposition and etching process without using a mask process, unnecessary components can be omitted from the display device 10, and the area of the non-display region NDA can be minimized.

[0138] The side shape or cross-sectional profile of the bank structure BNS can be a structure formed due to different etching rates between the different materials respectively providing the first bank layer BN1 and the second bank layer BN2 in an etching process. According to the embodiment, the second bank layer BN2 can include a material having an etching rate slower than that of the first bank layer BN1, and the first bank layer BN1 can be etched much more during the etching process to be recessed with respect to the second bank layer BN2, thereby exposing the lower surface of the second bank layer BN2 at the tip BN2_TP of the second bank layer BN2 and forming an undercut portion at each tip BN2_TP of the second bank layer BN2.

[0139] The second bank layer BN2 may include a metal material different from that of the first bank layer BN1. The metal material of the second bank layer BN2 may be a material that is removed together with the metal material of the first bank layer BN1 by dry etching but is not etched by wet etching or is etched at a much slower etching rate than the metal material of the first bank layer BN1 by wet etching. In an embodiment, the first bank layer BN1 may include aluminum (Al), and the second bank layer BN2 may include titanium (Ti).

[0140] The tip BN2_TP of the second bank layer BN2 may overlap with the common electrodes CE1 to CE3 in a third direction DR3, where the third direction DR3 may be perpendicular to the substrate SUB and / or the plane defined by the first direction DR1 and the second direction DR2 that cross each other. In addition, the tip BN2_TP of the second bank layer BN2 may overlap with the light-emitting layers EL1 to EL3 in the bank openings in the third direction DR3. In addition, the tip BN2_TP of the second bank layer BN2 may overlap with the pixel defining layer PDL in the bank openings in the third direction DR3. The common electrodes CE1 to CE3 may be formed below the lower surface of the tip BN2_TP of the second bank layer BN2. A part of the common electrodes CE1 to CE3 may face the lower surface of the second bank layer BN2 at the tip BN2_TP. The maximum distance from the substrate SUB to each of the common electrodes CE1 to CE3 may be less than the maximum distance from the substrate SUB to the second bank layer BN2. Here, the distance may be defined along the third direction DR3 and is thus considered a vertical distance.

[0141] The display device 10 may include trace patterns TRP2 to TRP3 on the bank structure BNS, which are traces of a deposition process. In the deposition process, a trace pattern TRP1 is also formed on the bank structure BNS (see Figure 15 ). Referring to Figure 5 、 Figure 6 and Figure 15 , the trace patterns TRP1 to TRP3 may include organic patterns ELP1 to ELP3, electrode patterns CEP1 to CEP3, and capping patterns CPP, and may be disposed on the second bank layer BN2 to surround the emission regions EA1 to EA3.

[0142] In an embodiment of a method of providing a display device 10, the trace patterns TRP1 to TRP3 may be traces of a material layer, and the traces of the material layer are formed by the disconnection of the tip BN2_TP of the material layer by the bank structure BNS when they are separated from the light-emitting layers EL1 to EL3, the common electrodes CE1 to CE3, and the capping layer CAP in the emission regions EA1 to EA3 provided in the material layer. The light-emitting layers EL1 to EL3, the common electrodes CE1 to CE3, and the capping layer CAP may be patterns formed in the bank openings, while various material layer traces are provided outside the bank openings. In addition, the organic patterns ELP1 to ELP3 as the emission layer material traces may be separated from the light-emitting layers EL1 to EL3 by the tip BN2_TP of the bank structure BNS, the electrode patterns CEP1 to CEP3 as the electrode material traces may be separated from the common electrodes CE1 to CE3 by the tip BN2_TP of the bank structure BNS, and the capping pattern CPP as the capping material trace may be separated from the capping layer CAP by the tip BN2_TP of the bank structure BNS. The trace patterns TRP1 to TRP3 may be the result of patterning performed in a region around or adjacent to the emission regions EA1 to EA3, or around (or adjacent to) the bank openings.

[0143] According to an embodiment, the plurality of organic patterns ELP1 to ELP3 may include the same material as the light-emitting layers EL1 to EL3 and may be provided on the bank structure BNS. Since the light-emitting layers EL1 to EL3 are formed by a process of depositing respective material layers on the entire surface of the display device 10, portions of the material layers forming the light-emitting layers EL1 to EL3 may be deposited on the bank structure BNS as material traces in addition to the emission regions EA1 to EA3.

[0144] For example, the organic patterns ELP1 to ELP3 may be provided on the bank structure BNS. The organic patterns ELP1 to ELP3 may include a first organic pattern ELP1, a second organic pattern ELP2, and a third organic pattern ELP3 provided on the second bank layer BN2 of the bank structure BNS.

[0145] The first organic pattern ELP1 may include the same material as the first light-emitting layer EL1 of the first light-emitting element ED1. The second organic pattern ELP2 may include the same material as the second light-emitting layer EL2 of the second light-emitting element ED2, and the third organic pattern ELP3 may include the same material as the third light-emitting layer EL3 of the third light-emitting element ED3. Each of the organic patterns ELP1 to ELP3 may be formed in a process of forming the light-emitting layers EL1, EL2, or EL3, which include the same materials as the organic patterns ELP1, ELP2, or ELP3. The organic patterns ELP1 to ELP3 may be respectively disposed adjacent to the emission regions EA1 to EA3 in which the light-emitting layers EL1 to EL3 are disposed. Here, the organic patterns ELP1 to ELP3 and the light-emitting layers EL1 to EL3 may be respectively in the same layer as each other. Because they are in the same layer, these elements may be formed in the same process and / or may include the same materials as each other, these elements may be corresponding parts of the same material layer, these elements may be in the same layer by forming an interface with the same underlying layer or the same overlying layer, and so on, without being limited thereto.

[0146] According to an embodiment, the plurality of electrode patterns CEP1 to CEP3 may include the same materials as the common electrodes CE1 to CE3, and may be disposed on the bank structure BNS. The first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be respectively directly disposed on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3. The arrangement relationship between the electrode patterns CEP1 to CEP3 and the organic patterns ELP1 to ELP3 may be the same as the arrangement relationship between the light-emitting layers EL1 to EL3 of the light-emitting elements ED1 to ED3 and the common electrodes CE1 to CE3.

[0147] The display device 10 may include a capping pattern CPP disposed on the bank structure BNS. The capping pattern CPP may be directly disposed on the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3. The arrangement relationship between the capping pattern CPP and the electrode patterns CEP1 to CEP3 may be the same as the arrangement relationship between the common electrodes CE1 to CE3 of the light-emitting elements ED1 to ED3 and the capping layer CAP.

[0148] The thin film encapsulation layer TFEL may be disposed on the light-emitting elements ED1 to ED3 and the bank structure BNS, and may cover the light-emitting elements ED1 to ED3 and the bank structure BNS. The thin film encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from infiltrating into the light-emitting element layer EML. The thin film encapsulation layer TFEL may include at least one organic layer to protect the light-emitting element layer EML from foreign substances such as dust.

[0149] In an embodiment, the thin film encapsulation layer TFEL may include a lower inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and an upper inorganic encapsulation layer TFE3 stacked in sequence.

[0150] Each of the lower inorganic encapsulation layer TFE1 and the upper inorganic encapsulation layer TFE3 may include at least one inorganic insulating material. The inorganic insulating material may be any one of silicon oxide, silicon nitride, and silicon oxynitride, but is not limited thereto. For example, it may be alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0151] The organic encapsulation layer TFE2 may include a polymer-based material. Examples of the polymer-based material may include acrylic resin, epoxy resin, polyimide, and polyethylene. For example, the organic encapsulation layer TFE2 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The organic encapsulation layer TFE2 may be formed by curing a monomer or applying a polymer.

[0152] The lower inorganic encapsulation layer TFE1 may be provided in a plurality of patterns on the light-emitting elements ED1 to ED3 and the bank structure BNS. The lower inorganic encapsulation layer TFE1 may include a first inorganic layer TL1, a second inorganic layer TL2, and a third inorganic layer TL3 respectively provided corresponding to different emission regions EA1 to EA3. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may include an inorganic insulating material to cover the light-emitting elements ED1 to ED3 respectively. The first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may prevent the light-emitting elements ED1 to ED3 from being damaged by external air.

[0153] Since the lower inorganic encapsulation layer TFE1 (the first inorganic layer TL1 to the third inorganic layer TL3) may be formed by chemical vapor deposition (CVD), the lower inorganic material may be formed along the steps of the layer on which the lower inorganic material is deposited. For example, each of the first inorganic layer TL1, the second inorganic layer TL2, and the third inorganic layer TL3 may form a thin layer even along the surface or profile under the undercut formed by the tip BN2_TP of the bank structure BNS.

[0154] In Figure 5 and Figure 6 , for example, the thickness of the lower inorganic encapsulation layers TL1 to TL3 that seal the outer surfaces of the light-emitting elements ED1 to ED3 is uneven. However, the lower inorganic encapsulation layers TL1 to TL3 may be provided with a uniform thickness along the upper surface, side surface, and lower surface of the second bank layer BN2, the side surface of the first bank layer BN1, and the upper surface of the common electrodes CE1 to CE3. The thickness of the layer may be obtained in a direction orthogonal to the corresponding surface along which the layer is provided.

[0155] The lower inorganic encapsulation layer TFE1 may have a multi-layer structure, but may also have a single-layer structure depending on the area. The lower inorganic encapsulation layer TFE1 may include one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The specific material may be silicon oxide, silicon nitride, and / or silicon oxynitride. Each of the first inorganic layer TL1 to the third inorganic layer TL3 may include a lower insulating layer containing silicon (Si) and nitrogen (N), and an upper insulating layer disposed on the lower insulating layer and containing silicon (Si) and oxygen (O). The lower insulating layer may further include oxygen, but the upper insulating layer may be richer in oxygen (rich in O) than the lower insulating layer. The upper insulating layer may further include nitrogen, but the lower insulating layer may be richer in nitrogen (rich in N) than the upper insulating layer. That is, the oxygen content of the upper insulating layer may be greater than the oxygen content of the lower insulating layer. The nitrogen content of the lower insulating layer may be greater than the nitrogen content of the upper insulating layer. The thickness of the lower insulating layer may be much greater than the thickness of the upper insulating layer.

[0156] Each of the first inorganic layer TL1 to the third inorganic layer TL3 of the lower inorganic encapsulation layer TFE1 may have a wing portion spaced apart from the upper surface of the second bank layer BN2, and a part of another lower inorganic encapsulation layer among the first inorganic layer TL1 to the third inorganic layer TL3 may be disposed on and below the wing portion. Accordingly, the corresponding wing portions of the first inorganic layer TL1 to the third inorganic layer TL3 may support each other in the thickness direction DR3. Accordingly, the step coverage of the first inorganic layer TL1 to the third inorganic layer TL3 may be supplemented by overlapping the wing portions.

[0157] The first inorganic layer TL1 may not overlap with the second emission region EA2 and the third emission region EA3, and may be disposed in the first emission region EA1 and on a portion of the bank structure BNS around or directly adjacent to the first emission region EA1. Similarly, the second inorganic layer TL2 may not overlap with the first emission region EA1 and the third emission region EA3, and may be disposed in the second emission region EA2 and on the bank structure BNS around the second emission region EA2. Similarly, the third inorganic layer TL3 may not overlap with the first emission region EA1 and the second emission region EA2, and may be disposed in the third emission region EA3 and on the bank structure BNS around the third emission region EA3. On the bank structure BNS, at different regions adjacent to the light-emitting region, the first inorganic layer TL1 and the second inorganic layer TL2 may overlap each other, the second inorganic layer TL2 and the third inorganic layer TL3 may overlap each other, and the first inorganic layer TL1 and the third inorganic layer TL3 may overlap each other.

[0158] The first inorganic layer TL1 disposed on the first light-emitting element ED1 may include a main body portion TL1_B, a first wing portion TL1_W1, and a second wing portion TL1_W2. The main body portion TL1_B of the first inorganic layer TL1 may be disposed on the first common electrode CE1 and may

[0159] include a portion surrounded by the bank structure BNS. The first wing portion TL1_W1 of the first inorganic layer TL1 may be the portion of the first inorganic layer TL1 that is farthest from the substrate SUB and / or the main body portion TL1_B. The first wing portion TL1_W1 may be disposed on the second bank layer BN2, but may be spaced apart from the upper surface of the second bank layer BN2. The second wing portion TL1_W2 of the first inorganic layer TL1 may connect the main body portion TL1_B of the first inorganic layer TL1 and the first wing portion TL1_W1 of the first inorganic layer TL1 to each other, but may be spaced apart from the upper surface of the second bank layer BN2. The first wing portion TL1_W1 and the second wing portion TL1_W2 of the first inorganic layer TL1 may be located above the second bank layer BN2 and may have a wing shape protruding from the main body portion TL1_B of the first inorganic layer TL1 in the thickness direction DR3.

[0160] The first wing portion TL1_W1 of the first inorganic layer TL1 may include a first side surface TL1_W1_S1 overlapping with the first light-emitting layer EL1 and a second side surface TL1_W1_S2 opposite to the first side surface TL1_W1_S1. The second wing portion TL1_W2 of the first inorganic layer TL1 may include a first side surface TL1_W2_S1 overlapping with the first light-emitting layer EL1 and a second side surface TL1_W2_S2 opposite to the first side surface TL1_W2_S1. The second side surface TL1_W1_S2 of the first wing portion TL1_W1 of the first inorganic layer TL1 may protrude much more than the second side surface TL1_W2_S2 of the second wing portion TL1_W2 of the first inorganic layer TL1. The first wing portion TL1_W1 of the first inorganic layer TL1 may include a tip TL1_TP1, and an undercut structure may be formed below the tip TL1_TP1.

[0161] The first side surface TL1_W1_S1 of the first wing portion TL1_W1 of the first inorganic layer TL1 and the first side surface TL1_W2_S1 of the second wing portion TL1_W2 of the first inorganic layer TL1 may be aligned to form a flat surface.

[0162] The main part TL1_B of the first inorganic layer TL1 may include a first side surface TL1_B_S1 facing the side surface of the second bank layer BN2. The first side surface TL1_B_S1 of the main part TL1_B of the first inorganic layer TL1 may overlap with the first light-emitting layer EL1 and may be much more recessed than the second side surface TL1_W1_S2 of the first wing part TL1_W1 of the first inorganic layer TL1 and the second side surface TL1_W2_S2 of the second wing part TL1_W2 of the first inorganic layer TL1. The first side surface TL1_B_S1 of the main part TL1_B of the first inorganic layer TL1 may be spaced apart from the side surface of the second bank layer BN2 or may be in contact with the side surface of the second bank layer BN2.

[0163] Void spaces may exist in some regions of the second bank layer BN2. A first void space VD1 surrounded by the second wing part TL1_W2 of the first inorganic layer TL1, the main part TL1_B of the first inorganic layer TL1, and the second inorganic layer TL2 (or the third inorganic layer TL3) may exist. The first void space VD1 may be a space or gap formed by removing the first trace pattern TRP1 occupying the space. The thickness of the first void space VD1 may be defined as a first distance h1 (or a first thickness) between the second bank layer BN2 and the second wing part TL1_W2 of the first inorganic layer TL1. The first distance h1 of the first void space VD1 is equal to a second distance h2 (or a second thickness) between the first pixel electrode AE1 and the main part TL1_B of the first inorganic layer TL1, and the first distance h1 between the second bank layer BN2 and the second wing part TL1_W2 of the first inorganic layer TL1 is equal to the second distance h2 between the first pixel electrode AE1 and the main part TL1_B of the first inorganic layer TL1. That is, the thickness of the first void space VD1 may be the sum of the thicknesses of the first light-emitting layer EL1 and the first common electrode CE1 in the first emission region EA1. When the capping layer CAP is formed, the thickness of the first void space VD1 may be equal to the sum of the above thickness and the thickness of the capping layer CAP.

[0164] The main part TL1_B of the first inorganic layer TL1 may include silicon (Si), oxygen (O), and nitrogen (N). The main part TL1_B of the first inorganic layer TL1 may include a lower insulating layer containing silicon (Si) and nitrogen (N) and an upper insulating layer provided on the lower insulating layer and containing silicon (Si) and oxygen (O). The lower insulating layer may include silicon nitride or silicon oxynitride. The upper insulating layer may include silicon oxide.

[0165] The first wing portion TL1_W1 of the first inorganic layer TL1 may include silicon (Si) and oxygen (O). The nitrogen content of the first wing portion TL1_W1 of the first inorganic layer TL1 may be very small, negligible or zero. The first wing portion TL1_W1 of the first inorganic layer TL1 may include the upper insulating layer described above and may not include the lower insulating layer.

[0166] The second wing portion TL1_W2 of the first inorganic layer TL1 may include silicon (Si) and oxygen (O), and optionally, may further include nitrogen (N).

[0167] The thickness of the first wing portion TL1_W1 of the first inorganic layer TL1 may be less than the thickness of the second wing portion TL1_W2 of the first inorganic layer TL1. The thickness of the protruding tip TL1_TP1 of the first wing portion TL1_W1 of the first inorganic layer TL1 may be much less than the thickness of the second wing portion TL1_W2 of the first inorganic layer TL1.

[0168] The second inorganic layer TL2 disposed on the second light-emitting element ED2 may include a main body portion TL2_B, a first wing portion TL2_W1, a second wing portion TL2_W2, a third wing portion TL2_W3, a first connection portion TL2_C1, a second connection portion TL2_C2, and a third connection portion TL2_C3. The main body portion TL2_B of the second inorganic layer TL2 may be disposed on the second common electrode CE2 and may include a portion surrounded by the bank structure BNS. The first wing portion TL2_W1 of the second inorganic layer TL2 may be the portion of the second inorganic layer TL2 farthest from the substrate SUB and may be disposed on the second bank layer BN2 and the first wing portion TL1_W1 of the first inorganic layer TL1. The first connection portion TL2_C1 of the second inorganic layer TL2 may be disposed between the first wing portion TL1_W1 of the first inorganic layer TL1 and the second bank layer BN2, that is, may be disposed below the tip TL1_TP1 of the first wing portion TL1_W1 of the first inorganic layer TL1. The third wing portion TL2_W3 of the second inorganic layer TL2 may protrude from the first connection portion TL2_C1 of the second inorganic layer TL2 in the thickness direction DR3 of the substrate SUB. The second wing portion TL2_W2 of the second inorganic layer TL2 may connect the third wing portion TL2_W3 and the first wing portion TL2_W1 of the second inorganic layer TL2. The second connection portion TL2_C2 of the second inorganic layer TL2 may be connected to the first connection portion TL2_C1 of the second inorganic layer TL2 and may be disposed on the second side surface TL1_W2_S2 of the second wing portion TL1_W2 of the first inorganic layer TL1. The third connection portion TL2_C3 of the second inorganic layer TL2 may connect the second connection portion TL2_C2 and the main body portion TL2_B of the second inorganic layer TL2 and may be disposed on the second bank layer BN2 and the second trace pattern TRP2.

[0169] The first inorganic layer TL1 and the second inorganic layer TL2 may overlap each other in the thickness direction DR3 of the substrate SUB on the bank structure BNS between the first emission region EA1 and the second emission region EA2. The first wing portion TL1_W1 of the first inorganic layer TL1 and the first wing portion TL2_W1 of the second inorganic layer TL2 may overlap each other. The tip TL1_TP1 of the first inorganic layer TL1 and the tip TL2_TP1 of the second inorganic layer TL2 may overlap each other. The tip TL1_TP1 of the first inorganic layer TL1 may not overlap with the second trace pattern TRP2. The second trace pattern TRP2 is provided on the bank structure BNS between the first emission region EA1 and the second emission region EA2, but is not provided on the bank structure BNS between the second emission region EA2 and the third emission region EA3. A second void space VD2 from which the second trace pattern TRP2 is removed may exist on the bank structure BNS between the second emission region EA2 and the third emission region EA3.

[0170] The first wing portion TL2_W1 and the second wing portion TL2_W2 of the second inorganic layer TL2 may be spaced apart from the upper surface of the first wing portion TL1_W1 of the first inorganic layer TL1. The space between the first wing portion TL2_W1 of the second inorganic layer TL2 and the first wing portion TL1_W1 of the first inorganic layer TL1 may be filled with the organic encapsulation layer TFE2.

[0171] The first wing portion TL2_W1 of the second inorganic layer TL2 may include a first side surface TL2_W1_S1 adjacent to the second light-emitting layer EL2 and a second side surface TL2_W1_S2 opposite to the first side surface TL2_W1_S1. The second wing portion TL2_W2 of the second inorganic layer TL2 may include a first side surface TL2_W2_S1 adjacent to the second light-emitting layer EL2 and a second side surface TL2_W2_S2 opposite to the first side surface TL2_W2_S1. The third wing portion TL2_W3 of the second inorganic layer TL2 may include a first side surface TL2_W3_S1 adjacent to the second light-emitting layer EL2 and a second side surface TL2_W3_S2 opposite to the first side surface TL2_W3_S1.

[0172] The second side surface TL2_W1_S2 of the first wing portion TL2_W1 of the second inorganic layer TL2 may protrude much more than the second side surface TL2_W2_S2 of the second wing portion TL2_W2 of the second inorganic layer TL2. The first wing portion TL2_W1 of the second inorganic layer TL2 may include a tip TL2_TP1, and an undercut structure may be formed below the tip TL2_TP1. The second side surface TL2_W1_S2 of the first wing portion TL2_W1 of the second inorganic layer TL2 may protrude much more than the second side surface TL2_W3_S2 of the third wing portion TL2_W3 of the second inorganic layer TL2.

[0173] In Figure 6 it, the second side surface TL2_W2_S2 of the second wing portion TL2_W2 of the second inorganic layer TL2 protrudes much more than the second side surface TL2_W3_S2 of the third wing portion TL2_W3 of the second inorganic layer TL2. However, the present disclosure is not limited thereto. The second side surface TL2_W2_S2 of the second wing portion TL2_W2 of the second inorganic layer TL2 may also be aligned with the second side surface TL2_W3_S2 of the third wing portion TL2_W3 of the second inorganic layer TL2, or may be recessed much more than the second side surface TL2_W3_S2 of the third wing portion TL2_W3 of the second inorganic layer TL2.

[0174] The first side surface TL2_W1_S1 of the first wing portion TL2_W1 of the second inorganic layer TL2, the first side surface TL2_W2_S1 of the second wing portion TL2_W2 of the second inorganic layer TL2, and the first side surface TL2_W3_S1 of the third wing portion TL2_W3 of the second inorganic layer TL2 may be aligned to form a flat surface. That is, the respective side surfaces may be coplanar with each other to form a flat surface.

[0175] The first connection portion TL2_C1 of the second inorganic layer TL2 may be adjacent to the first wing portion TL1_W1 of the first inorganic layer TL1. The first connection portion TL2_C1 of the second inorganic layer TL2 may contact the lower surface of the first wing portion TL1_W1 of the first inorganic layer TL1 to support the tip TL1_TP1 of the first inorganic layer TL1 and prevent air from penetrating from the outside.

[0176] The second connection portion TL2_C2 of the second inorganic layer TL2 may be adjacent to the second wing portion TL1_W2 of the first inorganic layer TL1. The second connection portion TL2_C2 of the second inorganic layer TL2 may contact the second side surface TL1_W2_S2 of the second wing portion TL1_W2 of the first inorganic layer TL1 to block the moisture penetration path.

[0177] The third connection portion TL2_C3 of the second inorganic layer TL2 may be disposed on the second bank layer BN2 and the second trace pattern TRP2. A part of the lower surface of the third connection portion TL2_C3 of the second inorganic layer TL2 may contact the second bank layer BN2, and another part may contact the second trace pattern TRP2. That is, a part of the upper surface of the second bank layer BN2 may contact the third connection portion TL2_C3 of the second inorganic layer TL2, and another part of the upper surface of the second bank layer BN2 may contact the second organic pattern ELP2.

[0178] There may be minute void spaces between the first connection portion TL2_C1, the second connection portion TL2_C2, and the third connection portion TL2_C3 of the second inorganic layer TL2. That is, the first connection portion TL2_C1, the second connection portion TL2_C2, and the third connection portion TL2_C3 may together define a void. A wider part of the void may be defined at the second connection portion TL2_C2, and the width (or volume) of the void may decrease in a direction away from the second connection portion TL2_C2. The first connection portion TL2_C1 and the third connection portion TL2_C3 of the second inorganic layer TL2 may be joined to each other at positions spaced apart from the second connection portion TL2_C2, thereby ensuring the structural stability of the second inorganic layer TL2.

[0179] The main body portion TL2_B of the second inorganic layer TL2 and the third connection portion TL2_C3 of the second inorganic layer TL2 may include silicon (Si), oxygen (O), and nitrogen (N). The main body portion TL2_B of the second inorganic layer TL2 and the third connection portion TL2_C3 of the second inorganic layer TL2 may include a lower insulating layer containing silicon (Si) and nitrogen (N) and an upper insulating layer disposed on the lower insulating layer and containing silicon (Si) and oxygen (O). The lower insulating layer may include silicon nitride or silicon oxynitride. The upper insulating layer may include silicon oxide.

[0180] The first wing portion TL2_W1 of the second inorganic layer TL2 may include silicon (Si) and oxygen (O). The nitrogen content of the first wing portion TL2_W1 of the second inorganic layer TL2 may be very small or zero. The first wing portion TL2_W1 of the second inorganic layer TL2 may include the upper insulating layer described above and may not include the lower insulating layer.

[0181] The second wing portion TL2_W2 and the third wing portion TL2_W3 of the second inorganic layer TL2 may include silicon (Si) and oxygen (O), and optionally may also include nitrogen (N).

[0182] The first connection portion TL2_C1 and the second connection portion TL2_C2 of the second inorganic layer TL2 may include silicon (Si) and nitrogen (N). The oxygen content of the first connection portion TL2_C1 and the second connection portion TL2_C2 of the second inorganic layer TL2 may be very small or zero. The first connection portion TL2_C1 and the second connection portion TL2_C2 of the second inorganic layer TL2 may include the lower insulating layer described above and may not include the upper insulating layer.

[0183] The thickness of the first wing portion TL2_W1 of the second inorganic layer TL2 may be less than the thickness of the second wing portion TL2_W2 of the second inorganic layer TL2. The thickness of the protruding tip TL2_TP1 of the first wing portion TL2_W1 of the second inorganic layer TL2 may be much less than the thickness of the second wing portion TL2_W2 of the second inorganic layer TL2.

[0184] The third distance h3 (or the third thickness) of the third wing portion TL2_W3 of the second inorganic layer TL2 may be equal to the fifth distance h5 (or the fifth thickness) between the second pixel electrode AE2 and the main body portion TL2_B of the second inorganic layer TL2. The fifth distance h5 between the second pixel electrode AE2 and the main body portion TL2_B of the second inorganic layer TL2 may be the sum of the thicknesses of the second light-emitting layer EL2 and the second common electrode CE2 in the second emission region EA2. When forming the capping layer CAP, the fifth distance h5 may be the sum of the above thicknesses and the thickness of the capping layer CAP. The fourth distance h4 (or the fourth thickness) between the first wing portion TL1_W1 of the first inorganic layer TL1 and the first wing portion TL2_W1 of the second inorganic layer TL2 may be greater than the fifth distance h5 between the second pixel electrode AE2 and the main body portion TL2_B of the second inorganic layer TL2.

[0185] Reference Figure 5 , the tip structure of the second inorganic layer TL2 may also be formed on the second bank layer BN2 between the second emission region EA2 and the third emission region EA3 as in Figure 6 , and the third inorganic layer TL3 may be disposed above and below the tip structure. The tip structure of the first inorganic layer TL1 may be formed on the second bank layer BN2 between the third emission region EA3 and the first emission region EA1, and the third inorganic layer TL3 may be disposed above and below the tip structure.

[0186] The organic encapsulation layer TFE2 is disposed on the lower inorganic encapsulation layers TL1 to TL3. A portion of the organic encapsulation layer TFE2 may be disposed between the first wing portions TL1_W1, TL2_W1, and TL3_W1 of the first inorganic layer TL1 to the third inorganic layer TL3. The organic encapsulation layer TFE2 may not directly contact the second bank layer BN2 between the emission regions EA1 to EA3.

[0187] The upper inorganic encapsulation layer TFE3 may be disposed on the organic encapsulation layer TFE2. The upper inorganic encapsulation layer TFE3 may include alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0188] The pattern within the light blocking layer BM may be disposed on the thin film encapsulation layer TFEL. The light blocking layer BM may include (or define) a plurality of holes OPT1 to OPT3 (e.g., light blocking layer openings) that are disposed to overlap with the emission regions EA1 to EA3, respectively. For example, the first hole OPT1 may overlap with the first emission region EA1. The second hole OPT2 may overlap with the second emission region EA2, and the third hole OPT3 may overlap with the third emission region EA3. The area or size of the holes OPT1 to OPT3 may be greater than the area or size of the emission regions EA1 to EA3, respectively. Since the holes OPT1 to OPT3 of the light blocking layer BM are formed to be larger than the emission regions EA1 to EA3, the light emitted from the emission regions EA1 to EA3 can be seen from the outside of the display device 10, such as by a user, not only from the front but also from the side of the display device 10.

[0189] The light blocking layer BM may include a light absorbing material. For example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black. However, the present disclosure is not limited thereto. The light blocking layer BM may prevent color mixing by preventing visible light from intruding between the first emission region EA1, the second emission region EA2, and the third emission region EA3, thereby improving the color gamut of the display device 10.

[0190] The display device 10 may include a plurality of color filters CF1 to CF3 disposed in the emission regions EA1 to EA3. The color filters CF1 to CF3 may be disposed to correspond to the emission regions EA1 to EA3, respectively. For example, the color filters CF1 to CF3 may be disposed on the light blocking layer BM including the holes OPT1 to OPT3 corresponding to the emission regions EA1 to EA3. The holes OPT1 to OPT3 of the light blocking layer BM may be formed to overlap with the emission regions EA1 to EA3 or the openings of the bank structure BNS, and may form a light output region through which the light emitted from the emission regions EA1 to EA3 is output to the outside of the display device 10. The color filters CF1 to CF3 may each have an area larger than the holes OPT1 to OPT3 of the light blocking layer BM. The color filters CF1 to CF3 may each completely cover the light output region formed by the holes OPT1 to OPT3.

[0191] The color filters CF1 to CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, which are respectively arranged to correspond to different emission regions EA1 to EA3. Each of the color filters CF1 to CF3 may include a colorant (such as a dye or a pigment) that absorbs light in a wavelength band other than the light in a specific wavelength band, and may be arranged to correspond to the color of the light emitted from one of the emission regions EA1 to EA3. For example, the first color filter CF1 may be a red color filter that overlaps with the first emission region EA1 and transmits only the first light of red. The second color filter CF2 may be a green color filter that overlaps with the second emission region EA2 and transmits only the second light of green, and the third color filter CF3 may be a blue color filter that overlaps with the third emission region EA3 and transmits only the third light of blue.

[0192] Each of the color filters CF1 to CF3 may be spaced apart from other adjacent color filters CF1 to CF3 on the light blocking layer BM. The color filters CF1 to CF3 may cover the holes OPT1 to OPT3 of the light blocking layer BM and may respectively have an area larger than that of the holes OPT1 to OPT3. However, each of the color filters CF1 to CF3 may have a region that allows it to be spaced apart from other color filters CF1 to CF3 on the light blocking layer BM. However, the present disclosure is not limited thereto. Each of the color filters CF1 to CF3 may also partially overlap with an adjacent color filter CF1 to CF3. In this case, the portions of different color filters CF1 to CF3 that do not overlap with the emission regions EA1 to EA3 may overlap with each other on the light blocking layer BM, which will be described later. Since the color filters CF1 to CF3 overlap with each other in the display device 10, the intensity of the reflected light caused by external light can be reduced. In addition, by adjusting the arrangement, shape, and area of the color filters CF1 to CF3 in the plan view, the color of the reflected light caused by external light can be controlled.

[0193] The outer coating OC may be provided on the color filters CF1 to CF3 to flatten the upper ends of the color filters CF1 to CF3. The outer coating OC may be a colorless light-transmitting layer that does not have a color in the visible light band. For example, the outer coating OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0194] Now, the process of manufacturing the display device 10 according to an embodiment will be described with reference to other drawings.

[0195] Figure 7 is a flowchart showing the process of manufacturing (or providing) the display device 10 according to an embodiment. Figures 8 to 20 is a detailed cross-sectional view sequentially showing the processes in the method of providing the display device 10 according to an embodiment.

[0196] Figures 8 to 20Schematically shown is a process of forming a bank structure BNS and a light-emitting element ED in a light-emitting element layer EML of a display device 10 and forming a thin film encapsulation layer TFEL on the light-emitting element layer EML. In the following description of the process of manufacturing the display device 10, the formation process of each layer will not be described, and the formation order of each layer will be described.

[0197] Reference Figure 8 , a plurality of pixel electrodes AE1 to AE3 spaced apart from each other, a sacrificial layer SFL corresponding to the preliminary sacrificial layers of the pixel electrodes AE1 to AE3, a pixel defining material layer PDLL as a preliminary pixel defining layer, and a plurality of bank material layers BNL1 and BNL2 as preliminary bank layers are formed (or provided) on the entire second passivation layer PAS2 of the encapsulation layer.

[0198] Although not shown in the drawings, a thin film transistor layer TFTL as a circuit layer (or pixel circuit layer) can be provided on the substrate SUB. The structure of the thin film transistor layer TFTL is the same as that described above with reference to Figure 5 and thus its detailed description will be omitted.

[0199] Reference Figure 9 , a mask pattern (or photoresist) PR is formed on the second bank material layer BNL2 corresponding to the regions between adjacent pixel electrodes AE1 to AE3, and a first etching process is performed using the mask pattern (or photoresist) PR as a mask to partially etch the first bank material layer BNL1 and the second bank material layer BNL2. Holes can be formed in the preliminary bank layer by the first etching process. The mask patterns (or photoresists) PR can be spaced apart from each other on the second bank material layer BNL2 (or along the second bank material layer BNL2), and can be arranged to expose the regions of the preliminary pixel defining layer that overlap with the pixel electrodes AE1 to AE3 respectively.

[0200] In an embodiment, the first etching process can be performed as an anisotropic dry etching. Holes or openings can be formed in the regions overlapping with the pixel electrodes AE1 to AE3. These holes can form openings between the solid portions (material portions) of the bank structure BNS of the bank structure BNS.

[0201] Reference Figure 10, an undercut structure of the first bank layer BN1 can be formed through a second etching process. In the second etching process, the first bank material layer BNL1 can be etched faster than the second bank material layer BNL2, and the side surfaces of the upper portions defining the bank openings corresponding to the respective pixel electrodes AE1 to AE3 of the second bank layer BN2 can be formed to protrude much more than the side surfaces of the lower portions defining the bank openings of the first bank layer BN1. The side surfaces of the second bank layer BN2 can protrude much more than the side surfaces of the first bank layer BN1 in the direction toward the bank holes to form the tips BN2_TP of the bank structure BNS. Through the lower surfaces of the second bank layer BN2 exposed to the bank holes and the corresponding side surfaces of the first bank layer BN1, undercuts can be formed below each tip BN2_TP.

[0202] In an embodiment, the second etching process can be an isotropic wet etching. The second etching process can use an alkali-based etchant. A completed form of the bank structure BNS having the first bank layer BN1 and the second bank layer BN2 can be obtained through the second etching process.

[0203] As Figure 11 shown, a part of the pixel defining material layer PDLL can be removed through a third etching process in the regions corresponding to the respective pixel electrodes AE1 to AE3. The third etching process can include a dry etching operation for removing a part of the pixel defining material layer PDLL. Here, in the dry etching operation, the sacrificial layer SFL between the preliminary pixel defining layer and the respective pixel electrodes AE1 to AE3 can protect the pixel electrodes AE1 to AE3 from the influence of the plasma. Here, at the bank openings, the exposed regions of the preliminary sacrificial layer are exposed to the outside of the preliminary pixel defining layer.

[0204] As Figure 12 shown, a fourth etching process for partially removing the exposed portions of the sacrificial layer SFL can be performed to form a residual pattern RP. The fourth etching process can include a wet etching operation and can remove the portions of the sacrificial layer SFL exposed to the bank holes and the portions of the sacrificial layer SFL respectively provided between the extended portions of the pixel defining layer PDL and the pixel electrodes AE1 to AE3. However, in the region closest to the innermost wall of the pixel defining layer PDL, the sacrificial layer SFL may not be completely removed. The remaining portions of the sacrificial layer SFL can be retained to respectively provide the residual pattern RP between the extended portions of the pixel defining layer PDL and the pixel electrodes AE1 to AE3. The pixel electrodes AE1 to AE3 can be exposed to the bank openings through the fourth etching process. Here, the extended portions of the pixel defining layer PDL and the residual pattern RP can form a stepped structure at the upper portions of the pixel openings corresponding to the light emitting regions.

[0205] As Figure 13As shown, the mask pattern (or photoresist) PR is removed. Here, at the opening of the bank portion, the exposed areas of the respective pixel electrodes AE1 to AE3 are exposed to the outside of the pixel defining layer PDL and the residual pattern RP.

[0206] As Figure 14 shown, within the opening of the bank portion of the first emission area EA1, a first light-emitting layer EL1, a first common electrode CE1, and a capping layer CAP are deposited on the first pixel electrode AE1 in a first pattern to form a first light-emitting element ED1. Here, since the corresponding preliminary material layers for forming the first light-emitting layer EL1, the first common electrode CE1, and the capping layer CAP are formed on the entire surface of the substrate SUB, the first light-emitting material layer ELPL1, the first electrode material layer CEPL1, and the capping material layer CPPL can also be formed on the second bank layer BN2 in a second pattern of the corresponding preliminary material layers.

[0207] When providing the preliminary light-emitting layer, the first pattern for the first light-emitting layer EL1 and the second pattern for the first light-emitting material layer ELPL1 can be separated (or disconnected) from each other by the tip BN2_TP of the second bank layer BN2. Similarly, when providing the preliminary electrode layer, the first pattern for the first common electrode CE1 and the second pattern for the first electrode material layer CEPL1 can be separated from each other by the tip BN2_TP of the second bank layer BN2, and when providing the preliminary capping layer, the first pattern for the capping layer CAP and the second pattern for the capping material layer CPPL can be separated from each other by the tip BN2_TP of the second bank layer BN2. The first light-emitting material layer ELPL1 can be formed on the second bank layer BN2 while the first light-emitting layer EL1 is formed on the first pixel electrode AE1. The first electrode material layer CEPL1 can be formed on the first light-emitting material layer ELPL1 while the first common electrode CE1 is formed on the first light-emitting layer EL1.

[0208] The first light-emitting layer EL1 and the first common electrode CE1 can be formed by a deposition process. In the opening of the bank portion, the material may not be deposited smoothly due to the tip BN2_TP of the second bank layer BN2. However, since the materials of the first light-emitting layer EL1 and the first common electrode CE1 are deposited in a direction inclined with respect to the upper surface of the substrate SUB rather than in a direction perpendicular to the upper surface of the substrate SUB, they can even be deposited in the area covered by the tip BN2_TP of the second bank layer BN2. That is, the preliminary material layers of the first light-emitting layer EL1 and the first common electrode CE1 can be deposited on the side surface below the tip BN2_TP of the second bank layer BN2.

[0209] The deposition process for forming the common electrodes CE1 to CE3 can be performed at an angle relatively closer to the horizontal direction than the deposition process for forming the light-emitting layers EL1 to EL3. Accordingly, the common electrodes CE1 to CE3 can contact the side surfaces of the first bank layer BN1 over an area larger than the area covered by the light-emitting layers EL1 to EL3, such that the corresponding common electrodes CE1 to CE3 extend further upward on the side surfaces of the first bank layer BN1. Alternatively, the common electrodes CE1 to CE3 can be deposited on the side surfaces of the first bank layer BN1 to a position higher than the light-emitting layers EL1 to EL3. The different common electrodes CE1 to CE3 can be electrically connected to each other by contacting the first bank layer BN1 having high conductivity.

[0210] Reference Figure 14 , a first light-emitting material layer ELPL1 (which is a preliminary form of the first organic pattern ELP1), a first electrode material layer CEPL1 (which is a preliminary form of the first electrode pattern CEP1), and a capping material layer CPPL (which is a preliminary form of the capping pattern CPP) can be deposited on the second bank layer BN2, adjacent to and surrounding the bank openings corresponding to the emission regions EA1 to EA3, respectively. Some or all of the layers within the first trace pattern TRP1 can be removed in a subsequent process.

[0211] A first inorganic material layer TLL1, which is formed as a previous inorganic layer, covers the first light-emitting element ED1 and the capping layer CAP. The first inorganic material layer TLL1 can be formed to completely cover the outer surfaces of the first light-emitting element ED1, the bank layers BN1 and BN2, the capping layer CAP, the first light-emitting material layer ELPL1, the first electrode material layer CEPL1, and the capping material layer CPPL, without any breaks or disconnections. Specifically, the first inorganic material layer TLL1 is formed on the upper surface of the first common electrode CE1, the upper surface of the capping layer CAP, the side surfaces of the first bank layer BN1, the lower and upper surfaces of the second bank layer BN2, and the upper surfaces of the first electrode material layer CEPL1 and the capping material layer CPPL.

[0212] Reference Figure 15, a fifth etching process for partially removing a portion of the first inorganic material layer TLL1 is performed to expose a portion of the capping material layer CPPL to the outside of the preliminary inorganic layer. That is, the first trace pattern TRP1 is exposed to the outside of the etched inorganic material layer. In an embodiment, the fifth etching process may include isotropic dry etching. A mask pattern PR may be formed on the first inorganic material layer TLL1 at a position overlapping with the first pixel electrode AE1. The first inorganic material layer TLL1 that is not covered by the mask pattern PR and a portion of the first inorganic material layer TLL1 covered by the mask pattern PR may be removed. Here, all of the first inorganic material layer TLL1 may be removed except for a portion corresponding to the bank opening overlapping with the mask pattern PR and a portion adjacent to the bank opening. Removing the portion of the first inorganic material layer TLL1 exposes the first trace pattern TRP1 to the outside of the first inorganic material layer TLL1.

[0213] The silicon nitride or silicon oxynitride of the first inorganic material layer TLL1 that is covered by the mask pattern PR and surrounds the bank opening may be removed to form a protruding side surface of the first inorganic material layer TLL1. That is, a lower thickness portion of the first inorganic material layer TLL1 may be selectively removed. The first wing portion TL1_W1 and the second wing portion TL1_W2 of the first inorganic layer TL1 may be obtained by the fifth etching process. The first inorganic material layer TLL1 is removed from the region overlapping with the second emission region EA2 and the third emission region EA3 and the corresponding regions surrounding these light-emitting regions.

[0214] Next, referring to Figure 16 , a sixth etching process for removing the first light-emitting material layer ELPL1, the first electrode material layer CEPL1, and the capping material layer CPPL is performed to expose the second bank layer BN2, the second pixel electrode AE2, and the third pixel electrode AE3 to the outside of the first inorganic material layer TLL1. In an embodiment, the sixth etching process may be an isotropic wet etching operation. Not only the first electrode pattern CEP1, the first organic pattern ELP1, and the capping pattern CPP of the first trace pattern TRP1 provided on the second bank layer BN2 may be removed, but also the first light-emitting material layer ELPL1, the first electrode material layer CEPL1, and the capping material layer CPPL in the second emission region EA2 and the third emission region EA3 that are not covered by the first inorganic material layer TLL1 may be removed. Thus, at the first emission region EA1, the first electrode pattern CEP1, the first organic pattern ELP1, and the capping pattern CPP of the first trace pattern TRP1 provided between the second wing portion TL1_W2 of the first inorganic layer TL1 and the second bank layer BN2 may also be removed. All of the first trace pattern TRP1 may be completely removed, and no portion of the first trace pattern TRP1 may be retained in the final form of the display device 10. Returning toFigure 5 and Figure 6 , for example, along the pixel circuit layer, any part of the previously formed first trace pattern TRP1 is not retained.

[0215] Removing the portions of the first electrode pattern CEP1, the first organic pattern ELP1, and the capping pattern CPP of the first trace pattern TRP1 that are disposed between the second wing portion TL1_W2 of the first inorganic layer TL1 and the second bank layer BN2 provides an undercut structure of the first inorganic layer TL1 at the first emission region EA1. The undercut structure may define a first void space VD1. The emission region structure including the patterns of the first inorganic layer TL1 to the first pixel electrode AE1 at the first emission region EA1 may be a first emission region structure (or a previous emission region structure).

[0216] As Figure 17 shown, a second light-emitting layer EL2, a second common electrode CE2, and a capping layer CAP are deposited on the second pixel electrode AE2 to form a second light-emitting element ED2. Then, a second inorganic material layer TLL2 (which is a subsequent inorganic layer) is formed to cover the second light-emitting element ED2 and the capping layer CAP. In this process, a material layer is deposited on the entire surface of the substrate SUB (which includes the previous emission region structure) as shown in Figure 14 shown. However, these materials are deformed or broken into upper and lower layers by the tip TL1_TP1 of the first inorganic layer TL1 and the tip BN2_TP of the second bank layer BN2. A second light-emitting material layer ELPL2, a second electrode material layer CEPL2, and a capping material layer CPPL may be disposed on the second bank layer BN2 and the first wing portion TL1_W1 of the first inorganic layer TL1.

[0217] The second inorganic material layer TLL2 is formed to cover the second light-emitting element ED2 and the capping layer CAP. The second inorganic material layer TLL2 may also be formed on the lower surface of the tip TL1_TP1 of the first inorganic layer TL1 and may be formed to completely cover the second bank layer BN2, the capping layer CAP, the capping material layer CPPL, and the upper surface and side surfaces of the first inorganic layer TL1 without any broken parts. However, the space between the second wing portion TL1_W2 of the first inorganic layer TL1 and the upper surface of the second bank layer BN2 may not be completely filled with the second inorganic material layer TLL2. Here, the subsequent inorganic layer may be bent or folded onto itself at the first void space VD1 to cover or block the entrance to the first void space VD1.

[0218] As Figure 18 shown, the second inorganic material layer TLL2 may be partially removed to form a second inorganic layer TL2 that overlaps with the second emission region EA2 and the edge around the second emission region EA2. This process may be similar to the process for removing Figure 15by performing a dry etching operation on the first inorganic material layer TLL1 in

[0219] Next, as Figure 19 shown, the second electrode material layer CEPL2, the second light-emitting material layer ELPL2, and the capping material layer CPPL can be removed except for the region between the previous emission region structure (the first inorganic layer TL1 to the first pixel electrode AE1) and the current emission region structure (the second inorganic layer TL2 to the second pixel electrode AE2). This process can be similar to Figure 16 the process of

[0220] but without removing the portion of the second trace pattern TRP2 that is disposed between the first emission region EA1 and the second emission region EA2 and surrounded by the second inorganic layer TL2. Removing the portion of the second light-emitting material layer ELPL2, the second electrode material layer CEPL2, and the capping material layer CPPL of the second trace pattern TRP2 in a preliminary form that is between the wing portion on the right side of the second inorganic layer TL2 and the second bank layer BN2 provides an undercut structure of the second inorganic layer TL2 at the right side of the second emission region EA2. The undercut structure can define a second void space VD2. Here, the second inorganic layer TL2 as another subsequent inorganic layer can be bent or folded onto itself at the second void space VD2 to cover or block the entrance to the second void space VD2. The emission region structure including the second inorganic layer TL2 to the second pixel electrode AE2 at the second emission region EA2 can be the second emission region structure (or subsequent emission region structure).

[0221] To form the third emission region structure, a process similar to Figures 17 to 19 the process of Figure 20 can be performed to form a third light-emitting element ED3 and a third inorganic layer TL3 in the third emission region EA3, as

[0222] shown. Here, the third electrode material layer, the third light-emitting material layer, and the capping material layer CPPL of the third trace pattern TRP3 can be removed except for the regions between the second emission region structure (the second inorganic layer TL2 to the second pixel electrode AE2) and the current emission region structure (the third inorganic layer TL3 to the third pixel electrode AE3) and between the previous emission region structure (the first inorganic layer TL1 to the first pixel electrode AE1) and the current emission region structure (the third inorganic layer TL3 to the third pixel electrode AE3). That is, a portion of the third trace pattern TRP3 can be retained at the opposite side of the third emission region EA3, while a portion of the second trace pattern TRP2 is only retained at one side of the second emission region EA2, and a portion of the first trace pattern TRP1 is not retained at the side of the first emission region EA1.

[0222] Forming Figure 20 on the basis of the stacked structure inFigure 5 and Figure 6 , although not shown in the drawings, an organic encapsulation layer TFE2, an upper inorganic encapsulation layer TFE3, a light blocking layer BM, a color filter layer CFL, and an outer coating OC of a thin film encapsulation layer TFEL are formed on the light emitting elements ED1 to ED3 and the bank structure BNS of the underlying stacked structure to generate the display device 10. The structures of the thin film encapsulation layer TFEL, the light blocking layer BM, the color filter layer CFL, and the outer coating OC are the same as those described above, and thus their detailed descriptions will be omitted.

[0223] In the display device and the method of providing the same according to the embodiment, the previously formed lower inorganic encapsulation layer may have wing portions on the second bank layer, and the subsequently formed adjacent lower inorganic encapsulation layer may cover the top and bottom of the previously formed wing portions. Since the sealing between the lower inorganic encapsulation layer and the light emitting element at the previously formed and subsequently formed wing portions of the lower inorganic encapsulation layer is excellent, the reliability of the display device can be improved.

[0224] Reference Figure 5 and Figure 6, for example, the display device 10 includes: a pixel defining layer PDL on a substrate SUB, and first and second pixel openings (e.g., at a first emission region EA1 and a second emission region EA2) that respectively expose a first pixel electrode AE1 and a second pixel electrode AE2 to the outside of the pixel defining layer PDL; a first light emitting layer EL1 and a first common electrode CE1 in the first pixel opening on the first pixel electrode AE1; a second light emitting layer EL2 and a second common electrode CE2 in the second pixel opening on the second pixel electrode AE2; a bank (e.g., a bank structure BNS) on the pixel defining layer PDL, the bank including a first bank layer BN1 and a second bank layer BN2 on the first bank layer BN1, the first bank layer BN1 including side surfaces that respectively define lower bank openings corresponding to the first and second pixel openings (e.g., a volume portion coplanar with the first bank layer BN1 covering the first emission region EA1 and the second emission region EA2), the second bank layer BN2 including side surfaces that respectively define upper bank openings corresponding to the lower bank openings (e.g., a volume portion coplanar with the second bank layer BN2 covering the first emission region EA1 and the second emission region EA2), the side surface of the second bank layer BN2 protruding further than the side surface of the first bank layer BN1 to define a tip (e.g., tip BN2_TP) of the second bank layer BN2, and the tip including an upper surface of the second bank layer BN2; a lower inorganic encapsulation layer TFE1 of an encapsulation layer on the bank, the lower inorganic encapsulation layer TFE1 including a first inorganic pattern (or the first inorganic layer described above) TL1 and a second inorganic pattern (or the second inorganic layer described above) TL2, the first inorganic pattern TL1 including a main body portion TL1_B on the first common electrode CE1 and a first wing portion TL1_W1 overlapping and spaced apart from the upper surface of the second bank layer BN2, the second inorganic pattern TL2 including a main body portion TL2_B on the second common electrode CE2, a first wing portion TL2_W1 overlapping the first wing portion TL1_W1 of the first inorganic pattern TL1, and a first connection portion TL2_C1 connecting the main body portion TL2_B and the first wing portion TL2_W1 of the second inorganic pattern TL2 and between the first wing portion TL1_W1 of the first inorganic pattern TL1 and the second bank layer BN2.

[0225] The first inorganic pattern TL1 may further include a second wing portion TL1_W2 that connects the main body portion TL1_B of the first inorganic pattern TL1 and the first wing portion TL1_W1 of the first inorganic pattern TL1 to each other. The second wing portion TL1_W2 is spaced apart from the upper surface of the second bank layer BN2, and the first wing portion TL1_W1 of the first inorganic pattern TL1 further protrudes from the second wing portion TL1_W2 of the first inorganic pattern TL1 in the direction toward the second inorganic pattern TL2 to overlap with the first connection portion TL2_C1 of the second inorganic pattern TL2.

[0226] Along the thickness direction DR3 of the substrate SUB, the second inorganic pattern TL2 may further sequentially include a second wing portion TL2_W2 and a third wing portion TL2_W3 from the first wing portion TL2_W1 to the first connection portion TL2_C1 of the second inorganic pattern TL2. The second wing portion TL2_W2 of the second inorganic pattern TL2 protrudes further in the direction toward the first inorganic pattern TL1 than the third wing portion TL2_W3 to overlap with the first wing portion TL1_W1 of the first inorganic pattern TL1, and the first wing portion TL2_W1 of the second inorganic pattern TL2 protrudes further in the direction toward the first inorganic pattern TL1 than the second wing portion TL2_W2 of the second inorganic pattern TL2 to overlap with the first wing portion TL1_W1 of the first inorganic pattern TL1.

[0227] A first void space VD1 is defined between the second wing portion TL1_W2 of the first inorganic pattern TL1 and the upper surface of the second bank layer BN2 spaced apart therefrom, and the first connection portion TL2_C1 of the second inorganic pattern TL2 between the first wing portion TL1_W1 of the first inorganic pattern TL1 and the second bank layer BN2 covers the first void space VD1.

[0228] The second inorganic pattern TL2 may further include a second connection portion TL2_C2 coplanar with the second wing portion TL1_W2 of the first inorganic pattern TL1, and a third connection portion TL2_C3 that connects the second connection portion TL2_C2 of the second inorganic pattern TL2 and the main body portion TL2_B of the second inorganic pattern TL2 to each other.

[0229] The light-emitting layer may include a second light-emitting layer EL2 and a second organic pattern ELP2. The second organic pattern ELP2 is on the second bank layer BN2 and along the substrate SUB between the first emission region EA1 and the second emission region EA2. A part of the second bank layer BN2 is between the first emission region EA1 and the second emission region EA2, and the part contacts both the third connection portion TL2_C3 of the second inorganic pattern TL2 and the second organic pattern ELP2 of the light-emitting layer.

[0230] At a position between the first pixel opening and the second pixel opening, a first connection portion TL2_C1 of the second inorganic pattern TL2 contacts a lower surface of a first wing portion TL1_W1 of the first inorganic pattern TL1, and a second connection portion TL2_C2 of the second inorganic pattern TL2 contacts an outer surface of a second wing portion TL1_W2 of the first inorganic pattern TL1.

[0231] The organic encapsulation layer TFE2 of the encapsulation layer can be on the lower encapsulation inorganic layer TFE1. A first wing portion TL2_W1 of the second inorganic pattern TL2 is spaced apart from a first wing portion TL1_W1 of the first inorganic pattern TL1 along the thickness direction DR3 of the substrate SUB, and the organic encapsulation layer TFE2 extends between the first wing portion TL1_W1 of the first inorganic pattern TL1 and the first wing portion TL2_W1 of the second inorganic pattern TL2.

[0232] A method includes: providing pixel electrodes AE1 to AE3 of a light-emitting element ED spaced apart from each other on a substrate SUB, a sacrificial layer SFL on each of the pixel electrodes AE1 to AE3, and a pixel definition material layer PDLL in each of the sacrificial layers SFL ( Figure 8 ); providing a first bank material layer BNL1 and a second bank material layer BNL2 on the pixel definition material layer PDLL ( Figure 8 ); exposing the pixel definition material layer PDLL to the outside of the first bank material layer BNL1 and the second bank material layer BNL2 by etching the first bank material layer BNL1 and the second bank material layer BNL2 in regions respectively overlapping the pixel electrodes AE1 to AE3 to provide bank openings of a bank structure BNS, and exposing side surfaces of both the first bank material layer BNL1 and the second bank material layer BNL2 at the bank openings of the bank structure BNS ( Figure 9 ); etching a side surface of the first bank material layer BNL1 to expose a lower surface of the second bank material layer at the bank openings to provide a first bank layer BN1 and a second bank layer BN2 of the bank structure BNS defining the bank openings therein ( Figure 10 ); at the bank openings of the bank structure BNS, exposing the pixel electrodes AE1 to AE3 to the outside of the pixel definition layer PDL by etching the exposed pixel definition material layer PDLL and etching the sacrificial layer ( Figure 11 and Figure 12 ); providing a first light-emitting material layer ELPL1 on the exposed pixel electrodes AE1 to AE3 and on the bank structure BNS, the first light-emitting material layer ELPL1 including a first light-emitting layer EL1 on a first pixel electrode AE1 among the pixel electrodes AE1 to AE3 and a first light-emitting material layer ELPL1 separated from the first light-emitting layer EL1 and on the bank structure BNS ( Figure 14); A first electrode material layer CEPL1 is provided on the first light-emitting material layer ELPL1. The first electrode material layer CEPL1 includes a first common electrode CE1 on the first light-emitting layer EL1 and a first electrode material layer CEPL1 on the first light-emitting material layer ELPL1( Figure 14 ); A first inorganic material layer TLL1 of the encapsulation layer is provided on the first electrode material layer CEPL1( Figure 14 ); A mask pattern PR is provided on the first inorganic material layer TLL1. The mask pattern PR overlaps with the first pixel electrode AE1 at the first bank opening among the bank openings and overlaps with a first portion of the first inorganic material layer TLL1 adjacent to the first bank opening. The mask pattern PR exposes a second portion of the first inorganic material layer TLL1, and the second portion is farther from the first bank opening than the first portion( Figure 15 ); And removing the first portion and the second portion of the first inorganic material layer TLL1( Figure 16 ).

[0233] Removing the first portion and the second portion of the first inorganic material layer TLL1 includes isotropic etching, and the isotropic etching provides a first inorganic pattern TL1 that covers the first common electrode CE1 and defines a wing portion of the first inorganic pattern TL1, and the wing portion corresponds to the first portion of the first inorganic material layer TLL1 and overlaps with the bank structure BNS( Figure 15 and Figure 16 ).

[0234] The first light-emitting material layer ELPL1 and the first electrode material layer CEPL1 together define a first trace pattern TRP1. Removing the first portion and the second portion of the first inorganic material layer TLL1 exposes the first trace pattern TRP1 to the outside of the first inorganic material layer TLL1( Figure 15 ). Here, the method may further include removing the first trace pattern TRP1( Figure 16 ), and after removing the first trace pattern TRP1, providing a second light-emitting material layer ELPL2 on the first inorganic pattern TL1, on the pixel electrodes AE1 to AE3, and on the bank structure BNS. The second light-emitting material layer ELPL2 includes a second light-emitting layer EL2 on the second pixel electrode AE2 among the pixel electrodes AE1 to AE3 and a second organic pattern ELP2 separated from the second light-emitting layer EL2 and on the bank structure BNS. A second electrode material layer CEPL2 is provided on the second light-emitting material layer ELPL2. The second electrode material layer CEPL2 includes a second common electrode CE2 on the second light-emitting layer EL2 and a second electrode pattern CEP2 on the second organic pattern ELP2, and, on the first inorganic pattern TL1 and on the bank structure BNS, providing a second inorganic material layer TLL2 of the encapsulation layer on the second electrode material layer CEPL2(Figure 17 )。

[0235] Providing a second light-emitting material layer ELPL2 including a wing portion of the first inorganic pattern TL1 separates the second light-emitting layer EL2 into a first pattern on the wing portion ( Figure 17 a portion of the second organic pattern ELP2 on the first inorganic pattern TL1 in ), and a second pattern on the bank structure BNS and adjacent to the wing portion ( Figure 17 a portion of the second organic pattern ELP2 on the first bank layer BN1 in ). Providing a second inorganic material layer TLL2 includes extending the second inorganic material layer TLL2 between the first pattern and the second pattern of the second light-emitting layer EL2 and between the wing portion of the first inorganic pattern TL1 and the bank structure BNS (e.g., in Figure 17 , the second inorganic material layer TLL2 folds on itself near the first inorganic pattern TL1).

[0236] However, the effects of the present disclosure are not limited to the effects set forth herein. By referring to the claims, the above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0237] Although the present disclosure has been specifically illustrated and described with reference to embodiments of the present disclosure, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims. These embodiments should be considered only in a descriptive sense and not for purposes of limitation.

Claims

1. A display device, characterized in that include: A first pixel electrode and a second pixel electrode are spaced apart from each other on the substrate; a pixel defining layer, disposed on the substrate and exposing the first pixel electrode and the second pixel electrode; A first light-emitting layer and a first common electrode, wherein the first light-emitting layer is on the first pixel electrode, and the first common electrode is on the first light-emitting layer; a second light-emitting layer and a second common electrode, the second light-emitting layer being on the second pixel electrode, and the second common electrode being on the second light-emitting layer; A first bank layer is disposed on the pixel defining layer; a second bank layer disposed on the first bank layer and including a side surface that protrudes more than a side surface of the first bank layer; a first inorganic layer including a body portion disposed on the first common electrode and a first wing portion disposed on the second bank layer but spaced apart from an upper surface of the second bank layer; as well as The second inorganic layer includes a body portion disposed on the second common electrode, a first connection portion disposed between the first wing portion of the first inorganic layer and the second bank layer, and a first wing portion disposed on the first wing portion of the first inorganic layer.

2. The display device according to claim 1, characterized in that The first inorganic layer also includes a second wing portion, which connects the main portion of the first inorganic layer and the first wing portion of the first inorganic layer and is spaced apart from the upper surface of the second embankment layer, wherein the first wing portion of the first inorganic layer includes a first side surface overlapping with the first light-emitting layer and a second side surface opposite to the first side surface, the second wing portion of the first inorganic layer includes a first side surface overlapping with the first light-emitting layer and a second side surface opposite to the first side surface of the second wing portion, and the second side surface of the first wing portion of the first inorganic layer protrudes much more than the second side surface of the second wing portion of the first inorganic layer.

3. The display device according to claim 1, characterized in that The first wing portion of the second inorganic layer is spaced apart from the first wing portion of the first inorganic layer in a thickness direction of the substrate.

4. The display device according to claim 1, characterized in that The second inorganic layer also includes a third wing portion protruding from the first connecting portion of the second inorganic layer in the thickness direction of the substrate and a second wing portion connecting the third wing portion of the second inorganic layer and the first wing portion of the second inorganic layer, wherein the first wing portion of the second inorganic layer includes a first side surface adjacent to the second light-emitting layer and a second side surface opposite to the first side surface of the first wing portion of the second inorganic layer, the second wing portion of the second inorganic layer includes a first side surface adjacent to the second light-emitting layer and a second side surface opposite to the first side surface of the second wing portion of the second inorganic layer, and the second side surface of the first wing portion of the second inorganic layer protrudes much more than the second side surface of the second wing portion of the second inorganic layer.

5. The display device according to claim 2, characterized in that: defining a first void space between the second wing portion of the first inorganic layer and the upper surface of the second bank layer spaced apart therefrom, and The first inorganic layer and the second inorganic layer cover the first void space.

6. The display device according to claim 2, characterized in that: The second inorganic layer also includes a second connecting portion connected to the first connecting portion of the second inorganic layer and disposed on the second side surface of the second wing portion of the first inorganic layer, and a third connecting portion connecting the second connecting portion of the second inorganic layer and the body portion of the second inorganic layer.

7. The display device according to claim 6, characterized in that: The display device also includes a second organic pattern, which is arranged on the second embankment layer and includes the same material as the second light-emitting layer, wherein a portion of the second embankment layer contacts the third connecting portion of the second inorganic layer and another portion of the second embankment layer contacts the second organic pattern.

8. The display device according to claim 6, characterized in that: The first connection portion of the second inorganic layer contacts a lower surface of the first wing portion of the first inorganic layer, and the second connection portion of the second inorganic layer contacts the second side surface of the second wing portion of the first inorganic layer.

9. The display device according to claim 2, characterized in that: The thickness of the first wing portion of the first inorganic layer is smaller than the thickness of the second wing portion of the first inorganic layer, and A distance between the first wing portion of the first inorganic layer and the first wing portion of the second inorganic layer is greater than a distance between the second pixel electrode and the body portion of the second inorganic layer.

10. The display device according to claim 1, characterized in that: The display device further includes a residual pattern disposed between the pixel defining layer and the first pixel electrode and between the pixel defining layer and the second pixel electrode.

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