Semiconductor package

Abstract

The semiconductor package may include: a package substrate; a first semiconductor die electrically and mechanically coupled to the package substrate; a second semiconductor die electrically and mechanically coupled to the package substrate; and a reinforcement structure mechanically coupled to at least the first vertical surface of the first semiconductor die and the second vertical surface of the second semiconductor die such that the reinforcement structure surrounds an entirety smaller than the first semiconductor die and the second semiconductor die. The semiconductor package further includes an underfill material formed between the top surface of the package substrate and bottom surfaces of the first semiconductor die and the second semiconductor die. The reinforcement structure may include a polymer material in a space between the first semiconductor die and the second semiconductor die. The polymeric material may be a polymer matrix composite having a modulus greater than that of the underfill material.

Description

Technical Field

[0001] Embodiments of the present utility model relate to a package, and particularly to a semiconductor package. Background Art

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing materials of insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Typically, dozens, hundreds, or thousands of integrated circuits are manufactured on a single semiconductor wafer, and the individual die on the wafer are separated by cutting along scribe lines. The individual die are typically packaged separately, for example, in a multi-chip module, or in other types of packages.

[0003] As semiconductor packages become more complex, the package size often becomes larger to accommodate a greater number of integrated circuits and / or die per package. These larger and more complex semiconductor packages pose additional challenges for achieving effective and reliable electrical interconnections within the semiconductor package. Other challenges include mechanical problems associated with mismatches in the coefficient of thermal expansion (CTE) between package components, resulting in warping, cracking, delamination, etc. Summary of the Invention

[0004] Some embodiments of the present utility model provide a semiconductor package, including: a package substrate; a first semiconductor die, electrically and mechanically coupled to the package substrate; a second semiconductor die, electrically and mechanically coupled to the package substrate; and a reinforcement structure, mechanically coupled to at least a first vertical surface of the first semiconductor die and a second vertical surface of the second semiconductor die, wherein the reinforcement structure surrounds less than the entirety of the first semiconductor die and the second semiconductor die.

[0005] According to one embodiment, a bottom fill material is further included, formed between a top surface of the package substrate and bottom surfaces of the first semiconductor die and the second semiconductor die.

[0006] According to one embodiment, the reinforcement structure includes a polymer matrix composite material having a modulus greater than that of the bottom fill material.

[0007] According to one embodiment, the reinforcement structure includes a polymer material located in a space between the first semiconductor die and the second semiconductor die.

[0008] According to one embodiment, a first length of the reinforcement structure is less than or equal to a second length of the first semiconductor die and the second semiconductor die.

[0009] According to an embodiment, a first length of the strengthening structure is greater than a second length of the first semiconductor die and the second semiconductor die, such that the strengthening structure contacts at least two side surfaces of the first semiconductor die and the second semiconductor die.

[0010] According to an embodiment, a first thickness of the strengthening structure is less than or equal to a second thickness of the first semiconductor die and the second semiconductor die.

[0011] According to an embodiment, a first thickness of the strengthening structure is greater than a second thickness of the first semiconductor die and the second semiconductor die, such that the strengthening structure contacts at least one top surface of the first semiconductor die and the second semiconductor die.

[0012] According to an embodiment, the strengthening structure includes two or more separate portions, each separate portion contacting the first vertical surface of the first semiconductor die and the second vertical surface of the second semiconductor die.

[0013] Some other embodiments of the present invention provide a semiconductor package, including: a package substrate; a first semiconductor die electrically and mechanically coupled to the package substrate; a second semiconductor die electrically and mechanically coupled to the package substrate; and a strengthening structure formed in a vertical space between the first semiconductor die and the second semiconductor die, wherein the strengthening structure includes a first width that is less than or equal to a second width of the first semiconductor die and the second semiconductor die. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following will detail various aspects of the present disclosure in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0015] Figure 1A is a vertical cross-sectional exploded view of the components of a semiconductor package during package assembly and surface mount processes.

[0016] Figure 1B is a vertical cross-sectional view showing an assembled semiconductor package mounted on the surface of a support substrate.

[0017] Figure 2A is a top view of a semiconductor package including an external strengthening structure.

[0018] Figure 2B is Figure 2A a vertical cross-sectional view of the semiconductor package.

[0019] Figure 2C isFigure 2B Vertical cross-sectional view of the enlarged portion of the semiconductor package.

[0020] According to various embodiments, Figure 3A is a top view of another semiconductor package.

[0021] According to various embodiments, Figure 3B is Figure 3A vertical cross-sectional view of the semiconductor package.

[0022] According to various embodiments, Figure 4A is a top view of another semiconductor package.

[0023] According to various embodiments, Figure 4B is a top view of another semiconductor package.

[0024] According to various embodiments, Figure 4C is a top view of another semiconductor package.

[0025] According to various embodiments, Figure 5A is a top view of another semiconductor package.

[0026] According to various embodiments, Figure 5B is Figure 5A vertical cross-sectional view of a part of the semiconductor package.

[0027] According to various embodiments, Figure 5C is similar Figure 5A vertical cross-sectional view of a part of an alternative semiconductor package.

[0028] According to various embodiments, Figure 6A is a top view of another semiconductor package.

[0029] According to various embodiments, Figure 6B is a top view of another semiconductor package.

[0030] According to various embodiments, Figure 7 is a flowchart showing operations of a method of forming a semiconductor package.

[0031] Description of reference numerals:

[0032] 100: Package

[0033] 102: Substrate

[0034] 104: Die / Stack

[0035] 106: Die / Stack

[0036] 108: Interposer

[0037] 110: Substrate

[0038] 112: Solder ball

[0039] 114: Surface

[0040] 116: Surface

[0041] 118: Arrow

[0042] 120: Bump

[0043] 122: Underfill portion

[0044] 124: Bump

[0045] 126: Surface

[0046] 128: Underfill portion

[0047] 130: Bonding pad

[0048] 132: Bonding pad

[0049] 134: Underfill portion

[0050] 200: Package

[0051] 202: Frame

[0052] 204: Reinforcing structure

[0053] 206: Adhesive

[0054] 208: Region

[0055] 210: Crack

[0056] 300: Package

[0057] 302: Reinforcing structure

[0058] 306: Surface

[0059] 500: Package

[0060] 700: Method

[0061] 702: Operation

[0062] 704: Operation

[0063] 706: Operation

[0064] 104a: Die

[0065] 104b: Die

[0066] 106a: Die

[0067] 106b: Die

[0068] 122a: Underfill material / portion

[0069] 122b: Underfill material / portion

[0070] 302a: Portion / reinforcing structure

[0071] 302b: Portion / reinforcing structure

[0072] 302c: Portion / reinforcing structure

[0073] 304a: Surface

[0074] 304b: Surface

[0075] 304c: Surface

[0076] 304c1: Surface

[0077] 304c2: Surface

[0078] 304d: Surface

[0079] 304d1: Surface

[0080] 304d2: Surface

[0081] 304e: Surface

[0082] 304f: Surface

[0083] 308a: Length

[0084] 308b: Length

[0085] 309a: Length

[0086] 310a: Width

[0087] 310b: Width

[0088] 311a: Width

[0089] 311b: Width

[0090] 312a: Thickness

[0091] 312b: Thickness

[0092] 313b: Length

[0093] 400a: Package

[0094] 400b: Package

[0095] 400c: Package

[0096] 500a: Portion

[0097] 500b: Package

[0098] 500c: Portion / Package

[0099] 600a: Package

[0100] 600b: Package

[0101] B - B’: Cross - section

[0102] C: Dashed rectangle Detailed implementation manners

[0103] The following content provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. Specific examples of the following described components and configuration manners are used to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first component is formed above or on the second component, which may include embodiments where the first component and the second component are formed in direct contact, and may also include embodiments where additional components are formed between the first component and the second component, such that the first component and the second component are not in direct contact. In addition, the embodiments of the present disclosure may repeat element symbols and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0104] Spatial relative terms may be used herein, such as "under", "below", "lower", "above", "higher", etc. Similar terms are used to facilitate the description of the relationship between one (some) component or feature and another (some) component or feature in the drawings. Spatial relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatial relative adjectives used therein will also be interpreted according to the turned orientation. Unless otherwise explicitly stated, elements with the same reference numerals are assumed to be formed of the same material and have thicknesses within the same thickness range.

[0105] Generally speaking, in a semiconductor package, one or more semiconductor integrated circuit (IC) dies can be mounted on a common substrate, which can also be referred to as a "package substrate". In some embodiments, the electrical connection to the semiconductor package can be achieved by mounting the package substrate on a support substrate (such as a printed circuit board (PCB)) that includes electrical interconnections. The semiconductor die or multi-die chip can be attached to the package substrate using a mass reflow process to melt solder portions, which can then re-solidify to form metallurgical bonds between the semiconductor die (or multi-die chip) and corresponding electrical bonding structures on the package substrate. The semiconductor package can also include various reinforcement structures (also known as wadding structures) to protect the semiconductor IC die and reduce or eliminate mechanical damage that may be caused by thermal expansion stress / strain, which may be caused by the differences in the coefficient of thermal expansion (CTE) of the various components of the semiconductor package.

[0106] Mechanical problems may include mechanical stress / strain, warpage, delamination, etc. In this regard, during the assembly and operation of semiconductor devices, mechanical stress may be applied to the package due to factors such as thermal expansion and contraction, vibration, and external factors. Excessive mechanical stress may cause wire bonds, solder joints, or the package itself to fail. To alleviate this problem, appropriate package designs, selection of materials with suitable mechanical properties, and the use of reinforcement structures (such as wadding structures) can be employed. Warpage refers to the bending or distortion of a semiconductor package. Warpage may occur due to the CTE mismatch between different materials used in the package components. Excessive warpage may lead to poor electrical connections, stress concentration, and reliability issues. Appropriate material selection, thermal management, and package design techniques can help minimize warpage.

[0107] Delamination refers to the separation of different layers or interfaces within a semiconductor package. Delamination may be caused by factors such as moisture absorption, thermal cycling, and mechanical stress. Delamination may result in a decrease in electrical performance, loss of mechanical strength, and increased vulnerability to environmental factors. Effective sealing techniques, moisture-resistant materials, and appropriate manufacturing processes can help prevent delamination.

[0108] The present disclosure provides various embodiments of semiconductor packages. It can be beneficial to provide a reinforcement structure (e.g., a stuffing structure) formed in the central portion of the semiconductor package, which provides mechanical support for semiconductor dies attached to the package substrate but surrounds less than (i.e., does not enclose) the entirety of the semiconductor dies. Thus, the reinforcement structure can strengthen the semiconductor package without overly restricting the relative movement (e.g., caused by thermal expansion) of the various components of the semiconductor package. Accordingly, the semiconductor dies of the various embodiments disclosed in the present disclosure can be configured to allow a greater degree of thermal expansion compared to related semiconductor packages that may be more restricted. A greater degree of thermal expansion can serve to reduce thermal stress / strain that might otherwise cause cracking, deformation, and delamination in the semiconductor package.

[0109] A semiconductor package according to one embodiment may include: a package substrate; a first semiconductor die electrically and mechanically coupled to the package substrate; a second semiconductor die electrically and mechanically coupled to the package substrate; and a reinforcement structure mechanically coupled to a first vertical surface of at least the first semiconductor die and a second vertical surface of the second semiconductor die such that the reinforcement structure surrounds less than the entirety of the first semiconductor die and the second semiconductor die (i.e., does not enclose the first semiconductor die and / or the second semiconductor die). The semiconductor package further includes an underfill material formed between a top surface of the package substrate and bottom surfaces of the first semiconductor die and the second semiconductor die. The reinforcement structure includes a polymeric material located in a space between the first semiconductor die and the second semiconductor die. The polymeric material may be a polymer matrix composite having a modulus greater than that of the underfill material.

[0110] Another semiconductor package according to an embodiment may include: a package substrate; a first semiconductor die electrically and mechanically coupled to the package substrate; a second semiconductor die electrically and mechanically coupled to the package substrate; and a reinforcement structure formed in a vertical space between the first semiconductor die and the second semiconductor die. The reinforcement structure may have a first thickness that is less than or equal to a second thickness of the first semiconductor die and the second semiconductor die, and the reinforcement structure may have a first width that is less than or equal to a second width of the first semiconductor die and the second semiconductor die. The semiconductor package may further include an underfill material formed between a top surface of the package substrate and bottom surfaces of the first semiconductor die and the second semiconductor die, and the reinforcement structure may have a modulus greater than that of the underfill material.

[0111] An exemplary method of forming a semiconductor package may include: attaching a first semiconductor die to a package substrate to electrically and mechanically couple the first semiconductor die to the package substrate; attaching a second semiconductor die to the package substrate to electrically and mechanically couple the second semiconductor die to the package substrate; and forming a reinforcement structure that is mechanically coupled to a first vertical surface of at least the first semiconductor die and a second vertical surface of the second semiconductor die, such that the reinforcement structure surrounds less than the entirety of the first semiconductor die and the entirety of the second semiconductor die (i.e., does not enclose the first semiconductor die and / or the second semiconductor die). The method may further include forming an underfill material between a top surface of the package substrate and bottom surfaces of the first semiconductor die and the second semiconductor die, such that the underfill material has a modulus less than that of the reinforcement structure.

[0112] Figure 1A is a vertical cross-sectional exploded view of components of the semiconductor package 100 during package assembly and surface mounting processes. Figure 1B is a vertical cross-sectional view showing the assembled semiconductor package 100 mounted on the surface of a support substrate 102 (e.g., a printed circuit board (PCB)). The semiconductor package 100 is merely an example type of semiconductor package, and it should be understood that similar assembly and mounting processes may be used for other types of semiconductor packages.

[0113] Referring to FIGS. 1A and 1B, the semiconductor package may include integrated circuit (IC) semiconductor components, such as a first semiconductor die 104 and a second semiconductor die 106. During the package assembly process, the first semiconductor die 104 and the second semiconductor die 106 may be mounted on an interposer 108 to form a semiconductor module. The interposer 108 on which the first semiconductor die 104 and the second semiconductor die 106 are mounted may be mounted on a package substrate 110 to form the semiconductor package 100 using a plurality of metal bumps 124. The semiconductor package 100 may then be mounted on a support substrate 102 (e.g., a printed circuit board (PCB)) by mounting the package substrate 110 on the support substrate 102 using an array of solder balls 112 on a bottom surface 114 of the package substrate 110.

[0114] A parameter that can ensure a proper interconnection between the package substrate 110 and the support substrate 102 is the degree of co-planarity between the surfaces of the solder balls 112, which may be with the mounting surface (i.e., Figure 1A(which contacts the upper surface 116 of the middle support substrate 102). The low coplanarity between the solder balls 112 may result in solder cold joints (i.e., insufficient melting of the solder material, resulting in a poor joint that is prone to cracking and separation) and / or solder bridging problems (i.e., the solder material from one solder ball 112 contacts the material from an adjacent solder ball 112, resulting in an unintended connection (i.e., an electrical short circuit) during the reflow process).

[0115] The deformation of the package substrate 110, such as the warping caused by stress in the package substrate 110, may be the reason for the low coplanarity of the solder balls 112 during the surface mounting of the package substrate 110 onto the support substrate 102. Figure 1B Fig. shows a package substrate 110 including a warping deformation. The warping deformation of the package substrate 110 may cause a change in the distance between the lower surface 114 of the package substrate 110 and the upper surface 116 of the support substrate 102. This deformation of the package substrate 110 may increase the risk of defective solder joints with the underlying support substrate 102. For example, as Figure 1B shown, the deformation of the package substrate 110 may cause at least some of the solder joints between the package substrate 110 and the support substrate 102 to fail completely, as Figure 1B indicated by the arrow 118 in. Figure 1B In the exemplary embodiment shown, the deformation of the package substrate 110 may have a bow - shape or a cup - shape, such that the separation between the lower surface 114 of the package substrate 110 and the upper surface 116 of the support substrate 102 may be minimized at the periphery of the package substrate 110 and may increase towards the center of the package substrate 110.

[0116] The deformation of the package substrate 110 is not uncommon, especially in the case of semiconductor packages used in high - performance computing applications. These high - performance semiconductor packages 100 tend to be relatively large and may include a plurality of semiconductor dies (e.g., 104, 106) mounted to the package substrate 110, which may increase the likelihood that the package substrate 110 may warp or undergo other deformations. Such deformations may pose challenges for the effective solder - mounting of such package substrates 110 onto the support substrate 102.

[0117] In various embodiments, the first semiconductor die 104 can be a three-dimensional device, such as a three-dimensional integrated circuit (3DICs), a system-on-chip (SoC), or a system on integrated chips (SoIC) component. The three-dimensional semiconductor die 104 can be formed by placing chips on top of chips on a semiconductor wafer layer. These three-dimensional devices can provide improved integration density and other advantages, such as faster speed and higher bandwidth, due to the reduced interconnect length between stacked chips. In some embodiments, the first three-dimensional semiconductor die 104 can also be referred to as a "first die stack".

[0118] The second semiconductor die 106 can be different from the first semiconductor die 104 in its structure, design, and / or function. One or more second semiconductor dies 106 can be three-dimensional semiconductor dies, which can also be referred to as "second die stacks". In some embodiments, one or more second semiconductor dies 106 can include memory devices, such as high bandwidth memory (HBM) devices. In the examples shown in FIGS. 1A and 1B, the semiconductor package 100 can include an SoC die stack 104 and an HBM die stack 106, but it should be understood that the semiconductor package 100 can include more or fewer semiconductor dies.

[0119] Referring again to Figure 1B , the first semiconductor die 104 and the second semiconductor die 106 can be mounted on the interposer 108. In some embodiments, the interposer 108 can be an organic interposer including a polymer dielectric material (e.g., a polyimide material) with a plurality of metal interconnect structures extending therethrough. In other embodiments, the interposer 108 can be a semiconductor interposer, such as a silicon interposer, with a plurality of interconnect structures (e.g., through-silicon vias) extending therethrough. Other suitable configurations for the interposer 108 are encompassed within the scope of the present disclosure. The interposer 108 can include a plurality of conductive bonding pads on the upper and lower surfaces of the interposer, and a plurality of conductive interconnects extending through the interposer 108 between the upper and lower bonding pads of the interposer. The conductive interconnects can distribute and route electrical signals between the first semiconductor die 104, the second semiconductor die 106, and the underlying package substrate 110. Thus, the interposer 108 can also be referred to as a redistribution layer (RDL). In other embodiments, the interposer 108 can be omitted and the semiconductor dies (104, 106) can be directly mounted to the package substrate 110.

[0120] A plurality of metal bumps 120, such as micro-bumps, can electrically connect the conductive pads on the bottom surfaces of the first semiconductor die 104 and the second semiconductor die 106 to the conductive pads on the upper surface of the interposer 108 (or in other embodiments, to the conductive pads (not shown) on the package substrate 110). In one non-limiting embodiment, the metal bumps 120 in the form of micro-bumps can include a plurality of first metal stacks, such as a plurality of Cu-Ni-Cu stacks, located on the bottom surfaces of the first semiconductor die 104 and the second semiconductor die 104, and a plurality of second metal stacks (e.g., Cu-Ni-Cu stacks) located on the upper surface of the interposer 108. A solder material, such as tin (Sn), can be located between the corresponding first and second metal stacks to electrically connect the first semiconductor die 104 and the second semiconductor die 106 to the interposer 108. Other suitable materials for the metal bumps 120 are within the scope of the present disclosure.

[0121] After the first semiconductor die 104 and the second semiconductor die 106 are mounted on the interposer 108, a first underfill material portion 122 can optionally be provided around the metal bumps 120 and in the space between the bottom surfaces of the first semiconductor die 104, the second semiconductor die 104, and the upper surface of the interposer 108, as Figure 1B shown. The first underfill material portion 122 can also be provided in the space that laterally separates the adjacent first semiconductor die 104 and the second semiconductor die 106 of the semiconductor package 100. In various embodiments, the first underfill material portion 122 can include an epoxy-based material, which can include a composite of a resin and a filler material.

[0122] Referring again to Figure 1B , the interposer 108 can be mounted on the package substrate 110, and the package substrate 110 can provide mechanical support for the interposer 108 and the first semiconductor die 104 and the second semiconductor die 106 mounted on the interposer 108. The package substrate 110 can include suitable materials, such as organic materials (e.g., polymers and / or thermoplastic materials), semiconductor materials (e.g., semiconductor wafers, such as silicon wafers), ceramic materials, glass materials, combinations thereof. Other suitable substrate materials are also within the scope of the present disclosure. In various embodiments, the package substrate 110 can include a plurality of conductive pads (not shown) in the upper surface 126 of the package substrate 110. A plurality of metal bumps 124, such as C4 solder bumps, can electrically connect the conductive pads (not shown) on the bottom surface of the interposer 108 to the conductive pads on the upper surface 126 of the package substrate 110. In various embodiments, the metal bumps 124 can include a suitable solder material, such as tin (Sn), although other suitable solder materials are also within the scope of the present disclosure.

[0123] The second underfill material portion 128 can be disposed in the space surrounding the metal bumps 124 and between the bottom surface of the interposer 108 and the upper surface 126 of the package substrate 110, as Figure 1B shown. In various embodiments, the second underfill material portion 128 can include an epoxy-based material, which can include a composite of a resin and a filler material. In some embodiments, a lid or cover layer (not shown in FIGS. 1A and 1B) can be mounted to the package substrate 110 and can provide a package around the upper and side surfaces of the first semiconductor die 104 and the second semiconductor die 106.

[0124] As described above, the package substrate 110 can be mounted to a support substrate 102, such as a printed circuit board (PCB). Other suitable support substrates 102 are within the scope of the present disclosure. The package substrate 110 can include a plurality of conductive bonding pads 130 in the lower surface 114 of the package substrate 110. A plurality of conductive interconnects (not shown) can extend through the package substrate 110 between the conductive bonding pads on the upper surface 126 and the lower surface 114 of the package substrate 110. A plurality of solder balls (or bump structures) 112 can electrically connect the conductive bonding pads 130 on the lower surface 114 of the package substrate 110 to a plurality of conductive bonding pads 132 on the upper surface 116 of the support substrate 102.

[0125] The conductive bonding pads 130 of the package substrate 110 and the conductive bonding pads 132 of the support substrate 102 can be formed of a suitable conductive material, such as copper. Other suitable conductive materials are also within the scope of the present disclosure. The plurality of solder balls 112 on the lower surface 114 of the package substrate 110 can form an array of solder balls 112, such as a ball grid array (BGA), which can include an array pattern corresponding to the array pattern of the conductive bonding pads 132 located on the upper surface 116 of the support substrate 102. In one non-limiting example, the array of solder balls 112 can include a grid pattern and can have a pitch (i.e., the distance between the centers of respective solder balls 112 and the centers of respective adjacent solder balls 112). In an exemplary embodiment, the pitch can be between approximately 0.8 and 1.0 millimeters (mm), but larger and smaller pitches can be used. The solder balls 112 can include any suitable solder material, such as tin, lead, silver, indium, zinc, nickel, bismuth, antimony, cobalt, copper, germanium, their alloys, their combinations, etc. Other suitable materials for the solder balls 112 are also within the scope of the present disclosure.

[0126] In some embodiments, the lower surface 114 of the encapsulation substrate 110 may include a coating (not shown) of solder resist (SR) material, which may also be referred to as a “solder mask”. The SR material coating may provide a protective coating for the encapsulation substrate 110 and any underlying circuit patterns formed on or within the encapsulation substrate 110. The SR material coating may also inhibit the adhesion of solder material to the lower surface 114 of the encapsulation substrate 110 during the reflow process. In embodiments where the lower surface 114 of the encapsulation substrate 110 includes an SR coating, the SR material coating may include a plurality of openings through which the conductive bonding pads 130 may be exposed.

[0127] In various embodiments, each of the conductive bonding pads 130 in different regions of the encapsulation substrate 110 may have the same size and shape. In the embodiments shown in FIGS. 1A and 1B, the surface of the conductive bonding pad 130 may be substantially coplanar with the lower surface 114 of the encapsulation substrate 110. In some embodiments, the encapsulation substrate 110 may include a solder resist (SR) coating. Alternatively, the surface of the conductive bonding pad 130 may be recessed relative to the lower surface 114 of the encapsulation substrate 110. In some embodiments, the surface of the conductive bonding pad 130 may be raised relative to the lower surface 114 of the encapsulation substrate 110.

[0128] Referring again to FIGS. 1A and 1B, solder balls 112 may be disposed above the corresponding conductive bonding pads 130. In one non-limiting example, the conductive bonding pad 130 may have a width dimension between about 500 micrometers (μm) and about 550 μm (e.g., about 530 μm), and the solder ball 112 may have an outer diameter between about 600 μm and about 650 μm (e.g., about 630 μm). Larger and smaller sizes of the solder balls 112 and / or conductive bonding pads 130 are also within the scope of the present disclosure.

[0129] The first solder reflow process may include subjecting the encapsulation substrate 110 to an elevated temperature (e.g., at least about 250° C.) to melt the solder balls 112 and cause the solder balls 112 to adhere to the conductive bonding pads 130. After the first solder reflow process, the encapsulation substrate 110 may be cooled to re-solidify the solder balls 112. After the first solder reflow process, the solder balls 112 may adhere to the conductive bonding pads 130. Each solder ball 112 may extend a vertical height from the lower surface 114 of the encapsulation substrate 110, which may be less than the outer diameter of the solder ball 112 before the first reflow process. For example, when the outer diameter of the solder ball 112 is between about 600 μm and about 650 μm (e.g., about 630 μm), the vertical height of the solder ball 112 after the first reflow process may be between about 500 μm and about 550 μm (e.g., about 520 μm).

[0130] In various embodiments, as Figure 1B shown, the process of mounting the package substrate 110 onto the support substrate 102 may include aligning the package substrate 110 above the support substrate 102 such that the solder balls 112 contacting the conductive bonding pads 130 of the package substrate 102 may be located above corresponding bonding pads (e.g., conductive bonding pads 132) on the support substrate 102. Then a second solder reflow process may be performed. The second solder reflow process may include subjecting the package substrate 110 to an elevated temperature (e.g., at least about 250 °C) to melt the solder balls 112 and cause the solder balls 112 to adhere to the corresponding conductive bonding pads 132 on the support substrate 110. Surface tension may keep the package substrate 110 aligned with the support substrate 102 as the solder material cools and solidifies. When the solder balls 112 solidify, the package substrate 110 may be located above the upper surface 116 of the support substrate 102 by a stand-off height that may be between about 0.4 mm and about 0.5 mm, although greater or smaller stand-off heights are within the scope of the present disclosure.

[0131] After mounting the package substrate 110 onto the support substrate 102, a third underfill material portion 134 may be provided in the space surrounding the solder balls 112 and in the space between the lower surface 114 of the package substrate 110 and the upper surface 116 of the support substrate 102, as Figure 1B shown. In various embodiments, the third underfill material portion 134 may include an epoxy-based material, which may include a composite of a resin and a filler material.

[0132] Figure 2A is a top view of a semiconductor package 200 that includes an external reinforcement structure 204, which may be provided to reduce or eliminate Figure 1B the warping deformation of the package substrate 110 shown. The dashed line labeled B-B' represents Figure 2B a cross-section of the semiconductor package 200 shown, as described in more detail below. The semiconductor package 200 may be similar to the semiconductor package 100 of FIGS. 1A and 1B. In this regard, the semiconductor package 200 may include a first semiconductor die 104 and a second semiconductor die 106 mounted to an interposer 108 (e.g., refer to Figure 2B ). The interposer 108 may be mounted to the package substrate 110 as described above with reference to FIGS. 1A and 1B. The semiconductor package 200 may include a first underfill material portion 122 disposed in the space that laterally separates adjacent first semiconductor die 104 and second semiconductor die 106 of the semiconductor package 200. The semiconductor package 200 may also include a second underfill material portion 128, e.g., as Figure 2BAs shown, it can be located in the space around the metal bumps 124 and in the space between the bottom surface of the interposer 108 and the upper surface 126 of the package substrate 110.

[0133] The semiconductor package 200 may further include an epoxy molding compound (EMC), which may be applied to the gap formed between the interposer 108, the first semiconductor die 104, and the second semiconductor die 106 to form a multi-die EMC frame 202. The EMC material may include an epoxy-based compound, which may be hardened (i.e., cured) to provide a dielectric material portion having sufficient rigidity and mechanical strength. The EMC material may include an epoxy resin, a hardener, silica (as a filler material), and other additives. Depending on the viscosity and fluidity, the EMC material may be provided in a liquid form or a solid form.

[0134] Liquid EMC may provide better handling, good fluidity, fewer voids, better filling, and fewer flow marks. Solid EMC may provide smaller cure shrinkage, better stand-off, and less die shift. A high filler content (e.g., 85% by weight) in the EMC material may shorten the time in the molding compound, reduce the molding compound shrinkage, and reduce the molding compound warpage. A uniform filler size distribution in the EMC material may reduce flow marks and may increase fluidity. The cure temperature of the EMC material may be in the range of 125°C to 150°C. The multi-die EMC frame 202 may be cured at the cure temperature to form an EMC matrix that laterally surrounds each of the first semiconductor die 104 and the second semiconductor die 106. The excess portion of the multi-die EMC frame 202 may be removed from above the horizontal plane of the top surface of the semiconductor dies (104, 106) by a planarization process, such as CMP.

[0135] Figure 2B is Figure 2A a cross-sectional view of the semiconductor package 200. The external reinforcement structure 204 may be attached to the package substrate 110 using an adhesive 206 and may be formed of metal, insulator, semiconductor, ceramic, etc. For example, in one embodiment, the external reinforcement structure 204 may include copper, the atomic percentage of which is greater than 80%, such as greater than 90%, greater than 95%, greater than 99%, etc. In other embodiments, larger or smaller percentages may be used. As Figure 2AAs shown, the external reinforcement structure 204 can be configured as a ring located at the periphery of the encapsulation substrate 110. Thus, the external reinforcement structure 204 can form a single structure. Alternatively, the external reinforcement structure 204 can include a plurality of discontinuous portions (not shown). In addition, the external reinforcement structure 204 does not need to be located near the periphery of the encapsulation substrate 110. Instead, the external reinforcement structure 204 can be located in any area on the encapsulation substrate 110 that may be subject to mechanical deformation, such as warping.

[0136] The external reinforcement structure 204 can provide enhanced mechanical support for the encapsulation substrate 110, thereby reducing or eliminating mechanical deformation, such as the warping of the encapsulation substrate 110 described and shown above. Figure 1B Therefore, the external reinforcement structure 204 can be selected to have a mechanical strength (e.g., modulus) greater than that of the encapsulation substrate 110. As described above, the encapsulation substrate 110 can include organic materials (e.g., polymers and / or thermoplastic materials), semiconductor materials (e.g., semiconductor wafers, such as silicon wafers), ceramic materials, glass materials, combinations thereof, etc. Therefore, the material selection for the external reinforcement structure 204 can be based on the mechanical properties of the encapsulation substrate 110. For example, as Figure 2B shown, the presence of the external reinforcement structure 204 can reduce or eliminate Figure 1B the warping deformation of the encapsulation substrate 110 shown. However, the presence of the external reinforcement structure 204 may cause other mechanical problems, as described in more detail below with reference to Figure 2C more detail.

[0137] Figure 2C is Figure 2B a cross-sectional view of an enlarged portion of the semiconductor package. Figure 2C The area shown is Figure 2B the dashed rectangle labeled C in Figure 2C For some material compositions, the coefficient of thermal expansion of the components of the semiconductor package 200 may not match that of the external reinforcement structure 204. Therefore, thermal expansion stress may be generated during thermal cycling. Such thermal stress may lead to mechanical degradation of the semiconductor package 200. For example, as

[0138] In various disclosed embodiments, one or more additional strengthening structures (not shown) may be provided to mitigate thermal stress generated between components of the semiconductor package 200 and the external strengthening structure 204. For example, in some embodiments, a package strengthening structure (not shown) may be formed within the package substrate 110 (e.g., Figure 2C within the region 208). Alternatively, other methods of forming a semiconductor package may mitigate the above-described problems related to mechanical deformation / deterioration that may occur due to thermally induced stress / strain, as described in more detail below with reference to FIGS. 3A through 6B.

[0139] According to various embodiments, Figure 3A is a top view of another semiconductor package 300, and Figure 3B is Figure 3A a vertical cross-sectional view of the semiconductor package 300. The plane defining the Figure 3B vertical cross-sectional view is shown by the cross-section B-B' shown in Figure 3A . As shown in FIGS. 3A and 3B, the semiconductor package 300 may include a package substrate 110; a first semiconductor die 104, electrically and mechanically coupled to the package substrate 110; a second semiconductor die 106, electrically and mechanically coupled to the package substrate 110; and a strengthening structure 302, mechanically coupled to at least a first vertical surface 304a of the first semiconductor die 104 and a second vertical surface 304b of the second semiconductor die 106. The package substrate 110 may also be electrically and mechanically coupled to a support substrate 102, such as a PCB. In some embodiments, an external strengthening structure 204 may also be included, as described in more detail with reference to FIGS. 2A through 2C. However, compared to the semiconductor package 100 of the embodiments of FIGS. 1A and 1B and the semiconductor package 200 of the embodiments of FIGS. 2A through 2C, the semiconductor package 300 of FIGS. 3A and 3B may omit the interposer 108 in some embodiments.

[0140] As shown in FIGS. 3A and 3B, the reinforcement structure 302 may be formed only in the central portion of the semiconductor package 300. In this way, the reinforcement structure 302 surrounds less than the entirety of the first semiconductor die 104 and less than the entirety of the second semiconductor die 106 (i.e., does not surround the first semiconductor die 104 and / or does not surround the second semiconductor die 106). Thus, the reinforcement structure 302 is different from the multi-die EMC frame 202 of the semiconductor package 200 of FIGS. 2A-2C, which surrounds the first semiconductor die 104 and the second semiconductor die 106. Accordingly, the reinforcement structure 302 can reinforce the semiconductor package 300 without unduly restricting the relative movement (e.g., thermal expansion) of the various components of the semiconductor package 300 (e.g., the first semiconductor die 104 and the second semiconductor die 106). As such, compared to the semiconductor package 200 of FIGS. 2A-2C, the first semiconductor die 104 and the second semiconductor die 106 can be configured to allow an additional degree of thermal expansion. Such a configuration can serve to reduce thermal stress / strain that might otherwise cause cracking, deformation, and delamination as shown in the semiconductor package 200 of FIGS. 2A-2C. In this regard, for some applications, the semiconductor package 300 of FIGS. 3A and 3B can provide benefits compared to the semiconductor package 200 of FIGS. 2A-2C.

[0141] The semiconductor package 300 of FIGS. 3A and 3B may further include first underfill materials (122a, 122b) formed between the upper surface 126 of the package substrate 110 and the bottom surfaces 306 of the first semiconductor die 104 and the second semiconductor die 106. The semiconductor package 300 may further include a second underfill material 128 formed between the upper surface 116 of the support substrate 102 and the lower surface 114 of the package substrate 110. The reinforcement structure 302 may be formed of a polymeric material having a modulus greater than that of the first underfill materials (122a, 122b). In other embodiments, the reinforcement structure 302 may have a modulus less than that of the first underfill materials (122a, 122b). For example, the reinforcement structure 302 may be a polymer matrix composite material that may have a modulus (and other properties) that can be adjusted by adjusting the composition of the polymer matrix composite (e.g., changing the composition of the polymeric material and / or the density and composition of the filler material).

[0142] As Figure 3BAs shown, the reinforcement structure 302 can be formed in the space between the first semiconductor die 104 and the second semiconductor die 106 such that the reinforcement structure 302 contacts the upper surface 126 of the package substrate 110 and the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106. Thus, the reinforcement structure 302 can effectively divide the first underfill materials (122a, 122b) into a first portion 122a and a second portion 122b. For example, the reinforcement structure 302 can be formed after attaching the first semiconductor die 104 and the second semiconductor die 106 to the package substrate 110 but before forming the first underfill materials (122a, 122b). In other embodiments (not shown), the reinforcement structure 302 can be formed after forming the first underfill materials (122a, 122b). Thus, the reinforcement structure 302 can be formed on top of the first underfill materials (122a, 122b). In such an embodiment, the first portion 122a and the second portion 122b can form a continuous layer of underfill material (not shown).

[0143] As Figure 3A shown, in some embodiments, the reinforcement structure 302 can have a first length 308a, and the first length 308a can be approximately equal to the corresponding second length 308b of the first semiconductor die 104 and the second semiconductor die 106. Similarly, in some embodiments, the reinforcement structure 302 can have a first width 310a, and the first width 310a can be approximately equal to the second width 310b, where the second width 310b corresponds to the size of the space between the first semiconductor die 104 and the second semiconductor die 106. As Figure 3B shown, in some embodiments, the reinforcement structure 302 can also have a first thickness 312a (measured with respect to the upper surface 126 of the package substrate 110), which can be approximately equal to the second thickness 312b of the first semiconductor die 104 and the second semiconductor die 106 (measured with respect to the upper surface 126 of the package substrate 110). In various other embodiments, the reinforcement structure 302 can have various values for the first length 308a, the first width 310a, and the first thickness 312a, which are relative to the corresponding second length 308b, second width 310b, and second thickness 312b of the first semiconductor die 104 and the second semiconductor die 106, as described in more detail below with reference to FIGS. 4A to 5C. For example, in some embodiments, the reinforcement structure 302 can have a first length 308a that is approximately less than the corresponding second length 308b of the first semiconductor die 104 and the second semiconductor die 106. In other embodiments, the reinforcement structure 302 can have a first length 308a that is greater than the corresponding second length 308b of the first semiconductor die 104 and the second semiconductor die 106.

[0144] According to various embodiments, FIGS. 4A to 4C are top views of corresponding semiconductor packages (400a, 400b, 400c) having various configurations of a reinforcement structure 302. As Figure 4A shown, for example, a first length 308a of the reinforcement structure 302 may be less than a second length 308b of the first semiconductor die 104 and the second semiconductor die 106. Thus, in Figure 4A the semiconductor package 400a, the reinforcement structure 302 may be formed to contact only a portion of a first vertical surface 304a of the first semiconductor die 104 and a portion of a second vertical surface 304b of the second semiconductor die 106.

[0145] In other embodiments, the reinforcement structure 302 may have other configurations, in which the reinforcement structure 302 may contact various other surfaces of the first semiconductor die 104 and the second semiconductor die 106. For example, as Figure 4B shown, a first length 308a of the reinforcement structure 302 may be greater than a second length 308b of the first semiconductor die 104 and the second semiconductor die 106. In addition, a first width 310a of the reinforcement structure 302 may be greater than a second width 310b, which corresponds to a dimension of a space between the first semiconductor die 104 and the second semiconductor die 106. Thus, the reinforcement structure 302 may be formed to contact at least two side surfaces (304c, 304d) of the first semiconductor die 104 and the second semiconductor die 106. In this regard, in addition to contacting the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106, the reinforcement structure 302 may also be formed to contact a third vertical surface 304c1 and a fourth vertical surface 304c2 of the first semiconductor die 104 and a fifth vertical surface 304d1 and a sixth vertical surface 304d2 of the second semiconductor die 106.

[0146] In additional embodiments, as Figure 4C shown in the semiconductor package 400c, the reinforcement structure 302 may be formed as two or more separate parts (302a, 302b, 302c), each part contacting the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106. In Figure 4CIn an example embodiment of semiconductor package 400c, the reinforcement structure 302 may include a first portion 302a, a second portion 302b, and a third portion 302c. In other embodiments, the reinforcement structure 302 may have more or fewer separate portions, and each separate portion may contact a first vertical surface 304a of the first semiconductor die 104 and a second vertical surface 304b of the second semiconductor die 106. In still other embodiments, the various separate portions of the reinforcement structure 302 may be formed to contact various other surfaces of the first semiconductor die 104 and the second semiconductor die 106 (e.g., a third vertical surface 304c1, a fourth vertical surface 304c2, a fifth vertical surface 304d1, a sixth vertical surface 304d2).

[0147] The reinforcement structure 302 in the example semiconductor packages (400a, 400b, 400c) of FIGS. 4A through 4C may provide various degrees of mechanical restraint to the first semiconductor die 104 and the second semiconductor die 106. For example, Figure 4A a reinforcement structure 302 that only contacts the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106 may provide a lesser degree of restraint to the first semiconductor die 104 and the second semiconductor die 106 than Figure 4B the reinforcement structure 302 of semiconductor package 400b. In this regard, Figure 4B the reinforcement structure 302 of semiconductor package 400b, which is formed to contact six surfaces (304a, 304b, 304c1, 304c2, 304d1, 304d2), may provide a greater degree of mechanical restraint between the first semiconductor die 104 and the second semiconductor die 106 than Figure 4A the reinforcement structure 302 of semiconductor package 400a (which is formed to contact only two surfaces (304a, 304b)).

[0148] In other embodiments, Figure 4C the reinforcement structures (302a, 302b, 302c) of semiconductor package 400c may provide a greater or lesser degree of mechanical restraint to the first semiconductor die 104 and the second semiconductor die 106 relative to the reinforcement structure 302 of semiconductor package 400a and semiconductor package 400b. For example, in some embodiments, the reinforcement structure 302 of semiconductor package 400c may provide a greater mechanical restraint than semiconductor package 400a and a lesser mechanical restraint than semiconductor package 400b. In this regard, the degree to which the first semiconductor die 104 and the second semiconductor die 106 are mechanically restrained may be selected for a particular application through the corresponding design of the reinforcement structure 302.

[0149] According to various embodiments, Figure 5Ais a top view of another semiconductor package 500, Figure 5B is Figure 5A a vertical cross-sectional view of a portion 500a of the semiconductor package 500. According to various embodiments, Figure 5C is similar Figure 5A a vertical cross-sectional view of a portion 500c of an alternative semiconductor package. The plane defining the vertical cross-sectional views of FIGS. 5B and 5C is represented by Figure 5A section line B-B’. The semiconductor package 500 may be similar to the semiconductor packages 300 of FIGS. 3A and 3B. In this regard, the semiconductor package 500 may include a package substrate 110; a first semiconductor die 104, electrically and mechanically coupled to the package substrate 110; a second semiconductor die 106, electrically and mechanically coupled to the package substrate 110; and a reinforcement structure 302, mechanically coupled to a first vertical surface 304a of at least the first semiconductor die 104 and a second vertical surface 304b of the second semiconductor die 106. The semiconductor package 500 may further include an external reinforcement structure 204, and the package substrate may be attached to a support substrate 102.

[0150] Similar to the semiconductor packages 300, 400a, 400b, 400c of the embodiments described above with reference to FIGS. 3A to 4C, the reinforcement structure 302 of the semiconductor package 500 may be configured to surround less than the entirety of the first semiconductor die 104 and less than the entirety of the second semiconductor die 106 (i.e., not enclose the first semiconductor die 104 and / or not enclose the second semiconductor die 106). Thus, compared with Figure 2B the EMC die frame 202, the reinforcement structure 302 may mechanically limit the first semiconductor die 104 and the second semiconductor die 106 to a lesser extent, which may be beneficial in some applications. For example, as described above, the reduced mechanical limitation of the first semiconductor die 104 and the second semiconductor die 106 may allow for greater relative thermal expansion, which may serve to reduce stress and strain caused by thermal expansion.

[0151] As Figure 5B shown, compared with Figure 3B the semiconductor package 300, the reinforcement structure 302 may have a first thickness 312a, which may be less than a second thickness 312b of the first semiconductor die 104 and the second semiconductor die 106. Thus, the reinforcement structure 302 of the semiconductor package 500 may limit the first semiconductor die 104 and the second semiconductor die 106 to a lesser extent than the corresponding reinforcement structure 302 of the semiconductor package 300 shown Figure 3B in. In this regard, the first thickness 312a may be selected such that the reinforcement structure 302 provides a predetermined degree of mechanical limitation to the first semiconductor die 104 and the second semiconductor die 106.

[0152] In another embodiment, as Figure 5C shown, the reinforcement structure 302 may have a first thickness 312a, and the first thickness 312a may be greater than the second thickness 312b of the first semiconductor die 104 and the second semiconductor die 106. In addition, as Figure 4B shown in the embodiment of the semiconductor package 400b of, the first width 310a of the reinforcement structure 302 may be greater than the second width 310b, which corresponds to the size of the space between the first semiconductor die 104 and the second semiconductor die 106. Thus, in the case of surrounding less than the whole of the first semiconductor die 104 and less than the whole of the second semiconductor die 106 (i.e., the reinforcement structure 302 does not surround the first semiconductor die 104 and / or does not surround the second semiconductor die 106), the reinforcement structure 302 may be configured to contact at least the first top surface 304e of the first semiconductor die 104 and the second top surface 304f of the second semiconductor die 106, so as to mechanically support the first semiconductor die 104 and the second semiconductor die 106.

[0153] In this regard, in addition to contacting the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106, the reinforcement structure 302 may also be formed to contact the first top surface 304e of the first semiconductor die 104 and the second top surface 304f of the second semiconductor die 106. By contacting the four surfaces (304a, 304b, 304e, 304f), Figure 5C the reinforcement structure 302 of the embodiment part 500c of the semiconductor package may provide relatively greater mechanical confinement to the first semiconductor die 104 and the second semiconductor die 106 than the corresponding reinforcement structure 302 of the semiconductor packages 500 / 500b of FIGS. 5A and 5B.

[0154] According to various embodiments, FIGS. 6A and 6B are top views of additional semiconductor packages 600a and 600b, respectively. The semiconductor package 600a may include a first semiconductor die 104 and two second semiconductor dies (106a, 106b), each electrically and mechanically coupled to a package substrate 110. Similarly, the semiconductor package 600b may include two first semiconductor dies (104a, 104b) and two second semiconductor dies (106a, 106b), each electrically and mechanically coupled to a package substrate 110. The additional semiconductor packages may include a first semiconductor die 104, a second semiconductor die 106, and a third semiconductor die (not shown). The first semiconductor package 600a and the second semiconductor package 600b may each further include a corresponding reinforcement structure 302, which may be coupled to two or more semiconductor dies (104, 104a, 104b, 106a, 106b). The first semiconductor package 600a and the second semiconductor package 600b may each further include an external reinforcement structure 204, and the corresponding package substrate 110 may be electrically and mechanically coupled to a support substrate 102.

[0155] As described above with reference to FIGS. 3A through 5C, the reinforcement structures 302 of the first semiconductor package 600a and the second semiconductor package 600b may be configured to limit, but surround less than the entirety of each semiconductor die (104, 104a, 104b, 106a, 106b). The lengths 308a, 309a, the width 311a, and the thickness (not shown) of the reinforcement structure 302 may vary in the first semiconductor package 600a and the second semiconductor package 600b, as described above with respect to other embodiments. In this regard, each reinforcement structure 302 may have a first length 308a, and the first length 308a may be greater than, less than, or equal to a second length 308b corresponding to the length of one or more semiconductor dies (104, 106). For example, in Figure 6A the semiconductor package 600a, the first length 308a may be greater than the second length 308b corresponding to the length of the second semiconductor dies (106a, 106b). Conversely, in Figure 6B the semiconductor package 600b, the first length 309a may be approximately equal to the second length 313b, and the second length 313b corresponds to the combined length of the first semiconductor dies (104a, 104b) and the second semiconductor dies (106a, 106b).

[0156] Similarly, each reinforcement structure 302 in the first semiconductor package 600a and the second semiconductor package 600b may have a first width 311a, and the first width 311a may be greater than, less than, or equal to a second width 311b corresponding to the width of one or more semiconductor dies (104, 106). For example, inFigure 6A in semiconductor packages 600a and Figure 6B in semiconductor packages 600b, the first width 311a can be approximately equal to the second width 311b, which corresponds to the widths of two second semiconductor dies (106a, 106b). Various other embodiments can include a reinforcement structure 302 having corresponding lengths 308a, 309a, width 311a, and thickness (not shown in FIGS. 6A and 6B). The length 308a, length 309a, width 311a, and thickness of the corresponding reinforcement structure 302 can each vary independently to provide mechanical reinforcement to the corresponding semiconductor package (300, 400a, 400b, 400c, 600a, 600b), and the mechanical reinforcement can be optimized for a particular application. Thus, the reinforcement structure 302 can reinforce the semiconductor package (300, 400a, 400b, 400c, 500, 500c, 600a, 600b) without unduly restricting the relative movement (e.g., thermal expansion) of the various components of the semiconductor package (300, 400a, 400b, 400c, 500, 500c, 600a, 600b). As such, the first semiconductor die 104 and the second semiconductor die 106 can be configured to allow an additional degree of thermal expansion, which can serve to reduce thermal stress / strain that might otherwise cause cracking, deformation, and delamination in other embodiments that may have increased restrictions.

[0157] According to various embodiments, Figure 7 is a flow chart showing the operations of a method 700 of forming a semiconductor package (300, 400a, 400b, 400c, 500, 500c, 600a, 600b). In operation 702, the method 700 can include attaching a first semiconductor die 104 to a package substrate 110, electrically and mechanically coupling the first semiconductor die 104 to the package substrate 110. In operation 704, the method 700 can include attaching a second semiconductor die 106 to the package substrate 110, electrically and mechanically coupling the second semiconductor die 106 to the package substrate 110. In operation 706, the method 700 can include forming a reinforcement structure 302, mechanically coupling to a first vertical surface 304a of at least the first semiconductor die 104 and a second vertical surface 304b of the second semiconductor die 106, such that the reinforcement structure 302 surrounds less than the entirety of the first semiconductor die 104 and less than the entirety of the second semiconductor die 106 (i.e., the reinforcement structure 302 does not enclose the first semiconductor die 104 and / or does not enclose the second semiconductor die 106).

[0158] Method 700 may further include forming underfill materials (122a, 122b) between the top surface 126 of the encapsulation substrate and the bottom surfaces of the first semiconductor die 104 and the second semiconductor die 106, such that the underfill materials (122a, 122b) have a modulus of less than that of the reinforcement structure 302. According to operation 706, method 700 may further include forming the reinforcement structure 302. In one embodiment, according to operation 706, the reinforcement structure 302 is formed and mechanically coupled to at least the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106, such that the reinforcement structure 302 surrounds less than the entirety of the first semiconductor die 104 and less than the entirety of the second semiconductor die 106. In some embodiments, operation 706 of forming the reinforcement structure 302 further includes forming the reinforcement structure 302 to include two or more separate portions (302a, 302b, 302c), each separate portion in contact with the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106. Method 700 may further include attaching one or more additional semiconductor dies (104a, 104b, 106a, 106b) to the encapsulation substrate, such that the one or more additional semiconductor dies (104a, 104b, 106a, 106b) are electrically and mechanically coupled to the encapsulation substrate 110. In this regard, forming the reinforcement structure 302 may further include forming the reinforcement structure 302 to couple to the one or more additional semiconductor dies (104a, 104b, 106a, 106b), but surrounding less than the entirety of the one or more additional semiconductor dies (104a, 104b, 106a, 106b).

[0159] Referring to all the figures and in accordance with various embodiments of the present disclosure, the present disclosure provides a semiconductor package (300, 400a, 400b, 400c, 500, 500c, 600a, 600b). The semiconductor package (300, 400a, 400b, 400c, 500, 500c, 600a, 600b) includes: an encapsulation substrate 110; a first semiconductor die 104, electrically and mechanically coupled to the encapsulation substrate 110; a second semiconductor die 106, electrically and mechanically coupled to the encapsulation substrate 110; and a reinforcement structure 302, mechanically coupled to at least the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106, such that the reinforcement structure 302 surrounds less than the entirety of the first semiconductor die 104 and the second semiconductor die 106 (i.e., the reinforcement structure 302 does not enclose the first semiconductor die 104 and / or does not enclose the second semiconductor die 106).

[0160] The semiconductor packages (300, 400a, 400b, 400c, 500, 500c, 600a, 600b) further include underfill materials (122a, 122b) formed between the top surface 126 of the package substrate 110 and the bottom surfaces 306 of the first semiconductor die 104 and the second semiconductor die 106. The reinforcing structure 302 may include a polymer matrix composite material having a modulus greater than that of the underfill materials (122a, 122b). In some embodiments, the reinforcing structure 302 includes a polymer material located in the space between the first semiconductor die 104 and the second semiconductor die 106. In some embodiments, the first length (308a, 309a) of the reinforcing structure 302 is less than or equal to the second length (308b, 313b) of the first semiconductor die 104 and the second semiconductor die 106.

[0161] In some embodiments, the first length 308a of the reinforcing structure 302 may be greater than the second length 308b of the first semiconductor die 104 and the second semiconductor die 106 such that the reinforcing structure 302 contacts at least two side surfaces (304c, 304d) of the first semiconductor die 104 and the second semiconductor die 106. Similarly, the first thickness 312a of the reinforcing structure 302 may be less than or equal to the second thickness 312b of the first semiconductor die 104 and the second semiconductor die 106. In some embodiments, the first thickness 312a of the reinforcing structure 302 may be greater than the second thickness 312b of the first semiconductor die 104 and the second semiconductor die 106 such that the reinforcing structure 302 contacts at least one top surface 126 of the first semiconductor die 104 and the second semiconductor die 106.

[0162] In some embodiments, the reinforcing structure 302 may include two or more separate portions (302a, 302b, 302c), each separate portion contacting the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106. The semiconductor packages (300, 400a, 400b, 400c, 500, 500c, 600a, 600b) may further include one or more additional semiconductor dies (104a, 104b, 106a, 106b) electrically and mechanically coupled to the package substrate 110. In these embodiments, the reinforcing structure 302 is further coupled to the one or more additional semiconductor dies (104a, 104b, 106a, 106b) but surrounds less than the entirety of the one or more additional semiconductor dies (104a, 104b, 106a, 106b) (i.e., the reinforcing structure 302 does not surround the first semiconductor die 104 and / or does not surround the second semiconductor die 106).

[0163] According to some other embodiments, the present disclosure provides a semiconductor package (300, 400a, 400b, 400c, 500, 500c, 600a, 600b), comprising: a package substrate 110; a first semiconductor die 104, electrically and mechanically coupled to the package substrate 110; a second semiconductor die 106, electrically and mechanically coupled to the package substrate 110; and a reinforcing structure 302, formed in a vertical space between the first semiconductor die 104 and the second semiconductor die 106. A first thickness 312a of the reinforcing structure 302 may be less than or equal to a second thickness 312b of the first semiconductor die 104 and the second semiconductor die 106. In addition, the reinforcing structure 302 may include a first width (310a, 311a), and the first width (310a, 311a) may be less than or equal to a second width (310b, 311b) of the first semiconductor die 104 and the second semiconductor die 106.

[0164] The semiconductor package (300, 400a, 400b, 400c, 500, 500c, 600a, 600b) may further include an underfill material (122a, 122b), formed between a top surface 126 of the package substrate 110 and bottom surfaces 306 of the first semiconductor die 104 and the second semiconductor die 106. The reinforcing structure 302 may include a modulus greater than that of the underfill material (122a, 122b). In some embodiments, the reinforcing structure 302 may further include a polymer matrix composite.

[0165] In some embodiments, the reinforcing structure 302 may be coupled only to a first vertical surface 304a of the first semiconductor die 104 and a second vertical surface 304b of the second semiconductor die 106. In some other embodiments, the reinforcing structure 302 includes two or more separate portions (302a, 302b, 302c), each separate portion in contact with the first vertical surface 304a of the first semiconductor die 104 and the second vertical surface 304b of the second semiconductor die 106. The semiconductor package (300, 400a, 400b, 400c, 500, 500c, 600a, 600b) may further include one or more additional semiconductor dies (104a, 104b, 106a, 106b), electrically and mechanically coupled to the package substrate 110. In these embodiments, the reinforcing structure 302 may be further coupled to the one or more additional semiconductor dies (104a, 104b, 106a, 106b), but surrounding less than the entirety of the one or more additional semiconductor dies (104a, 104b, 106a, 106b).

[0166] The above-described embodiments provide semiconductor packages (300, 400a, 400b, 400c, 500, 500c, 600a, 600b), and it can be beneficial to provide a reinforcement structure 302 formed in the central portion of the semiconductor packages (300, 400a, 400b, 400c, 500, 500c, 600a, 600b), which provides mechanical support for semiconductor dies (104, 104a, 140b, 106, 106a, 106b) attached to the package substrate 110, but surrounds less than the whole of the semiconductor dies. Thus, the reinforcement structure 302 can reinforce the semiconductor packages (300, 400a, 400b, 400c, 500, 500c, 600a, 600b) without unduly restricting the relative actuation (e.g., caused by thermal expansion) of the various components of the semiconductor packages (300, 400a, 400b, 400c, 500, 500c, 600a, 600b). Therefore, compared with the semiconductor package 200 that may be more restricted, the semiconductor dies (104, 106) of the semiconductor packages (300, 400a, 400b, 400c, 500, 500c, 600a, 600b) can be configured to allow a greater degree of thermal expansion, which can serve to reduce thermal stress / strain that might otherwise cause cracking, deformation, and delamination in the semiconductor package 200.

[0167] The features of several embodiments are outlined above so that those skilled in the art can better understand the perspective of the embodiments of the present disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not depart from the concept and scope of the embodiments of the present disclosure, and various changes, substitutions, and replacements can be made without departing from the concept and scope of the embodiments of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the claims.

Claims

1. A semiconductor package, characterized in that, Comprising: A packaging substrate; A first semiconductor die, electrically and mechanically coupled to the packaging substrate; A second semiconductor die, electrically and mechanically coupled to the packaging substrate; and A reinforcing structure, mechanically coupled to at least a first vertical surface of the first semiconductor die and a second vertical surface of the second semiconductor die, wherein the reinforcing structure surrounds less than the entirety of the first semiconductor die and the second semiconductor die.

2. The semiconductor package according to claim 1, wherein Further comprising an underfill material formed between a top surface of the packaging substrate and bottom surfaces of the first semiconductor die and the second semiconductor die.

3. The semiconductor package according to claim 2, wherein The reinforcing structure comprises a polymer matrix composite material having a modulus greater than that of the underfill material.

4. The semiconductor package according to claim 1, wherein The reinforcing structure comprises a polymer material located in a space between the first semiconductor die and the second semiconductor die.

5. The semiconductor package according to claim 4, wherein A first length of the reinforcing structure is less than or equal to a second length of the first semiconductor die and the second semiconductor die.

6. The semiconductor package according to claim 4, wherein, A first length of the reinforcing structure is greater than a second length of the first semiconductor die and the second semiconductor die such that the reinforcing structure contacts at least two side surfaces of the first semiconductor die and the second semiconductor die.

7. The semiconductor package according to claim 4, wherein, A first thickness of the reinforcing structure is less than or equal to a second thickness of the first semiconductor die and the second semiconductor die.

8. The semiconductor package according to claim 4, wherein, A first thickness of the reinforcing structure is greater than a second thickness of the first semiconductor die and the second semiconductor die such that the reinforcing structure contacts at least a top surface of the first semiconductor die and the second semiconductor die.

9. The semiconductor package according to claim 4, wherein, The reinforcing structure comprises two or more separate portions, each separate portion contacting the first vertical surface of the first semiconductor die and the second vertical surface of the second semiconductor die.

10. A semiconductor package, characterized in that, Comprising: A packaging substrate; A first semiconductor die, electrically and mechanically coupled to the packaging substrate; A second semiconductor die, electrically and mechanically coupled to the packaging substrate; and A reinforcing structure formed in a vertical space between the first semiconductor die and the second semiconductor die, wherein the reinforcing structure comprises a first width that is less than or equal to a second width of the first semiconductor die and the second semiconductor die.

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