Circuit for suppressing impact current of direct-current power supply equipment

Abstract

The utility model discloses a circuit for suppressing impact current of direct current power supply equipment, which comprises a time-delay circuit, the time-delay circuit is connected with a switching circuit and an impact suppression circuit, the switching circuit is connected with a filter circuit, and the time-delay circuit, the switching circuit and the impact suppression circuit are all connected with a circuit input end. And the switching circuit, the impact suppression circuit and the filter circuit are all connected with the circuit output end. The direct-current power supply equipment impulse current suppression circuit meets the impulse current suppression requirement of airborne equipment, the function of the direct-current power supply equipment impulse current suppression circuit is not affected by the temperature environment, and the power loss of normal work is not increased.

Description

Technical Field

[0001] The utility model belongs to the technical field of suppression circuits and relates to a circuit for suppressing inrush current of DC power supply equipment. Background Art

[0002] With the rapid development of civil aviation aircraft and the increasing requirements for reliability, higher requirements are also imposed on the power supply of airborne equipment. When an airborne equipment is powered on, a large inrush current will be generated, which affects the load capacity of the on-board power supply and has a great impact on the reliability and stability of the aircraft. The most commonly used method for limiting inrush current is the series use of a thermistor or a power resistor. The prior art mainly connects an NTC thermistor or a power resistor in series to the input line of the equipment power supply. Its principle is to generate a reverse potential at the moment of current impact by using the resistor, so as to limit the inrush current in the circuit and play a role in protecting the circuit. Connecting an NTC varistor in series is the simplest circuit at present, but its current limiting effect is greatly affected by the ambient temperature. When starting at a low temperature, the resistance value of the NTC thermistor is too large and the current is limited too small, which may affect the start. When starting at a high temperature, the resistance value of the NTC thermistor is too small to achieve the effect of limiting current. On the other hand, its power loss also affects the overall conversion efficiency of the power supply. The power resistor is only suitable for the use of small-power equipment. The continuous heating of the resistor and the increase of power loss brought by slightly higher power have a great impact on the overall performance of the equipment.

[0003] In summary, the prior art has the problem that the inrush current suppression circuit of the airborne equipment power supply has a poor current limiting effect. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a circuit for suppressing inrush current of DC power supply equipment, which solves the problem that the inrush current suppression circuit of the airborne equipment power supply in the prior art has a poor current limiting effect.

[0005] The technical solution adopted by the utility model is that a circuit for suppressing inrush current of DC power supply equipment includes a delay circuit, the delay circuit is connected with a switch circuit and an inrush suppression circuit, the switch circuit is connected with a filter circuit, the delay circuit, the switch circuit and the inrush suppression circuit are all connected to the circuit input end, and the switch circuit, the inrush suppression circuit and the filter circuit are all connected to the circuit output end.

[0006] The characteristics of the utility model also lie in:

[0007] The delay circuit includes a first resistor, one end of the first resistor is connected to the circuit input end, and the other end is respectively connected to the fourth resistor, the positive electrode of the first capacitor and the positive electrode of the second capacitor. The end of the fourth resistor far from the first resistor, the negative electrode of the first capacitor and the negative electrode of the second capacitor are all grounded.

[0008] Both ends of the first resistor are connected to the switch circuit, and one end of the first resistor connecting the circuit input terminal is connected to the impact suppression circuit.

[0009] The switch circuit includes a second resistor. One end of the second resistor is connected to the source electrode of the field effect transistor, and the other end is respectively connected to the collector electrode of the triode and the gate electrode of the field effect transistor. The emitter electrode of the triode is connected to a fifth resistor, and the end of the fifth resistor far from the triode is grounded.

[0010] One end of the second resistor connecting the source electrode of the field effect transistor is connected to the circuit input terminal, the first resistor, and the impact suppression circuit. The base electrode of the triode is connected to the first resistor, the fourth resistor, the positive electrode of the first capacitor, and the positive electrode of the second capacitor. The drain electrode of the field effect transistor is connected to the impact suppression circuit, the circuit output terminal, and the filter circuit.

[0011] The impact suppression circuit includes a third resistor. One end of the third resistor is respectively connected to the circuit input terminal, the first resistor, the second resistor, and the source electrode of the field effect transistor, and the other end is connected to the circuit output terminal, the drain electrode of the field effect transistor, and the filter circuit.

[0012] The filter circuit includes a third capacitor and a fourth capacitor connected in parallel. One end of the third capacitor is connected to the circuit output terminal, the third resistor, and the drain electrode of the field effect transistor, and the other end is grounded; one end of the fourth capacitor is connected to the circuit output terminal, the third resistor, and the drain electrode of the field effect transistor, and the other end is grounded.

[0013] The beneficial effects of the present utility model are as follows: The present utility model uses a power resistor to suppress the impact current, meeting the requirements of the power supply design. The triode and the field effect transistor are used together to control the delayed startup of the airborne equipment. After the current impact at the millisecond level ends, the field effect transistor conducts, and the power resistor no longer generates power loss. The present utility model meets the requirements for suppressing the impact current of the airborne equipment, its function will not be affected by the temperature environment, and it does not increase the power loss during normal operation. Description of the Drawings

[0014] Figure 1 is a schematic structural diagram of the circuit for suppressing the impact current of the direct current power supply equipment of the present utility model.

[0015] In the figure, 1. First resistor; 2. Second resistor; 3. Third resistor; 4. Fourth resistor; 5. Fifth resistor; 6. First capacitor; 7. Second capacitor; 8. Third capacitor; 9. Fourth capacitor; 10. Triode; 11. Field effect transistor. Detailed Embodiment

[0016] The present utility model will be described in detail below in conjunction with the drawings and the detailed embodiment.

[0017] The circuit for suppressing the impact current of the direct current power supply equipment, such as Figure 1As shown in the figure, it includes a delay circuit, which is connected to a switch circuit and a shock suppression circuit. The switch circuit is connected to a filtering circuit. The delay circuit, the switch circuit, and the shock suppression circuit are all connected to the circuit input terminal, and the switch circuit, the shock suppression circuit, and the filtering circuit are all connected to the circuit output terminal.

[0018] The delay circuit includes a first resistor R1. One end of the first resistor R1 is connected to the circuit input terminal, and the other end is respectively connected to one end of a fourth resistor R4, the positive electrode of a first capacitor C6, and the positive electrode of a second capacitor C7. The other end of the fourth resistor R4 away from the first resistor R1, the negative electrode of the first capacitor C6, and the negative electrode of the second capacitor C7 are all grounded. Both ends of the first resistor R1 are connected to the switch circuit, and the end of the first resistor R1 connected to the circuit input terminal is connected to the shock suppression circuit.

[0019] The delay circuit reduces the rate of change of the resistor level through the charging process required by the capacitor when power is applied. The first resistor R1 and the fourth resistor R4 perform voltage division, and the first capacitor C6 and the second capacitor C7 are connected in parallel across the fourth resistor R4 to form an RC delay circuit. When power is applied, the first capacitor C6 and the second capacitor C7 are first charged to reduce the rate of increase of the level of the fourth resistor R4.

[0020] The switch circuit includes a second resistor R2. One end of the second resistor R2 is connected to the source electrode of a field effect transistor Q11, and the other end is respectively connected to the collector of a triode Q10 and the gate of the field effect transistor Q11. The emitter of the triode Q10 is connected to a fifth resistor R5, and the other end of the fifth resistor R5 away from the triode Q10 is grounded. The end of the second resistor R2 connected to the source electrode of the field effect transistor Q11 is connected to the circuit input terminal, the first resistor R1, and the shock suppression circuit. The base of the triode Q10 is connected to the first resistor R1, the fourth resistor R4, the positive electrode of the first capacitor C6, and the positive electrode of the second capacitor C7. The drain of the field effect transistor Q11 is connected to the shock suppression circuit, the circuit output terminal, and the filtering circuit.

[0021] The switch circuit is output by the voltage of the resistor in the delay circuit to control the on-off of the triode Q10, and then the on-off of the field effect transistor Q11 is controlled by the change of the collector voltage after the triode Q10 is turned on. In the switch circuit, the positive voltage of the fourth resistor R4 in the delay circuit is connected to the base input of the triode Q10 through a wire. The second resistor R2 is connected to the collector of the triode Q10 for level pull-up, and the fifth resistor R5 is connected to the emitter of the triode Q10 for level pull-down to increase the base level when the triode Q10 is turned on. The circuit input terminal is connected to the source port of the field effect transistor Q11, and the collector of the triode Q10 is connected to the gate of the field effect transistor Q11 through a wire. At the moment of power-on, the triode Q10 is in the cut-off state. After the action of the RC delay circuit, the triode Q10 is turned on, thereby controlling the delayed conduction of the field effect transistor Q11. The drain of the field effect transistor Q11 is connected to the circuit output terminal.

[0022] The impact suppression circuit includes a third resistor 3. One end of the third resistor 3 is connected to the circuit input terminal, the first resistor 1, the second resistor 2, and the source electrode of the field effect transistor 11 respectively, and the other end is connected to the circuit output terminal, the drain electrode of the field effect transistor 11, and the filter circuit.

[0023] The impact suppression circuit is connected in parallel between the source electrode and the drain electrode of the field effect transistor 11. When just powered on, the field effect transistor 11 is not conducting, and the third resistor 3 provides a current path to suppress current impact. During normal operation, the triode 10 conducts, so that the field effect transistor 11 conducts. Since the on-impedance of the field effect transistor 11 is very low, basically no current flows through the third resistor 3, and the power supply has basically no loss, which does not affect the working state of the airborne equipment. The suppression effect on the impact current is mainly affected by the resistance value of the selected third resistor 3.

[0024] The filter circuit includes a third capacitor 8 and a fourth capacitor 9 connected in parallel. One end of the third capacitor 8 is connected to the circuit output terminal, the third resistor 3, and the drain electrode of the field effect transistor 11, and the other end is grounded; one end of the fourth capacitor 9 is connected to the circuit output terminal, the third resistor 3, and the drain electrode of the field effect transistor 11, and the other end is grounded. The filter circuit filters the output power supply.

[0025] This circuit can be directly added to the power input circuit without additional control. According to the magnitude of the impact current of the equipment and the requirements of the power supply characteristics, the capacitance and resistance values in the delay circuit and the resistance value of the third resistor 3 can be adjusted to achieve the target effect.

[0026] Embodiment 1

[0027] As Figure 1 shown, this embodiment proposes a circuit for suppressing the impact current of a DC-powered device, including a delay circuit. The delay circuit is connected to a switch circuit and an impact suppression circuit. The switch circuit is connected to a filter circuit. The delay circuit, the switch circuit, and the impact suppression circuit are all connected to the circuit input terminal. The switch circuit, the impact suppression circuit, and the filter circuit are all connected to the circuit output terminal.

[0028] Embodiment 2

[0029] As Figure 1As shown in the figure, the present embodiment proposes a circuit for suppressing the inrush current of a DC power supply device, including a delay circuit. The delay circuit is connected to a switch circuit and an inrush suppression circuit. The switch circuit is connected to a filter circuit. The delay circuit, the switch circuit, and the inrush suppression circuit are all connected to the circuit input terminal, and the switch circuit, the inrush suppression circuit, and the filter circuit are all connected to the circuit output terminal. The delay circuit includes a first resistor 1. One end of the first resistor 1 is connected to the circuit input terminal, and the other end is respectively connected to the fourth resistor 4, the positive electrode of the first capacitor 6, and the positive electrode of the second capacitor 7. The end of the fourth resistor 4 far from the first resistor 1, the negative electrode of the first capacitor 6, and the negative electrode of the second capacitor 7 are all grounded. Both ends of the first resistor 1 are connected to the switch circuit, and the end of the first resistor 1 connected to the circuit input terminal is connected to the inrush suppression circuit.

[0030] Embodiment 3

[0031] As Figure 1 shown in the figure, the present embodiment proposes a circuit for suppressing the inrush current of a DC power supply device, including a delay circuit. The delay circuit is connected to a switch circuit and an inrush suppression circuit. The switch circuit is connected to a filter circuit. The delay circuit, the switch circuit, and the inrush suppression circuit are all connected to the circuit input terminal, and the switch circuit, the inrush suppression circuit, and the filter circuit are all connected to the circuit output terminal. The delay circuit includes a first resistor 1. One end of the first resistor 1 is connected to the circuit input terminal, and the other end is respectively connected to the fourth resistor 4, the positive electrode of the first capacitor 6, and the positive electrode of the second capacitor 7. The end of the fourth resistor 4 far from the first resistor 1, the negative electrode of the first capacitor 6, and the negative electrode of the second capacitor 7 are all grounded. Both ends of the first resistor 1 are connected to the switch circuit, and the end of the first resistor 1 connected to the circuit input terminal is connected to the inrush suppression circuit. The switch circuit includes a second resistor 2. One end of the second resistor 2 is connected to the source electrode of the field effect transistor 11, and the other end is respectively connected to the collector of the triode 10 and the gate of the field effect transistor 11. The emitter of the triode 10 is connected to a fifth resistor 5, and the end of the fifth resistor 5 far from the triode 10 is grounded. The end of the second resistor 2 connected to the source electrode of the field effect transistor 11 is connected to the circuit input terminal, the first resistor 1, and the inrush suppression circuit. The base of the triode 10 is connected to the first resistor 1, the fourth resistor 4, the positive electrode of the first capacitor 6, and the positive electrode of the second capacitor 7. The drain of the field effect transistor 11 is connected to the inrush suppression circuit, the circuit output terminal, and the filter circuit. The triode 10 uses an NPN type triode, and the model is PMBT2222A; V CBO = 75V, V CEO = 40V, V EBO = 6V, I C = 600mA. The field effect transistor 11 uses a P-channel enhancement type MOSFET, and the model is STP601D; V DSS = -60V, V GSS = ±20V, I S = -30A, R DS= 28 mΩ.

[0032] Example 4

[0033] As Figure 1 shown, this embodiment proposes a circuit for suppressing the inrush current of a DC power supply device, including a delay circuit. The delay circuit is connected to a switch circuit and an inrush current suppression circuit. The switch circuit is connected to a filter circuit. The delay circuit, the switch circuit, and the inrush current suppression circuit are all connected to the circuit input terminal. The switch circuit, the inrush current suppression circuit, and the filter circuit are all connected to the circuit output terminal. The delay circuit includes a first resistor 1. One end of the first resistor 1 is connected to the circuit input terminal, and the other end is respectively connected to the fourth resistor 4, the positive electrode of the first capacitor 6, and the positive electrode of the second capacitor 7. The end of the fourth resistor 4 far from the first resistor 1, the negative electrode of the first capacitor 6, and the negative electrode of the second capacitor 7 are all grounded. Both ends of the first resistor 1 are connected to the switch circuit, and the end of the first resistor 1 connected to the circuit input terminal is connected to the inrush current suppression circuit. The switch circuit includes a second resistor 2. One end of the second resistor 2 is connected to the source electrode of the field effect transistor 11, and the other end is respectively connected to the collector of the triode 10 and the gate of the field effect transistor 11. The emitter of the triode 10 is connected to a fifth resistor 5, and the end of the fifth resistor 5 far from the triode 10 is grounded.

[0034] The end of the second resistor 2 connected to the source electrode of the field effect transistor 11 is connected to the circuit input terminal, the first resistor 1, and the inrush current suppression circuit. The base of the triode 10 is connected to the first resistor 1, the fourth resistor 4, the positive electrode of the first capacitor 6, and the positive electrode of the second capacitor 7. The drain of the field effect transistor 11 is connected to the inrush current suppression circuit, the circuit output terminal, and the filter circuit. The inrush current suppression circuit includes a third resistor 3. One end of the third resistor 3 is respectively connected to the circuit input terminal, the first resistor 1, the second resistor 2, and the source electrode of the field effect transistor 11, and the other end is connected to the circuit output terminal, the drain of the field effect transistor 11, and the filter circuit. The filter circuit includes a third capacitor 8 and a fourth capacitor 9 connected in parallel. One end of the third capacitor 8 is connected to the circuit output terminal, the third resistor 3, and the drain of the field effect transistor 11, and the other end is grounded; one end of the fourth capacitor 9 is connected to the circuit output terminal, the third resistor 3, and the drain of the field effect transistor 11, and the other end is grounded.

[0035] Instance verification is carried out on the series NTC thermistor, the series power resistor, and the present invention respectively. The airborne equipment is powered by +28V DC, and the load current is 0.8A.

[0036] Using a series NTC thermistor to suppress the inrush current, in order to achieve the current suppression effect, the thermistor needs to reach an impedance of more than 10 ohms at room temperature, and the resistance temperature coefficient cannot be too large. Then, when the device is working normally, the temperature of the selected thermistor has reached nearly 100 degrees, the power loss increases by nearly 2W, the device is extremely easy to be damaged, and the safety of the device is reduced.

[0037] A series power resistor is used to suppress the inrush current. Through tests, the power resistor needs to reach more than 8 ohms, the resistor loss is more than 5.12 W, which is manifested as heat loss. The required resistor volume is huge, and it will cause the voltage of the backend power supply to drop by more than 6.4 V, affecting the normal operation of the device and not meeting the design requirements.

[0038] By using the circuit of the present utility model, the third resistor 3 using a 0.8 W and 10-ohm power resistor can meet the design requirements for suppressing the inrush current. The device has a small package volume, is convenient for assembly, does not increase the power loss of the device, and its performance is not affected.

Claims

1. A circuit for suppressing the inrush current of a DC-powered device, characterized in that, It includes a delay circuit, which is connected to a switch circuit and a surge suppression circuit. The switch circuit is connected to a filter circuit. The delay circuit, the switch circuit, and the surge suppression circuit are all connected to the circuit input terminal, and the switch circuit, the surge suppression circuit, and the filter circuit are all connected to the circuit output terminal.

2. The circuit for suppressing the inrush current of a DC-powered device according to claim 1, characterized in that, The delay circuit includes a first resistor (1). One end of the first resistor (1) is connected to the circuit input terminal, and the other end is respectively connected to the fourth resistor (4), the positive electrode of the first capacitor (6), and the positive electrode of the second capacitor (7). The end of the fourth resistor (4) away from the first resistor (1), the negative electrode of the first capacitor (6), and the negative electrode of the second capacitor (7) are all grounded.

3. The circuit for suppressing the inrush current of a DC-powered device according to claim 2, characterized in that, Both ends of the first resistor (1) are connected to the switch circuit, and the end of the first resistor (1) connected to the circuit input terminal is connected to the surge suppression circuit.

4. The circuit for suppressing the inrush current of a DC-powered device according to claim 3, wherein, The switch circuit includes a second resistor (2). One end of the second resistor (2) is connected to the source electrode of the field effect transistor (11), and the other end is respectively connected to the collector of the triode (10) and the gate of the field effect transistor (11). The emitter of the triode (10) is connected to a fifth resistor (5), and the end of the fifth resistor (5) away from the triode (10) is grounded.

5. The circuit for suppressing the inrush current of a DC-powered device according to claim 4, wherein The end of the second resistor (2) connected to the source electrode of the field effect transistor (11) is connected to the circuit input terminal, the first resistor (1), and the surge suppression circuit. The base of the triode (10) is connected to the first resistor (1), the fourth resistor (4), the positive electrode of the first capacitor (6), and the positive electrode of the second capacitor (7). The drain of the field effect transistor (11) is connected to the surge suppression circuit, the circuit output terminal, and the filter circuit.

6. The circuit for suppressing the inrush current of a DC-powered device according to claim 5, characterized in that, The surge suppression circuit includes a third resistor (3). One end of the third resistor (3) is respectively connected to the circuit input terminal, the first resistor (1), the second resistor (2), and the source electrode of the field effect transistor (11), and the other end is connected to the circuit output terminal, the drain of the field effect transistor (11), and the filter circuit.

7. The circuit for suppressing the inrush current of a DC-powered device according to claim 6, characterized in that, The filter circuit includes a third capacitor (8) and a fourth capacitor (9) connected in parallel. One end of the third capacitor (8) is connected to the circuit output terminal, the third resistor (3), and the drain of the field effect transistor (11), and the other end is grounded; one end of the fourth capacitor (9) is connected to the circuit output terminal, the third resistor (3), and the drain of the field effect transistor (11), and the other end is grounded.

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