Display device

Abstract

A display device is provided. The display device includes a display module including a signal line electrically connected to a pixel and defining an end portion farthest from the pixel, and a signal pad electrically connected to the signal line and to which an electrical signal is supplied from an electronic component external to the display module. The signal pad includes a first conductive pattern electrically connected to an end portion of the signal line at the first conductive pattern, a second conductive pattern facing the first conductive pattern and electrically connected to the first conductive pattern, an insulating pattern between the first conductive pattern and the second conductive pattern, and a protruding pattern protruding from the insulating pattern. The signal pad is electrically connected to the electronic component at a protruding pattern that protrudes from the second conductive pattern and overlaps the insulating pattern.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of, and all benefits derived from, Korean Patent Application No. 10 - 2023 - 0109443, filed on August 22, 2023, the entire content of which is hereby incorporated by reference. Technical field

[0003] In this disclosure, it relates to a display device and a method of manufacturing (or providing) a display device. More specifically, in this disclosure, it relates to a pad region of a display device. Background art

[0004] A display device includes a display area as an active area that is activated in response to an electrical signal. The display device can detect an input applied from the outside (e.g., outside the display device), and at the same time, display various images through the display area to provide information to the outside of the display device, such as to a user.

[0005] A display device includes a display panel and a circuit board. The display panel can be electrically connected to a main board through the circuit board. A driving chip can be mounted on the display panel. Summary of the utility model

[0006] This disclosure provides a display device with improved bonding reliability and a method of manufacturing (or providing) a display device.

[0007] Embodiments of the present disclosure provide a display device including a display module, wherein the display module includes pixels, signal lines electrically connected to the pixels and defining an end portion farthest from the pixels, and signal pads electrically connected to the signal lines and receiving electrical signals from electronic components outside the display module, and the signal pads include a first conductive pattern, a second conductive pattern, an insulating pattern, and a protruding conductive pattern. The signal pads are electrically connected to the end portions of the signal lines at the first conductive pattern, the second conductive pattern faces the first conductive pattern and is electrically connected to the first conductive pattern, the insulating pattern is between the first conductive pattern and the second conductive pattern facing each other, the signal pads are electrically connected to the electronic components at the protruding conductive pattern, and the protruding conductive pattern protrudes from the second conductive pattern and overlaps the insulating pattern in a plane (e.g., in a plan view).

[0008] In an embodiment, the protruding conductive pattern may include a metal, and the insulating pattern may include a polymer. For example, the protruding conductive pattern may be made of a metal, and the insulating pattern may be made of a polymer.

[0009] In an embodiment, the protruding conductive pattern may include copper or silver.

[0010] In an embodiment, the second conductive pattern may include a protruding portion extending along the insulating pattern and protruding from the first conductive pattern, and the protruding conductive pattern may protrude from the protruding portion of the second conductive pattern.

[0011] In an embodiment, the first conductive pattern may extend farther than the side surface of the insulating pattern to define an upper surface of the first conductive pattern exposed outside the insulating pattern, and the second conductive pattern may further include a protruding portion in contact with the side surface and the upper surface of the insulating pattern and an extending portion extending from the protruding portion and also from the insulating pattern, and the extending portion is in contact with the upper surface of the first conductive pattern.

[0012] In an embodiment, the entirety of the protruding conductive pattern may overlap with the insulating pattern.

[0013] In an embodiment, each of the protruding conductive pattern and the second conductive pattern may have a side surface, and the side surface of the protruding conductive pattern may be substantially aligned with the side surface of the second conductive pattern.

[0014] In an embodiment, the protruding conductive pattern may include one of a trapezoidal cross-sectional shape, an inverted trapezoidal cross-sectional shape, and a linear cross-sectional shape.

[0015] In an embodiment, the second conductive pattern may include a first layer, a second layer, and a third layer in a direction from the insulating pattern to the protruding conductive pattern. The thicker second layer may have a higher conductivity than each of the first layer and the third layer, and a portion of the second layer may be exposed outside the third layer to contact the protruding conductive pattern, and the protruding conductive pattern may contact the portion of the second layer exposed outside the third layer.

[0016] In an embodiment, the second conductive pattern may further include an oxide film sequentially stacked in a direction from the insulating pattern to the protruding conductive pattern, and a portion of the second layer may be exposed outside both the oxide film and the third layer, and the protruding conductive pattern may contact the portion of the second layer exposed outside both the oxide film and the third layer.

[0017] In an embodiment, within the signal pad, the protruding conductive pattern may be provided as a plurality, thereby including a plurality of protruding conductive patterns spaced apart from each other along the insulating pattern.

[0018] In an embodiment, within the signal pad, the insulating pattern and the protruding conductive pattern may each be provided as a plurality such that a plurality of insulating patterns and a plurality of protruding conductive patterns are included, and the plurality of protruding conductive patterns may respectively overlap with the plurality of insulating patterns.

[0019] In an embodiment, the display module may further include a pad insulating layer between the first conductive pattern of the signal pad and the end portion of the signal line. In the signal pad, a contact hole may be defined in the pad insulating layer to expose the end portion of the signal line to the outside of the pad insulating layer and spaced apart from the insulating pattern in the direction along the signal pad, and the first conductive pattern may contact the end portion of the signal line through the contact hole defined in the pad insulating layer.

[0020] In an embodiment, in the signal pad, the insulating pattern and the contact hole may each be provided in plurality, and the plurality of insulating patterns may be between adjacent contact holes among the plurality of contact holes.

[0021] In an embodiment, the pixel may include a light-emitting element, a transistor electrically connected to the light-emitting element and including a semiconductor pattern and a gate overlapping the semiconductor pattern, an upper electrode on the gate of the transistor, and a plurality of connection electrodes electrically connected to the transistor and on different layers. The end portion of the signal line may be in the same layer as the layer of the gate or the upper electrode of the transistor, the first conductive pattern may be in the same layer as the layer of the first connection electrode among the plurality of connection electrodes, and the second conductive pattern may be in the same layer as the layer of the second connection electrode different from the first connection electrode among the plurality of connection electrodes.

[0022] In an embodiment, the electronic component may include a bump electrode. The electronic component is electrically connected to the signal pad of the display module at the bump electrode, and an adhesive layer between the display module and the electronic component may bond the display module to the electronic component. In the adhesive layer, a protruding conductive pattern may contact the bump electrode to electrically connect the electronic component to the display module.

[0023] In an embodiment of the present disclosure, a method of manufacturing or providing a display device includes: providing a preliminary signal pad including a first conductive pattern of a signal line connected to a display module of the display device, a second conductive pattern on the first conductive pattern, and an insulating pattern between the first conductive pattern and the second conductive pattern; and forming (or providing) a protruding conductive pattern on the preliminary signal pad to form a display pad of the display module, where the display module of the display device is connected to an electronic component of the display device at the signal pad, and forming the protruding conductive pattern on the preliminary signal pad may include an inverse offset printing process.

[0024] In an embodiment, providing the protruding conductive pattern may further include providing a layer of metal ink including a solvent and metal nanoparticles on a pad movable relative to the preliminary signal pad.

[0025] In an embodiment, providing the protruding conductive pattern may further include: after providing the layer of metal ink, transferring a part of the layer of metal ink from the pad to the carrier, which provides a printed pattern corresponding to the remaining part of the layer of metal ink on the pad; transferring the printed pattern from the pad to the second conductive pattern of the preliminary signal pad, and the printed pattern overlaps with the insulating pattern of the preliminary signal pad; and sintering the printed pattern on the second conductive pattern and overlapping with the insulating pattern of the preliminary signal pad to form the protruding conductive pattern of the signal pad.

[0026] In an embodiment, providing the protruding conductive pattern may further include: after providing the layer of metal ink, directly transferring a part of the layer of metal ink from the pad to the second conductive pattern of the preliminary signal pad, which provides a printed pattern of the layer of metal ink on the preliminary signal pad, and the printed pattern overlaps with the insulating pattern of the preliminary signal pad; and sintering the printed pattern on the second conductive pattern and overlapping with the insulating pattern of the preliminary signal pad to form the protruding conductive pattern of the signal pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0028] Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure;

[0029] Figure 2A and Figure 2B is an exploded perspective view of a display device according to an embodiment of the present disclosure;

[0030] Figure 3 is a cross-sectional view of a display module according to an embodiment of the present disclosure;

[0031] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure;

[0032] Figure 5 is a cross-sectional view of a pixel according to an embodiment of the present disclosure;

[0033] Figure 6 is an enlarged exploded perspective view showing a pad area of a display device according to an embodiment of the present disclosure;

[0034] Figure 7A is a plan view schematically showing a pad area according to an embodiment of the present disclosure;

[0035] Figure 7B and Figure 7C correspond to respectively Figure 7ACross-sectional views of line A-A' and line B-B';

[0036] Figures 8A to 8C corresponds to Figure 7A Cross-sectional view of line B-B';

[0037] Figure 9A corresponds to Figure 7A Cross-sectional view of line B-B' and shows the bonding structure of a display device according to an embodiment of the present disclosure;

[0038] Figure 9B is Figure 9A Enlarged cross-sectional view of region XX';

[0039] Figures 10A to 10D Schematic plan view showing a pad region according to an embodiment of the present disclosure;

[0040] Figure 11A and Figure 11B Schematic plan view showing a pad region according to an embodiment of the present disclosure;

[0041] Figures 12A to 12G Cross-sectional view showing a method of manufacturing (or providing) a display device according to an embodiment of the present disclosure; and

[0042] Figure 13A and Figure 13B Cross-sectional view showing a method of manufacturing (or providing) a display device according to an embodiment of the present disclosure. Detailed Description of the Invention

[0043] In this specification, it will be understood that when an element (or region, layer, portion, or the like) is referred to as being related to another element such as "on," "connected to," or "coupled to" another element, it may be directly on, directly connected to, or directly coupled to the other element, or intervening elements may be disposed therebetween. In contrast, when an element (or region, layer, portion, or the like) is referred to as being related to another element such as "directly" "on," "directly connected to," or "directly coupled to" another element, there are no intervening elements therebetween.

[0044] Throughout the specification, like reference numerals or symbols refer to like elements. In the figures and text of the present disclosure, reference numerals indicating a singular form of an element may also be used to refer to a plurality of singular elements. In the drawings, the thickness, ratio, and dimensions of elements are exaggerated for effective description of the technical content.

[0045] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, "a", "an", "the" and "at least one" do not denote a limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly dictates otherwise. Thus, the "a" element referred to in a claim following by "the" element includes one element and a plurality of elements. For example, unless the context clearly dictates otherwise, "an element" has the same meaning as "at least one element". "At least one" should not be construed as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, first component, first region, first layer or first section discussed below could be termed a second element, second component, second region, second layer or second section without departing from the scope of the present disclosure. Similarly, a second element, second component, second region, second layer or second section could be termed a first element, first component, first region, first layer or first section.

[0047] Moreover, the terms "below", "on lower side", "above", "on upper side" or similar terms may be used to describe the relationship of elements shown in the drawings. These terms have relative concepts and are described based on the directions indicated in the drawings.

[0048] It will also be understood that the terms "comprises", "includes" and / or "have", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will also be understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0050] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 1 is a perspective view of a display device DD according to an embodiment of the present disclosure. Figure 2A and Figure 2B is an exploded perspective view of the display device DD according to an embodiment of the present disclosure.

[0052] Figure 2B Exemplarily shown is Figure 2A the bending area BA shown in is in a bent state.

[0053] Referring to Figure 1 , in this specification, a mobile phone is shown as an example of the display device DD. The display device DD according to an embodiment of the present disclosure can be applied not only to large electronic devices such as televisions and monitors, but also to small and medium-sized electronic devices such as tablet computers, car navigation systems, game consoles, and smart watches.

[0054] The display device DD may have a rectangular shape on a plane with a long side extending in a first direction DR1 and a short side extending in a second direction DR2 that intersects the first direction DR1 (e.g., a planar shape along a plane defined by the first direction DR1 and the second direction DR2). However, the embodiments of the present disclosure are not limited thereto, and the display device DD may have various shapes such as a circular shape and a polygonal shape on a plane.

[0055] Hereinafter, a direction intersecting the plane defined by the first direction DR1 and the second direction DR2 that intersect each other is defined as a third direction DR3. In this specification, "when viewed on a plane" may refer to a state when viewed from (or along) the third direction DR3. The thickness of the display device DD and various components or layers of the display device DD may be defined along the third direction DR3 (e.g., the thickness direction).

[0056] The display device DD can be rigid or flexible. "Being flexible" can mean having bending characteristics and can include structures from a fully folded state to structures that can be bent at the nanometer level. For example, the flexible display device DD can include a foldable display device, a rollable display device, or a foldable display device. Various components or layers of the display device DD can be bendable, rollable, foldable, flexible, etc. together with each other.

[0057] The display device DD can display an image IM through a display surface DD-IS. An icon image is shown as an example of the image IM. The display surface DD-IS can be parallel to the plane defined by a first direction DR1 and a second direction DR2.

[0058] The display surface DD-IS can include a display area DD-DA for displaying the image IM and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA can be an area or a planar region that does not display the image IM. However, embodiments of the present disclosure are not limited thereto, and the non-display area DD-NDA can be adjacent to any side of the display area DD-DA while excluding the other side of the display area DD-DA, or can be completely omitted.

[0059] Referring to Figure 2A and Figure 2B , the display device DD can include a window WM, a display module DM, and a housing member BC.

[0060] The window WM can be arranged above the display module DM and can transmit the image IM provided from the display module DM to the outside (e.g., to the outside of the display device DD), such as to a user. The window WM can include a transmissive area TA and a non-transmissive area NTA. The transmissive area TA can overlap with the display area DD-DA shown in Figure 1 and has a shape (e.g., a planar shape) corresponding to the display area DD-DA. Although not shown in the drawings, the window WM can include a base layer and a functional layer arranged on the base layer. The functional layer can include a protective layer, an anti-fingerprint layer, etc. The base layer of the window WM can be made of glass, sapphire, plastic, or the like. The base layer of the window WM can include an optically transparent insulating material. For example, the base layer of the window WM can include a glass film or a plastic film, or include a glass substrate and a plastic film joined to each other by an adhesive.

[0061] The non-transmissive area NTA can be related to Figure 1The non-display area DD-NDA overlaps with that shown in the figure and has a shape corresponding to the non-display area DD-NDA. The non-transmissive area NTA may be an area having a light transmittance relatively lower than that of the transmissive area TA. The non-transmissive area NTA may be defined, for example, in a partial area of the base layer of the window WM by a border pattern, and an area where no border pattern is arranged or the border pattern is excluded may be defined as the transmissive area TA. However, embodiments of the present disclosure are not limited thereto, and the non-transmissive area NTA may also be omitted.

[0062] Although not shown in the drawings, an anti-reflection layer may be arranged between the window WM and the display module DM. The anti-reflection layer may reduce the reflectance of external light incident from the outside of the display device DD. The anti-reflection layer may include a color filter. The color filter may have a predetermined arrangement. For example, the arrangement of the color filter may be considered in view of the emission color of the pixels PX (for example, refer to Figure 4 ) included in the display panel DP to be described later. In addition, the anti-reflection layer may further include a black matrix adjacent to the color filter.

[0063] According to an embodiment of the present disclosure, the display module DM may include a display panel DP and an input sensor ISU serving as an input sensing layer or an input sensing panel.

[0064] The display panel DP may be any one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical systems (MEMS) display panel, an electro-wetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and a quantum dot light-emitting display panel. However, embodiments of the present disclosure are not particularly limited thereto. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0065] The input sensor ISU may include any one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. The input sensor ISU may be formed (or provided) on the display panel DP by a continuous process, or manufactured (or provided) separately and then bonded to the upper side of the display panel DP by an adhesive member, and the input sensor ISU is not limited to any one embodiment of the present disclosure.

[0066] The display device DD may further include a driving chip DC arranged on the display panel DP. The display device DD may further include a circuit board PB arranged on the display panel DP. In this embodiment, the circuit board PB may be a flexible circuit board, but embodiments of the present disclosure are not limited thereto. For example, the circuit board PB may be rigid. The circuit board PB may electrically connect the display panel DP and a main circuit board (for example, a main board) to each other.

[0067] The driving chip DC may include driving elements for driving the pixels PX of the display panel DP, such as data driving circuits. Figure 2AThe structure in which the driving chip DC is mounted on the display panel DP is shown, but the embodiments of the present disclosure are not limited thereto. For example, the driving chip DC may also be mounted on the circuit board PB. In the present embodiment, the driving chip DC and the circuit board PB directly mounted on the display panel DP may be collectively referred to as the electronic components (or external components) of the display device DD. Hereinafter, the description of the bonding structure of the display panel DP and the circuit board PB may be equivalently applied to another electronic component such as the driving chip DC in addition to the circuit board PB.

[0068] The display panel DP may include a bending region BA and a non-bending region adjacent to the bending region BA. The non-bending regions may be provided as a plurality, including a first non-bending region NBA1 and a second non-bending region NBA2 that are arranged at intervals in a direction such as the first direction DR1 (or along a direction such as the first direction DR1) with the bending region BA interposed therebetween.

[0069] The bending region BA may be defined as a region where the display panel DP can be bent around a virtual bending axis BX extending in the second direction DR2. The first non-bending region NBA1 may be a region overlapping with the transmissive region TA, and the second non-bending region NBA2 may be defined as a region where the circuit board PB is connected to the display module DM (or the display panel DP). When the bending region BA is bent around the bending axis BX, the circuit board PB and the driving chip DC may be disposed at the rear surface of the display panel DP, such as below the rear surface of the display panel DP. Although not shown in the drawings, additional components may be arranged to compensate for the step difference between the circuit board PB and the rear surface of the display panel DP caused by the bending region BA.

[0070] According to an embodiment, in the second direction DR2, the width of the first non-bending region NBA1 may be greater than the widths of the bending region BA and the second non-bending region NBA2. However, the embodiments of the present disclosure are not limited thereto, and the width of the bending region BA in the second direction DR2 may be provided as decreasing in the direction from the first non-bending region NBA1 to the second non-bending region NBA2, and is not limited to any one embodiment of the present disclosure.

[0071] As Figure 2B shown, due to the partial bending of the display panel DP, the bent display device DD (or the display module DM) may include a circuit board PB that is disposed on the rear surface of the display panel DP or facing the rear surface and is electrically bonded to the display panel DP.

[0072] The accommodating member BC may accommodate the display module DM and may be coupled to the window WM. The circuit board PB may be disposed at one end of the display panel DP, and at the end of the display panel DP that will be referred to Figure 3The described circuit element layer DP-CL is electrically connected to the display panel DP at the display panel DP. Although not shown in the drawings, the display device DD may further include a main board, an electronic module mounted on the main board, a camera module, a power module, and the like.

[0073] Although a mobile phone has been described as the display device DD, in this specification, for the display device DD, it is sufficient to include at least two electronic components joined to each other. The display panel DP and the driving chip DC mounted on the display panel DP correspond to different electronic components, and these alone can constitute the display device DD. The display panel DP and the circuit board PB connected to the display panel DP also correspond to different electronic components, and these alone can constitute the display device DD. In addition, the main board and the electronic module mounted on the main board can constitute the display device DD. Hereinafter, the display device DD according to an embodiment of the present disclosure will be described focusing on the joining structure of the display panel DP and the driving chip DC mounted on the display panel DP.

[0074] Figure 3 is a cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0075] Referring to Figure 3 , the display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and an upper insulating layer TFL. The input sensor ISU may be disposed on the upper insulating layer TFL.

[0076] The display panel DP may include a display area DP-DA as a display region and a non-display area DP-NDA as a non-display region. The display area DP-DA of the display panel DP may correspond to Figure 1 the display area DD-DA shown in Figure 2A and / or Figure 1 the transmissive area TA shown in Figure 2A , and the non-display area DP-NDA may correspond to

[0077] the non-display area DD-NDA shown in

[0078] The circuit element layer DP-CL may include at least one intermediate insulating layer and circuit elements. The intermediate insulating layer may include at least one inorganic intermediate layer and at least one organic intermediate layer. The circuit elements may include signal lines, driving circuits of pixels (e.g., the pixel driving circuit hereinafter), etc. The insulating layer, semiconductor layer, and conductive layer are formed by coating, deposition, etc. Thereafter, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by photolithography and etching processes. Through such processes, semiconductor patterns, conductive patterns, signal lines, etc. are formed. Patterns arranged on the same layer may be formed by the same process. Hereinafter, patterns formed by the same process mean patterns including the same material and the same stacking structure. Since in the same layer, multiple elements may be formed (or provided) in the same process and / or include the same material as each other, the multiple elements may be corresponding parts of the same material layer, and the multiple elements may be on the same layer by forming an interface with the same lower layer or upper layer, etc., and is not limited thereto.

[0079] The display element layer DP-OLED may include a plurality of light-emitting elements OLED. The display element layer DP-OLED may further include an organic layer such as a pixel defining layer PDL (e.g., refer to Figure 5 ).

[0080] Relative to other layers in the display module DM, the upper insulating layer TFL may seal the display element layer DP-OLED. The upper insulating layer TFL may be disposed on the display element layer DP-OLED. The upper insulating layer TFL may overlap with the display area DP-DA and the non-display area DP-NDA. The upper insulating layer TFL may overlap with at least a part of the non-display area DP-NDA. For example, the upper insulating layer TFL may include a thin film encapsulation layer as an encapsulation layer.

[0081] The thin film encapsulation layer may include a stacking structure of an inorganic layer, an organic layer, and an inorganic layer. The upper insulating layer TFL may protect the display element layer DP-OLED from moisture, oxygen, and foreign substances such as dust particles. However, embodiments of the present disclosure are not limited thereto, and in addition to the thin film encapsulation layer, the upper insulating layer TFL may further include an additional insulating layer. For example, in order to control the refractive index, an optical insulating layer may also be included.

[0082] According to an embodiment of the present disclosure, a packaging substrate may be provided instead of the upper insulating layer TFL. In this case, the packaging substrate may be opposite to the base layer BL, and the circuit element layer DP-CL and the display element layer DP-OLED may be disposed between the packaging substrate and the base layer BL facing each other.

[0083] The input sensor ISU may be directly disposed on the display panel DP. In this specification, "component A is directly disposed on component B" means that no intermediate layer is disposed between component A and component B. In the present embodiment, the input sensor ISU may be manufactured by a continuous process with the display panel DP. However, the technical scope of the present disclosure is not limited thereto, and the input sensor ISU may be provided as a separate panel and bonded to the display panel DP through an adhesive layer. For example, the input sensor ISU may be omitted.

[0084] Figure 4 is a plan view of a display panel DP according to an embodiment of the present disclosure.

[0085] Referring to Figure 4 , the display panel DP may include pixels PX provided as a plurality (including a plurality of pixels PX), a gate driving circuit GDC, a plurality of signal lines SGL, and signal pads DP-PD provided as a plurality (including a plurality of signal pads DP-PD).

[0086] The pixels PX may be disposed in the display area DP-DA. Each of the pixels PX includes a light-emitting element OLED (e.g., referring to Figure 5 ) and a pixel driving circuit connected (e.g., electrically connected) thereto. In an embodiment, the light-emitting element OLED may be an organic light-emitting element. The gate driving circuit GDC sequentially outputs a gate signal as an electrical signal to a plurality of gate lines GL to be described later. One or more layers or patterns of transistors of the gate driving circuit GDC may be formed by the same process as the process of forming the layers or patterns of transistors of the pixels PX (e.g., a low-temperature polysilicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process). The display panel DP may further include another driving circuit that provides an emission control signal for light emission to the pixels PX.

[0087] The plurality of signal lines SGL may include a plurality of gate lines GL, a plurality of data lines DL, a power line PL, and a control signal line CSL. The plurality of gate lines GL may each be connected to a corresponding one of the pixels PX among the pixels PX, and the plurality of data lines DL may each be connected to a corresponding one of the pixels PX among the pixels PX. The power line PL may be connected to the pixels PX. The control signal line CSL may provide a control signal as an electrical signal to a scan driving circuit (e.g., the gate driving circuit GDC).

[0088] A plurality of signal lines SGL may overlap with the display area DP-DA and the non-display area DP-NDA. Each of the plurality of signal lines SGL may include a line portion LP. Although not shown in the drawings, each of the plurality of signal lines SGL may also include a pad portion. The line portion LP may overlap with the display area DP-DA and the non-display area DP-NDA. The pad portion may be connected to an end portion (which may also be referred to as an end part) of the line portion LP, such as an end that is farthest from the display area (e.g., the display area DP-DA) along the corresponding signal line. The connection between the pad portion and the line portion LP will be described in detail with reference to Figure 7A The connection between the pad portion and the line portion LP will be described in detail.

[0089] A plurality of signal pads DP-PD may include a first pad PD1, a second pad PD2, and a third pad PD3. An area in which the first pad PD1 and the second pad PD2 are arranged may be defined as a first pad area PA1, and an area in which the third pad PD3 is arranged may be defined as a second pad area PA2.

[0090] The first pad area PA1 may be an area that overlaps with the Figure 2A driver chip DC shown in, and the second pad area PA2 may be an area that overlaps with the Figure 2A circuit board PB shown in. The first pad area PA1 may include a first area B1 (or first region) in which the first pad PD1 is arranged and a second area B2 (or second region) in which the second pad PD2 is arranged. The first pad area PA1 and the second pad area PA2 may be arranged in the non-display area DP-NDA. The first pad area PA1 and the second pad area PA2 may be spaced apart from each other in a first direction DR1.

[0091] The first pads PD1 may be provided in plurality to define a first pad row within the first area B1, the second pads PD2 may be provided in plurality to define a second pad row within the second area B2, and the third pads PD3 may be provided in plurality to define a third pad row within the second pad area PA2. An exemplary illustration shows one pad row arranged in each of the first area B1 and the second area B2 of the first pad area PA1, but embodiments of the present disclosure are not limited thereto, and a plurality of pad rows may also be arranged in one of the corresponding areas or regions of the first pad area PA1.

[0092] Each of the plurality of first pads PD1 may be connected to a corresponding one of the data lines DL among the data lines DL. Although not shown in the drawings, the first pad PD1 and the second pad PD2 may be electrically connected to each other. Each of the second pads PD2 may be connected to each of the third pads PD3 through a connection signal line S-CL.

[0093] The circuit board PB may include a plurality of substrate bump electrodes PB-BP. The substrate bump electrodes PB-BP may be arranged in the second direction DR2. The substrate bump electrodes PB-BP of the circuit board PB may contact the third pad PD3 in the second pad region PA2 to be connected to the third pad PD3 in the second pad region PA2. When contacting, an interface may be formed therebetween. The substrate bump electrodes PB-BP of the circuit board PB may correspond to the third pad PD3 of the display panel DP in terms of, for example, position, size, etc.

[0094] Figure 5 is a cross-sectional view of a pixel PX according to an embodiment of the present disclosure.

[0095] Referring to Figure 4 and Figure 5 and

[0096] Figure 5 Exemplarily, one transistor TR is shown, but the embodiments of the present disclosure are not limited thereto. The pixel PX according to an embodiment may include seven transistors and at least one capacitor, and the seven transistors and the capacitor may be electrically connected to each other in various ways. However, the number of each of the transistors and capacitors constituting the pixel PX is not limited to any one embodiment of the present disclosure.

[0097] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, conductive signal lines, etc. The insulating layer, semiconductor layer, and conductive layer are formed (or provided) by coating, deposition, etc. Thereafter, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned by photolithography. In such a manner, semiconductor patterns, conductive patterns, conductive signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED are formed.

[0098] The base layer BL may include a synthetic resin film. The base layer BL may have a multilayer structure. For example, the base layer BL may have a three-layer structure of a synthetic resin layer, an inorganic layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide-based resin layer, and the material is not particularly limited thereto. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, or the like.

[0099] In an embodiment, the circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, a first insulating layer 10 to a sixth insulating layer 60, a transistor TR, a connection signal line SCLd, an upper electrode UE, a first connection electrode CNE1, and a second connection electrode CNE2.

[0100] At least one inorganic layer is disposed on the upper surface of the base layer BL. The inorganic layer may be formed of multiple layers or include multiple layers. The barrier layer BRL may be disposed on the base layer BL. The buffer layer BFL may be disposed on the barrier layer BRL. The barrier layer BRL and the buffer layer BFL may be inorganic layers.

[0101] A semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, embodiments of the present disclosure are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide.

[0102] Figure 5 Only a part of the semiconductor pattern is shown, and the semiconductor pattern may be further disposed in another area of the pixel PX in a plane, such as multiple semiconductor patterns included in the semiconductor layer of the circuit element layer DP-CL. The semiconductor patterns may be arranged across multiple pixels PX according to a specific rule. The semiconductor pattern may change in electrical properties according to whether the area or region is doped. The semiconductor pattern may include a first area and a second area. The first area may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped area doped with a P-type dopant.

[0103] The first area has a higher conductivity (e.g., electrical conductivity) than the second area and basically serves as a transistor electrode or a transistor signal line. The second area may be a lightly doped area or an undoped area and basically corresponds to the active area (or channel) of the transistor. In other words, a part of the semiconductor pattern may be the active area of the transistor, another part may be the source area or drain area of the transistor, and another part may be a connection electrode or a connection signal line.

[0104] As Figure 5 shown, the source S as the source area of the transistor TR, the active part A as the active area, and the drain D as the drain area may be formed of a semiconductor layer.

[0105] Figure 5 A part of the connection signal line SCLd formed of a semiconductor layer is shown, such as in the same layer as the semiconductor pattern of the transistor TR. In an embodiment, the connection signal line SCLd may be electrically connected to any drain D among multiple transistors in the pixel PX.

[0106] The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 may cover the semiconductor pattern. The first insulating layer 10 may overlap the plurality of pixels PX in common. A gate G is disposed on the first insulating layer 10. The gate G may be a part of a metal pattern in the first metal material layer. The gate G may overlap the active portion A. In a method of providing a display panel DP, the gate G may be used as a mask in a doping process of a lower semiconductor material layer.

[0107] A second insulating layer 20 covering the gate G may be disposed on the first insulating layer 10. The second insulating layer 20 may overlap the plurality of pixels PX in common. An upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the gate G of the transistor TR. The upper electrode UE may be a part of a metal pattern in the second metal material layer. A part of the gate G and the upper electrode UE overlapping the gate G may define a capacitor.

[0108] A third insulating layer 30 covering the upper electrode UE may be disposed on the second insulating layer 20. A first connection electrode CNE1 disposed on the third insulating layer 30 may be connected to a connection signal line SCLd through a first contact hole CNT-1 (or at the first contact hole CNT-1) passing through the first insulating layer 10 to the third insulating layer 30.

[0109] A fourth insulating layer 40 covering the first connection electrode CNE1 may be disposed on the third insulating layer 30. Each of the first insulating layer 10 to the fourth insulating layer 40 may be an inorganic layer and / or an organic layer and have a single-layer or multi-layer structure.

[0110] In an embodiment, the first connection electrode CNE1 may also be disposed on the fourth insulating layer 40 and covered by a fifth insulating layer 50. Alternatively, according to an embodiment of the present disclosure, both the first connection electrode CNE1 disposed on the third insulating layer 30 and covered by the fourth insulating layer 40 and the first connection electrode CNE1 disposed on the fourth insulating layer 40 and covered by the fifth insulating layer 50 may be included.

[0111] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0112] The sixth insulating layer 60 covering the second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. A first electrode AE may be disposed on the sixth insulating layer 60. The first electrode AE may be connected to the second connection electrode CNE2 through a third contact hole CNT-3 passing through the sixth insulating layer 60. The first contact hole CNT-1 to the third contact hole CNT-3 may communicate with each other to commonly define a contact hole.

[0113] The circuit element layer DP-CL may include a plurality of connection electrodes connected to a plurality of transistors, and some of the plurality of connection electrodes may be disposed on (or in) different layers from each other. Although not shown in the drawings, the first connection electrode CNE1 may extend in a plane defined by a first direction DR1 and a second direction DR2 to be connected to the transistor TR. The positions of the plurality of connection electrodes are not limited to any one embodiment of the present disclosure.

[0114] The display element layer DP-OLED may include a pixel defining film PDL and a light emitting element OLED. The pixel defining film PDL as a pixel defining layer may have (or define) a pixel opening OPN defined therein. The pixel opening OPN of the pixel defining film PDL may expose at least a part of the first electrode AE to the outside of the pixel defining film PDL. In the present embodiment, the light emitting region PXA may be defined as a region or area corresponding to the part of the first electrode AE exposed to the outside of the pixel defining layer through the pixel opening OPN.

[0115] A hole control layer HCL may be commonly disposed in the light emitting region PXA and the non-light emitting region NPXA. The hole control layer HCL may include a hole transport layer and further include a hole injection layer. A light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in a region corresponding to the pixel opening OPN. That is, the light emitting layer EML may be formed individually for each pixel PX, such as formed as a discrete pattern. However, the embodiments of the present disclosure are not limited thereto, and the light emitting layer EML may also be formed to commonly span a plurality of pixels PX, such as by using an aperture mask in a method of providing the display panel DP.

[0116] An electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be formed to commonly span a plurality of pixels PX, such as by using an aperture mask in a method of providing the display panel DP.

[0117] A second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have an integrated form and be formed to commonly span a plurality of pixels PX. An upper insulating layer TFL may be disposed on the second electrode CE. The upper insulating layer TFL may include a plurality of thin films stacked in the thickness direction.

[0118] Figure 6 is an enlarged exploded perspective view showing a first pad region PA1 and a second pad region PA2 of a display device DD according to an embodiment of the present disclosure. Figure 6 Exemplarily shown are a driving chip DC and a circuit board PB disassembled from a display panel DP. Figure 6 The first pad PD1, the second pad PD2, the connection signal line SCLn, and the third pad PD3 in Figure 4 are the same as the first pad PD1, the second pad PD2, the connection signal line S-CL, and the third pad PD3 in

[0119] Referring to Figure 4 and Figure 6 the driving chip DC can be bonded to the display panel DP at the first pad region PA1 of the display panel DP through a first adhesive layer CF1. The circuit board PB can be bonded to the display panel DP at the second pad region PA2 of the display panel DP through a second adhesive layer CF2. The first adhesive layer CF1 and the second adhesive layer CF2 can include a synthetic resin having adhesiveness. According to the present embodiment, the first adhesive layer CF1 and the second adhesive layer CF2 may not include (e.g., exclude) conductive elements such as conventional conductive balls, and may include only a synthetic resin having conductivity, such as to provide a conductive adhesive pattern or layer.

[0120] The driving chip DC can include a driving integrated circuit D-IC and chip bump electrodes DC-BP mounted in the driving chip DC. The driving integrated circuit D-IC can include an upper surface DC-US as the upper surface of the chip and a lower surface DC-DS as the lower surface of the chip, and the lower surface DC-DS can be a surface facing the first pad PD1 and the second pad PD2, such as being closer to the display panel DP than the upper surface of the chip. The chip bump electrodes DC-BP can be arranged on the lower surface DC-DS of the driving integrated circuit D-IC.

[0121] The chip bump electrodes DC-BP can include a plurality of first bumps BP1 electrically connected to the display panel DP at a plurality of first pads PD1 respectively and a plurality of second bumps BP2 electrically connected to the display panel DP at a plurality of second pads PD2 respectively. The first bumps BP1 can be arranged along a second direction DR2, and the second bumps BP2 can be spaced apart from the first bumps BP1 in a first direction DR1 and arranged along the second direction DR2.

[0122] The driving chip DC can receive a first signal as an electrical signal from the outside (for example, outside the display device DD) through the second pad PD2 and the second bump BP2. The driving chip DC can provide a second signal as an electrical signal, which is generated based on the first signal, to the first pad PD1 through the first bump BP1. For example, the driving chip DC can include a data driving circuit. The first signal can be an image signal as a digital signal applied from the outside, and the second signal can be a data signal as an analog signal. The driving chip DC can generate an analog voltage corresponding to the gray value of the image signal. The data signal can be provided to the pixel PX through the Figure 4 data line DL shown in

[0123] Although not shown in the drawings, the first bump BP1 and the second bump BP2 can protrude from the lower surface DC-DS of the driving integrated circuit D-IC and / or be exposed to the outside of the driving chip DC. When the first adhesive layer CF1 hardens or is provided in a hardened form, the first pad PD1 and the first bump BP1 can be fixedly contacted with each other, and the second pad PD2 and the second bump BP2 can be fixedly contacted with each other to electrically connect the display panel DP to the driving chip DC.

[0124] The circuit board PB can include a base board layer P-BS and a substrate bump electrode PB-BP mounted on the circuit board PB. The circuit board PB can include an upper surface PB-US as an upper board surface and a lower surface PB-DS as a lower board surface, and the lower surface PB-DS can be a surface facing the third pad PD3, such as being closer to the display panel DP than the upper board surface. The substrate bump electrode PB-BP can be arranged on the lower surface PB-DS of the base board layer P-BS. A plurality of substrate bump electrodes PB-BP are electrically connected to the display panel DP at a plurality of third pads PD3 respectively. The substrate bump electrodes PB-BP can be arranged along the second direction DR2. The circuit board PB can provide an image signal, a driving voltage, and other control signals to the driving chip DC.

[0125] Although not shown in the drawings, the substrate bump electrode PB-BP can protrude from the lower surface PB-DS of the base board layer P-BS or be exposed at the lower surface PB-DS of the base board layer P-BS to be exposed to the outside of the circuit board PB. When the second adhesive layer CF2 hardens or is provided in a hardened form, the third pad PD3 and the substrate bump electrode PB-BP can be fixedly contacted with each other to electrically connect the display panel DP to the circuit board PB.

[0126] The electronic component may include a component substrate and component bump electrodes disposed on the lower side of the component substrate. In the case where the electronic component corresponds to the driving chip DC, the component substrate may correspond to the driving integrated circuit D-IC of the driving chip DC, and the component bump electrodes may correspond to the chip bump electrodes DC-BP. Alternatively, in the case where the electronic component corresponds to the circuit board PB, the component substrate may correspond to the base board layer P-BS of the circuit board PB, and the component bump electrodes may correspond to the substrate bump electrodes PB-BP.

[0127] Figure 7A is a plan view schematically showing the first pad region PA1 and / or the second pad region PA2 according to an embodiment of the present disclosure. Figure 7B and Figure 7C corresponds to Figure 7A is a cross-sectional view. Figures 8A to 8C corresponds to Figure 7A is a cross-sectional view. Figure 9A is a cross-sectional view showing the bonding structure of the display device DD according to an embodiment of the present disclosure. Figure 9B is Figure 9A is an enlarged cross-sectional view of the region XX' of. Figure 7B is along Figure 7A is a cross-sectional view of the first pad region PA1 and / or the second pad region PA2 taken along the line A-A', and Figure 7C and Figures 8A to 8C is a cross-sectional view of the first pad region PA1 and / or the second pad region PA2 taken along the line B-B' of 7A. Although the cross-sectional structure is shown in the plane defined by the second direction DR2 and the third direction DR3, it will be understood that Figures 7B to 9B the cross-section in may represent the structure in the plane defined by the first direction DR1 and the third direction DR3.

[0128] Figures 7A to 9B The single signal pad DP-PD (or signal pad structure) shown in may represent any one of a plurality of signal pads DP-PD including the first pad PD1 to the third pad PD3 described with reference to Figure 4 and Figure 6 The main planar dimension of the structure (which may be referred to as the main planar dimension) may define its length, and the planar dimension intersecting the main dimension (which may be referred to as the dimension) may define its width. Figure 7A shows a data line DL as an example of a conductive signal line, which includes a distance from the display area (e.g., along the length of the data line DL (e.g., the first direction DR1)) Figure 4The farthest end portion DL-E and the line portion DL-S shown in [Figure], the end portion DL-E and the line portion DL-S have different widths from each other (e.g., in the second direction DR2), but embodiments of the present disclosure are not limited thereto. The conductive signal line may be a different signal line other than the data line DL, and the end portion DL-E and the line portion DL-S may also have a uniform width without distinction therebetween. The line portion DL-S may correspond to Figure 4 the line portion LP in [Figure]. The end portion DL-E may correspond to Figure 4 the above-mentioned pad portion among the signal pads DP-PD in [Figure].

[0129] Hereinafter, the first pad region PA1 and the second pad region PA2 will be described focusing on the first pad region PA1 in which the data line DL is arranged. For the second pad region PA2, except that the connection signal line S-CL (see Figure 4 ) is arranged instead of the data line DL, the description of the first pad region PA1 can be applied.

[0130] Referring to Figure 7A , the signal pad DP-PD may include a first conductive pattern CL1, a second conductive pattern CL2, at least one insulating pattern SP, and at least one protruding pattern TP. Referring to Figure 7B , the first conductive pattern CL1 may be connected to the end portion DL-E of the data line DL through at least one contact hole OP-C serving as a pad contact hole. Figure 7A Exemplarily, a signal pad DP-PD including three contact holes OP-C, six insulating patterns SP, and six protruding patterns TP is shown.

[0131] In a plane, the end portion DL-E may have a shape extending in the first direction DR1, that is, having a length (main dimension) along the first direction DR1. That is, the end portion DL-E may have a dimension in the first direction DR1 that is larger than the dimension in the second direction DR2.

[0132] In a plane, the contact hole OP-C may overlap with the end portion DL-E. A plurality of contact holes OP-C may be arranged along the first direction DR1. A plurality of contact holes OP-C may be arranged to be separated from each other (e.g., spaced apart from each other) in the first direction DR1. In an embodiment, a plurality of contact holes OP-C may be respectively arranged on one side (first end or upper side) of the end portion DL-E in the first direction DR1, the other side (second end or lower side) of the end portion DL-E opposite to this side in the first direction DR1, and the central portion of the end portion DL-E. In a plane, a part of the first conductive pattern CL1 may overlap with the contact hole OP-C.

[0133] On a plane, the insulating pattern SP may overlap with the second conductive pattern CL2. On a plane, the insulating pattern SP may be disposed outside the contact hole OP-C, such as being spaced apart from the contact hole OP-C. In the present embodiment, a plurality of insulating patterns SP may be arranged along the first direction DR1. The plurality of insulating patterns SP may be arranged to be separated from each other in the first direction DR1.

[0134] In the present embodiment, the insulating pattern SP may be disposed between adjacent contact holes OP-C. In an embodiment, some of the insulating patterns SP may be disposed between the contact hole OP-C disposed on the upper side and the contact hole OP-C disposed in the central portion, and others of the insulating patterns SP may be disposed between the contact hole OP-C disposed on the lower side and the contact hole OP-C disposed in the central portion. Figure 7A Exemplarily, three insulating patterns SP are shown to be disposed between the contact hole OP-C disposed on the upper side and the contact hole OP-C disposed in the central portion, and three insulating patterns SP are disposed between the contact hole OP-C disposed on the lower side and the contact hole OP-C disposed in the central portion.

[0135] Figure 7A Exemplarily, the insulating pattern SP having a square shape (e.g., a planar shape of a square) on a plane is shown, but the embodiments of the present disclosure are not limited thereto. The shape of the insulating pattern SP may be changed to a planar shape such as a polygon, a circle, an ellipse, etc. other than a square. In addition, the insulating patterns SP are not limited to having the same shape as each other.

[0136] On a plane, at least a plurality of portions of the plurality of protruding patterns TP may respectively overlap with the plurality of insulating patterns SP. In the present embodiment, the plurality of insulating patterns SP may respectively overlap with the plurality of protruding patterns TP. That is, the plurality of protruding patterns TP may be respectively arranged corresponding to the plurality of insulating patterns SP. In the present embodiment, the plurality of protruding patterns TP may each overlap with the corresponding insulating pattern SP on a plane. The plurality of protruding patterns TP may each be disposed inside the corresponding insulating pattern SP on a plane. That is, in a plan view, the protruding pattern TP may have a size or area equal to or smaller than that of the corresponding insulating pattern SP so as to be disposed inside the corresponding insulating pattern SP. The corresponding protruding pattern TP may be spaced apart from the outer edge of the corresponding insulating pattern SP in a plan view, but is not limited thereto. The whole of the protruding conductive pattern (e.g., the protruding pattern TP) of the second conductive pattern CL2 may overlap with the insulating pattern SP.

[0137] Referring to Figures 7B to 8C , the end portion DL-E may be disposed on the first insulating layer 10. The end portion DL-E may be disposed on the same layer as the layer on which the gate G shown in Figure 5 is disposed (or the same layer as the layer in which Figure 5in the same layer as the layer of the gate G shown in). The end portion DL-E can be formed by the same process as the process of the gate G. The end portion DL-E can include the same material as the material of the gate G.

[0138] However, the position of the end portion DL-E is not limited thereto. The end portion DL-E can be disposed on the same layer as the layer on which the upper electrode UE shown in Figure 5 is disposed or in the same layer as the layer in which the upper electrode UE shown in Figure 5 is disposed, includes the same material as the material of the upper electrode UE, and has the same stacking structure as the stacking structure of the upper electrode UE. Some of the plurality of signal lines can be formed by the same process as the process of forming the gate G (see Figure 5 ), and others can be formed by the same process as the process of forming the upper electrode UE (see Figure 5 ).

[0139] The data line DL can be disposed on one layer and have an integrated form, but the embodiments of the present disclosure are not limited thereto. One data line DL can include a plurality of portions disposed on (or in) different layers from each other. For example, the line portion DL-S (see Figure 7A ) can include at least two portions.

[0140] The first conductive pattern CL1 can be disposed on the fourth insulating layer 40. The first conductive pattern CL1 can be connected to the end portion DL-E through the contact hole OP-C passing through the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. That is, the first conductive pattern CL1 can be in contact with the end portion DL-E through the contact hole OP-C. The second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 can be formed by the same process as the process of forming the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 of the display region DP-DA shown in Figure 4 .

[0141] In this specification, the set of insulating layers disposed between the end portion DL-E and the first conductive pattern CL1 can be defined as the pad insulating layer IL-P. In this embodiment, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40 can be defined as the pad insulating layer IL-P. The stacking structure of the pad insulating layer IL-P can be changed according to the stacking structure of the circuit element layer DP-CL. In the embodiment, the contact hole OP-C can be defined in an insulating layer whose number is greater than or less than the number of the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40.

[0142] The first conductive pattern CL1 and the end portion DL-E can be separated from each other by the pad insulating layer IL-P (for example, the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40) disposed therebetween.

[0143] The second conductive pattern CL2 may be disposed on the first conductive pattern CL1. A region of the second conductive pattern CL2 that does not overlap with the insulating pattern SP may be in contact with the first conductive pattern CL1. That is, in a plan view, a portion of the second conductive pattern CL2 adjacent to (e.g., non-overlapping with) the insulating pattern SP may be in contact with the first conductive pattern CL1.

[0144] In an embodiment, the first conductive pattern CL1 may be formed by the same process as the process of forming the first connection electrode CNE1 described with reference to Figure 5 previously, and the second conductive pattern CL2 may be formed by the same process as the process of forming the second connection electrode CNE2 described with reference to Figure 5 previously. The first conductive pattern CL1 may include the same material as the material of the first connection electrode CNE1 (see Figure 5 ), and the second conductive pattern CL2 may include the same material as the material of the second connection electrode CNE2 (see Figure 5 ), such as being in the same layer respectively.

[0145] Figure 7A and Figure 7B An embodiment in which the first conductive pattern CL1 is disposed on the fourth insulating layer 40 is exemplarily shown. According to an embodiment of the present disclosure, the first conductive pattern CL1 may be disposed on the third insulating layer 30, and in this case, the fourth insulating layer 40 may not be disposed in one or more of the first pad region PA1 and the second pad region PA2 (e.g., may be omitted from the corresponding pad region). However, the embodiments of the present disclosure are not limited thereto, and combinations of connection electrodes formed by the same process as the process of forming the first conductive pattern CL1 and the second conductive pattern CL2 may be variously selected according to the stacking structure of the circuit element layer DP-CL, as long as the first conductive pattern CL1 and the second conductive pattern CL2 disposed on different layers (or in different layers) are provided.

[0146] An embodiment in which the second conductive pattern CL2 has a larger planar area than the planar area of the first conductive pattern CL1 is exemplarily shown. The second conductive pattern CL2 extends farther than the edge of the first conductive pattern CL1, and the second conductive pattern CL2 covers the edge of the first conductive pattern CL1, but the embodiments of the present disclosure are not limited thereto. The second conductive pattern CL2 may have a planar area substantially the same as the planar area of the first conductive pattern CL1, and the edge of the second conductive pattern CL2 may be substantially aligned with the edge of the first conductive pattern CL1 in the thickness direction. Here, the outer surfaces of the first conductive pattern CL1 and the second conductive pattern CL2 may be aligned with each other, such as being coplanar with each other.

[0147] A portion of the second conductive pattern CL2 may include an overlapping portion that overlaps with the insulating pattern SP on a plane. The insulating pattern SP may be disposed between the first conductive pattern CL1 and the second conductive pattern CL2 in a cross-section (e.g., in the thickness direction). The insulating pattern SP may be disposed on the first conductive pattern CL1 and covered by the second conductive pattern CL2. The second conductive pattern CL2 may cover the upper surface U-SP and the side surface S-SP of the insulating pattern SP. In this specification, the lower surface D-SP of the insulating pattern SP is defined as the surface in contact with the first conductive pattern CL1, and the upper surface U-SP of the insulating pattern SP is defined as the surface opposite to the lower surface D-SP and in contact with the second conductive pattern CL2.

[0148] The insulating pattern SP may have a trapezoidal shape in a cross-section. The insulating pattern SP may have a side surface S-SP with a slope, and the slope formed by the side surface S-SP with respect to the lower surface D-SP may form an acute angle. However, the embodiments of the present disclosure are not limited thereto, and the insulating pattern SP may have a rectangular shape in a cross-section, or may also have an inverted trapezoidal shape.

[0149] The insulating pattern SP may include a polymer. The insulating pattern SP may include a thermosetting polymer. However, the embodiments of the present disclosure are not limited thereto, and the insulating pattern SP may include a thermoplastic polymer.

[0150] In an embodiment, the insulating pattern SP may be formed by the same process as the process of forming the fifth insulating layer 50 (see Figure 5 ) such that the insulating pattern SP and the fifth insulating layer 50 are in the same layer (e.g., the same material layer) with each other. Therefore, forming the insulating pattern SP may not require an additional process. However, the embodiments of the present disclosure are not limited thereto, and the combination of connection electrodes formed by the same process as the process of forming the first conductive pattern CL1 and the second conductive pattern CL2 may be variously selected according to the stacking structure of the circuit element layer DP-CL, and thus, the insulating layer formed by the same process as the process of forming the insulating pattern SP may also be variously selected.

[0151] The portion of the second conductive pattern CL2 covering the insulating pattern SP may protrude much more in the third direction DR3 than another portion (or the remaining portion) of the second conductive pattern CL2 from the first conductive pattern CL1 (or arranged relative to the first conductive pattern CL1). The protruding portion of the second conductive pattern CL2 may be referred to as the protruding portion CL2-T. The second conductive pattern CL2 may be in contact with the upper surface of the first conductive pattern CL1 in a region that does not overlap with the insulating pattern SP, the side surface S-SP of the insulating pattern SP, and the upper surface U-SP of the insulating pattern SP. That is, the protruding portion CL2-T may correspond to or be defined as the portion of the second conductive pattern CL2 that is in contact with the side surface S-SP and the upper surface U-SP of the insulating pattern SP.

[0152] The protruding pattern TP may be arranged on the second conductive pattern CL2. More specifically, the protruding pattern TP may be arranged on the protruding portion CL2-T of the second conductive pattern CL2. The protruding pattern TP may be arranged on the portion of the protruding portion CL2-T covering the upper surface U-SP of the insulating pattern SP. Here, within the signal pad DP-PD, the second conductive pattern CL2 includes the protruding portion CL2-T extending along the insulating pattern SP and protruding from the first conductive pattern CL1, and the protruding pattern TP protrudes from the protruding portion CL2-T of the second conductive pattern CL2. Refer to Figure 7C , for example, the first conductive pattern CL1 extends farther than the side surface S-SP of the insulating pattern SP to define the upper surface of the first conductive pattern CL1 exposed outside the insulating pattern SP. The second conductive pattern CL2 may further include the protruding portion CL2-T in contact with the side surface S-SP and the upper surface U-SP of the insulating pattern SP and an extending portion extending from the protruding portion CL2-T and extending farther than the first conductive pattern CL1 from the insulating pattern SP, and the extending portion is in contact with the upper surface of the first conductive pattern CL1.

[0153] The protruding pattern TP may include a metallic material. The protruding pattern TP may be formed by reverse offset printing, which will be described later. The protruding pattern TP may be formed by sintering a printed pattern including metallic ink. The metallic ink may include metal nanoparticles. Thus, the protruding pattern TP may include metal nanoparticles. This will be described in detail later.

[0154] The protruding pattern TP may include an upper surface U-TP, a lower surface D-TP opposite to the upper surface U-TP, and a side surface S-TP connecting the upper surface U-TP to the lower surface D-TP. In this specification, the lower surface D-TP of the protruding pattern TP is defined as the surface in contact with the second conductive pattern CL2, and the upper surface U-TP of the protruding pattern TP is defined as the surface opposite to the lower surface D-TP and facing the electronic component.

[0155] As Figure 7C shown, according to an embodiment of the present disclosure, the protruding pattern TP may have a trapezoidal shape in cross-section. The upper surface U-TP of the protruding pattern TP may have a width smaller than the width of the lower surface D-TP of the protruding pattern TP, and the inclination of the side surface S-TP of the protruding pattern TP with respect to the lower surface D-TP may form an acute angle. However, the shape of the protruding pattern TP is not limited thereto.

[0156] As Figure 8A shown, according to an embodiment of the present disclosure, the protruding pattern TPa may also have an inverted trapezoidal shape in cross-section. The upper surface U-TPa of the protruding pattern TPa may have a width larger than the width of the lower surface D-TPa of the protruding pattern TPa, and the inclination of the side surface S-TPa of the protruding pattern TPa with respect to the lower surface D-TPa may form an obtuse angle.

[0157] Alternatively, as Figure 8B shown, according to an embodiment of the present disclosure, the protruding pattern TPb may also have a linear shape such as a rectangular shape or a square shape in cross-section. The upper surface U-TPb of the protruding pattern TPb may have a width substantially the same as the width of the lower surface D-TPb of the protruding pattern TPb, and the inclination of the side surface S-TPb of the protruding pattern TPb with respect to the lower surface D-TPb may form a right angle.

[0158] Referring to Figure 7C , Figure 8A and Figure 8B , a portion of the uppermost surface of the second conductive pattern CL2 extends outward from the corresponding conductive protrusion (e.g., the protruding pattern TP) to be exposed outside the conductive protrusion. That is, the side surfaces of the conductive protrusion and the second conductive pattern CL2 may not be aligned.

[0159] Alternatively, as Figure 8C shown, according to an embodiment of the present disclosure, a first width w-TPc defined at the lower surface D-TPc of the protruding pattern TPc may be substantially the same as a second width w-CL2u of a protruding portion CL2-T of the second conductive pattern CL2 that covers the upper surface U-SP of the insulating pattern SP to form the uppermost surface. The side surface S-TPc of the protruding pattern TPc may be substantially aligned with an outer surface of a portion of the side surface S-SP of the second conductive pattern CL2 that covers the insulating pattern SP. Here, the side surface S-TPc and the outer surface may be coplanar with each other, but are not limited thereto.

[0160] The shape of the protruding pattern TPc is not limited to any one embodiment of the present disclosure and may be changed according to the conditions of the printing process of the protruding pattern and the ink (e.g., material, content of the material, etc.) used in the printing process. Although Figure 8CThe protruding pattern TPc therein has a trapezoidal shape in cross section, but the cross-sectional shape can be variously changed, such as being changed to an inverted trapezoid (see Figure 8A ), a linear shape (see Figure 8B ), and similar shapes.

[0161] Figure 9A Exemplarily shown is a driving chip DC as an electronic component of a display device DD. Figure 9A Shown is a chip bump electrode DC-BP (see Figure 6 ) of the driving chip DC, and a first bump BP1 among them contacts a protruding pattern TP of a pad electrode (e.g., such as a signal pad DP-PD). In an embodiment, for example, in combination with Figure 2A , Figure 4 , Figure 6 and Figure 7A , the display device DD includes a display module DM (or a display panel DP), the display module DM includes pixels PX, signal lines (such as data lines DL) electrically connected to the pixels PX and defining an end portion DL-E farthest from the pixels PX, and signal pads DP-PD electrically connected to the signal lines and providing electrical signals to the display module DM from an electronic component outside the display module DM. The signal pads DP-PD include a first conductive pattern CL1, a second conductive pattern CL2, an insulating pattern SP, and a protruding conductive pattern (e.g., the protruding pattern TP). The signal pads DP-PD are electrically connected to the end portion DL-E of the signal line at the first conductive pattern CL1. The second conductive pattern CL2 faces the first conductive pattern CL1 and is electrically connected to the first conductive pattern CL1. The insulating pattern SP is between the first conductive pattern CL1 and the second conductive pattern CL2 facing each other. The signal pads DP-PD are electrically connected to the electronic component at the protruding conductive pattern. The protruding conductive pattern protrudes from the second conductive pattern CL2 and overlaps the insulating pattern SP.

[0162] Due to the bonding pressure during the method of electrically connecting an electronic component (e.g., the driving chip DC) to the display panel DP, the first bump BP1 of the driving chip DC can pass through the thickness portion of the first adhesive layer CF1 to contact the protruding pattern TP. The finally formed first adhesive layer CF1 can surround the outer surfaces of the protruding pattern TP and the first bump BP1 to promote a stable physical connection therebetween. The first adhesive layer CF1 before hardening can have a viscosity lower than that of an anisotropic conductive film. On the other hand, a conventional anisotropic conductive film has a relatively high viscosity to maintain the alignment of conductive elements (e.g., balls or other shapes) therein.

[0163] Since the protruding pattern TP protrudes toward the first bump BP1, the protruding pattern TP and the first bump BP1 can be brought into closer contact with each other, and the contact resistance (e.g., resistance) therebetween can be reduced. Since the conventional conductive balls are omitted, even if the signal pads DP-PD are dense, short-circuit defects caused by the conductive balls can be reduced. Since the accessibility between the signal pads DP-PD and the first bump BP1 is improved to increase the electrical contact therebetween, the bonding pressure for bringing the signal pads DP-PD and the first bump BP1 into contact with each other can be reduced. As the bonding pressure is reduced, physical damage to the display panel DP or the electronic component that occurs during the bonding process can be reduced.

[0164] According to an embodiment of the present disclosure, the signal pads DP-PD may include an insulating pattern SP and a protruding pattern TP, and the protruding pattern TP may be disposed on the insulating pattern SP as a conductive contact and have a shape protruding from the insulating pattern SP. When the protruding pattern TP and the first bump BP1 can be brought into contact with each other, the insulating pattern SP can provide high resilience against the bonding pressure or shock absorption of the bonding pressure, and thereby, the protruding pattern TP and the bump electrode (e.g., the first bump BP1) can be brought into close contact with each other.

[0165] In addition, since the protruding pattern TP that physically contacts the bump electrode is disposed on the insulating pattern SP, even if the shape of the insulating pattern SP is deformed due to the bonding pressure during the bonding process, the component that directly contacts the bump electrode may have little deformation or no deformation. That is, even if the insulating pattern SP is deformed due to the bonding pressure, the protruding pattern TP can have a stable electrical connection with the bump electrode, and the bonding resistance between the protruding pattern TP and the bump electrode can be reduced. Therefore, it is possible to provide a display device DD having improved bonding reliability.

[0166] Referring to Figure 9B , according to an embodiment, the second conductive pattern CL2 may include a first layer L1, a second layer L2, and a third layer L3 stacked in sequence. The first layer L1 may cover the lower side of the second layer L2, and the third layer L3 may cover the upper side of the second layer L2. The second layer L2 may be thicker than the first layer L1 and the third layer L3. The second layer L2 may include a material having a higher conductivity than that of each of the first layer L1 and the third layer L3. The first layer L1 and the third layer L3 may include the same material, and the second layer L2 may include a material different from the materials of the first layer L1 and the third layer L3. For example, the first layer L1 and the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In an embodiment, an oxide film OXL may be further formed on the interface of the third layer L3 to cover the third layer L3. The oxide film OXL formed on the interface of the third layer L3 may include titanium oxide (TiO x)。The thickness portion at the third layer L3 and the thickness portion at the oxide film OXL can be considered together as the third layer L3 within the second conductive pattern CL2.

[0167] In the present embodiment, in the bonding process of the method for electrically connecting an electronic component to a display panel DP, as bonding pressure is applied to the protruding pattern TP and the second conductive pattern CL2, some of the metal nanoparticles NP in the protruding pattern TP can remove a portion of the oxide film OXL. In addition, others of the metal nanoparticles NP in the protruding pattern TP can also remove a portion of the third layer L3. That is, the material of the protruding pattern TP can penetrate the oxide film OXL and / or the third layer L3. Accordingly, a portion of the second layer L2 of the second conductive pattern CL2 can be exposed to the outside of the third layer L3 and the oxide film OXL at the corresponding recess defined therein. That is, the protruding pattern TP can include a portion that is in direct contact with the second layer L2 of the second conductive pattern CL2 and the third layer L3 of the second conductive pattern CL2.

[0168] The electrical contact resistance in the case where the protruding pattern TP is in contact with the oxide film OXL and / or the third layer L3 can be higher than the electrical contact resistance in the case where the protruding pattern TP is in contact with the second layer L2. Additionally, in the case where the protruding pattern TP is in contact with the second layer L2 in order to have a relatively low contact resistance, the protruding pattern TP and the second conductive pattern CL2 can have a more stable connection with each other. According to the present embodiment, since the protruding pattern TP is formed to include a portion in direct contact with the second layer L2, the contact resistance between the protruding pattern TP and the second conductive pattern CL2 can be reduced, thereby forming a signal pad DP-PD in which components are physically and electrically stably connected to each other.

[0169] Figures 10A to 10D is a plan view schematically showing a first pad region PA1 and / or a second pad region PA2 according to an embodiment of the present disclosure. Components that are the same / similar to the components described with reference to Figures 1 to 9B are denoted by the same / similar reference numerals or symbols, and repeated descriptions will be omitted and the differences will be mainly described.

[0170] Referring to Figures 10A to 10D , in the present embodiment, the number of protruding patterns TP arranged on the same insulating pattern SP can be set in various ways. The number of insulating patterns SP arranged between adjacent contact holes OP-C within the signal pad DP-PD can also be set in various ways. The number of contact holes OP-C arranged to overlap with the end portion DL-E can also be set in various ways.

[0171] As Figures 10A to 10DAs shown, an insulating pattern SP may be disposed between adjacent contact holes OP-C. The insulating pattern SP may have a shape that extends longitudinally in a first direction DR1. That is, the insulating pattern SP may have a length dimension in the first direction DR1 that is larger than the width dimension in a second direction DR2. The insulating pattern SP may have a rectangular shape in a plane. A plurality of protruding patterns TP may be disposed on one insulating pattern SP. The plurality of protruding patterns TP may be arranged on one insulating pattern SP, spaced apart from each other along the first direction DR1.

[0172] Figure 10A and Figure 10C Exemplarily, three contact holes OP-C and two insulating patterns SP are shown disposed on a single end portion DL-E.

[0173] Figure 10B and Figure 10D Exemplarily, two contact holes OP-C and a single insulating pattern SP between the two contact holes OP-C are shown disposed on the end portion DL-E. The two contact holes OP-C may be respectively disposed on one side (or upper side) of the end portion DL-E in the first direction DR1 and on the other side (or lower side) of the end portion DL-E in the first direction DR1.

[0174] Furthermore, in the present embodiment, the distance between the protruding patterns TP can be set in various ways.

[0175] Figure 10A and Figure 10B Adjacent protruding patterns TP are shown disposed separated from each other by a first distance d1. Figure 10A Exemplarily, for the same signal pad DP-PD, three protruding patterns TP are shown disposed on one insulating pattern SP such that a total of six protruding patterns TP are disposed on two insulating patterns SP. Figure 10B Exemplarily, for the same signal pad DP-PD, six protruding patterns TP are shown disposed on one insulating pattern SP.

[0176] Figure 10C and Figure 10D Adjacent protruding patterns TP are shown disposed separated from each other by a second distance d2. The second distance d2 may be less than the first distance d1. That is, Figure 10C and Figure 10D Protruding patterns TP are shown arranged at a narrower interval than Figure 10A and Figure 10B the protruding patterns TP shown in Figure 10C Exemplarily, within the same signal pad DP-PD, five protruding patterns TP are shown disposed on one insulating pattern SP such that a total of ten protruding patterns TP are disposed on two insulating patterns SP. Figure 10DExemplarily, eleven protruding patterns TP are arranged on an insulating pattern SP within the same signal pad DP-PD.

[0177] The number of contact holes OP-C, insulating patterns SP, and protruding patterns TP is not limited to Figures 10A to 10D the number shown in, and can be set in various ways within a single signal pad among multiple signal pads.

[0178] Figure 11A and Figure 11B are plan views schematically showing a first pad region PA1 and / or a second pad region PA2 according to an embodiment of the present disclosure. Components identical / similar to those described with reference to Figures 1 to 9B are denoted by the same / similar reference numerals or symbols, and repeated descriptions will be omitted and the differences will be mainly described.

[0179] Referring to Figure 11A , in the present embodiment, multiple protruding patterns TP can respectively overlap multiple insulating patterns SP, and the number of insulating patterns SP arranged between adjacent contact holes OP-C can be set in various ways.

[0180] Figure 11A Exemplarily, two insulating patterns SP and two protruding patterns TP respectively overlapping the two insulating patterns SP are arranged between adjacent contact holes OP-C, but the embodiments of the present disclosure are not limited thereto. Between adjacent contact holes OP-C, one insulating pattern SP and one protruding pattern TP can be arranged, and four or more insulating patterns SP and four or more protruding patterns TP can also be arranged. Here, the width w-SP of the insulating pattern SP in the second direction DR2 (e.g., referring to Figure 11B ) can be smaller than the width w-DLE of the end portion DL-E in the second direction DR2 (e.g., referring to Figure 11B ).

[0181] Referring to Figure 11B , in the present embodiment, multiple protruding patterns TP can be arranged to respectively overlap multiple insulating patterns SP, and the planar size of the insulating pattern SP can be set in various ways. That is, the size of the insulating pattern SP in the first direction DR1 and the size of the insulating pattern SP in the second direction DR2 can be set in various ways. As shown in Figure 11B , in the embodiment, the width w-SP of the insulating pattern SP in the second direction DR2 can be substantially the same as the width w-DLE of the end portion DL-E in the second direction DR2.

[0182] Hereinafter, a method of manufacturing (or providing) a display device DD according to an embodiment will be described with reference to the accompanying drawings. To describe the manufacturing method of the display device DD according to the embodiment, the content that duplicates the above-described display device DD according to the embodiment will be omitted.

[0183] Figures 12A to 12G is a cross-sectional view showing a process or operation of a method of manufacturing a display device DD according to an embodiment of the present disclosure.

[0184] According to an embodiment of the present disclosure, a method of manufacturing a display device DD may include: providing a preliminary signal pad DP-PDI including a first conductive pattern CL1 connected to a signal line (such as a data line DL, etc.), a second conductive pattern CL2 disposed on the first conductive pattern CL1, and an insulating pattern SP disposed between the first conductive pattern CL1 and the second conductive pattern CL2; and forming a protruding pattern TP on the preliminary signal pad DP-PDI to form a signal pad DP-PD. In an embodiment, forming the protruding pattern TP may be performed by an offset printing process. That is, a method of providing the signal pad DP-PD of the display device DD includes providing a preliminary signal pad DP-PDI and providing a protruding conductive pattern on the preliminary signal pad DP-PDI to form the signal pad DP-PD of the display module DM, at which the display module DM of the display device DD is connected to an electronic component of the display device DD.

[0185] Refer to Figures 12A to 12G , a method of manufacturing or providing a display device DD according to an embodiment of the present disclosure may include providing a preliminary signal pad DP-PDI and forming (or providing) a protruding pattern TP to form a signal pad DP-PD, at which the display panel DP is connected to an electronic component of the display device DD.

[0186] Refer to Figure 12A , the preliminary signal pad DP-PDI may include a first conductive pattern CL1, a second conductive pattern CL2 disposed on the first conductive pattern CL1, and an insulating pattern SP disposed between the first conductive pattern CL1 and the second conductive pattern CL2. Figure 12A Schematically shows that the preliminary signal pad DP-PDI is provided on the base layer BL, but a barrier layer BRL, a buffer layer BFL, a first insulating layer 10, a signal line (e.g., a data line DL), and a pad insulating layer IL-P as shown in Figure 5 , Figure 7B and Figure 7C may be further disposed between the base layer BL and the preliminary signal pad DP-PDI. The first conductive pattern CL1 may be connected to a signal line (e.g., a data line DL).

[0187] Refer toFigures 12B to 12G Providing a protruding pattern TP relative to a preliminary signal pad DP-PDI can be performed by an offset printing process.

[0188] Referring to Figure 12B , forming a protruding pattern TP according to an embodiment of the present disclosure (see Figure 12G ) can include applying a metal ink MI to a pad BK.

[0189] The pad BK can be wound around a roller RL having a cylindrical shape. A coater device CT can be used as a coater for applying the metal ink MI to a target object such as the pad BK. The roller RL can rotate, and at the same time, the metal ink MI can be applied to the entire surface of the pad BK through the coater device CT. In an embodiment, applying the metal ink MI can be performed by slit coating.

[0190] Figure 12C is an enlarged cross-sectional view showing Figure 12B the region YY'. Referring to Figure 12C , the conductive material of the metal ink MI can include a solvent SV and metal nanoparticles NP dispersed in the solvent SV. Here, providing a protruding conductive pattern can include providing a layer of the metal ink MI including the solvent SV and the metal nanoparticles NP onto the pad BK that is movable relative to the preliminary signal pad DP-PDI.

[0191] In an embodiment, the metal nanoparticles NP can include copper (Cu) or silver (Ag). However, embodiments of the present disclosure are not limited thereto, and the metal ink MI can include various types of conductive or metal nanoparticles NP as long as they are uniformly dispersed in the solvent SV in the form of nanoparticles and have conductivity in a sintered state.

[0192] In an embodiment, for the solvent SV, water, methanol, ethanol, alcohols, glycols, acetates, ethers, ketones, hydrocarbons, aromatic and halogen-substituted solvents, dimethyl sulfoxide solvents, their combinations, or the like can be used, but embodiments of the present disclosure are not limited thereto.

[0193] The metal ink MI can further include a binder. The binder may not reduce the densification between the metal nanoparticles NP. Alternatively, the metal ink MI can further include a dispersant. The dispersant can improve the dispersion stability of the metal ink MI. Alternatively, the metal ink MI can further include a surfactant or a viscosity control agent.

[0194] Referring to Figure 12D , providing a protruding pattern TP according to an embodiment of the present disclosure (see Figure 12G ) can include transferring a portion of the metal ink MI applied to the pad BK to a printed board CC as a receiving pattern.

[0195] The metal ink MI applied to the gasket BK can be transferred to the printing plate CC by contacting the printing plate CC. A concave pattern RP can be formed or defined between the solid portions of the printing plate CC, and the shape of the concave pattern RP can correspond to the protruding pattern TP of the display panel DP to be formed later (see Figure 12G ).

[0196] Among the metal ink MI applied to the gasket BK, the metal ink MI in contact with the printing plate CC can remain on the printing plate CC and can be removed from the gasket BK. The metal ink MI remaining on the printing plate CC can be referred to as the removed pattern MIrm. Among the metal ink MI applied to the gasket BK, due to the separation of the metal ink MI through the concave pattern RP, the metal ink MI not in contact with the printing plate CC can remain on the gasket BK as a protrusion of the metal ink MI. Therefore, a printed pattern MIpp as a protrusion of the metal ink MI having a shape corresponding to the protruding pattern TP to be formed later (see Figure 12G ) can be provided on the gasket BK and can be rotatable with the gasket BK around a roller (e.g., roller RL).

[0197] Referring to Figure 12E , forming the protruding pattern TP (see Figure 12G ) according to an embodiment of the present disclosure can include transferring the printed pattern MIpp as a protrusion of the metal ink MI from the gasket BK on the roller RL (e.g., at the preliminary signal pad DP-PDI) to the stacked structure of the preliminary display panel.

[0198] In this embodiment, the printed pattern MIpp can be transferred to the preliminary signal pad DP-PDI. The preliminary signal pad DP-PDI corresponds to the preliminary signal pad DP-PDI provided when the preliminary signal pad DP-PD was previously referred to Figure 12A . More specifically, the printed pattern MIpp can be transferred to the portion of the second conductive pattern CL2 that protrudes by being disposed on the insulating pattern SP (i.e., the protruding portion CL2-T (see Figure 7C )). The printed pattern MIpp can overlap with the insulating pattern SP described in the above various embodiments.

[0199] Figure 12E Exemplarily, a plurality of printed patterns MIpp are shown formed on one of the plurality of insulating patterns SP, but a plurality of insulating patterns SP can also be provided such that the plurality of printed patterns MIpp are arranged to respectively correspond to the plurality of insulating patterns SP.

[0200] Figure 12DExemplarily, it is shown that since the removal pattern MIrm is formed to have a trapezoidal shape in cross-section, the printed pattern MIpp is formed to have an inverted trapezoidal shape in cross-section. However, embodiments of the present disclosure are not limited thereto, and the removal pattern MIrm may also be formed to have an inverted trapezoidal or rectangular shape in cross-section, and correspondingly, the printed pattern MIpp may also be formed to have a trapezoidal or rectangular shape in cross-section.

[0201] Referring to Figures 12F to 12G , forming a protruding pattern TP according to an embodiment of the present disclosure may include sintering a printed pattern MIpp. The printed pattern MIpp according to this embodiment may be formed by transferring metal ink MI patterned through a printing plate CC (see Figure 12D ) onto a second conductive pattern CL2.

[0202] In this embodiment, heat or light may be used to sinter the printed pattern MIpp on a preliminary signal pad DP-PDI having an unsintered printed pattern (e.g., heat or light may be used to sinter the unsintered printed pattern MIpp on the preliminary signal pad DP-PDI), and a protruding pattern TP may be formed through the sintered printed pattern MIpp. By sintering the printed pattern MIpp, the solvent SV (see Figure 12C ) included in the printed pattern MIpp may be dried out, and the metal nanoparticles NP (see Figure 12C ) may be sintered. Figure 12F Exemplarily, it is shown that an optical sintering device PCS is used to sinter the printed pattern MIpp. Infrared rays (IR) or ultraviolet rays (UV) may be used for the optical treatment of the unsintered printed pattern MIpp. That is, providing a protruding conductive pattern may include: after providing a layer of metal ink MI, transferring a part of the layer of metal ink MI from a pad BK to a carrier, which provides a printed pattern MIpp corresponding to the remaining part of the layer of metal ink MI on the pad BK; transferring the printed pattern MIpp from the pad BK to a second conductive pattern CL2 of a preliminary signal pad DP-PDI, and the printed pattern MIpp overlaps with an insulating pattern SP of the preliminary signal pad DP-PDI; and sintering the printed pattern MIpp on the second conductive pattern CL2 and overlapping with the insulating pattern SP of the preliminary signal pad DP-PDI to form a protruding conductive pattern of the signal pad DP-PD.

[0203] By Figures 12A to 12G The signal pad DP-PD formed by the preliminary signal pad DP-PDI having the printed pattern MIpp in the operations in may have a planar shape similar to any one of the signal pads DP-PD in Figures 10A to 10D . However, embodiments of the present disclosure are not limited thereto, and in Figure 12EIn the transfer of the printed pattern MIpp, when each of the printed patterns MIpp is disposed on the corresponding insulating pattern SP, the signal pads DP-PD can be formed to have a planar shape similar to the planar shape in Figure 7A , Figure 11A or Figure 11B .

[0204] According to the present embodiment, a display device DD including signal pads DP-PD including an insulating pattern SP and a protruding pattern TP disposed on the insulating pattern SP can be manufactured or provided (see Figure 1 ). In the bonding process, due to the high resilience of the insulating pattern SP as a shock-absorbing member, the protruding pattern TP and the bump electrode of the electronic component can be in close contact with each other. At the same time, due to the influence of the deformation of the insulating pattern SP in the bonding process, the protruding pattern TP can have reduced deformation. Therefore, the protruding pattern TP and the bump electrode can have a stable electrical connection therebetween and have a reduced bonding resistance therebetween. Therefore, according to the present embodiment, it is possible to manufacture a display device DD including signal pads DP-PD having improved bonding reliability and electrical connection therebetween (see Figure 1 ).

[0205] Figure 13A and Figure 13B are cross-sectional views showing a method of manufacturing or providing a display device DD according to an embodiment of the present disclosure. Components that are the same / similar to the components described with reference to Figures 12A to 12G are denoted by the same / similar reference numerals or symbols, and repeated descriptions will be omitted and the differences will be mainly described. In the present embodiment, Figure 13A shows an operation that can be performed after applying the metal ink MI to the gasket BK previously described with reference to Figure 12B .

[0206] Referring to Figure 13A , the formation of the protruding pattern TP according to an embodiment of the present disclosure (see Figure 7A ) can include, after applying the metal ink MI to the gasket BK, directly transferring a part of the metal ink MI from the gasket BK to the second conductive pattern CL2.

[0207] That is, in the present embodiment, as in Figures 12D to 12GDifferent from the embodiments shown, the intermediate transfer of the metal ink MI applied to the gasket BK to a carrier such as the printing plate CC can be omitted, and the metal ink MI applied to the gasket BK can be directly transferred to the second conductive pattern CL2. In this embodiment, the insulating pattern SP can effectively serve as the printing plate CC. Therefore, the direct transfer of the protrusions of the metal ink MI can have the advantage of simplifying the process of providing the display panel DP. As used herein, a type of transfer surface useful in the present disclosure is known in the art as a printing plate (cliché). Other types of transfer surfaces can also be easily identified and used, such as carriers that provide various transfer surfaces.

[0208] The metal ink MI applied to the gasket BK can come into contact with the second conductive pattern CL2 protruding due to the insulating pattern SP, and thus can be transferred to the second conductive pattern CL2. A portion of the metal ink MI initially applied to the gasket BK in a single layer can come into contact with the second conductive pattern CL2 protruding due to the insulating pattern SP, and can be removed from the gasket BK by the adhesion force with the material of the second conductive pattern CL2, leaving a transferred portion of the layer of the metal ink MI on the second conductive pattern CL2.

[0209] In this embodiment, the metal ink MI transferred to the second conductive pattern CL2 can form a printed pattern MIpp' having a shape corresponding to the protruding pattern TP (see Figure 7A ). A plurality of printed patterns MIpp' can be arranged to correspond to the plurality of insulating patterns SP respectively. That is, the plurality of printed patterns MIpp' can be arranged to overlap the plurality of insulating patterns SP respectively. In an embodiment, the side surfaces of each of the plurality of printed patterns MIpp' can be substantially aligned with the outer surfaces of the portions of the second conductive pattern CL2 covering the corresponding insulating patterns SP.

[0210] Figure 13A Exemplarily, the printed pattern MIpp' is shown to be trapezoidal in cross-section. However, the embodiments of the present disclosure are not limited thereto, and the printed pattern MIpp' can also be formed in an inverted trapezoidal or rectangular shape.

[0211] Thereafter, referring to Figure 13B , according to an embodiment of the present disclosure, the formation of the protruding pattern TP (see Figure 7A) may include sintering an unsintered printed pattern MIpp'. In the present embodiment, the printed pattern MIpp' may be formed by directly transferring the metal ink MI initially applied to the gasket BK onto the second conductive pattern CL2 and patterning it while transferring (such as by the bonding force and / or adhesive force between the material of the metal ink MI and the material of the second conductive pattern CL2). By sintering the transferred printed pattern MIpp', a protruding pattern TP can be formed from the sintered transferred printed pattern MIpp' (see Figure 7A ). The description of sintering the printed pattern MIpp' will be equivalently applied to the description previously referred to Figures 12F to 12G . That is, providing a protruding conductive pattern may include: after providing a layer of the metal ink MI, directly transferring a part of the layer of the metal ink MI from the gasket BK onto the second conductive pattern CL2 of the preliminary signal pad DP-PDI, which provides a printed pattern MIpp' of the layer of the metal ink MI on the preliminary signal pad DP-PDI, and the printed pattern MIpp' overlaps with the insulating pattern SP of the preliminary signal pad DP-PDI; and sintering the printed pattern MIpp' on the second conductive pattern CL2 and overlapping with the insulating pattern SP of the preliminary signal pad DP-PDI to form a protruding conductive pattern of the signal pad DP-PD.

[0212] By Figure 12A , Figure 13A and Figure 13B The variously formed or provided signal pads DP-PD shown in (see Figure 7A ) may have a cross-sectional shape similar to that shown in Figure 8C . By Figure 12A , Figure 13A and Figure 13B The signal pads DP-PD formed by the operations shown in (see Figure 7A ) may have a planar shape similar to that shown in Figure 8A , Figure 11A or Figure 11B .

[0213] According to an embodiment of the present disclosure, through the insulating pattern SP in the signal pad DP-PD of the display panel DP, the uppermost conductive pattern (e.g., the protruding pattern TP) of the signal pad DP-PD (e.g., at the second conductive pattern CL2) can protrude toward an electronic component (e.g., a driving chip DC, a circuit board PB, and the like). In the absence of an anisotropic conductive film, the display panel DP can be bonded to the electronic component, thereby reducing electrical short circuit defects caused by conventional conductive balls of a conventional bonding film. As the bonding pressure for electrically connecting the electronic component to the display panel DP at the signal pad DP-PD of the display panel DP is reduced, physical damage to the display panel DP and / or the electronic component that occurs during the bonding process can be reduced.

[0214] According to an embodiment of the present disclosure, the signal pad DP-PD may include a protruding pattern TP disposed on the insulating pattern SP. Through the high resilience of the insulating pattern SP, the protruding pattern TP can be in close contact with the bump electrode of the electronic component. At the same time, the protruding pattern TP and the bump electrode can have a stable electrical connection with each other through physical contact therebetween. It is possible to provide a display device DD having improved bonding reliability and electrical connection between an external component (electronic component) and a pad electrode (e.g., the signal pad DP-PD) of the display panel DP.

[0215] According to an embodiment of the present disclosure, it is possible to manufacture or provide a display device DD including a signal pad DP-PD capable of improving bonding reliability.

[0216] Although embodiments of the present disclosure have been described, it is to be understood that the present disclosure should not be limited to these embodiments, but that various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present disclosure as claimed in the appended claims. Therefore, the technical scope of the present disclosure should not be limited to what is described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A display device, characterized in that, The display device includes: A display module, including: Pixels; Signal lines, the signal lines being electrically connected to the pixels and defining end portions farthest from the pixels; and Signal pads, the signal pads being electrically connected to the signal lines, and an electrical signal being provided to the signal pads from electronic components outside the display module, the signal pads including: A first conductive pattern, the signal pad being electrically connected to the end portion of the signal line at the first conductive pattern; A second conductive pattern, the second conductive pattern facing the first conductive pattern and being electrically connected to the first conductive pattern; An insulating pattern, the insulating pattern being between the first conductive pattern and the second conductive pattern facing each other; and A protruding conductive pattern, the signal pad being electrically connected to the electronic components at the protruding conductive pattern, the protruding conductive pattern protruding from the second conductive pattern and overlapping the insulating pattern.

2. The display device according to claim 1, wherein The protruding conductive pattern is made of metal, and The insulating pattern is made of polymer.

3. The display device according to claim 1, wherein Within the signal pad: The second conductive pattern includes a protruding portion extending along the insulating pattern and protruding from the first conductive pattern, and The protruding conductive pattern protrudes from the protruding portion of the second conductive pattern.

4. The display device according to claim 1, wherein The entirety of the protruding conductive pattern of the signal pad overlaps the insulating pattern.

5. The display device according to claim 1, wherein Each of the protruding conductive pattern and the second conductive pattern has a side surface, and The side surface of the protruding conductive pattern is aligned with the side surface of the second conductive pattern.

6. The display device according to claim 1, wherein The protruding conductive pattern includes one of a trapezoidal cross-sectional shape, an inverted trapezoidal cross-sectional shape, and a linear cross-sectional shape.

7. The display device according to claim 1, wherein Within the signal pad, the protruding conductive pattern is provided in plurality, so as to include a plurality of protruding conductive patterns spaced apart from each other along the insulating pattern.

8. The display device according to claim 1, wherein Within the signal pad: The insulating pattern and the protruding conductive pattern are each provided in plurality, such that a plurality of insulating patterns and a plurality of protruding conductive patterns are included, and The plurality of protruding conductive patterns respectively overlap the plurality of insulating patterns.

9. The display device according to claim 1, wherein The display module further includes a pad insulating layer between the first conductive pattern of the signal pad and the end portion of the signal line, and Within the signal pad: A contact hole is defined in the pad insulating layer to expose the end portion of the signal line to the outside of the pad insulating layer and to be spaced apart from the insulating pattern in the direction along the signal pad, and The first conductive pattern contacts the end portion of the signal line through the contact hole defined in the pad insulating layer.

10. The display device according to claim 1, wherein The electronic component includes a bump electrode, and the electronic component is electrically connected to the signal pad of the display module at the bump electrode; and The display device further includes an adhesive layer, which is between the display module and the electronic component, joins the display module to the electronic component, and within the adhesive layer, the protruding conductive pattern contacts the bump electrode to electrically connect the electronic component to the display module.

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