Display panel and display device

Abstract

The utility model provides a display panel and a display device, and belongs to the technical field of display, the display panel comprises a sub-pixel area, a non-sub-pixel area and a driving substrate, the driving substrate comprises a pixel driving circuit, one side of the driving substrate further comprises a light-emitting device located in the sub-pixel area, and the light-emitting device is located in the non-sub-pixel area. Comprising a first electrode, a light-emitting layer and a second electrode which are sequentially arranged in the thickness direction of the driving substrate. The first connecting part is located in the non-sub-pixel area and is in lap joint with the pixel driving circuit; the second connecting part is electrically connected with the first connecting part and the first electrode respectively; wherein the second connecting part comprises a first connecting line and / or a plurality of second connecting lines which are connected in parallel, and the maximum line width of the first connecting line is larger than the maximum line width of the second connecting lines.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] OLED (Organic Light Emitting Diode) display panels have the advantages of self-luminescence, wide viewing angles, wide color gamuts, high contrast ratios, being thin and light, etc., and are widely used in various display products. However, currently, the display panels are prone to defects such as dark spots and thin dark spots. Summary of the Utility Model

[0003] Based on the content of the background art, the present disclosure provides a display panel and a display device.

[0004] In a first aspect of the present disclosure, a display panel is provided, including a sub-pixel region and a non-sub-pixel region, and

[0005] a driving substrate, including a pixel driving circuit, and on one side of the driving substrate, further including:

[0006] a light-emitting device, located in the sub-pixel region, including a first electrode, a light-emitting layer, and a second electrode sequentially arranged in the thickness direction of the driving substrate;

[0007] a first connection part, located in the non-sub-pixel region and overlapping with the pixel driving circuit;

[0008] a second connection part, electrically connected to the first connection part and the first electrode respectively;

[0009] wherein, the second connection part includes a first connection line, and / or a plurality of second connection lines connected in parallel, and the maximum line width of the first connection line is greater than the maximum line width of the second connection lines.

[0010] Exemplarily, the size of the orthographic projection of the second connection part on the driving substrate in a target direction is greater than or equal to 1 / 5 of the size of the orthographic projection of the first electrode on the driving substrate in the target direction;

[0011] wherein, the target direction is orthogonal to the connection direction of the first connection part and the first electrode.

[0012] Exemplarily, the second connection part includes one first connection line, and the ratio of the maximum line width of the first connection line to the size of the first electrode in the line width direction is 0.2 to 1.

[0013] Exemplarily, there is a step difference between the first connection part and the first electrode, wherein the second connection part includes the first connection line or a plurality of the second connection lines at least in the area where the step difference is located.

[0014] Exemplarily, the display panel further includes:

[0015] A planarization layer located on the side of the driving substrate close to the light-emitting device; the positive projection of the planarization layer on the driving substrate covers the positive projection of the first electrode on the driving substrate and has no overlap with the positive projection of the first connection part on the driving substrate, so that there is the step difference between the first electrode and the first connection part;

[0016] Wherein, the positive projection of the first connection line or the plurality of the second connection lines on the driving substrate has an overlap with the positive projection of the planarization layer on the driving substrate.

[0017] Exemplarily, the second connection part includes one first connection line and a plurality of second connection lines;

[0018] Wherein, the plurality of second connection lines are respectively connected to the first connection line and the first electrode; alternatively, the first connection line is respectively connected to the plurality of second connection lines and the first electrode.

[0019] Exemplarily, the second connection part includes a plurality of second connection lines, the second connection line includes a first sub-connection line and a second sub-connection line connected in series in sequence, the second sub-connection line is located in the area where the step difference is located, and the line width of the second sub-connection line is greater than the line width of the first sub-connection line.

[0020] Exemplarily, the second connection part includes one first connection line, the first connection line includes a third sub-connection line connected to the first connection part, and a fourth sub-connection line connected between the third sub-connection line and the first electrode;

[0021] Wherein, the fourth sub-connection line is located in the area where the step difference is located, and the line width of the fourth sub-connection line is greater than the line width of the third sub-connection line.

[0022] Exemplarily, the ratio of the line width of the fourth sub-connection line to the dimension of the first electrode in the line width direction is 0.8 to 1.

[0023] Exemplarily, the sub-pixel region includes a plurality of light-emitting regions, and the plurality of light-emitting regions respectively correspond to a plurality of the light-emitting devices;

[0024] Among them, the first electrodes of different light-emitting devices located in the same sub-pixel region are connected to the same first connection portion through different second connection portions.

[0025] Exemplarily, the display panel further includes:

[0026] A planarization layer, located on a side of the driving substrate close to the light-emitting device, includes a plurality of spaced planar regions;

[0027] Among them, the orthographic projection of each planar region on the driving substrate covers the orthographic projection of the first electrodes in two adjacent sub-pixel regions on the driving substrate, and has no overlap with the orthographic projection of the first connection portion on the driving substrate.

[0028] Exemplarily, the first electrode includes a plurality of metal electrode layers sequentially arranged along the thickness direction of the driving substrate;

[0029] Among them, the second connection portion overlaps at least one of the plurality of metal electrode layers.

[0030] Exemplarily, the display panel further includes:

[0031] A passivation layer, laminated between the driving substrate and the light-emitting device, the orthographic projection of the passivation layer on the driving substrate covers the sub-pixel region and the non-sub-pixel region;

[0032] Among them, a first via hole is formed in the passivation layer, and the first connection portion is overlapped with the pixel driving circuit through the first via hole.

[0033] Exemplarily, the display panel further includes:

[0034] A buffer layer, located on a side of the driving substrate facing away from the light-emitting device;

[0035] A conductive light-shielding layer, located on a side of the buffer layer facing away from the light-emitting device, the orthographic projection of the conductive light-shielding layer on the driving substrate covers the orthographic projection of the first electrode on the driving substrate, and has an overlap with the orthographic projection of the first connection portion on the driving substrate; and,

[0036] A third connection portion, disposed on a side of the driving substrate close to the light-emitting device;

[0037] Among them, a second via hole is further formed in the buffer layer, the pixel driving circuit is electrically connected to the third connection portion through the conductive light-shielding layer located in the second via hole, and the first connection portion is connected to the third connection portion through the first via hole.

[0038] Exemplarily, the shape of the orthographic projection of the first via hole on the driving substrate is different from the shape of the orthographic projection of the second via hole on the driving substrate.

[0039] Exemplarily, the conductive light-shielding layer includes a first region and a second region. The orthographic projection of the first region on the driving substrate covers the first electrode, and the orthographic projection of the second region on the driving substrate overlaps with the non-subpixel region.

[0040] The conductive light-shielding layer further includes a third region located between the first region and the second region. Wherein, the orthographic projection of the third region on the driving substrate does not overlap with the orthographic projection of the second connection portion on the driving substrate.

[0041] In a second aspect of the embodiments of the present disclosure, a display device is provided, including the display panel according to any one of the first aspect.

[0042] The display panel provided by the present disclosure is adopted, which includes a subpixel region, a non-subpixel region, and a driving substrate. The driving substrate includes a pixel driving circuit. On one side of the driving substrate, there are further included: a light-emitting device located in the subpixel region, including a first electrode, a light-emitting layer, and a second electrode sequentially arranged in the thickness direction of the driving substrate; a first connection portion located in the non-subpixel region and lapped with the pixel driving circuit; a second connection portion electrically connected to the first connection portion and the first electrode respectively. Wherein, the second connection portion includes a first connection line or a plurality of parallel second connection lines. Each second connection line is connected to the first connection portion and the second electrode, and the maximum line width of the first connection line is greater than the maximum line width of the second connection line. Wherein, the first electrode of the light-emitting device is lapped with the pixel driving circuit through the first connection portion and the second connection portion, thereby realizing the driving of the light-emitting device by the pixel driving circuit. Since the second connection portion includes a first connection line or a plurality of parallel second connection lines, and the line width of the first connection line is greater than the line width of the second connection line, a larger electrical contact area can be provided between the first electrode and the first connection portion. On the one hand, the disconnection probability of the second connection portion can be reduced. On the other hand, when a certain second connection line in the second connection portion is disconnected, the other second connection lines can still maintain the connection of the path. Thus, the disconnection of the circuit connection between the first connection portion and the first electrode can be avoided, thereby avoiding the occurrence of dark dots and thin dark dot defects.

[0043] The above description is only an overview of the technical solutions of the present disclosure. In order to be able to understand the technical means of the present disclosure more clearly, it can be implemented according to the content of the specification. And in order to make the above and other objects, features, and advantages of the present disclosure more obvious and understandable, the following specifically describes the embodiments of the present disclosure. Description of the Drawings

[0044] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following will briefly introduce the drawings required for the description of the embodiments or related technologies. Obviously, the drawings in the following description are some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. It should be noted that the ratios in the drawings are only for illustration and do not represent the actual ratios.

[0045] Figure 1 Shows a schematic cross-sectional structure diagram of a display panel in an embodiment of the present disclosure;

[0046] Figure 2 And Figure 3 Respectively show Figure 1 Two top view plane schematic diagrams of the display panel shown;

[0047] Figures 4 - 6 Respectively show top view plane schematic diagrams of three display panels in an embodiment of the present disclosure;

[0048] Figures 7 - 9 Respectively show top view plane schematic diagrams of three sub-pixel regions in an embodiment of the present disclosure;

[0049] Figure 10 Shows a top view plane schematic diagram of another display panel in an embodiment of the present disclosure;

[0050] Figure 11 Shows Figure 10 The cross-sectional structure schematic diagram of the B-B' cross-section of the display panel;

[0051] Figure 12 Shows a cross-sectional structure schematic diagram at the second via;

[0052] Figure 13 Shows a top view plane schematic diagram of another display panel in this embodiment;

[0053] Figure 14 Shows Figure 13 The enlarged schematic diagram of the rectangular area AA in;

[0054] Figure 15 And Figure 16 Respectively show cross-sectional structure schematic diagrams of two other display panels in this embodiment;

[0055] Figure 17 Shows a top view plane schematic diagram of the display panel in Example 2.

[0056] Reference numerals:

[0057] 1a, sub-pixel region; 1b, non-sub-pixel region; 11, substrate; 12, buffer layer; 13, interlayer dielectric layer; 14, passivation layer; 15, planarization layer; 20, driving substrate; 21, source region; 22, source electrode; 23, gate layer; 24, gate insulating layer; 25, channel region; 26, drain region; 27, drain electrode; 28, third connection portion; 30, light-emitting device; 31, first electrode; 32, second electrode; 33, light-emitting layer; 311, first electrode layer; 312, second electrode layer; 313, third electrode layer; 314, fourth electrode layer; 41, first connection portion; 42, second connection portion; 421, first connection line; 422, second connection line; 50, conductive light-shielding layer; 60, pixel defining layer; 70, auxiliary structure; 71, first metal layer; 72, second metal layer; 73, third metal layer; 74, fourth metal layer; 75, fifth metal layer; 76, sixth metal layer; 51, first region; 52, second region; 53, third region; 131, first sub-via; 132, second sub-via; 141, first via; 143, second conductive metal; 422a, first sub-connection line; 422b, second sub-connection line; 421a, third sub-connection line; 421b, fourth sub-connection line. Detailed implementation manners

[0058] To make the above objects, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without making creative efforts shall fall within the protection scope of the present disclosure.

[0059] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes an angle state of more than 85° and less than 95°.

[0060] The polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, hexagons, etc., and there may be some small deformations caused by tolerances.

[0061] In the related art, in an OLED display panel, especially in a transparent OLED display panel, dark spots and thin dark spots are likely to occur in the display panel. The main reason is that the display panel includes a sub-pixel region and a non-sub-pixel region. There is a step difference between the anode of the light-emitting device located in the sub-pixel region and the film layer in the non-sub-pixel region. When the pixel driving circuit is connected to the anode, due to the existence of the step difference, the metal film layer is likely to break, resulting in the disconnection of the circuit connection between the anode and the pixel driving circuit. Subsequently, the contact between the anode and the pixel driving circuit is poor, so that the pixel cannot be lit, and then dark spots or thin dark spots appear.

[0062] In view of this, embodiments of the present disclosure propose a display panel. In this display panel, the anode of the light-emitting device can be electrically connected to the pixel driving circuit through multiple connection lines, or can be electrically connected to the pixel driving circuit through a widened connection line, or can be electrically connected to the pixel driving circuit through multiple connection lines and a widened connection line, thereby avoiding the problem of dark spots caused by the pixel driving circuit being unable to drive the light-emitting device.

[0063] Referring to Figures 1 - 3 as shown, Figure 1 FIG. shows a schematic cross-sectional structure diagram of the display panel, Figure 2 and Figure 3 respectively show Figure 1 two top-plan views of the display panel shown in Figures 1 - 3 As shown in

[0064] the display panel in this embodiment mainly includes a sub-pixel region 1a and a non-sub-pixel region 1b, and,

[0065] a driving substrate 20, including a pixel driving circuit. On one side of the driving substrate 20, it also includes:

[0066] a light-emitting device 30, located in the sub-pixel region 1a, including a first electrode 31, a light-emitting layer 33, and a second electrode 32 sequentially arranged in the thickness direction of the driving substrate 20;

[0067] a first connection portion 41, located in the non-sub-pixel region 1b and lapping with the pixel driving circuit;

[0068] a second connection portion 42, electrically connected to the first connection portion 41 and the first electrode 31 respectively;

[0069] In this embodiment, the display panel may include a sub-pixel region 1a and a non-sub-pixel region 1b. Here, the non-sub-pixel region is the region of the display panel other than the sub-pixel region. It should be noted that the sub-pixel region and the non-sub-pixel region are divisions of the plane where the display surface of the display panel is located. Specifically, both the sub-pixel region and the non-sub-pixel region may be located in the display area of the display panel.

[0070] In one example, the display panel may be a transparent display panel, so the driving substrate 20 may be a transparent driving substrate 20. The sub-pixel region may be referred to as the light-emitting region, and the non-sub-pixel region may be referred to as the light-transmitting region.

[0071] In this embodiment, the driving substrate 20 may include pixel driving circuits. The pixel driving circuits provide driving voltages for the light-emitting devices 30 on the display panel. It may include multiple pixel driving circuits, and the multiple pixel driving circuits respectively provide driving voltages for the multiple light-emitting devices 30. The pixel circuit may be a 3T1C driving circuit or a 7T1C driving circuit. Among them, the pixel driving circuit may include a conductive part, and the conductive part is located at the output end of the pixel driving circuit. Generally speaking, the first electrode 31 in the light-emitting device 30 may be connected to the conductive part of the pixel driving circuit.

[0072] In one example, as Figure 1 shown, the pixel driving circuits on the driving substrate 20 may be thin-film transistors TFTs. Among them, the driving substrate 20 may include a substrate substrate 11, an active layer on one side of the substrate substrate 11, a gate insulating layer 24 on the side of the active layer facing away from the substrate, a gate layer 23 on the side of the gate insulating layer 24 facing away from the substrate, an interlayer dielectric layer 13 on the side of the gate layer 23 facing away from the substrate substrate 11, a source electrode 22 and a drain electrode 27 on the side of the interlayer dielectric layer 13 facing away from the substrate substrate 11. Specifically, the active layer may include a channel region 25 corresponding to the gate layer 23, a source region 21 overlapping with the source electrode 22, and a drain region 26 overlapping with the drain electrode 27. The source region 21 and the drain region 26 are formed after conducting the active layer. Among them, the gate insulating layer 24, the source electrode 22, the drain electrode 27, the gate layer 23, and the active layer constitute a TFT. As Figure 1 shown, the conductive part may be the drain electrode 27. Among them, there is an electrical connection between the drain electrode 27 and the first electrode 31 in the light-emitting device 30.

[0073] Among them, the light-emitting device 30 can be located in the sub-pixel region. The light-emitting device 30 can include a first electrode 31, a light-emitting layer 33, and a second electrode 32. The first electrode 31 is disposed close to the driving substrate 20. The light-emitting layer 33 is located on a side of the first electrode 31 facing away from the driving substrate 20. The second electrode 32 is located on a side of the light-emitting layer 33 facing away from the driving substrate 20. The first electrode 31 can be a cathode, and the second electrode 32 can be an anode; alternatively, the first electrode 31 can be an anode and the second electrode 32 can be a cathode.

[0074] In one example, the second electrode 32 can entirely cover the driving substrate 20, and the light-emitting layer 33 can also entirely cover the driving substrate 20. That is to say, the second electrode 32 covers the sub-pixel region and the non-sub-pixel region, and the light-emitting layer 33 covers the sub-pixel region and the non-sub-pixel region. Among them, the orthographic projection of the first electrode 31 on the driving substrate 20 can be covered by the sub-pixel region.

[0075] In this embodiment, the first electrode 31 can be electrically connected to the conductive portion of the pixel driving circuit through a first connection portion 41 and a second connection portion 42. Specifically, as Figure 1 shown, the first connection portion 41 can be located in the non-sub-pixel region. The first connection portion 41 can overlap with the conductive portion of the pixel driving circuit to achieve electrical connection; one end of the second connection portion 42 is connected to the first connection portion 41, and the other end is electrically connected to the first electrode 31. It should be noted that the electrical connection referred to in this embodiment means that two metal elements are in direct contact; for example, the first electrode 31 and the second connection portion 42 are in direct contact, and the first connection portion 41 and the second connection portion 42 are in direct contact.

[0076] In this embodiment, the second connection portion 42 can include a first connection line 421 and / or a plurality of parallel second connection lines 422. Specifically, as Figure 2 shown, the second connection portion 42 can include a first connection line 421, or, as Figure 3 shown, the second connection portion 42 can include a plurality of parallel second connection lines 422. Or, in some examples, the second connection portion 42 can include a first connection line 421 and a plurality of parallel second connection lines 422. The parallel connection means that a plurality of second connection lines 422 form a plurality of independent current paths between the first electrode 31 and the first connection portion 41.

[0077] Among them, in the case of including the first connection line 421 and a plurality of parallel second connection lines 422, one ends of the plurality of second connection lines 422 are simultaneously connected to the first connection line 421. In this way, the second connection portion 42 can include the first connection line 421 and a plurality of second connection lines 422 connected in parallel to one end of the first connection line 421. The other ends of the plurality of second connection lines 422 can be connected to the first electrode 31 or the first connection portion 41. For specific details, reference can be made to the description of subsequent embodiments.

[0078] In this embodiment, the orthographic projection of the second connecting portion 42 on the driving substrate 20 may overlap with the first connecting portion 41 and overlap with the first electrode 31. For example, as Figure 2 shown, the second connecting portion includes a part overlapping with the first connecting portion and a part overlapping with the first electrode. In another example, the orthographic projection of the second connecting portion 42 on the driving substrate 20 may be adjacent to the first connecting portion and overlap with the first electrode 31. For example, as Figure 3 shown, one edge of one end of the second connecting portion is in direct contact with the edge of the first connecting portion, and the other end of the second connecting portion overlaps on the first electrode.

[0079] During specific implementation, each of the second connecting portions 42 connected to each of the plurality of light-emitting devices 30 may include a first connecting line 421. As Figure 2 shown, each of the second connecting portions 42 connected to each of the plurality of light-emitting devices 30 has only one first connecting line 421. Alternatively, each of the second connecting portions 42 connected to each of the plurality of light-emitting devices 30 may include a plurality of second connecting lines 422. As Figure 3 shown, each of the second connecting portions 42 connected to each of the plurality of light-emitting devices 30 includes a plurality of second connecting lines 422. Or, some of the second connecting portions 42 connected to some of the plurality of light-emitting devices 30 may only include one first connecting line 421, and the second connecting portions 42 connected to the other part of the light-emitting devices 30 may include a plurality of second connecting lines 422.

[0080] Exemplarily, referring to Figure 4 shown, a top-plan schematic diagram of another display panel is shown. As Figure 4 shown, the display panel includes a display area. The second connecting portions 42 connected to the plurality of light-emitting devices 30 in the middle area of the display area may include one first connecting line 421, and the second connecting portions 42 connected to the plurality of light-emitting devices 30 in the edge area of the display area may include a plurality of second connecting lines 422. Thus, the grid formed by the metal lines of the light-emitting devices 30 located in the middle area of the display area can be minimized. In this way, when the display panel is a transparent display panel, the diffraction effect caused by the grid formed between the metal line traces can be avoided, which affects the clear observation of the background object.

[0081] Among them, the maximum line width of the first connecting line 421 may be greater than the maximum line width of the second connecting line 422. That is to say, for two light-emitting devices 30, if the second connecting portion 42 connected to one of the light-emitting devices 30 only includes one first connecting line 421, and the second connecting portion 42 connected to the other light-emitting device 30 includes a plurality of second connecting lines 422, then the maximum line width of the first connecting line 421 is greater than the maximum line width of the second connecting line 422. For example, takingFigure 4 For example, the maximum line width of the first connection line 421 included in the second connection portion 42 to which the light-emitting device 30 in the middle region is connected is greater than the maximum line width of the second connection line 422 included in the second connection portion 42 to which the light-emitting device 30 in the edge region is connected. Another example is as Figure 2 and Figure 3 shown, Figure 2 the maximum line width of the first connection line 421 included in the second connection portion 42 to which the light-emitting device 30 in Figure 3 is connected is greater than the maximum line width of the second connection line 422 included in the second connection portion 42 to which the light-emitting device 30 in

[0082] That is to say, between the first connection portion 41 and the first electrode 31, it can be connected through the widened first connection line 421, or can be connected through multiple second connection lines 422. Among them, when connected through the widened first connection line 421, the contact area between the first electrode 31 and the first connection portion 41 can be increased, so that the first connection line 421 is not likely to break due to climbing, and the occurrence of wire breakage can be avoided, thereby reducing the probability of the occurrence of dark spots. When connected through multiple second connection lines 422, even if one second connection line 422 breaks, the electrical connection between the first electrode 31 and the first connection portion 41 can be maintained through the other unbroken second connection lines 422, thereby reducing the probability of the occurrence of dark spots.

[0083] In this embodiment, the line width may refer to the size of the connection line (the first connection line 421 and the second connection line 422) in the target direction, and the target direction is a direction orthogonal to the connection direction between the first connection portion 41 and the first electrode 31. As Figure 2 and Figure 3 shown, the target direction is the Y direction in the figure; correspondingly, the maximum line width may refer to the maximum size of the connection line in the target direction, such as the size of the region with the widest line width in the target direction.

[0084] Among them, both the first electrode 31 and the second electrode 32 can be transparent electrodes, which can be made of metal or metal oxide. For example, indium tin oxide can be used to form. The first connection portion 41 and the second connection portion 42 can be made of transparent metal or transparent metal oxide, and the thickness of the first electrode 31 can be greater than the thickness of the second electrode 32.

[0085] With the display panel of this embodiment, the first connection part 41 and the first electrode 31 can be connected by a first connection line 421 or a plurality of second connection lines 422 connected in parallel, and the line width of the first connection line 421 is greater than the line width of the second connection lines 422, so that a relatively large electrical contact area can be provided between the first electrode 31 and the first connection part 41. When connected by the first connection line 421, the disconnection probability of the second connection part 42 can be reduced; when connected by a plurality of second connection lines 422, when one of the second connection lines 422 in the second connection part 42 is disconnected, the other second connection lines 422 can still maintain the connection of the circuit. Thus, the disconnection of the circuit connection between the first connection part 41 and the first electrode 31 can be avoided, thereby avoiding the occurrence of dark dots and thin dark dot defects.

[0086] In some embodiments, regardless of whether the second connection part 42 includes a plurality of second connection lines 422 or only includes a first connection line 421, the size of the orthographic projection of the second connection part 42 on the driving substrate 20 in the target direction is greater than or equal to 1 / 5 of the size of the orthographic projection of the first electrode 31 on the driving substrate 20 in the target direction; wherein, the target direction is orthogonal to the connection direction of the first connection part 41 and the first electrode 31.

[0087] In this embodiment, when the second connection part 42 includes a first connection line 421, the size of the orthographic projection of the first connection line 421 on the driving substrate 20 in the target direction can be greater than or equal to 1 / 5 of the size of the orthographic projection of the first electrode 31 on the driving substrate 20 in the target direction. When the second connection part 42 includes a plurality of second connection lines 422, the sum of the sizes of the orthographic projections of the plurality of second connection lines 422 on the driving substrate 20 in the target direction can be greater than or equal to 1 / 5 of the size of the orthographic projection of the first electrode 31 on the driving substrate 20 in the target direction.

[0088] Wherein, the size of the orthographic projection of the connection line on the driving substrate 20 in the target direction can be understood as the line width of the connection line. In this way, the line width of the second connection part 42 can account for 1 / 5 or more of the size of the first electrode 31 in the line width direction, such as Figure 2 and Figure 3 the Y direction in. Correspondingly, the sum of the sizes of the orthographic projections of the plurality of second connection lines 422 on the driving substrate 20 in the target direction can refer to the sum of the line widths of the plurality of second connection lines 422. Specifically, the line width of the second connection part 42 can be 1 / 5, 1 / 3, 2 / 5, 1 / 2, 3 / 5, 4 / 5 or 0.9 of the size of the first electrode 31 in the line width direction.

[0089] In this embodiment, the second connecting portion 42 is made to have a relatively wide width as much as possible, so that the contact area with the first electrode 31 is large enough. Thus, whether it is a plurality of second connecting lines 422 or a single first connecting line 421, the risk of disconnection between the first connecting portion 41 and the first electrode 31 can be reduced.

[0090] In some other embodiments, the second connecting portion 42 may include a single first connecting line 421. The ratio of the maximum line width of the first connecting line 421 to the dimension of the first electrode 31 in the line width direction is 0.2 to 1. Herein, the dimension of the first electrode 31 in the line width direction may refer to the dimension of the first electrode 31 in the target direction.

[0091] Please refer to Figure 2 As shown, the second connecting portion 42 includes a single first connecting line 421. The maximum line width of the first connecting line 421 may account for 0.2, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, or 1 of the dimension of the first electrode 31 in the target direction. In the case of 1, the first connecting line 421 may have the same width as the first electrode 31, thereby avoiding the risk of breakage.

[0092] In some embodiments, as Figure 1 shown, the light-emitting device 30 may be integrally lifted on the driving substrate 20, such that there is a step difference between the first electrode 31 and the first connecting portion 41. The main reason for the existence of this step difference may be that: on the side of the driving substrate 20 close to the light-emitting device 30, there is an insulating film layer, and this insulating film layer may be only located in the sub-pixel region and not in the non-sub-pixel region. This insulating film layer may be an inorganic material film layer, an organic material film layer, or a film layer formed by superimposing inorganic materials and organic materials.

[0093] Due to the existence of the step difference, it is more likely to cause the second connecting portion 42 between the first electrode 31 and the first connecting portion 41 to break. Thus, in this embodiment, the second connecting portion 42 includes at least the first connecting line 421 or a plurality of second connecting lines 422 in the region where the step difference is located.

[0094] In this way, when forming the second connecting portion 42, in the region where the step difference exists, the risk of breakage is reduced by the widened first connecting line 421, or the electrical connection performance is ensured by forming a plurality of second connecting lines 422.

[0095] In a further example of this embodiment, the step difference may be formed due to the planarization layer 15. For example, the display panel may further include a planarization layer 15. Herein, the planarization layer 15 may be located in the sub-pixel region. In this way, when the display panel is a transparent display panel, it can enhance the light transmission performance of the non-sub-pixel region and can lift the light-emitting device 30.

[0096] Please continue to refer to Figure 1 、Figure 5 and Figure 6 as shown Figure 5 and Figure 6 respectively show Figure 1 two other top - view schematic diagrams of the display panel shown, as Figure 1 and Figure 5 shown, the flat layer 15 is located on the side of the driving substrate 20 close to the light - emitting device 30; the orthographic projection of the flat layer 15 on the driving substrate 20 covers the orthographic projection of the first electrode 31 on the driving substrate 20, and has no overlap with the orthographic projection of the first connection part 41 on the driving substrate 20;

[0097] wherein, the orthographic projection of the second connection part 42 on the driving substrate 20 has an overlap with the edge of the flat layer 15, and the second connection part 42 includes at least one first connection line 421 or a plurality of second connection lines 422 in the overlapping area where there is an overlap.

[0098] As Figure 1 shown, the orthographic projection of the flat layer 15 on the driving substrate 20 covers the orthographic projection of the first electrode 31 on the driving substrate 20, and has no overlap with the orthographic projection of the first connection part 41 on the driving substrate 20. In practice, the flat layer 15 can be located in the sub - pixel region and has no overlap with the non - sub - pixel region. As Figure 5 shown, since the second connection part 42 needs to connect the first electrode 31 and the first connection part 41, the orthographic projection of the second connection part 42 on the driving substrate 20 can overlap with the first electrode 31, the first connection part 41, and the flat layer 15 simultaneously.

[0099] Among them, the overlapping area should at least include the area where the second connection part 42 overlaps with the edge of the flat layer 15. For the convenience of layout production, the overlapping area can include the area where the second connection part 42 overlaps with the edge of the flat layer 15 and the area where it overlaps with the first electrode 31, that is, the overlapping area overlaps with the flat layer 15 and the first electrode 31 simultaneously. Among them, the outer contour of the orthographic projection of the overlapping area on the driving substrate 20 can be located outside the edge of the orthographic projection of the flat layer 15 on the driving substrate 20.

[0100] Among them, the second connection part 42 includes at least one first connection line 421 or a plurality of second connection lines 422 in the overlapping area. Specifically, either there is one first connection line 421 or there are a plurality of second connection lines 422 in the overlapping area. Among them, the area of the second connection part 42 except the overlapping area can include one connection line or a plurality of connection lines. Specifically, in the case where there is also one first connection line 421 in the overlapping area, if the area outside the overlapping area includes one connection line, the second connection part 42 can be regarded as a whole including one first connection line 421, as Figure 2 and Figure 5As shown, the line width of the first connection line 421 in the overlapping region can be greater than 1 / 5 of the size of the first electrode 31 in the line width direction, or the line width of the entire first connection line 421 is greater than 1 / 5 of the size of the first electrode 31 in the line width direction.

[0101] Specifically, the overlapping region may include a plurality of second connection lines 422. If the region outside the overlapping region includes one connection line, then as Figure 6 shown, the second connection portion 42 can be regarded as a structure including a first connection line 421 and a plurality of second connection lines 422 connected in parallel with the first connection line 421 as a whole. Among them, the first connection line 421 is connected to the first connection portion 41 and a plurality of second connection lines 422, and the plurality of second connection lines 422 can be connected to the first electrode 31. Thus, the orthographic projection of the second connection portion 42 on the driving substrate 20 can be in a comb shape.

[0102] Adopting the technical solution of this embodiment, on the one hand, it can enhance the climbing ability of the second connection portion 42 at the flat layer 15. For example, in the case of including the first connection line 421, its climbing ability is enhanced, making it not easy to break at the flat layer 15. On the other hand, it can also ensure the electrical connection with the first electrode 31 through a plurality of second connection lines 422. If one second connection line 422 is broken, the electrical connection can be ensured by other second connection lines 422, reducing the risk of disconnection between the second connection portion 42 and the first electrode 31.

[0103] Combined with the above embodiments, the second connection portion 42 can include a first connection line 421 and a plurality of second connection lines 422 at the same time. In some embodiments, the plurality of second connection lines 422 can be respectively connected to the first connection line 421 and the first electrode 31. Please refer to Figure 6 shown, one end of the first connection line 421 is in direct contact with the first connection portion 41, and the other end is in contact with one end of a plurality of second connection lines 422 at the same time. The other ends of the plurality of second connection lines 422 are in direct contact with the first electrode 31 at the same time.

[0104] Among them, in the case where the display panel includes a flat layer 15, and the flat layer 15 is located in the sub-pixel region and has no overlap with the non-sub-pixel region, the plurality of second connection lines 422 can be located in the overlapping region where the second connection portion 42 overlaps with the flat layer 15, that is, the orthographic projection of each second connection line 422 on the driving substrate 20 overlaps with the orthographic projection of the flat layer 15 on the driving substrate 20.

[0105] With this structure of the second connection portion 42, since the second connection portion 42 includes a plurality of second connection lines 422 connected to the first electrode 31, and when the second connection lines 422 are located in the overlapping region, when one of the second connection lines 422 breaks due to climbing, the connection between the first connection portion 41 and the first electrode 31 can still be ensured through other second connection lines 422, avoiding the occurrence of dark spots.

[0106] As described in the above embodiments, when the second connection portion 42 includes a first connection line 421 and a plurality of second connection lines 422, the first connection line 421 can be connected to the first electrode 31. Specifically, one end of the plurality of second connection lines 422 is in direct contact with the first connection portion 41 at the same time, the other ends of the plurality of second connection lines 422 are connected to one end of the first connection line 421 at the same time, and the other end of the first connection line 421 is connected to the first electrode 31.

[0107] Refer to Figure 7 As shown, a top - view plane schematic diagram of a sub - pixel in this case is shown. As Figure 7 As shown, when the display panel includes a planarization layer 15, and the planarization layer 15 is located in the sub - pixel region and does not overlap with the non - sub - pixel region, the first connection line 421 can be located in the overlapping region where the second connection portion 42 overlaps with the planarization layer 15. One end of the first connection line 421 is connected to the first connection portion 41 through a plurality of second connection lines 422 connected in parallel, and the other end is connected to the first electrode 31. Moreover, the orthographic projection of the first connection line 421 on the driving substrate 20 overlaps with the orthographic projection of the planarization layer 15 on the driving substrate 20.

[0108] With this structure of the second connection portion 42, since the second connection portion 42 includes a first connection line 421 connected to the first electrode 31, and the line width of the first connection line 421 is relatively large, thus, it is possible to avoid the breakage of the second connection portion 42 at the climbing position, and thereby avoid the occurrence of dark spots.

[0109] In some embodiments, when the second connection portion 42 includes a first connection line 421, the line width of the first connection line 421 can be non - uniform, and the position of the maximum line width of the first connection line 421 can be located at the step difference. For example, please continue to refer to Figure 5 As shown, the second connection portion 42 includes a first connection line 421. The first connection line 421 includes a third sub - connection line 421a connected to the first connection portion 41, and a fourth sub - connection line 421b connected between the third sub - connection line 421a and the first electrode 31; wherein, the fourth sub - connection line 421b is located in the region where the step difference is located, and the line width of the fourth sub - connection line 421b is greater than the line width of the third sub - connection line 421a.

[0110] In this embodiment, one end of the fourth sub-connection line 421b is connected to the third sub-connection line 421a, and the other end is connected to the first electrode 31. The other end of the third sub-connection line 421a is connected to the first connection portion 41, and the line width of the third sub-connection line 421a is smaller than that of the fourth sub-connection line 421b, so that the line width of the first connection line 421 can gradually become wider in the connection direction from the first connection portion 41 to the first electrode 31.

[0111] Among them, the line width of the third sub-connection line 421a can be uniform or non-uniform. In the case of non-uniformity, the orthographic projection of the second connection portion 42 on the driving substrate 20 is trapezoidal or the like. Specifically, the fourth sub-connection line 421b is located in the area where the step exists. For example, the orthographic projection of the fourth sub-connection line 421b on the driving substrate 20 may overlap with the orthographic projection of the flat layer 15 on the driving substrate 20, so that the second connection portion 42 is widened in the area where the step exists, reducing the risk of slope breakage.

[0112] In a further example of this embodiment, since the line width of the third sub-connection line 421a included in the second connection portion 42 is smaller in the area outside the area where the step exists, the line width of the fourth sub-connection line 421b can be set larger. For example, the ratio of the line width of the fourth sub-connection line 421b to the dimension of the first electrode 31 in the line width direction is 0.8 to 1. It can be 0.8, 0.85, 0.9, 0.95 or 1. When adopting this example, in the case where the display panel is a transparent display panel, on the one hand, the area of the second connection portion 42 in the light-transmitting area can be reduced, improving the light transmittance. On the other hand, the slope climbing ability of the second connection portion 42 in the area where the step exists can be ensured, avoiding the occurrence of disconnection.

[0113] In some embodiments, when the second connection portion 42 includes a plurality of second connection lines 422, the line width of each second connection line 422 can also be non-uniform, and the increased line width is located in the area where the step exists. Specifically, please refer to Figure 8 shown, which shows a top plan schematic view of another sub-pixel. As Figure 8 shown, the second connection portion 42 includes a plurality of second connection lines 422, and the second connection line 422 includes a first sub-connection line 422a and a second sub-connection line 422b connected in series in sequence.

[0114] Among them, the second sub-connection line 422b is located in the area where the step exists, and the line width of the second sub-connection line 422b is greater than that of the first sub-connection line 422a.

[0115] In this embodiment, the second connection portion 42 includes a plurality of second connection lines 422. Each second connection line 422 includes a first sub-connection line 422a with a smaller line width and a second sub-connection line 422b with a larger line width. Thus, the line width of each second connection line 422 is non-uniform, and the region with a larger line width is located in the region where the step difference is present.

[0116] Of course, in some examples, some of the second connection lines 422 include the first sub-connection line 422a and the second sub-connection line 422b. In this way, the line width of some of the second connection lines 422 is non-uniform, while the line width of the remaining second connection lines 422 is uniform. For this, please refer to Figure 9 shown, which shows a top plan view schematic diagram of another sub-pixel. Different from the sub-pixel shown in Figure 8 the second connection portion 42 includes a plurality of second connection lines 422. The line width of some of the second connection lines 422 is non-uniform, and its larger line width is located in the region where the step difference is present. For example, the line width of the second connection line 422 in the middle is non-uniform; the line width of the remaining second connection lines 422 is uniform, such as the line width of the second connection lines 422 on both sides of the second connection portion 42 is uniform.

[0117] Adopting the structure of the second connection portion 42 of this embodiment enables multiple connection lines to be simultaneously provided between the first connection portion 41 and the first electrode 31, and the connection area in the region where the step difference is present is relatively wide. Thus, the probability of occurrence of dark spots can be further reduced.

[0118] In some embodiments, the sub-pixel region can be divided into multiple light-emitting regions. Then, one light-emitting device 30 can be configured for each light-emitting region. The first electrodes 31 of the multiple light-emitting devices 30 in the same sub-pixel region can be connected to the same connection portion, and the light-emitting devices 30 located in different light-emitting regions are connected to different second connection portions 42.

[0119] Please refer to Figure 10 and Figure 11 shown, Figure 10 which shows a top plan view schematic diagram of another display panel. Figure 11 shows Figure 10 a cross-sectional structure schematic diagram of the B-B' section of the display panel shown in Figure 10 shown. Each sub-pixel region can be divided into two, three, or four light-emitting regions. For example, Figure 10 the sub-pixel region in

[0120] In this embodiment, the same sub-pixel region may include the same number of light-emitting devices 30 as the number of light-emitting regions. Among them, the positive projections of the first electrodes 31 of the light-emitting devices 30 located in different light-emitting regions within the same sub-pixel region do not overlap on the driving substrate 20. In this case, in one example, the second electrodes 32 of the light-emitting devices 30 located in different light-emitting regions within the same sub-pixel region may be connected to each other, and the light-emitting layers 33 of the light-emitting devices 30 located in different light-emitting regions within the same sub-pixel region may be connected to each other. Alternatively, in another example, the second electrodes 32 of the light-emitting devices 30 located in different light-emitting regions within the same sub-pixel region may be connected to each other, and the light-emitting layers 33 of the light-emitting devices 30 located in different light-emitting regions within the same sub-pixel region may not overlap, that is to say, the light-emitting layers 33 in different light-emitting regions may be independent of each other.

[0121] As Figure 10 and 11 shown, the first electrodes 31 of multiple light-emitting devices 30 within the same sub-pixel region may be connected to the same first connection portion 41 through their respective corresponding second connection portions 42. By way of example, as Figure 10 shown, the sub-pixel region is divided into two light-emitting regions, and the first electrodes 31 of the light-emitting devices 30 in the two light-emitting regions do not overlap. For example, it includes a light-emitting device 30R1 and a light-emitting device 30R2. Among them, the light-emitting device 30R1 is connected to the first connection portion 41 through three second connection lines 422, and the light-emitting device 30R2 is also connected to the first connection portion 41 through three second connection lines 422.

[0122] When using the display panel of this embodiment, in the case where a sub-pixel region is divided into multiple light-emitting regions, the multiple light-emitting regions can be respectively connected to the first connection portion 41 through their respective second connection portions 42. In this way, when the second connection portion 42 of one light-emitting region is broken, normal light emission can still be achieved through another light-emitting region. Moreover, when the second connection portion 42 of one light-emitting region is broken, the current on the first connection portion 41 is not shunted, thereby increasing the light-emitting brightness of the normally light-emitting light-emitting region. Compared with the case where all multiple light-emitting regions are normally light-emitting, the brightness loss can be reduced. Thus, the probability of the sub-pixel having a dark spot / thin dark spot is further reduced.

[0123] In a further example of this embodiment, when the sub-pixel region includes multiple light-emitting regions, the structures of the second connection portions 42 corresponding to each light-emitting region may be the same. For example, each may include multiple second connection lines 422, or each may include a first connection line 421. It should be noted that when each includes a first connection line 421, to prevent the second connection portions 42 of different light-emitting regions from contacting each other, there is no overlap between the second connection portions 42 corresponding to different light-emitting regions. For example, the line width of the first connection line 421 may be smaller than the size of the first electrode 31 in the line width direction (i.e., the target direction), so that there is no overlap between the second connection portions 42 of two adjacent light-emitting regions.

[0124] Alternatively, the structures of the second connection portions 42 corresponding to multiple light-emitting regions may not be completely the same. For example, the second connection of one light-emitting region includes multiple second connection lines 422, and the second connection portion 42 of another light-emitting region includes a first connection line 421. In this way, the same sub-pixel region can supply power to the first electrode 31 through the second connection portions 42 with two different structures. In this way, a sub-pixel region can avoid slope breakage through the widened first connection line 421 and ensure the power supply of the first electrode 31 through multiple second connection lines 422.

[0125] In a further example of this embodiment, as Figure 11 shown, a pixel defining layer 60 may be provided on one side of the driving substrate 20. The pixel defining layer 60 includes multiple openings, and among them, the multiple openings are used to define the light-emitting regions in each sub-pixel region. Specifically, in one example, there is a first distance between the openings located in the same sub-pixel region, and there is a second distance between the openings for adjacent two sub-pixel regions. Then, the second distance may be greater than the first distance. As Figure 10 shown, the distance between multiple light-emitting regions within the same sub-pixel region may be smaller than the distance between the light-emitting regions located in different sub-pixel regions and adjacent to each other.

[0126] In a further example of this embodiment, there is a step difference between the first electrode 31 and the first connection portion 41. The main reason for the existence of the step difference may be that there is a planarization layer 15 in the sub-pixel region, while there is no planarization layer 15 in the non-sub-pixel region.

[0127] In one example, the planarization layer 15 may cover multiple light-emitting regions of a sub-pixel region, so that each sub-pixel region may correspond to an independent planarization layer 15.

[0128] In another example, the planarization layer 15 may cover two adjacent sub-pixel regions, so that two adjacent sub-pixel regions may correspond to an independent planarization layer 15. Specifically, please continue to refer to Figure 10As shown, the display panel further includes: a flat layer 15, which is located on the side of the driving substrate 20 close to the light-emitting device 30 and includes a plurality of spaced flat areas; wherein, the orthographic projection of each flat area on the driving substrate 20 covers the orthographic projection of the first electrode 31 in two adjacent sub-pixel areas on the driving substrate 20, and has no overlap with the orthographic projection of the first connection portion 41 on the driving substrate 20.

[0129] In this embodiment, the flat layer 15 may include a plurality of flat areas, each flat area may cover two adjacent sub-pixel areas, and in the case where each sub-pixel area includes a plurality of light-emitting areas, each flat area may cover the plurality of light-emitting areas included in two adjacent sub-pixel areas. Among them, as described in the above embodiment, there is no overlap between the flat area and the first connection portion 41, so that there is a step difference between the first connection portion 41 and the first electrode 31.

[0130] Among them, the plurality of sub-pixel areas may be arranged in rows and columns, then the flat area may cover two adjacent sub-pixel areas in the row direction, or may cover two adjacent sub-pixel areas in the column direction (not shown in the figure). As Figure 10 shown, in the case where one flat area covers two adjacent sub-pixel areas, the first connection portions 41 and the second connection portions 42 corresponding to the two sub-pixel areas may be symmetrically distributed, thereby facilitating the wiring of the light-emitting device 30.

[0131] Since one flat area can cover two adjacent sub-pixel areas, the patterning process of the flat layer 15 can be simplified.

[0132] In some embodiments, an exemplary description is given of the connection structure between the first connection portion 41 and the pixel driving circuit. Specifically, please refer to Figure 1 shown, the display panel may further include a passivation layer 14, which may be laminated between the driving substrate 20 and the light-emitting device 30, and the orthographic projection of the passivation layer 14 on the driving substrate 20 covers the light-emitting area and the non-light-emitting area;

[0133] Among them, a first via hole 141 is formed in the passivation layer 14, and the first connection portion 41 is overlapped with the pixel driving circuit through the first via hole 141.

[0134] In this embodiment, the passivation layer 14 may be located between the flat layer 15 and the driving substrate 20. A first via hole 141 is formed in the passivation layer 14. The first via hole 141 may be a circular via hole or an oval via hole. There is a first conductive metal in the first via hole 141. The first connection portion 41 is in direct contact with the first conductive metal. The first connection portion 41 and the first conductive metal may be of the same material. The first conductive metal is in direct contact with the conductive portion of the pixel driving circuit, such as the drain electrode 27, so as to realize the electrical connection between the first connection portion 41 and the pixel driving circuit.

[0135] In still other embodiments, when the display panel is a transparent display panel, the pixel driving circuit can generally be formed in the sub-pixel region to reduce the area it occupies in the light-transmitting region. While the first connecting portion 41 is located in the non-sub-pixel region (light-transmitting region), the connection distance between the first connecting portion 41 and the pixel driving circuit located in the sub-pixel region is relatively long. In such a case, a plurality of vias can be formed, and the plurality of vias can be provided in different film layers, so that the first connecting portion 41 is connected to the pixel driving circuit.

[0136] Please continue to refer to Figure 1 as shown, the display panel further includes:

[0137] a buffer layer 12, located on the side of the driving substrate 20 away from the light-emitting device 30;

[0138] a conductive light-shielding layer 50, located on the side of the buffer layer 12 away from the light-emitting device 30. The orthographic projection of the conductive light-shielding layer 50 on the driving substrate 20 covers the orthographic projection of the first electrode 31 on the driving substrate 20, and overlaps with the orthographic projection of the first connecting portion 41 on the driving substrate 20;

[0139] a third connecting portion 28, provided on the side of the driving substrate 20 close to the light-emitting device 30;

[0140] wherein, a second via is further formed in the buffer layer 12, and the pixel driving circuit is electrically connected to the third connecting portion 28 through the conductive light-shielding layer 50 located in the second via, and the first connecting portion 41 is connected to the third connecting portion 28 through a first via 141.

[0141] In this embodiment, the buffer layer 12 can function to block moisture and impurity ions in the driving substrate 20 (especially organic materials), and can also function to increase hydrogen ions for the subsequently formed active layer. The material of the buffer layer 12 is an insulating material, which can insulate and isolate the conductive light-shielding layer 50 from the active layer; the buffer layer 12 can include silicon nitride, silicon oxide, or silicon oxynitride. In some embodiments, the buffer layer 12 can be omitted according to the type of the driving substrate 20 or the process conditions.

[0142] In this embodiment, a passivation layer 14 is formed between the driving substrate 20 and the light-emitting device 30, and the driving substrate 20 may include a substrate 11, a conductive light-shielding layer 50 on one side of the substrate 11, a buffer layer 12 on one side of the conductive light-shielding layer 50, an active layer on the side of the buffer layer 12 facing away from the substrate 11, a gate insulating layer 24 on the side of the active layer facing away from the substrate, a gate layer 23 on the side of the gate insulating layer 24 facing away from the substrate, an interlayer dielectric layer 13 on the side of the gate layer 23 facing away from the substrate 11, and a source electrode 22 and a drain electrode 27 on the side of the interlayer dielectric layer 13 facing away from the substrate 11. Correspondingly, the second vias may be formed in the interlayer dielectric layer 13 and the buffer layer 12, that is to say, the second vias may penetrate through the interlayer dielectric layer 13 and the buffer layer 12.

[0143] Among them, the first via 141 penetrates through the passivation layer 14, the second vias penetrate through the interlayer dielectric layer 13 and the buffer layer 12, a second conductive metal 143 may be formed in the second vias, and the second conductive metal 143 is in direct contact with the conductive light-shielding layer 50. In this embodiment, the drain electrode 27 of the pixel driving circuit is in direct contact with the second conductive metal 143, and a third connection portion 28 is provided on the driving substrate 20, and the third connection portion 28 is in direct contact with the second conductive metal 143, so that the conductive region of the drain electrode 27 is extended through the conductive metal in the second vias, and the first connection portion 41 may be connected to the third connection portion 28 through the first via 141, realizing the connection between the first connection portion 41 and the pixel driving circuit. As Figure 1 shown, the drain electrode 27 is in direct contact with the second conductive metal 143, the second conductive metal 143 is in direct contact with the conductive light-shielding layer 50, is in direct contact with the third connection portion 28 through the conductive light-shielding layer 50, the third connection portion 28 is in direct contact with the first conductive metal in the first via 141, and the first conductive metal is also in direct contact with the first connection portion 41, thereby realizing the electrical connection between the first connection portion 41 and the pixel driving circuit.

[0144] Among them, the conductive metal in the second vias may be the same as the metal material of the drain electrode 27.

[0145] Among them, the orthographic projection of the third connection portion 28 on the substrate 11 may cover the orthographic projection of the first connection portion 41 on the substrate 11, or the orthographic projection of the third connection portion 28 on the substrate 11 may be covered by the orthographic projection of the first connection portion 41 on the substrate 11.

[0146] Among them, the second via can include a plurality of sub-vias. For example, it includes a first sub-via 131 located in the interlayer dielectric layer 13 and a second sub-via 132 located in the buffer layer 12. The orthographic projections of the first sub-via 131 and the second sub-via 132 on the substrate 11 overlap. In order to prevent the second via from etching into the active layer, the second via can avoid opening holes in the active layer. Please refer to Figure 12 As shown, a schematic cross-sectional structure at the second via is shown. As Figure 12 shown, the distance from the bottom of the first sub-via 131 to the substrate 11 can be greater than the distance from the side of the active layer close to the light-emitting device 30 to the substrate 11. The second sub-via 132 can be away from the opening of the active layer. Thus, both the first sub-via 131 and the second sub-via 132 can bypass the opening of the active layer.

[0147] Among them, referring to Figure 13 As shown, a schematic top-plan view of the display panel of this embodiment is shown. As Figure 13 shown, the orthographic projection of the conductive light-shielding layer 50 on the substrate 11 can cover the light-emitting device 30 and the first connection portion 41. Specifically, the shape of the orthographic projection of the conductive light-shielding layer 50 on the substrate 11 can be similar to the pattern formed among the first connection portion 41, the light-emitting device 30, and the second connection portion 42.

[0148] In this embodiment, the conductive light-shielding layer 50 can include a first region 51 and a second region 52. The first region 51 can be used to shield the thin-film transistor. The second region 52 can be located in the non-sub-pixel region. The second region 52 can be connected to the first region 51 or not connected to the first region 51. Figure 12 What is shown is the case where the first region 51 and the second region 52 are connected.

[0149] Among them, the orthographic projection of the conductive light-shielding layer 50 on the substrate 11 covers the orthographic projection of a sub-pixel region on the substrate 11, and there is no overlap between the orthographic projections of the conductive light-shielding layers 50 corresponding to different sub-pixel regions on the substrate 11, so as to avoid the problem of connection between the conductive light-shielding layers 50 of two adjacent sub-pixel regions, resulting in the series connection of multiple sub-pixel regions. Specifically, in the case where a sub-pixel region includes a plurality of light-emitting regions and each light-emitting region includes a light-emitting device 30, the conductive light-shielding layer 50 can cover a plurality of light-emitting regions at the same time.

[0150] Combined with the above-described embodiments, the display panel further includes a planarization layer 15. The planarization layer 15 includes a plurality of planarization regions. The orthographic projection of a planarization region on the substrate 11 can cover the orthographic projections of two adjacent sub-pixel regions on the substrate 11. Then, the orthographic projection of the conductive light-shielding layer 50 on the substrate 11 can also overlap with the orthographic projection of the planarization layer 15 on the substrate 11.

[0151] In this embodiment, in the case of including the first via hole 141 and the second via hole, the shapes of the first via hole 141 and the second via hole may be different. Exemplarily, referring to Figure 14 as shown, it shows Figure 13 an enlarged schematic view of the rectangular area AA in Figure 14 as shown. From the enlarged view of the second region 52 of the conductive light-shielding layer 50, the shapes of the orthographic projections of the first via hole 141 and the second via hole on the driving substrate 20 may be different. For example, the shape of the orthographic projection of the first via hole 141 on the driving substrate 20 may be oval, and the shape of the orthographic projection of the second via hole on the driving substrate 20 may be circular. Among them, when the shape of the orthographic projection of the first via hole 141 on the driving substrate 20 is oval, the area for the current to flow from the second via hole to the first via hole 141 can be enhanced, thereby improving the driving performance of the light-emitting device 30.

[0152] In some embodiments, the orthographic projections of the first via hole 141 and the second via hole on the driving substrate 20 may have no overlap or may have overlap, as Figure 1 shown, showing the case of no overlap.

[0153] In some examples, the second via hole may overlap with the orthographic projection of the second connection portion 42 on the driving substrate 20, and the orthographic projection of the first via hole 141 on the driving substrate 20 may have no overlap with the orthographic projection of the second connection portion 42 on the driving substrate 20. Or, in some cases, the orthographic projection of the first via hole 141 on the driving substrate 20 may also overlap with the orthographic projection of the second connection portion 42 on the driving substrate 20. Or, the second via hole may have no overlap with the orthographic projection of the second connection portion 42 on the driving substrate 20.

[0154] In some examples, as described above, the conductive light-shielding layer 50 may include a first region 51 and a second region 52. The orthographic projection of the first region 51 on the driving substrate 20 covers the first electrode 31, and the orthographic projection of the second region 52 on the driving substrate 20 overlaps with the non-subpixel region. Accordingly, the conductive light-shielding layer 50 further includes a third region 53 located between the first region 51 and the second region 52; wherein, the orthographic projection of the third region 53 on the driving substrate 20 has no overlap with the orthographic projection of the second connection portion 42 on the driving substrate 20.

[0155] In this embodiment, as Figure 13As shown, the orthographic projection of the first region 51 on the driving substrate 20 covers the orthographic projection of the first electrode 31 on the driving substrate 20 and is covered by the orthographic projection of the planarization layer 15 on the driving substrate 20; the orthographic projection of the second region 52 on the driving substrate 20 may cover the orthographic projection of the first connection portion 41 on the driving substrate 20; wherein, the area of the second region 52 on the side away from the driving substrate 20 is smaller than the area of the first region 51 on the side away from the driving substrate 20, so that the area occupied by the light-transmitting region can be reduced and the light transmittance of the display panel can be enhanced.

[0156] Wherein, as Figure 13 shown, the first region 51 and the second region 52 may be connected through a third region 53, and the third region 53, the first region 51 and the second region 52 may be formed by a patterning process. Specifically, the orthographic projection of the third region 53 on the driving substrate 20 does not overlap with the orthographic projection of the second connection portion 42 on the driving substrate 20. Thus, a coupling capacitance can be avoided from being formed between the third region 53 and the second connection portion 42.

[0157] In this embodiment, when the second connection portion 42 includes a first connection line 421, the line width of the first connection line 421 is smaller than the dimension of the first electrode 31 in the line width direction; when the second connection portion 42 includes a plurality of second connection lines 422, there is no overlap between the second connection lines 422 and the third region 53.

[0158] In some embodiments, the first electrode 31 may be formed by stacking a plurality of metal electrode layers to improve the conductivity of the first electrode 31. Specifically, the first electrode 31 may include a plurality of metal electrode layers sequentially arranged along the thickness direction of the driving substrate 20; wherein, the second connection portion 42 may overlap with at least one of the plurality of metal electrode layers.

[0159] In this embodiment, the first electrode 31 may include two or more metal electrode layers. Among them, the orthographic projection of the metal electrode layer closest to the driving substrate 20 on the driving substrate 20 may cover the orthographic projections of the other metal electrode layers on the driving substrate 20, and the orthographic projections of the other metal electrode layers on the driving substrate 20 may substantially coincide.

[0160] For example, as Figure 1 shown, the first electrode 31 may include a first electrode layer 311, a second electrode layer 312, a third electrode layer 313 and a fourth electrode layer 314. The orthographic projection of the first electrode layer 311 on the driving substrate 20 may cover the orthographic projections of the second electrode layer 312, the third electrode layer and the fourth electrode layer on the driving substrate 20, and the orthographic projections of the second electrode layer 312, the third electrode layer and the fourth electrode layer on the driving substrate 20 may coincide.

[0161] Among them, the second connection part 42 can be in direct contact with the first electrode layer 311. For example, the second connection part 42 can overlap on the side of the first electrode layer 311 facing away from the driving substrate 20. Or, in some other examples, the second connection part 42 can also be in direct contact with the first electrode layer 311 and the second electrode layer 312 respectively. Refer to Figure 15 As shown, another cross-sectional structure schematic diagram of the display panel is shown. For example, Figure 15 As shown, the second connection part 42 can also be in direct contact with the first electrode layer 311 and the second electrode layer 312 respectively; or, in some other examples, the second connection part 42 can be in direct contact with the first electrode layer 311, the second electrode layer 312, and the third electrode layer 313.

[0162] Specifically, when the second connection part 42 includes a first connection line 421, it means that the first connection part 41 and the first electrode 31 are connected by a widened metal line. Since the line width of the first connection line 421 is relatively wide, its climbing ability is enhanced. Then, the first connection line 421 can be in direct contact with the first electrode layer 311 and the second electrode layer 312 respectively, or in direct contact with the first electrode layer 311, the second electrode layer 312, and the third electrode layer 313.

[0163] Among them, when the second connection part 42 includes multiple second connection lines 422, it means that the first connection part 41 and the first electrode 31 are connected by multiple metal lines. Then, compared with the first connection line 421, the climbing ability of the second connection lines 422 is weaker. Then, the second connection lines 422 can be in direct contact with the first electrode layer 311, or in direct contact with the first electrode layer 311 and the second electrode layer 312.

[0164] In this embodiment, when the second connection part 42 overlaps with multiple metal electrode layers, since the second connection part 42 can overlap with at least one metal electrode layer, a good contact is maintained between the second connection part 42 and the first electrode 31, thereby reducing the risk of disconnection between the first electrode 31 and the first connection part 41.

[0165] In an example of this embodiment, still referring to Figure 1 As shown, the display panel can include a pixel defining layer 60. The pixel defining layer 60 includes multiple openings, and the light-emitting device 30 is located in the openings. Among them, when the second connection part 42 is only in direct contact with the first electrode layer 311, the orthographic projection of the second connection part 42 on the driving substrate 20 can be covered by the orthographic projection of the pixel defining layer 60 on the driving substrate 20. Thus, the second connection part 42 can be protected by the pixel defining layer 60.

[0166] Among them, the orthographic projection of the first connection portion 41 on the driving substrate 20 can also be covered by the orthographic projection of the pixel defining layer 60 on the driving substrate 20, thereby realizing insulation between the first connection portion 41 and the second electrode 32 and avoiding short - circuiting between the second electrode 32 and the first connection portion 41.

[0167] Of course, when the second connection portion 42 is in direct contact with multiple metal electrode layers, a partial outer contour of the orthographic projection of the second connection portion 42 on the substrate 11 can coincide with a partial outer contour of the orthographic projection of the pixel defining layer 60 on the driving substrate 20, as Figure 15 shown.

[0168] In some other embodiments, since the thickness of the second electrode 32 is relatively thin, the resistance of the second electrode 32 is relatively large and the voltage drop is relatively large, resulting in a relatively large difference in the current of the sub - pixels in the central region and the edge region of the display panel. In practice, an auxiliary electrode structure can be provided for the second electrode 32. Referring to Figure 16 shown, a schematic cross - sectional structure diagram of another display panel is shown. As Figure 16 shown, the display panel further includes an auxiliary structure 70. Among them, both the second electrode 32 and the light - emitting layer 33 are disconnected at the position of the auxiliary structure 70, and the second electrode 32 is in direct contact with the auxiliary structure 70 to achieve electrical connection between the second electrode 32 and the auxiliary structure 70.

[0169] Specifically, the auxiliary structure 70 may include a plurality of metal layers sequentially arranged in the thickness direction of the driving substrate 20. The cross - sectional structure of the plurality of metal layers in the thickness direction of the driving substrate 20 may be an "I" - shaped structure, and there is a relatively large step difference between the auxiliary structure 70 and the driving substrate 20, so that the light - emitting layer 33 and the second electrode 32 are broken by climbing at the auxiliary structure 70, thereby disconnecting the second electrode 32 and the light - emitting layer 33 at the auxiliary structure 70. Thus, the light - emitting layer 33 and the second electrode 32 are sequentially stacked on the side of the auxiliary structure 70 facing away from the driving substrate 20.

[0170] As Figure 16 shown, for example, the auxiliary structure 70 may include a first metal layer 71, a second metal layer 72, a third metal layer 73, a fourth metal layer 74, a fifth metal layer 75, and a sixth metal layer 76 sequentially arranged in the thickness direction of the driving substrate 20. Among them, the first metal layer is arranged on the same layer as the drain electrode 27 of the pixel driving circuit. The outer contour of the orthographic projection of the fourth metal layer and the fifth metal layer on the driving substrate 20 is located within the outer contour of the orthographic projection of the third metal layer on the driving substrate 20 and within the outer contour of the orthographic projection of the sixth metal layer on the driving substrate 20. Among them, the second metal layer is formed in a third via hole opened in the passivation layer 14. Figure 16 The third via hole is not marked in

[0171] In this embodiment, the auxiliary structure 70 may be located in the non-subpixel region. Moreover, there is no overlap between one auxiliary structure 70 and the first connection portion 41, and there is no overlap between the auxiliary structure 70 and the pixel driving circuit. In practice, one auxiliary structure 70 may be connected to the second electrodes 32 of a column of light-emitting devices 30 simultaneously, or one auxiliary structure 70 may be connected to the second electrode 32 of a single light-emitting device 30. Thus, the second electrodes 32 of multiple light-emitting devices 30 may be respectively connected to multiple auxiliary structures 70.

[0172] In this embodiment, since the auxiliary structure 70 is electrically connected to the second electrode 32, the resistance of the second electrode 32 can be reduced, the voltage drop can be reduced, the current difference between the subpixels in the central region and the edge region of the display panel can be reduced, and the uniformity of the display brightness of the display panel can be improved.

[0173] Next, several specific examples will be combined to exemplarily illustrate the display panel of the present disclosure.

[0174] Example 1. Please refer to Figure 16 and Figure 13 As shown, the display panel in this embodiment includes:

[0175] A driving substrate 20, including a pixel driving circuit. The driving substrate 20 includes a substrate 11, a conductive light-shielding layer 50 on one side of the substrate 11, a buffer layer 12 on one side of the conductive light-shielding layer 50, an active layer on the side of the buffer layer 12 facing away from the substrate 11, a gate insulating layer 24 on the side of the active layer facing away from the substrate, a gate layer 23 on the side of the gate insulating layer 24 facing away from the substrate, and an interlayer dielectric layer 13 on the side of the gate layer 23 facing away from the substrate 11, a source electrode 22 and a drain electrode 27 on the side of the interlayer dielectric layer 13 facing away from the substrate 11.

[0176] Among them, on one side of the driving substrate 20, there is also a passivation layer 14. A first via 141 is formed on the passivation layer 14. A first sub-via 131 is formed in the interlayer dielectric layer 13. A second sub-via 132 is formed in the buffer layer 12. The orthographic projection of the first sub-via 131 on the substrate 11 covers the orthographic projection of the second sub-via 132 on the substrate 11. The first sub-via 131 and the second sub-via 132 constitute a second via. A first conductive metal is formed in the first via 141, and a second conductive metal 143 is formed in the second via;

[0177] Among them, a planarization layer 15 is further formed on the side of the passivation layer 14 facing away from the driving substrate 20. The planarization layer 15 is located in the subpixel region and may have no overlap with the non-subpixel region;

[0178] The light-emitting device 30 is located on the side of the flat layer 15 facing away from the driving substrate 20, and the orthographic projection of the light-emitting device 30 on the substrate substrate 11 is covered by the flat layer 15. The light-emitting device 30 includes a first electrode 31, a light-emitting layer 33, and a second electrode 32 that are sequentially arranged in the thickness direction of the driving substrate 20.

[0179] The first connection portion 41 is located in the non-subpixel region.

[0180] The second connection portion 42 is electrically connected to the first connection portion 41 and the first electrode 31 respectively.

[0181] Wherein, the second connection portion 42 includes a first connection line 421. The line width of the first connection line 421 is uniform, and the line width can be greater than 3 / 5 of the size of the first electrode 31 in the line width direction and less than the size of the first electrode 31 in the line width direction.

[0182] Wherein, the drain electrode 27 is electrically connected to the second conductive metal 143. The second conductive metal 143 is electrically connected to the conductive light-shielding layer 50. The second conductive metal 143 is connected to the third connection portion 28. The third connection portion 28 is electrically connected to the first conductive metal. The first conductive metal is connected to the first connection portion 41. The first connection portion 41 is connected to the second connection portion 42. The second connection portion 42 is electrically connected to the first electrode 31. Specifically, the first connection line 421 is in direct contact with the first electrode layer 311 in the first electrode 31.

[0183] Wherein, the conductive light-shielding layer 50 includes a first region 51, a second region 52, and a third region 53 connecting the first region 51 and the second region 52. The orthographic projection of the first region 51 on the substrate substrate 11 covers a subpixel region, and there is no overlap between the first regions 51 corresponding to different subpixel regions. The orthographic projection of the second region 52 on the substrate substrate 11 covers the first connection portion 41. The orthographic projection of the third region 53 on the substrate substrate 11 does not overlap with the first connection line 421.

[0184] Wherein, a subpixel region includes two light-emitting regions. There is no overlap between the first electrodes 31 in the two light-emitting regions, and they are connected to the same first connection portion 41 through their respective first connection lines 421.

[0185] In addition, an auxiliary structure 70 is further included. The auxiliary structure 70 is located in the non-subpixel region. The auxiliary structure 70 includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, and a sixth metal layer that are sequentially arranged in the thickness direction of the driving substrate 20. The light-emitting layer 33 and the second electrode 32 are disconnected at the auxiliary structure 70. The second electrode 32 is electrically connected to the auxiliary structure 70 to reduce the resistance of the second electrode 32.

[0186] Example 2, please refer to Figure 16 and Figure 17As shown in the figure, the difference between the display panel in this embodiment and that in Example 1 is that: the second connection part 42 includes a plurality of second connection lines 422 arranged in parallel, and the line widths of the second connection lines 422 are uniform.

[0187] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which may include the display panel in the above embodiment. Among them, the display device may be a transparent display device.

[0188] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference may be made to each other.

[0189] Finally, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, commodity or device including the said element.

[0190] The above has introduced in detail a display panel and a display device provided by the present disclosure. Specific examples are used in this article to elaborate on the principle and implementation manner of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure; at the same time, for those of ordinary skill in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present disclosure.

[0191] Those skilled in the art will easily think of other implementation schemes of the present disclosure after considering the specification and practicing the utility model disclosed herein. The present disclosure aims to cover any variations, uses or adaptive changes of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and the embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0192] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

[0193] As used herein, the terms "one embodiment", "an embodiment", or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. In addition, it should be noted that the examples of the phrase "in one embodiment" herein do not necessarily all refer to the same embodiment.

[0194] In the specification provided herein, a large number of specific details are set forth. However, it can be understood that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0195] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In a unit claim listing several devices, several of these devices may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

[0196] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, and not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display panel, characterized in that, It includes a sub-pixel region (1a) and a non-sub-pixel region (1b), and a driving substrate (20), including a pixel driving circuit, and on one side of the driving substrate (20), it further includes: a light-emitting device (30), located in the sub-pixel region (1a), including a first electrode, a light-emitting layer, and a second electrode sequentially arranged in the thickness direction of the driving substrate (20); a first connection portion (41), located in the non-sub-pixel region (1b) and overlapping with the pixel driving circuit; a second connection portion (42), electrically connected to the first connection portion (41) and the first electrode respectively; wherein, the second connection portion (42) includes a first connection line (421), and / or a plurality of parallel second connection lines (422), and the maximum line width of the first connection line (421) is greater than the maximum line width of the second connection lines (422).

2. The display panel according to claim 1, wherein The size of the orthographic projection of the second connection portion (42) on the driving substrate (20) in the target direction is greater than or equal to 1 / 5 of the size of the orthographic projection of the first electrode on the driving substrate (20) in the target direction; wherein, the target direction is orthogonal to the connection direction between the first connection portion (41) and the first electrode.

3. The display panel according to claim 1, wherein, The second connection portion (42) includes one first connection line (421), and the ratio of the maximum line width of the first connection line (421) to the size of the first electrode in the line width direction is 0.2 to 1.

4. The display panel according to claim 1, wherein There is a step difference between the first connection portion (41) and the first electrode, and wherein, the second connection portion (42) includes the first connection line (421) or a plurality of the second connection lines (422) at least in the region where the step difference is located.

5. The display panel according to claim 4, wherein The display panel further includes: a planarization layer (15), located on the side of the driving substrate (20) close to the light-emitting device (30); the orthographic projection of the planarization layer (15) on the driving substrate (20) covers the orthographic projection of the first electrode on the driving substrate (20), and has no overlap with the orthographic projection of the first connection portion (41) on the driving substrate (20), so that there is the step difference between the first electrode and the first connection portion (41); wherein, the orthographic projection of the first connection line (421) or a plurality of the second connection lines (422) on the driving substrate (20) has an overlap with the orthographic projection of the planarization layer (15) on the driving substrate (20).

6. The display panel according to any one of claims 1-5, characterized in that, The second connection portion (42) includes one first connection line (421) and a plurality of the second connection lines (422); wherein, a plurality of the second connection lines (422) are respectively connected to the first connection line (421) and the first electrode; or, the first connection line (421) is respectively connected to a plurality of the second connection lines (422) and the first electrode.

7. The display panel according to claim 4, wherein, The second connection part (42) includes a plurality of the second connection lines (422). The second connection line (422) includes a first sub-connection line (422a) and a second sub-connection line (422b) connected in series in sequence. The second sub-connection line (422b) is located in the area where the step difference is located, and the line width of the second sub-connection line (422b) is greater than the line width of the first sub-connection line (422a).

8. The display panel according to claim 4, characterized in that, The second connection part (42) includes one first connection line (421). The first connection line (421) includes a third sub-connection line (421a) connected to the first connection part (41), and a fourth sub-connection line (421b) connected between the third sub-connection line (421a) and the first electrode; Wherein, the fourth sub-connection line (421b) is located in the area where the step difference is located, and the line width of the fourth sub-connection line (421b) is greater than the line width of the third sub-connection line (421a).

9. The display panel according to claim 8, wherein, The ratio of the line width of the fourth sub-connection line (421b) to the size of the first electrode in the line width direction is 0.8 to 1.

10. The display panel according to claim 1, characterized in that, The sub-pixel region (1a) includes a plurality of light-emitting regions, and the plurality of light-emitting regions respectively correspond to a plurality of the light-emitting devices (30); Wherein, the first electrodes of different light-emitting devices (30) located in the same sub-pixel region (1a) are connected to the same first connection part (41) through different second connection parts (42).

11. The display panel according to claim 1, wherein The display panel further includes: A planarization layer (15), located on a side of the driving substrate (20) close to the light-emitting device (30), and includes a plurality of spaced planar regions; Wherein, the orthographic projection of each planar region on the driving substrate (20) covers the orthographic projection of the first electrodes in two adjacent sub-pixel regions (1a) on the driving substrate (20), and has no overlap with the orthographic projection of the first connection part (41) on the driving substrate (20).

12. The display panel according to claim 1, wherein The first electrode includes a plurality of metal electrode layers arranged in sequence along the thickness direction of the driving substrate (20); Wherein, the second connection part (42) overlaps with at least one of the plurality of metal electrode layers.

13. The display panel according to claim 1, characterized in that, The display panel further includes: A passivation layer (14), laminated between the driving substrate (20) and the light-emitting device (30). The orthographic projection of the passivation layer (14) on the driving substrate (20) covers the sub-pixel region (1a) and the non-sub-pixel region (1b); Wherein, a first via hole is formed in the passivation layer (14), and the first connection part (41) is overlapped with the pixel driving circuit through the first via hole.

14. The display panel according to claim 13, wherein The display panel further includes: A buffer layer (12), located on a side of the driving substrate (20) facing away from the light-emitting device (30); A conductive light-shielding layer (50) is located on a side of the buffer layer (12) away from the light-emitting device (30). A positive projection of the conductive light-shielding layer (50) on the driving substrate (20) covers a positive projection of the first electrode on the driving substrate (20), and overlaps with a positive projection of the first connecting portion (41) on the driving substrate (20); and, A third connecting portion (28) is provided on a side of the driving substrate (20) close to the light-emitting device (30); Wherein, a second via hole is further formed in the buffer layer (12), and the pixel driving circuit is electrically connected to the third connecting portion (28) through the conductive light-shielding layer (50) located in the second via hole, and the first connecting portion (41) is connected to the third connecting portion (28) through the first via hole.

15. The display panel according to claim 14, characterized in that, A shape of a positive projection of the first via hole on the driving substrate (20) is different from a shape of a positive projection of the second via hole on the driving substrate (20).

16. The display panel according to claim 14, wherein The conductive light-shielding layer (50) includes a first region (51) and a second region (52). A positive projection of the first region (51) on the driving substrate (20) covers the first electrode, and a positive projection of the second region (52) on the driving substrate (20) overlaps with the non-sub-pixel region (1b); The conductive light-shielding layer (50) further includes a third region (53) located between the first region (51) and the second region (52); wherein, a positive projection of the third region (53) on the driving substrate (20) does not overlap with a positive projection of the second connecting portion (42) on the driving substrate (20).

17. A display device, characterized in that, A display panel according to any one of claims 1-16.

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