High-reliability SiCMOS tube gate drive circuit

Abstract

The utility model discloses a high-reliability SiCMOS tube gate drive circuit, which is characterized in that a PWM signal input end of a wiring interference adjusting circuit is used for connecting a PWM signal output end of a PWM signal driver, and a PWM signal output end of the wiring interference adjusting circuit after wiring interference is eliminated is connected with a signal input end of a switching speed adjusting circuit; the PWM signal output end of the switching speed adjusting circuit after waveform adjustment is connected with the signal input end of the peak suppression circuit, the peak suppression PWM signal output end of the peak suppression circuit is connected with the signal input end of the compensation circuit, and the PWM signal output end of the compensation circuit after waveform compensation is used for driving the grid electrode of the SiCMOS tube. According to the utility model, the problem that the driving of the SiCMOS tubes applied in high voltage, high frequency and floating is unstable can be solved, and the driving of the SiCMOS tubes used in parallel also has a good effect, so that the SiCMOS tubes can work reliably and stably.

Description

Technical Field

[0001] The utility model relates to the field of SiCMOS transistor gate driving, and particularly refers to a high-reliability SiCMOS transistor gate driving circuit. Background Technique

[0002] The existing driving for SiCMOS transistors uses a driving IC supporting ordinary MOS transistors. After long-term use, it is found that this driving method has low reliability for SiCMOS transistors. Through analysis, it is found that SiCMOS transistors have relatively strict requirements for the stability of driving signals. The driving voltage of SiCMOS transistors is generally -10V to 22V, while the driving voltage of ordinary MOS transistors is generally +30V to -30V. As a result, under the driving conditions supporting ordinary MOS transistors, SiCMOS transistors are prone to damage. Especially for floating ground applications, the driving signal of the upper transistor is easily interfered with and becomes abnormal, damaging the SiCMOS transistor. Therefore, a high-reliability SiCMOS transistor gate driving circuit is necessary to improve the stability and reliability of the SiCMOS transistor driving signal. Summary of the Invention

[0003] The utility model provides a high-reliability SiCMOS transistor gate driving circuit, which can stably and reliably drive the SiCMOS transistor gate.

[0004] To achieve this purpose, the utility model provides a high-reliability SiCMOS transistor gate driving circuit, which includes a first trace interference adjustment circuit, a first switching speed adjustment circuit, a first spike suppression circuit, and a first compensation circuit; the PWM signal input end of the first trace interference adjustment circuit is used to connect the PWM signal output end of the PWM signal driver, the PWM signal output end after eliminating trace interference of the first trace interference adjustment circuit is connected to the signal input end of the first switching speed adjustment circuit, the PWM signal output end after adjusting the waveform of the first switching speed adjustment circuit is connected to the signal input end of the first spike suppression circuit, the spike suppression PWM signal output end of the first spike suppression circuit is connected to the signal input end of the first compensation circuit, and the PWM signal output end after waveform compensation of the first compensation circuit is used to drive the SiCMOS transistor gate.

[0005] Further, the PWM wave signal driver includes a PWM driving chip, capacitors C5 to C7, electrolytic capacitor C8, resistor R11, and power supply Vc. The negative voltage pin V of the PWM driving chip EE is connected in parallel with capacitors C5 and C6 between the ground pin GND2, and the negative voltage pin V of the PWM driving chip EE is connected to the power supply pin V of the PWM driving chip CCA capacitor C7, an electrolytic capacitor C8 and a power supply Vc are connected in parallel. The positive pole of the power supply Vc is connected to the power supply pin V of the PWM drive chip. CC The negative pole of the power supply Vc is connected to the negative voltage pin V of the PWM drive chip. EE The positive pole of the electrolytic capacitor C8 is connected to the positive pole of the power supply Vc, and the negative pole of the electrolytic capacitor C8 is connected to the negative pole of the power supply Vc. One end of the resistor R11 is connected to the output pin OUT of the PWM drive chip, and the other end of the resistor R11 and the ground terminal GND2 of the PWM drive chip form the PWM signal output terminal of the PWM wave signal driver.

[0006] Furthermore, the first trace interference adjustment circuit includes a resistor R7, a resistor R8 and a capacitor C3. One end of the resistor R7 is connected to the other end of the resistor R11, the other end of the resistor R7 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the ground terminal GND2 of the PWM drive chip. Both ends of the capacitor C3 form the PWM signal output terminal after eliminating trace interference of the first trace interference adjustment circuit.

[0007] Furthermore, the first switching speed adjustment circuit includes a resistor R3, a resistor R4 and a diode D4. One end of the resistor R3 is connected to the other end of the resistor R7, the other end of the resistor R3 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to one end of the resistor R3, and one end of the resistor R8 and the other end of the resistor R3 form the PWM signal output terminal after adjusting the waveform of the first switching speed adjustment circuit.

[0008] Furthermore, the first spike suppression circuit includes a diode D1 and a diode D2. The cathode of the diode D2 is connected to one end of the resistor R4, the anode of the diode D2 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to one end of the resistor R8, and the cathode of the diode D2 and the cathode of the diode D1 form the spike suppression PWM signal output terminal of the first spike suppression circuit.

[0009] Furthermore, the first compensation circuit includes a resistor R1 and a capacitor C1. A resistor R1 and a capacitor C1 are connected in parallel between the cathode of the diode D1 and the gate of the SiCMOS transistor Q1. Both ends of the resistor R1 form the PWM signal output terminal after waveform compensation of the first compensation circuit.

[0010] Furthermore, the SiCMOS transistor Q1 and the SiCMOS transistor Q2 form a driving half-bridge. The drain of the SiCMOS transistor Q1 is connected to the DC input voltage Vbus, the source of the SiCMOS transistor Q1 is used to connect to the drain of the SiCMOS transistor Q2, the source of the SiCMOS transistor Q2 is grounded to GND, and the gate of the SiCMOS transistor Q2 is controlled by another set of SiCMOS transistor gate drive circuits.

[0011] Further, another set of SiCMOS transistor gate drive circuits includes a second trace interference adjustment circuit, a second switching speed adjustment circuit, a second spike suppression circuit, and a second compensation circuit; the PWM signal input terminal of the second trace interference adjustment circuit is used to connect to the PWM signal output terminal of another PWM signal driver, the PWM signal output terminal of the second trace interference adjustment circuit after eliminating trace interference is connected to the signal input terminal of the second switching speed adjustment circuit, the PWM signal output terminal of the second switching speed adjustment circuit after adjusting the waveform is connected to the signal input terminal of the second spike suppression circuit, the spike suppression PWM signal output terminal of the second spike suppression circuit is connected to the signal input terminal of the second compensation circuit, and the PWM signal output terminal of the second compensation circuit after waveform compensation is used to drive the gate of the SiCMOS transistor.

[0012] Further, the second trace interference adjustment circuit includes a resistor R9, a resistor R10, and a capacitor C4. One end of the resistor R9 is connected to the other end of the resistor R11 of another PWM signal driver, the other end of the resistor R9 is connected to one end of the capacitor C4, the other end of the capacitor C4 is connected to one end of the resistor R10, the other end of the resistor R10 is connected to the ground terminal GND2 of the PWM driving chip of another PWM signal driver, and both ends of the capacitor C4 form the PWM signal output terminal of the second trace interference adjustment circuit after eliminating trace interference.

[0013] The second switching speed adjustment circuit includes a resistor R5, a resistor R6, and a diode D5. One end of the resistor R5 is connected to the other end of the resistor R9, the other end of the resistor R5 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to the anode of the diode D5, the cathode of the diode D5 is connected to one end of the resistor R5, and one end of the resistor R10 and the other end of the resistor R5 form the PWM signal output terminal of the second switching speed adjustment circuit after adjusting the waveform.

[0014] Further, the second spike suppression circuit includes a diode D3 and a diode D6. The cathode of the diode D3 is connected to one end of the resistor R6, the anode of the diode D3 is connected to the anode of the diode D6, the cathode of the diode D6 is connected to one end of the resistor R10, and the cathode of the diode D6 and the cathode of the diode D3 form the spike suppression PWM signal output terminal of the second spike suppression circuit. The second compensation circuit includes a resistor R2 and a capacitor C2. A resistor R2 and a capacitor C2 are connected in parallel between the cathode of the diode D6 and the gate of the SiCMOS transistor Q2, and both ends of the resistor R2 form the PWM signal output terminal of the first compensation circuit after waveform compensation.

[0015] Advantages of the present utility model: The present utility model can suppress the positive spike signal and negative spike signal of the PWM wave signal, effectively suppress the oscillation of the signal, improve the stability and reliability of the drive signal, thereby avoiding the problem of mis-conduction of SiCMOS devices. Moreover, the drive circuit of the present utility model can play a very good role in the parallel use of SiCMOS transistors. In high-power circuits, most SiCMOS transistors are used in parallel, which can reduce costs, but the stability and reliability of the drive signal determine the parallel use of SiCMOS transistors. The present utility model enables the drive signal of the SiCMOS transistor gate to be stably and reliably driven through a simple and reliable peripheral circuit, and can effectively eliminate the instability of the SiCMOS transistor drive signal. Brief Description of the Drawings

[0016] Figure 1 is the circuit diagram of the PWM wave signal driver of the present utility model;

[0017] Figure 2 is the circuit diagram of the drive circuit of the present utility model;

[0018] Figure 3 is the rise and fall time diagram of the PWM wave of the present utility model;

[0019] Figure 4 is the drive trace of the present utility model Figure 1 ;

[0020] Figure 5 is the drive trace of the present utility model Figure 2 ;

[0021] Figure 6 is the drive waveform diagram before improvement of the present utility model;

[0022] Figure 7 is the drive waveform diagram after improvement of the present utility model. Detailed Embodiments

[0023] The following further elaborates on the present utility model in conjunction with the accompanying drawings and specific embodiments:

[0024] As Figure 2The high-reliability SiCMOS transistor gate drive circuit shown includes a first trace interference adjustment circuit, a first switching speed adjustment circuit, a first spike suppression circuit, and a first compensation circuit; the PWM signal input terminal of the first trace interference adjustment circuit is used to connect to the PWM signal output terminal of the PWM signal driver, the PWM signal output terminal after eliminating trace interference of the first trace interference adjustment circuit is connected to the signal input terminal of the first switching speed adjustment circuit, the PWM signal output terminal after adjusting the waveform of the first switching speed adjustment circuit is connected to the signal input terminal of the first spike suppression circuit, the spike suppression PWM signal output terminal of the first spike suppression circuit is connected to the signal input terminal of the first compensation circuit, and the PWM signal output terminal after waveform compensation of the first compensation circuit is used to drive the SiCMOS transistor gate.

[0025] The PWM wave signal driver includes a PWM driver chip, capacitors C5 to C7, electrolytic capacitor C8, resistor R11, and power supply Vc. The negative voltage pin V of the PWM driver chip EE is connected in parallel with capacitors C5 and C6 between the ground pin GND2, and the negative voltage pin V of the PWM driver chip EE is connected in parallel with capacitor C7, electrolytic capacitor C8, and power supply Vc between the power supply pin V of the PWM driver chip CC The positive pole of the power supply Vc is connected to the power supply pin V of the PWM driver chip CC The negative pole of the power supply Vc is connected to the negative voltage pin V of the PWM driver chip EE The positive pole of the electrolytic capacitor C8 is connected to the positive pole of the power supply Vc, the negative pole of the electrolytic capacitor C8 is connected to the negative pole of the power supply Vc, one end of the resistor R11 is connected to the output pin OUT of the PWM driver chip, and the other end of the resistor R11 and the ground terminal GND2 of the PWM driver chip form the PWM signal output terminal of the PWM wave signal driver.

[0026] Such as Figure 1As shown, the PWM wave signal driver uses the NCP51752 drive chip of ON Semiconductor. There are two capacitors respectively between the VEE pin and the GND2 pin and between the VCC pin and the VEE pin of the ON Semiconductor NCP51752 drive chip. The capacitors C5 and C6 between the VEE pin and the GND2 pin and the capacitors C7 and electrolytic capacitor C8 between the VCC pin and the VEE pin are preferably in the form of one large and one small and placed as close as possible to the chip pins. It is only necessary to keep one large and one small in terms of capacitance. The VCC pin is powered externally, and the VEE pin can provide a negative voltage for the drive signal. When the SiCMOS transistor is turned off, the voltage of the drive signal will be clamped to the negative voltage of the VEE pin for reliable turn-off. The external power supply Vc of the VCC pin provides a positive voltage for the drive signal to drive the conduction of the SiCMOS transistor. In addition, when placing the drive chip in the PCB layout, it should be placed as close as possible to the MOS transistor. Similarly, other similar drive chips can be connected and laid out on the PCB in this way.

[0027] The first trace interference adjustment circuit includes a resistor R7, a resistor R8, and a capacitor C3. One end of the resistor R7 is connected to the other end of the resistor R11, the other end of the resistor R7 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the ground terminal GND2 of the PWM drive chip. Both ends of the capacitor C3 form the PWM signal output terminal after eliminating the trace interference of the first trace interference adjustment circuit.

[0028] In the first trace interference adjustment circuit, the values of R7 and R8 can be flexibly selected according to the actual situation, or two zero-ohm beads can be used for impedance matching of the circuit. It can be understood as a high-pass filter of the resistor and the capacitor. By filtering, some peak voltages of the PWM wave become smaller. It is recommended that the value of the capacitor C3 does not exceed 1 nF, and it can be selected according to the parameters of the SiCMOS transistor. If the value is too large, it mainly affects the turn-on speed of the SiCMOS transistor and thus affects the efficiency.

[0029] The first switching speed adjustment circuit includes a resistor R3, a resistor R4, and a diode D4. One end of the resistor R3 is connected to the other end of the resistor R7, the other end of the resistor R3 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to one end of the resistor R3, and one end of the resistor R8 and the other end of the resistor R3 form the PWM signal output terminal after adjusting the waveform of the first switching speed adjustment circuit.

[0030] In the first switching speed adjustment circuit, R3 and R4 can be flexibly and reasonably matched according to the actual driving waveform and the parameters of the SiCMOS transistor. In addition, the diode D4 is usually a fast-recovery Schottky diode, and the parasitic capacitance of the diode also affects the driving waveform. The resistor R3 mainly limits the magnitude of the driving current, thereby changing the rise time of the PWM wave to obtain the waveform and rise time we need. The resistor R4 and the diode D4 form a discharge circuit for the PWM wave. By adjusting the size of the resistor R4, the fall time of the PWM wave can be adjusted, so as to obtain the fall time and waveform we want. As Figure 3 shown, as the resistance value of the resistor R3 increases, the rise time of the PWM wave slows down. As the resistance value of the resistor R4 increases, the fall time of the PWM wave slows down.

[0031] The first spike suppression circuit includes a diode D1 and a diode D2. Among them, the cathode of the diode D2 is connected to one end of the resistor R4, the anode of the diode D2 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to one end of the resistor R8, and the cathode of the diode D2 and the cathode of the diode D1 form the spike suppression PWM signal output end of the first spike suppression circuit.

[0032] The zener diodes D2 and D1 are usually fast-recovery zener diodes, which can effectively stabilize the voltage for high-frequency switching signals. For example, the voltage range between the gate and source of the SiCMOS transistor is usually -10V to 22V. Then, a zener diode with a voltage of about 5V can be selected for D1. Since the full-conduction voltage of the SiCMOS transistor usually needs to be about 18V, a zener diode with a voltage of about 19 - 20V can be selected for D2. When the positive spike voltage of the PWM wave is too large, it can be clamped by the zener diode D2 to control the positive spike at the voltage spike we want. When the negative spike voltage of the PWM wave is too large, it can be clamped by the zener diode D1 to control the positive spike at the voltage spike we want.

[0033] The first compensation circuit includes a resistor R1 and a capacitor C1. Among them, the resistor R1 and the capacitor C1 are connected in parallel between the cathode of the diode D1 and the gate of the SiCMOS transistor Q1, and both ends of the resistor R1 form the PWM signal output end after waveform compensation of the first compensation circuit.

[0034] Currently, the SiCMOS transistor has two source electrodes, one connected to the ground wire and the other connected to the driver. The value of the resistor R1 is usually between 10K and 50K. Usually, when the driver has no output, it further ensures that the power device Q1 is in the off state. When the driver has not yet started working, it ensures that the gate voltage of the power device Q1 does not exceed the turn-on threshold. The value of the capacitor C1 is mainly matched with C3. For most SiCMOS transistors, the total capacitance is not recommended to exceed 1nF. Additionally, during PCB layout, it should be placed as close as possible to the SiCMOS transistor.

[0035] The SiCMOS transistor Q1 and the SiCMOS transistor Q2 form a driving half-bridge. The drain of the SiCMOS transistor Q1 is connected to the DC input voltage Vbus. The source of the SiCMOS transistor Q1 is used to connect to the drain of the SiCMOS transistor Q2. The source of the SiCMOS transistor Q2 is grounded to GND. The gate of the SiCMOS transistor Q2 is controlled by another set of SiCMOS transistor gate drive circuits.

[0036] The SiCMOS transistor Q1 in the circuit is usually referred to as floating ground drive, and Q2 is usually ground drive. The drive circuit for Q2 is the same as that for Q1, as Figure 2 shown. Among them, the drain of the SiCMOS transistor Q1 is connected to the supply voltage Vbus. The source of the SiCMOS transistor Q1 is connected to the drain of the SiCMOS transistor Q2. The source of the SiCMOS transistor Q2 is connected to the ground. The SiCMOS transistor Q1 and the SiCMOS transistor Q2 form a half-bridge configuration. The circuit of the present utility model can be applied to the drive of half-bridges, full-bridges, or individual MOS transistors, etc.

[0037] Another set of SiCMOS transistor gate drive circuits includes a second trace interference adjustment circuit, a second switching speed adjustment circuit, a second spike suppression circuit, and a second compensation circuit. The PWM signal input terminal of the second trace interference adjustment circuit is used to connect to the PWM signal output terminal of another PWM signal driver. The PWM signal output terminal of the second trace interference adjustment circuit after eliminating trace interference is connected to the signal input terminal of the second switching speed adjustment circuit. The PWM signal output terminal of the second switching speed adjustment circuit after adjusting the waveform is connected to the signal input terminal of the second spike suppression circuit. The spike suppression PWM signal output terminal of the second spike suppression circuit is connected to the signal input terminal of the second compensation circuit. The PWM signal output terminal of the second compensation circuit after waveform compensation is used to drive the SiCMOS transistor gate.

[0038] The second trace interference adjustment circuit includes a resistor R9, a resistor R10, and a capacitor C4. One end of the resistor R9 is connected to the other end of a resistor R11 of another PWM signal driver. The other end of the resistor R9 is connected to one end of the capacitor C4. The other end of the capacitor C4 is connected to one end of the resistor R10. The other end of the resistor R10 is connected to the ground terminal GND2 of the PWM driver chip of another PWM signal driver. Both ends of the capacitor C4 form the PWM signal output terminal after eliminating trace interference of the second trace interference adjustment circuit.

[0039] The second switching speed adjustment circuit includes a resistor R5, a resistor R6, and a diode D5. One end of the resistor R5 is connected to the other end of the resistor R9. The other end of the resistor R5 is connected to one end of the resistor R6. The other end of the resistor R6 is connected to the anode of the diode D5. The cathode of the diode D5 is connected to one end of the resistor R5. One end of the resistor R10 and the other end of the resistor R5 form the PWM signal output terminal after adjusting the waveform of the second switching speed adjustment circuit.

[0040] The second spike suppression circuit includes a diode D3 and a diode D6. The cathode of the diode D3 is connected to one end of the resistor R6. The anode of the diode D3 is connected to the anode of the diode D6. The cathode of the diode D6 is connected to one end of the resistor R10. The cathode of the diode D6 and the cathode of the diode D3 form the spike suppression PWM signal output terminal of the second spike suppression circuit. The second compensation circuit includes a resistor R2 and a capacitor C2. A resistor R2 and a capacitor C2 are connected in parallel between the cathode of the diode D6 and the gate of the SiCMOS transistor Q2. Both ends of the resistor R2 form the PWM signal output terminal after waveform compensation of the second compensation circuit.

[0041] When connecting the output of the PWM wave signal driver and the input of the trace interference adjustment circuit, the following basic principles should be followed: The trace should be as thick as possible on the basis of meeting the overcurrent requirement, the trace distance should be as short as possible, and the trace of the drive signal needs to be in the differential trace mode. The differential trace mode has strong anti-interference ability, and the coupling between the two differential traces is very good. When there is noise interference from the outside world, it is almost simultaneously coupled to both lines, so the common-mode noise from the outside world can be basically completely cancelled. As shown in Figure 4 where Figure 5 is a relatively poor trace mode, with a thin trace and a large surrounding area, poor anti-interference ability, and is easily interfered.

[0042] After comprehensive optimization through the effective measures of the present utility model, the drive signal can reach an ideal state. The drive signal waveform before optimization and improvement is as shown in Figure 6As shown, near the rising edge and falling edge of the driving signal waveform, that is, in the time periods of t1 to t2 and t3 to t4, the oscillation and spike phenomena of the driving signal waveform can be clearly seen. After the optimization of the gate driving circuit of this SiCMOS transistor, the improved driving signal waveform can be clearly seen, as Figure 7 shown. In the time periods of t5 to t5' and t6 to t6', the oscillation and spike phenomena of the driving signal waveform can be seen to be significantly reduced, making the signal more stable and enabling the SiCMOS transistor to work safely and reliably.

[0043] The above are only the preferred embodiments of the present invention, and do not impose any formal restrictions on the structure of the present invention. Any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

[0044] The content not detailed in this specification belongs to the prior art well known to those skilled in the art.

Claims

1. A high-reliability SiCMOS gate drive circuit, characterized in that: It includes a first trace interference adjustment circuit, a first switching speed adjustment circuit, a first spike suppression circuit, and a first compensation circuit; the PWM signal input terminal of the first trace interference adjustment circuit is used to connect to the PWM signal output terminal of the PWM signal driver, the PWM signal output terminal after eliminating trace interference of the first trace interference adjustment circuit is connected to the signal input terminal of the first switching speed adjustment circuit, the PWM signal output terminal after adjusting the waveform of the first switching speed adjustment circuit is connected to the signal input terminal of the first spike suppression circuit, the spike suppression PWM signal output terminal of the first spike suppression circuit is connected to the signal input terminal of the first compensation circuit, and the PWM signal output terminal after waveform compensation of the first compensation circuit is used to drive the gate of the SiCMOS transistor.

2. The high-reliability SiCMOS transistor gate drive circuit according to claim 1, wherein: The PWM wave signal driver includes a PWM driving chip, capacitors C5 to C7, electrolytic capacitor C8, resistor R11 and power supply Vc. The negative voltage pin V of the PWM driving chip EE is connected in parallel with capacitors C5 and C6 between the ground pin GND2. The negative voltage pin V of the PWM driving chip EE is connected in parallel with the power pin V of the PWM driving chip CC between which are connected in parallel capacitor C7, electrolytic capacitor C8 and power supply Vc. The positive pole of power supply Vc is connected to the power pin V of the PWM driving chip CC , and the negative pole of power supply Vc is connected to the negative voltage pin V of the PWM driving chip EE . The positive pole of electrolytic capacitor C8 is connected to the positive pole of power supply Vc, and the negative pole of electrolytic capacitor C8 is connected to the negative pole of power supply Vc. One end of resistor R11 is connected to the output pin OUT of the PWM driving chip, and the other end of resistor R11 and the ground terminal GND2 of the PWM driving chip form the PWM signal output terminal of the PWM wave signal driver.

3. The high-reliability SiCMOS transistor gate drive circuit according to claim 2, characterized in that: The first trace interference adjustment circuit includes a resistor R7, a resistor R8, and a capacitor C3. One end of the resistor R7 is connected to the other end of the resistor R11, the other end of the resistor R7 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to one end of the resistor R8, the other end of the resistor R8 is connected to the ground terminal GND2 of the PWM driver chip, and both ends of the capacitor C3 form the PWM signal output terminal after eliminating trace interference of the first trace interference adjustment circuit.

4. A highly reliable SiCMOS transistor gate drive circuit according to claim 3, characterized in that: The first switching speed adjustment circuit includes a resistor R3, a resistor R4, and a diode D4. One end of the resistor R3 is connected to the other end of the resistor R7, the other end of the resistor R3 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to the anode of the diode D4, the cathode of the diode D4 is connected to one end of the resistor R3, and one end of the resistor R8 and the other end of the resistor R3 form the PWM signal output terminal after adjusting the waveform of the first switching speed adjustment circuit.

5. A high-reliability SiCMOS transistor gate drive circuit according to claim 4, characterized in that: The first spike suppression circuit includes a diode D1 and a diode D2. The cathode of the diode D2 is connected to one end of the resistor R4, the anode of the diode D2 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to one end of the resistor R8, and the cathode of the diode D2 and the cathode of the diode D1 form the spike suppression PWM signal output terminal of the first spike suppression circuit.

6. The high-reliability SiCMOS transistor gate drive circuit according to claim 5, characterized in that: The first compensation circuit includes a resistor R1 and a capacitor C1. A resistor R1 and a capacitor C1 are connected in parallel between the cathode of the diode D1 and the gate of the SiCMOS transistor Q1, and both ends of the resistor R1 form the PWM signal output terminal after waveform compensation of the first compensation circuit.

7. The high-reliability SiCMOS transistor gate drive circuit according to claim 6, characterized in that: The SiCMOS transistor Q1 and the SiCMOS transistor Q2 form a driving half-bridge. The drain of the SiCMOS transistor Q1 is connected to the DC input voltage Vbus, the source of the SiCMOS transistor Q1 is used to connect to the drain of the SiCMOS transistor Q2, the source of the SiCMOS transistor Q2 is grounded to GND, and the gate of the SiCMOS transistor Q2 is controlled by another SiCMOS transistor gate driving circuit.

8. A highly reliable SiCMOS transistor gate drive circuit according to claim 7, characterized in that: Another set of SiCMOS transistor gate drive circuits includes a second trace interference adjustment circuit, a second switching speed adjustment circuit, a second spike suppression circuit, and a second compensation circuit; the PWM signal input terminal of the second trace interference adjustment circuit is used to connect the PWM signal output terminal of another PWM signal driver, and the PWM signal output terminal of the second trace interference adjustment circuit after eliminating trace interference is connected to the signal input terminal of the second switching speed adjustment circuit. The PWM signal output terminal of the second switching speed adjustment circuit after adjusting the waveform is connected to the signal input terminal of the second spike suppression circuit. The spike suppression PWM signal output terminal of the second spike suppression circuit is connected to the signal input terminal of the second compensation circuit, and the PWM signal output terminal of the second compensation circuit after waveform compensation is used to drive the SiCMOS transistor gate.

9. A high-reliability SiCMOS transistor gate drive circuit according to claim 8, characterized in that: The second trace interference adjustment circuit includes resistor R9, resistor R10, and capacitor C4. One end of resistor R9 is connected to the other end of resistor R11 of another PWM signal driver. The other end of resistor R9 is connected to one end of capacitor C4. The other end of capacitor C4 is connected to one end of resistor R10. The other end of resistor R10 is connected to the ground terminal GND2 of the PWM driver chip of another PWM signal driver. Both ends of capacitor C4 form the PWM signal output terminal of the second trace interference adjustment circuit after eliminating trace interference. The second switching speed adjustment circuit includes resistor R5, resistor R6, and diode D5. One end of resistor R5 is connected to the other end of resistor R9. The other end of resistor R5 is connected to one end of resistor R6. The other end of resistor R6 is connected to the anode of diode D5. The cathode of diode D5 is connected to one end of resistor R5. One end of resistor R10 and the other end of resistor R5 form the PWM signal output terminal of the second switching speed adjustment circuit after adjusting the waveform.

10. A high-reliability SiCMOS transistor gate drive circuit according to claim 9, characterized in that: The second spike suppression circuit includes diode D3 and diode D6. The cathode of diode D3 is connected to one end of resistor R6. The anode of diode D3 is connected to the anode of diode D6. The cathode of diode D6 is connected to one end of resistor R10. The cathode of diode D6 and the cathode of diode D3 form the spike suppression PWM signal output terminal of the second spike suppression circuit. The second compensation circuit includes resistor R2 and capacitor C2. A resistor R2 and a capacitor C2 are connected in parallel between the cathode of diode D6 and the gate of SiCMOS transistor Q2. Both ends of resistor R2 form the PWM signal output terminal of the second compensation circuit after waveform compensation.

Images