N-type heterojunction cell and photovoltaic module

Abstract

The utility model provides an N-type heterojunction cell and a photovoltaic module, and relates to the technical field of solar cells. The N-type heterojunction battery comprises a silicon substrate, and the silicon substrate is provided with a first surface and a second surface which are oppositely arranged. An aluminum oxide layer, a front doping layer, a front transparent conductive oxide layer and a first metal electrode are sequentially stacked on the first surface. And a back intrinsic layer, a back doping layer, a back transparent conductive oxide layer and a second metal electrode are sequentially laminated on the second surface. The cell structure is beneficial for ensuring the forbidden band width of the passivation layer and improving the cell efficiency.

Description

Technical Field

[0001] The utility model relates to the technical field of solar cells, and more specifically, to an N-type heterojunction cell and a photovoltaic module. Background Art

[0002] The crystalline silicon heterojunction solar cell (Hetero junction Technology, HJT) deposits an amorphous silicon thin film on crystalline silicon. It combines the advantages of crystalline silicon cells and thin film cells, and has the characteristics of simple structure, low process temperature, good passivation effect, etc.

[0003] Taking the N-type heterojunction cell as an example, the middle is an N-type silicon substrate. On the front surface of the silicon substrate, an intrinsic amorphous silicon thin film and a P-type microcrystalline silicon thin film are sequentially deposited to form a P-N junction. On the back surface of the silicon substrate, an intrinsic amorphous silicon thin film and an N-type microcrystalline silicon thin film are sequentially deposited to form a back surface field. And transparent conductive thin films are deposited on both sides of the cell for conduction. Finally, double-sided metal electrodes are formed on the transparent conductive thin films.

[0004] After research by the inventor, it is found that in the existing heterojunction cell structure, the doping layer mostly uses microcrystalline silicon. Due to the complex manufacturing process of microcrystalline silicon, the costs of various equipment and processes are relatively high, and the energy consumption is high, which is not conducive to environmental protection and energy conservation. Summary of the Utility Model

[0005] The purpose of the utility model is to provide an N-type heterojunction cell and a photovoltaic module, which can simplify the process difficulty, reduce energy consumption, reduce production costs, and improve the conversion efficiency of the cell.

[0006] The embodiments of the utility model are implemented as follows:

[0007] In a first aspect, the utility model provides an N-type heterojunction cell, including:

[0008] A silicon substrate having a first surface and a second surface disposed opposite to each other;

[0009] An alumina layer, a front doping layer, a front transparent conductive oxide layer, and a first metal electrode are sequentially stacked on the first surface;

[0010] Wherein, the front doping layer includes a P-type polysilicon layer and a P-type polycrystalline silicon carbide layer. The P-type polysilicon layer is located on the side of the alumina layer away from the silicon substrate; the P-type polycrystalline silicon carbide layer is located on the side of the P-type polysilicon layer away from the alumina layer;

[0011] A back intrinsic layer, a back doping layer, a back transparent conductive oxide layer, and a second metal electrode are sequentially stacked on the second surface.

[0012] In an alternative embodiment, the thickness ratio of the alumina layer to the front doping layer is from 1:3 to 1:20. Such a setting is conducive to improving the passivation effect, ensuring the bandgap width, and enhancing the cell efficiency.

[0013] In an alternative embodiment, the thickness of the alumina layer is 5 nm to 15 nm.

[0014] In an alternative embodiment, the thickness of the front doping layer is 20 nm to 45 nm.

[0015] In an alternative embodiment, the thickness ratio of the p-type polysilicon layer to the p-type polycrystalline silicon carbide layer is from 1:0.5 to 1:1.5.

[0016] In an alternative embodiment, the thickness of the p-type polysilicon layer is 10 nm to 30 nm.

[0017] In an alternative embodiment, the thickness of the p-type polycrystalline silicon carbide layer is 15 nm to 20 nm. With such a setting, the refractive index of the p-type polysilicon layer is higher and the refractive index of the p-type polycrystalline silicon carbide layer is lower. The refractive index of the front doping layer decreases from bottom to top, which is conducive to enhancing the light absorption ability. It can improve the carrier mobility, achieve a higher open-circuit voltage, and increase the photoelectric conversion efficiency.

[0018] In an alternative embodiment, the back intrinsic layer is a hydrogenated amorphous silicon carbide layer, and the thickness of the back intrinsic layer is 3 nm to 15 nm. With such a setting, double-sided passivation of the silicon substrate is achieved, and the passivation effect is better. It can reduce interface defects and bulk recombination, improve the carrier mobility, achieve a higher open-circuit voltage, and increase the photoelectric conversion efficiency.

[0019] In an alternative embodiment, the back doping layer is a hydrogenated microcrystalline silicon carbide layer, and the thickness of the back doping layer is 10 nm to 50 nm.

[0020] In an alternative embodiment, the thickness of the back transparent conductive oxide layer is greater than that of the front transparent conductive oxide layer.

[0021] In an alternative embodiment, the thickness of the silicon substrate is 80 μm to 180 μm.

[0022] In a second aspect, the present utility model provides a photovoltaic module, including a battery string, and encapsulation adhesive films respectively disposed on two sides of the battery string. The battery string includes a plurality of N-type heterojunction cells as described in any one of the foregoing embodiments, and the plurality of N-type heterojunction cells are connected in series in sequence.

[0023] The beneficial effects of the embodiments of the present utility model include:

[0024] The N-type heterojunction battery provided by the embodiment of the present utility model has a stacked structure of a P-type polysilicon layer and a P-type polycrystalline silicon carbide layer for the front doping layer. By using polysilicon instead of the existing microcrystalline silicon, the process difficulty is reduced, the equipment and process costs for preparing polysilicon are lower, the energy consumption is lower, and more significant economic benefits can be achieved in mass production. In addition, a carbon-containing P-type polycrystalline silicon carbide layer is adopted in the front doping layer, so that the front doping layer has the characteristic of a high refractive index at the bottom layer, which is beneficial to increasing the light absorption capacity. And an alumina layer is used as a passivation layer, with better passivation effect, which can improve the carrier mobility, achieve a higher open-circuit voltage, and improve the photoelectric conversion efficiency.

[0025] The photovoltaic module provided by the embodiment of the present utility model includes the above-mentioned N-type heterojunction battery. On the premise of ensuring the band gap width and battery efficiency, it can also reduce the process difficulty, reduce the equipment cost and process cost, have lower energy consumption, have more significant economic benefits in mass production, and be beneficial to energy conservation and environmental protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present utility model, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 It is a schematic structural diagram of the N-type heterojunction battery provided by the embodiment of the present utility model.

[0028] Reference numerals: 100 - N-type heterojunction battery; 110 - silicon substrate; 111 - first surface; 112 - second surface; 120 - alumina layer; 130 - front doping layer; 131 - P-type polysilicon layer; 132 - P-type polycrystalline silicon carbide layer; 141 - front transparent conductive oxide layer; 151 - first metal electrode; 160 - back intrinsic layer; 170 - back doping layer; 142 - back transparent conductive oxide layer; 152 - second metal electrode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the drawings in the embodiments of the present utility model. Obviously, the described embodiments are some, but not all, of the embodiments of the present utility model. Usually, the components of the embodiments of the present utility model described and illustrated in the drawings here can be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the present utility model provided in the accompanying drawings is not intended to limit the scope of the present utility model claimed, but merely represents selected embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present utility model without creative efforts shall fall within the scope of protection of the present utility model.

[0031] It should be noted that like reference numerals and letters denote like items in the following drawings, and thus, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings.

[0032] In the description of the present utility model, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the utility model product is usually placed during use. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present utility model. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0033] In addition, terms such as "horizontal" and "vertical" do not mean that the components are required to be absolutely horizontal or hanging, but can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0034] In the description of the present utility model, it should also be noted that unless otherwise clearly specified and defined, the terms "set", "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0035] In the existing heterojunction battery structure, the front doping layer mostly uses microcrystalline silicon. Due to the complex manufacturing process of microcrystalline silicon, the costs of various equipment and processes are relatively high, and the energy consumption is relatively high, which is not conducive to environmental protection and energy conservation.

[0036] In order to overcome at least one defect in the prior art, this embodiment proposes an N-type heterojunction battery, which can simplify the process difficulty, reduce the energy consumption, reduce the production cost, and improve the battery conversion efficiency.

[0037] Please refer to Figure 1 , this embodiment provides an N-type heterojunction battery 100, which includes a silicon substrate 110 having a first surface 111 and a second surface 112 disposed opposite to each other. An alumina layer 120, a front doping layer 130, a front transparent conductive oxide layer 141, and a first metal electrode 151 are sequentially stacked on the first surface 111. Among them, the front doping layer 130 includes a P-type polysilicon layer 131 and a P-type polycrystalline silicon carbide layer 132. The P-type polysilicon layer 131 is located on the side of the alumina layer 120 away from the silicon substrate 110; the P-type polycrystalline silicon carbide layer 132 is located on the side of the P-type polysilicon layer 131 away from the alumina layer 120. A back intrinsic layer 160, a back doping layer 170, a back transparent conductive oxide layer 142, and a second metal electrode 152 are sequentially stacked on the second surface 112. In this battery structure, the front doping layer 130 adopts a stacked structure of a P-type polysilicon layer 131 and a P-type polycrystalline silicon carbide layer 132. Using polysilicon instead of the existing microcrystalline silicon reduces the process difficulty. The equipment and process costs for preparing polysilicon are lower, and the energy consumption is lower, which has more significant economic benefits in mass production. In addition, the P-type polycrystalline silicon carbide layer 132 containing carbon is used in the front doping layer 130, making the front doping layer 130 have the characteristic of a high refractive index at the bottom layer, which is beneficial to increasing the light absorption ability. And the alumina layer 120 is used as a passivation layer, and the passivation effect is better, which is beneficial to ensuring the band gap width of the passivation layer, can improve the carrier mobility, realize a higher open circuit voltage, and improve the photoelectric conversion efficiency.

[0038] Optionally, the thickness ratio of the alumina layer 120 to the front doping layer 130 is 1:3 to 1:20. For example, the thickness ratio of the alumina layer 120 to the front doping layer 130 can be 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:8.5, 1:9, 1:10, 1:15, 1:18, or 1:19, etc. Or, in some embodiments, the thickness of the alumina layer 120 is 0.05 times to 0.35 times the thickness of the front doping layer 130.

[0039] Optionally, the thickness of the alumina layer 120 is 5 nm to 15 nm. For example, the thickness of the alumina layer 120 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 13.5 nm, 14 nm, 14.5 nm, or 15 nm, etc.

[0040] Optionally, the thickness of the front doping layer 130 is 20 nm to 45 nm. For example, the thickness of the front doping layer 130 is 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 30 nm, 32 nm, 35 nm, 36 nm, 38 nm, 40 nm, 42 nm, 43 nm, 44 nm or 45 nm, etc.

[0041] Optionally, the thickness ratio of the P-type polysilicon layer 131 to the P-type polycrystalline silicon carbide layer 132 is 1:0.5 to 1:1.5.

[0042] The thickness of the P-type polysilicon layer 131 is 10 nm to 30 nm. For example, the thickness of the P-type polysilicon layer 131 is 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 18 nm, 20 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm or 30 nm, etc.

[0043] The thickness of the P-type polycrystalline silicon carbide layer 132 is 15 nm to 20 nm. For example, the thickness of the P-type polycrystalline silicon carbide layer 132 is 15 nm, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm, etc.

[0044] It should be noted that in this embodiment, the refractive index of the P-type polysilicon layer 131 is higher, and the refractive index of the P-type polycrystalline silicon carbide layer 132 is lower. The P-type polysilicon layer 131 is closer to the first surface 111 of the silicon substrate 110 than the P-type polycrystalline silicon carbide layer 132. With this setting, the refractive index of the front doping layer 130 decreases from bottom to top, which is beneficial to improving the light absorption ability.

[0045] In some embodiments, the number of layers of the front doping layer 130 is not limited to two layers, and can also be three layers, four layers, five layers or more layers. For example, two P-type polysilicon layers 131 and two P-type polycrystalline silicon carbide layers 132 can be sequentially stacked on the alumina layer 120, as long as the refractive index of the front doping layer 130 decreases from bottom to top.

[0046] The material of the front transparent conductive oxide layer 141 includes but is not limited to indium tin oxide (ITO) thin film, indium tungsten oxide (IWO) thin film, indium titanium oxide (ITiO) thin film or aluminum zinc oxide (AZO) thin film. Optionally, the thickness of the front transparent conductive oxide layer 141 is 60 nm to 100 nm. For example, the thickness of the front transparent conductive oxide layer 141 is 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm or 100 nm, etc.

[0047] Similarly, the material of the back transparent conductive oxide layer 142 is the same as or similar to that of the front transparent conductive oxide layer 141. The material of the back transparent conductive oxide layer 142 includes, but is not limited to, indium tin oxide (ITO) thin film, indium tungsten oxide (IWO) thin film, indium titanium oxide (ITiO) thin film, or aluminum zinc oxide (AZO) thin film.

[0048] Optionally, the thickness of the back transparent conductive oxide layer 142 is greater than that of the front transparent conductive oxide layer 141. The thickness of the back transparent conductive oxide layer 142 is 70 nm to 120 nm. For example, the thickness of the back transparent conductive oxide layer 142 is 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, or 120 nm, etc.

[0049] The back transparent conductive oxide layer 142 and the front transparent conductive oxide layer 141 can be formed by deposition methods such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or RPD (Reactive Plasma Deposition), etc., without specific limitation here.

[0050] It should be noted that the transparent conductive oxide layer (TCO) can play the roles of conducting electricity, antireflection, and protecting the front doping layer 130 and the back doping layer 170 as an outer protective film. It can be understood that the transparent conductive oxide layer has the dual functions of optical transparency and conductivity, can effectively increase the collection of carriers, plays a key role in the collection of effective carriers, can reduce the reflection of light, plays a good light trapping role, and is beneficial to improving the battery efficiency.

[0051] Of course, in some embodiments, the front transparent conductive oxide layer 141 and the back transparent conductive oxide layer 142 can be single-layer, two-layer, three-layer, four-layer, five-layer, or more-layer structures respectively, without specific limitation here.

[0052] Optionally, the back intrinsic layer 160 is a hydrogenated amorphous silicon carbide layer, and the thickness of the back intrinsic layer 160 is 3 nm to 15 nm. For example, the thickness of the back intrinsic layer 160 is 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm, etc. The back intrinsic layer 160 adopts a hydrogenated amorphous silicon carbide layer a-SiC:H(i), as an intrinsic passivation layer, which can play a good passivation role, can improve the minority carrier lifetime in the silicon substrate 110, reduce interface defects and bulk recombination, and reduce the influence of the band mismatch existing at the heterojunction interface on carrier transport, which is beneficial to increasing the open circuit voltage.

[0053] In this embodiment, the aluminum oxide layer 120 on the front side of the silicon substrate 110 and the hydrogenated amorphous silicon carbide layer on the back side achieve double-sided passivation, which can reduce interface defects and bulk recombination, improve the carrier mobility, achieve a higher open-circuit voltage, and enhance the photoelectric conversion efficiency.

[0054] Optionally, the back doping layer 170 is a hydrogenated microcrystalline silicon carbide layer uc-SiC:H(n+), and the thickness of the back doping layer 170 is 10 nm to 50 nm. For example, the thickness of the hydrogenated microcrystalline silicon carbide layer is 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, or any value in the range of 10 nm to 50 nm. Using the hydrogenated microcrystalline silicon carbide layer is beneficial to ensure the bandgap width of the passivation layer and improve the cell efficiency.

[0055] In some embodiments, the back doping layer 170 can be a single-layer, double-layer, triple-layer, quadruple-layer, quintuple-layer, or more-layer structure. The back doping layer 170 can be a hydrogenated microcrystalline silicon carbide layer, or a combination of at least one or more of a hydrogenated amorphous silicon carbide layer, a hydrogenated amorphous silicon layer, a hydrogenated microcrystalline silicon carbide layer, a hydrogenated microcrystalline silicon layer, a hydrogenated polycrystalline silicon carbide layer, a hydrogenated polycrystalline silicon layer, a polycrystalline silicon carbide layer, and a polycrystalline silicon layer.

[0056] Optionally, the thickness of the silicon substrate 110 is 80 μm to 180 μm. For example, the thickness of the silicon substrate 110 is 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, or any other value in the range of 80 μm to 180 μm.

[0057] In this embodiment, an N-type silicon substrate 110 is used, such as Figure 1The c-Si(n) cell has a front junction. An alumina layer 120 is formed on the front surface, i.e., the first surface 111, of the silicon substrate 110 to play a passivation role. A hydrogenated amorphous silicon carbide layer is formed on the back surface, i.e., the second surface 112, of the silicon substrate 110 to play a passivation role. A double-sided passivation effect is achieved to ensure the bandgap width of the passivation layer. Among them, alumina is an excellent P-type passivation material. When paired with the N-type silicon substrate 110, the passivation layer itself can have field passivation ability. A stacked structure of a poly-Si(P+) P-type polysilicon layer 131 and a poly-SiC(P+) P-type polycrystalline silicon carbide layer 132 is formed on the side of the alumina layer 120 away from the silicon substrate 110. Since the polycrystalline silicon carbide layer is introduced, the addition of carbon elements is beneficial to increasing the bandgap width. Moreover, the P-type polycrystalline silicon carbide layer 132 has a lower refractive index than the P-type polysilicon layer 131, which is beneficial to increasing the light absorption ability, improving the carrier mobility, and achieving a higher open-circuit voltage. In addition, in this embodiment, the front doping layer 130 uses polysilicon and polycrystalline silicon carbide to replace the microcrystalline silicon in the existing structure. The manufacturing technology is simpler, the process difficulty is lower, the production efficiency is higher, the production cost is lower, the energy consumption is lower, it is more conducive to energy conservation and environmental protection, and it has significant economic benefits in mass production.

[0058] It can be understood that in this embodiment, the alumina layer 120 is used as the passivation layer, and the front doping layer 130 composed of the stacked structure of the P-type polysilicon layer 131 and the P-type polycrystalline silicon carbide layer 132 has excellent passivation effects, ensures the bandgap width, is beneficial to improving the carrier mobility, improving the battery efficiency, and thus achieving a higher open-circuit voltage. At the same time, a hydrogenated amorphous silicon carbide layer a-SiC:H(i) is used as the passivation layer on the back surface of the silicon substrate 110 to achieve a double-sided passivation effect. A hydrogenated microcrystalline silicon carbide layer uc-SiC:H(n+) is used as the back doping layer 170 on the side of the hydrogenated amorphous silicon carbide layer away from the silicon substrate 110. While ensuring the bandgap width of the passivation layer and the battery efficiency, the equipment cost is greatly reduced, and the energy consumption of polysilicon is lower than that of microcrystalline silicon during the production process, which is more energy-saving and environmentally friendly.

[0059] The preparation method of the N-type heterojunction battery 100 provided by the embodiment of the present invention is as follows:

[0060] (1) Cleaning and texturing

[0061] Select the silicon substrate 110. Optionally, an N-type silicon substrate 110 is used. The thickness of the silicon substrate 110 is 80 um to 180 um. The resistivity of the silicon substrate 110 is 0.1 Ω·cm to 10 Ω·cm.

[0062] Clean the silicon substrate 110. After the cleaning process, organic contaminants, metal impurities, and the surface damaged layer on the silicon wafer surface are removed. The clean surface of the silicon substrate 110 can reduce the defects and impurities introduced due to surface uncleanliness, thereby reducing the recombination loss of carriers at the junction interface.

[0063] After cleaning, texture the silicon substrate 110 to form a textured layer on the first surface 111 (front side) and the second surface 112 (back side) of the silicon substrate 110 respectively. The textured layer is conducive to multiple reflections and refractions of incident light on the surface, prolonging the optical path and increasing the photo-generated carriers.

[0064] (2) Passivation and doping layer deposition

[0065] Deposit an aluminum oxide film as a passivation layer on the first surface 111 of the silicon substrate 110 by using Plasma Enhanced Chemical Vapor Deposition (PECVD), Hot Wire Chemical Vapor Deposition (HWCVD), Low Pressure Chemical Vapor Deposition (LPCVD), or RF Plasma-Enhanced Chemical Vapor Deposition (RFPECVD) technology. Excellent surface passivation ability is an important condition for obtaining high cell efficiency. By utilizing the excellent passivation effect of the aluminum oxide layer 120, the minority carrier lifetime of the silicon substrate 110 can be significantly improved. Optionally, the deposition thickness of the aluminum oxide layer 120 is 5 nm to 15 nm.

[0066] Form a front doping layer 130 on the side of the aluminum oxide layer 120 away from the silicon substrate 110 by using PECVD, HWCVD, or LPCVD technology. Optionally, the deposition thickness of the front doping layer 130 is 20 nm to 45 nm. Among them, the front doping layer 130 includes a P-type polysilicon layer 131 and a P-type polycrystalline silicon carbide layer 132.

[0067] Optionally, first deposit a-Si:H(p+) on the aluminum oxide layer 120, and then perform a high-temperature annealing treatment at an annealing temperature of 750 °C to 900 °C to form Poly-Si(p+).

[0068] a-Si:H(p+) is deposited on the P-type polysilicon layer 131. Among them, an appropriate proportion of GeH4, CH4, O2, NO2, or NH3 gas is mixed into the silane gas deposited by plasma. For example, CH4 is doped during the amorphous silicon deposition process to prepare hydrogenated amorphous silicon carbide a-SiC:H, so as to deposit a-SiC:H(p+) on the P-type polysilicon layer 131. Then, a high-temperature annealing treatment is carried out, and the annealing temperature is 750 °C to 900 °C to prepare carbon-doped polysilicon, that is, Poly-SiC(p+). The addition of carbon elements is beneficial to increasing the band gap width of polysilicon.

[0069] PECVD, HWCVD or LPCVD technology is used to deposit a-SiC:H(i) on the second surface 112 of the silicon substrate 110 as the intrinsic passivation layer. The thickness of the hydrogenated amorphous silicon carbide layer a-SiC:H(i) is 3 nm to 15 nm.

[0070] PECVD, HWCVD or LPCVD technology is used to deposit a hydrogenated microcrystalline silicon carbide layer uc-SiC:H(n+) on the hydrogenated amorphous silicon carbide layer as the back doping layer 170. The thickness of the back doping layer 170 is 10 nm to 50 nm.

[0071] (3) Deposition of TCO film layers on the front and back

[0072] PVD or RPD equipment technology is used to deposit a transparent conductive film on the front doping layer 130 and the back doping layer 170 respectively to form transparent conductive oxide layers TCO on the front and back. Among them, the materials of TCO include but are not limited to indium tin oxide (ITO) thin film, indium tungsten oxide (IWO) thin film, indium titanium oxide (ITiO) thin film or aluminum-doped zinc oxide (AZO) thin film. The thickness of the TCO on the back is greater than that of the TCO on the front. Optionally, the thickness of the TCO on the front is 60 nm to 100 nm; the thickness of the TCO on the back is 70 nm to 120 nm.

[0073] (4) Metallization

[0074] Metallization is used to form a first metal electrode 151 on the surface of the TCO film layer on the front and a second metal electrode 152 on the surface of the TCO film layer on the back. This metallization process can adopt screen printing process or electroplating process. Optionally, the cell pattern of this heterojunction cell can adopt a multi-main grid line or a no-main grid line scheme. Among them, the grid lines on the back need to use etching or burning-through methods to achieve the contact between the grid lines and the silicon substrate 110.

[0075] The embodiment of the present utility model also provides a photovoltaic module, including a battery string and encapsulation adhesive films respectively arranged on both sides of the battery string. The battery string includes a plurality of N-type heterojunction cells 100 as described above, and the plurality of N-type heterojunction cells 100 are connected in series in sequence.

[0076] It can be understood that multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic arrays are connected to a busbar box, which can collect the current generated by the photovoltaic arrays. The collected current flows through an inverter and is converted into alternating current required by the mains power grid, and then is connected to the mains network to achieve solar power supply. This photovoltaic module can be applied in all fields that require solar power generation, including but not limited to photovoltaic power stations, such as ground power stations, rooftop power stations, or water surface power stations, etc., or on devices or apparatuses that use solar energy for power generation, such as user solar power supplies, solar street lights, solar cars, or solar buildings, etc.

[0077] In summary, the N-type heterojunction battery 100 and the photovoltaic module provided by the embodiments of the present invention have the following beneficial effects, including:

[0078] In the N-type heterojunction battery 100 provided by the embodiments of the present invention, the front doping layer 130 adopts a stacked structure of a layer of P-type polysilicon layer 131 and a layer of P-type polycrystalline silicon carbide layer 132. Using polysilicon instead of the existing microcrystalline silicon reduces the process difficulty. The equipment and process costs for preparing polysilicon are lower, the energy consumption is lower, and it has more significant economic benefits in mass production. In addition, the P-type polycrystalline silicon carbide layer 132 containing carbon is adopted in the front doping layer 130, so that the front doping layer 130 has the characteristic of a high refractive index at the bottom layer, which is beneficial to increasing the light absorption ability. And it is paired with an aluminum oxide layer 120 as a passivation layer, with better passivation effect, which can improve the carrier mobility, achieve a higher open-circuit voltage, and improve the photoelectric conversion efficiency. The back of the silicon substrate 110 adopts a hydrogenated amorphous silicon carbide layer as an intrinsic passivation layer to achieve double-sided passivation. The back doping layer 170 adopts a hydrogenated microcrystalline silicon carbide layer, with simpler manufacturing technology, lower process difficulty, higher production efficiency, lower production cost, lower energy consumption, more conducive to energy conservation and environmental protection, and has significant economic benefits in mass production.

[0079] The photovoltaic module provided by the embodiments of the present invention includes the above-mentioned N-type heterojunction battery 100. On the premise of ensuring the bandgap width and battery efficiency, it can also reduce the process difficulty, reduce the equipment cost and process cost, lower the energy consumption, have more significant economic benefits in mass production, and is conducive to energy conservation and environmental protection.

[0080] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An N-type heterojunction battery, characterized in that, Comprising: A silicon substrate having a first surface and a second surface disposed opposite to each other; An alumina layer, a front doping layer, a front transparent conductive oxide layer, and a first metal electrode are sequentially stacked on the first surface; Wherein, the front doping layer includes a P-type polysilicon layer and a P-type polycrystalline silicon carbide layer, the P-type polysilicon layer is located on the side of the alumina layer away from the silicon substrate; the P-type polycrystalline silicon carbide layer is located on the side of the P-type polysilicon layer away from the alumina layer; A back intrinsic layer, a back doping layer, a back transparent conductive oxide layer, and a second metal electrode are sequentially stacked on the second surface.

2. The N-type heterojunction battery according to claim 1, characterized in that The thickness ratio of the alumina layer to the front doping layer is 1:3 to 1:

20.

3. The N-type heterojunction battery according to claim 1, wherein The thickness of the alumina layer is 5nm to 15nm.

4. The N-type heterojunction battery according to claim 1, characterized in that, The thickness of the front doping layer is 20nm to 45nm.

5. The N-type heterojunction battery according to claim 1, wherein The thickness ratio of the P-type polysilicon layer to the P-type polycrystalline silicon carbide layer is 1:0.5 to 1:1.

5.

6. The N-type heterojunction battery according to claim 1, characterized in that, The thickness of the P-type polysilicon layer is 10nm to 30nm.

7. The N-type heterojunction cell according to claim 1, wherein, The thickness of the P-type polycrystalline silicon carbide layer is 15nm to 20nm.

8. The N-type heterojunction battery according to claim 1, wherein The back intrinsic layer is a hydrogenated amorphous silicon carbide layer, and the thickness of the back intrinsic layer is 3nm to 15nm.

9. The N-type heterojunction cell according to claim 1, wherein, The back doping layer is a hydrogenated microcrystalline silicon carbide layer, and the thickness of the back doping layer is 10nm to 50nm.

10. The N-type heterojunction battery according to claim 1, characterized in that, The thickness of the back transparent conductive oxide layer is greater than the thickness of the front transparent conductive oxide layer.

11. The N-type heterojunction battery according to any one of claims 1 to 10, characterized in that, The thickness of the silicon substrate is 80μm to 180μm.

12. A photovoltaic module, comprising a battery string and encapsulation adhesive films respectively disposed on two sides of the battery string, wherein, The battery string includes a plurality of N-type heterojunction batteries as described in any one of claims 1 to 11, and the plurality of N-type heterojunction batteries are sequentially connected in series.

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