Solar cell structure
By extending the emitter to the side and back face of the solar cell and incorporating an isolation layer, the emitter area is maximized, overcoming the area limitations of the front junction to enhance solar cell efficiency.
Patent Information
- Application Number
- CN202422279011.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-09-18
AI Technical Summary
In existing solar cells, the emitter area is limited by the front area of the battery, resulting in limited battery efficiency.
The emitter extends on the front and sides of the semiconductor substrate, and the emitter area is maximized by providing an isolation portion between the back field and the emitter and covering the insulating passivation film therebetween.
By increasing the emitter area, the efficiency of solar cells is improved, the front area limitation is eliminated, and the battery performance is improved.
Smart Images
Figure CN223110432U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of solar cell manufacturing, and particularly relates to a solar cell structure. Background Art
[0002] The pn junction and the emitter are important components of a solar cell. The photo-generated carriers near the pn junction or the emitter can be quickly separated by the built-in electric field and collected by the electrodes. However, the photo-generated carriers that are too far away from the pn junction or the emitter have a relatively high probability of being recombined by defects before reaching the vicinity of the pn junction. Therefore, appropriately increasing the emitter area can effectively increase the cell efficiency.
[0003] In a conventional front-junction cell, the emitter is located on the front surface of the cell, the back field is located on the back surface of the cell, and the isolation part is located on the side surface of the cell. The emitter area is limited by the area of the front surface of the cell, and the cell efficiency is restricted. Summary of the Utility Model
[0004] An embodiment of the utility model provides a solar cell structure, aiming to increase the emitter area of the front-junction solar cell, thereby improving the cell efficiency.
[0005] To achieve the above object, the technical solution adopted by the utility model is: to provide a solar cell structure, including: a semiconductor substrate, an emitter, a back field, and an isolation part. The semiconductor substrate has a first conductivity type; the back field is located on the back surface of the semiconductor substrate and has a first conductivity type; a first electrode is disposed on the back field; the back field includes a polysilicon layer, a polysilicon layer + a first tunneling layer, or a heavily doped layer formed by introducing a dopant of the same type on the back surface of the semiconductor substrate; the emitter is located on the front surface of the semiconductor substrate and extends to the side surface or the back surface of the semiconductor substrate, covering at least a part of the side surface. The emitter has a second conductivity type opposite to the first conductivity type; a second electrode is disposed on the emitter; a second tunneling layer may be selectively disposed or not disposed between the emitter and the semiconductor substrate; the isolation part is located between the back field and the emitter to isolate the back field from the emitter; the isolation part is covered with an insulating passivation film.
[0006] In an implementable manner, a first passivation film is disposed on the back field, and the first electrode is electrically connected to the back field through a window on the first passivation film.
[0007] In an implementable manner, the outer surface of the emitter is covered with a second passivation film, and the second electrode is electrically connected to the emitter through a window on the second passivation film; wherein the second passivation film covers the front and side surfaces of the semiconductor substrate; the first passivation film covers the back surface of the semiconductor substrate; the first passivation film and the second passivation film meet along the extension line of the back surface of the semiconductor substrate.
[0008] In an implementable manner, both the first passivation film and the second passivation film include any one of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide.
[0009] In an implementable manner, the emitter partially or completely covers the side surface of the semiconductor substrate.
[0010] In an implementable manner, the emitter extends to the back edge region of the semiconductor substrate at the same time.
[0011] In an implementable manner, the back surface of the semiconductor substrate is covered with a first tunneling layer, the front surface of the semiconductor substrate is covered with a second tunneling layer, and the back field and the emitter are respectively formed on the first tunneling layer and the second tunneling layer.
[0012] In an implementable manner, the thickness of the first tunneling layer ≤ 5 nm; the thickness of the second tunneling layer ≤ 5 nm.
[0013] Compared with the prior art, the beneficial effect of the solar cell structure provided by the present utility model is that: the emitter on the front surface of the front junction cell extends to the side surface and even the back surface of the semiconductor substrate, maximizing the emitter area, getting rid of the limitation of the area of the front surface of the semiconductor substrate on the emitter area, increasing the emitter area of the front junction solar cell, and thus improving the cell efficiency. Description of the Drawings
[0014] Figure 1 It is a schematic structural diagram of the solar cell structure provided by Embodiment 1 of the present utility model;
[0015] Figure 2 It is a schematic structural diagram of the solar cell structure provided by Embodiment 2 of the present utility model;
[0016] Figure 3 It is a schematic structural diagram of the solar cell structure provided by Embodiment 3 of the present utility model;
[0017] Figure 4 It is a schematic structural diagram of the solar cell structure provided by Embodiment 4 of the present utility model;
[0018] Description of the Reference Numerals:
[0019] 1. Semiconductor substrate; 2. Second electrode; 3. Emitter; 4. Second passivation film; 5. Back surface field; 6. First electrode; 7. First passivation film; 8. Isolation part; 9. First tunneling layer. Detailed implementation manners
[0020] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present utility model clearer and more understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.
[0021] Please refer to Figures 1 to 4 together, and now the solar cell structure provided by the present utility model will be described. The solar cell structure includes: a semiconductor substrate 1, an emitter 3, a back surface field 5 and an isolation part 8. The semiconductor substrate 1 has a first conductivity type; the back surface field 5 is located on the back surface of the semiconductor substrate 1 and has a first conductivity type; a first electrode 6 is provided on the back surface field 5; the back surface field 5 includes a polysilicon layer, a polysilicon layer + a first tunneling layer 9 or a heavily doped layer formed by introducing a dopant of the same type on the back surface of the semiconductor substrate 1, and the back surface field 5 is any one of them.
[0022] The emitter 3 is located on the front surface of the semiconductor substrate 1 and extends to the side surface or the back surface of the semiconductor substrate 1, covering at least part of the side surface. The emitter 3 has a second conductivity type opposite to the first conductivity type; a second electrode 2 is provided on the emitter 3; a second tunneling layer may be selectively provided or not provided between the emitter 3 and the semiconductor substrate 1.
[0023] The isolation part 8 is located between the back surface field 5 and the emitter 3 to isolate the back surface field 5 from the emitter 3; the isolation part 8 is covered with an insulating passivation film.
[0024] Compared with the prior art, the beneficial effect of the solar cell structure provided by the present utility model is that the emitter 3 on the front surface of the front junction cell extends to the side surface or even the back surface of the semiconductor substrate 1, maximizing the area of the emitter 3, getting rid of the limitation of the area of the front surface of the semiconductor substrate 1 on the area of the emitter 3, increasing the area of the emitter 3 of the front junction solar cell, and thus improving the cell efficiency.
[0025] In this application, the first electrode 6 may be a finger-like structure (grid line), or a metal layer covering the entire back surface or an opaque conductive layer. The metal layer or the conductive layer has a high reflectivity and can reflect the light incident on its surface back to the front surface or the side surface emitter 3 of the substrate.
[0026] An isolation portion 8 is located between the back surface field 5 and the emitter 3. The isolation portion 8 removes the emitter 3 and the back surface field, thereby exposing a portion of the substrate, and an insulating passivation film is covered on this exposed portion of the substrate. Its function is to prevent leakage caused by the connection between the emitter 3 and the back surface field, and can reduce surface recombination and increase the battery efficiency.
[0027] The isolation portion 8 can be covered by the first passivation film 7 or the second passivation film 4, or can be covered by a stack of the first passivation film 7 and the second passivation film 4, or can be covered by the first tunneling layer 9, or can be covered by other passivation films or antireflection layers except the first passivation film 7, the second passivation film 4 and the first tunneling layer 9.
[0028] The explanations of related terms are as follows:
[0029] Substrate: The base body of the solar cell, which is a semiconductor material and has a first conductivity type.
[0030] Emitter 3: A semiconductor region with a second conductivity type, which is opposite to the first conductivity type. The emitter 3 forms a pn junction with the substrate and is an important part of the solar cell. Increasing the light-receiving area or appropriately increasing the area of the emitter 3 can effectively increase the battery efficiency.
[0031] Back surface field 5: A semiconductor region with a first conductivity type. Its doping concentration is usually higher than that of the substrate, and forms a high-low junction with the substrate, which can effectively reduce the carrier recombination rate on the back surface of the battery, thereby increasing the battery efficiency.
[0032] Tunneling layer: Usually a passivation layer less than 2 nm, which can effectively improve the passivation quality. Carriers can pass through the tunneling layer through tunneling effect, or can directly pass through the tunneling layer through the pinholes on the tunneling layer.
[0033] Front junction cell: The pn junction and the emitter 3 are close to the front surface of the battery, that is, the light-receiving surface.
[0034] First conductivity type: In different regions of the solar cell, the main conductive particles can be electrons, which carry negative charges, and the corresponding conductivity type is n-type; or they can be holes, which carry positive charges, and the conductivity type is p-type. The conductivity types represented by p-type and n-type can be regarded as opposite. The first conductivity type is one of them, which can be p-type or n-type..
[0035] Second conductivity type: Opposite to the first conductivity type. If the first conductivity type is p-type, then the second conductivity type is n-type; if the first conductivity type is n-type, then the second conductivity type is p-type.
[0036] In some embodiments, refer to Figures 1 to 4 , a first passivation film 7 is provided on the back surface field 5, and the first electrode 6 is electrically connected to the back surface field 5 through a window on the first passivation film 7.
[0037] In some embodiments, referring to Figures 1 to 4 , a second passivation film 4 is covered on the outer surface of the emitter 3, and the second electrode 2 is electrically connected to the emitter 3 through a window on the second passivation film 4; wherein the second passivation film 4 covers the front and side surfaces of the semiconductor substrate 1; the first passivation film 7 covers the back surface of the semiconductor substrate 1; the first passivation film 7 and the second passivation film 4 are joined along the extension line of the back surface of the semiconductor substrate 1.
[0038] In some embodiments, referring to Figures 1 to 4 , both the first passivation film 7 and the second passivation film 4 include any one of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide. Among them, the first passivation film 7 and the second passivation film 4 can be multi-layered, can include an antireflection layer, and there can be a covering relationship. For example, in some regions, the first passivation film 7 can cover the second passivation film 4, or the second passivation film 4 covers the first passivation film 7.
[0039] In some embodiments, referring to Figures 1 to 4 , the emitter 3 partially or completely covers the side surface of the semiconductor substrate 1.
[0040] In some embodiments, referring to Figure 2 and Figure 4 , the emitter 3 simultaneously extends to the back edge region of the semiconductor substrate 1.
[0041] In the present application, the emitter 3 can extend outward from the front surface of the semiconductor substrate 1 so as to cover all side surfaces of the semiconductor substrate 1 and simultaneously cover the edge region of the back surface. At this time, the back surface field 5 on the back surface of the semiconductor substrate 1 does not cover the entire back surface. At this time, the isolation part 8 is located between the back surface field 5 on the back surface of the semiconductor substrate 1 and the emitter 3, and is annular as a whole.
[0042] In some embodiments, referring to Figures 3 to 4 , a first tunneling layer 9 is covered on the back surface of the semiconductor substrate 1, a second tunneling layer is covered on the front surface of the semiconductor substrate 1, and the back surface field 5 and the emitter 3 are respectively formed on the first tunneling layer 9 and the second tunneling layer.
[0043] Specifically, the emitter 3 can be directly formed on the front surface of the semiconductor substrate 1, or can be formed on a second tunneling layer (for example, silicon oxide with a thickness ≤ 5 nm) on the substrate surface. For example, first form a layer of second tunneling layer on the surface of the semiconductor substrate 1, and then deposit a polysilicon layer with a corresponding conductivity type on the second tunneling layer, and use this polysilicon layer as the emitter 3.
[0044] In some embodiments, referring to Figures 3 to 4, the back surface of the semiconductor substrate 1 is covered with a first tunneling layer 9, and a back field 5 is formed on the first tunneling layer 9. Specifically, the back field 5 can be directly formed on the substrate surface or on a passivation layer (e.g., silicon oxide with a thickness < 2 nm) on the surface of the semiconductor substrate 1.
[0045] In some embodiments, refer to Figures 3 to 4 , the thickness of the first tunneling layer 9 ≤ 5 nm; the thickness of the second tunneling layer ≤ 5 nm. For example, the thickness of the first tunneling layer 9 is 4 nm, 1.8 nm, 1.5 nm, 1 nm, etc. The thickness of the second tunneling layer can be the same as or different from that of the first tunneling layer 9.
[0046] For ease of understanding, four embodiments of the solar cell structure are given in this application:
[0047] Embodiment 1: The cell structure includes a semiconductor substrate 1, an emitter 3 on the front and side surfaces of the semiconductor substrate, an isolation portion 8 on the side surface of the semiconductor substrate 1, a back field 5 on the back surface of the semiconductor substrate 1, a first passivation film 7, a second passivation film 4, and grid lines, refer to Figure 1 as shown.
[0048] Embodiment 2: The cell structure includes a semiconductor substrate 1, an emitter 3 on the front, side, and back edge regions of the semiconductor substrate 1, an isolation portion 8 on the back surface of the semiconductor substrate 1, a back field 5, a first passivation film 7, a second passivation film 4, and grid lines, refer to Figure 2 as shown.
[0049] Embodiment 3: The back field 5 of the cell structure is a first tunneling layer 9 + polysilicon layer structure. The front emitter 3 extends to the side surface of the semiconductor substrate 1, refer to Figure 3 as shown.
[0050] Embodiment 4: The back field 5 of the cell structure is a first tunneling layer 9 + polysilicon layer structure. The front emitter 3 extends to the back edge region of the semiconductor substrate 1, refer to Figure 4 as shown.
[0051] The solar cell structure provided by this application has two preparation methods, specifically as follows:
[0052] Embodiment 1:
[0053] The preparation method of the solar cell structure provided by this application (the emitter 3 extends to a part of the side surface, refer to Figure 1 and Figure 3 ), includes the following steps:
[0054] Step 1, form an emitter 3 on the front and side surfaces of the semiconductor substrate 1, and the preparation method includes but is not limited to high-temperature diffusion.
[0055] Step 2: Use etching solution or laser etching to remove the emitter 3 on the side surfaces connected to the back of the semiconductor substrate 1 to form an isolated portion 8 not covered by the passivation film.
[0056] Step 3: Form a back surface field 5 on the back of the semiconductor substrate 1.
[0057] The preparation method is related to the type of the back surface field 5: If the back surface field 5 is made of crystalline silicon material and is directly formed on the back of the substrate, the method is to form the back surface field 5 by diffusing impurities of the same conductivity type to the back of the semiconductor substrate 1; if the back surface field 5 is of the type of the first tunneling layer 9 + polysilicon layer, the method is by means of vapor deposition, such as LPCVD, PECVD or PVD. First, deposit the first tunneling layer 9 on the back of the semiconductor substrate 1, and then deposit a doped polysilicon layer on the first tunneling layer 9.
[0058] Step 4: Form a second passivation film 4 on the emitter 3 on the front of the semiconductor substrate 1, the side emitter 3 and the isolated portion 8; the method is by means of vapor deposition, such as LPCVD, PECVD or PVD. The second passivation film 4 can include silicon nitride, silicon oxynitride, aluminum oxide, silicon oxide, etc., and can be a single layer or a stack.
[0059] Step 5: Form a first passivation film 7 on the back surface field 5 on the back of the semiconductor substrate 1; the method is by means of vapor deposition, such as LPCVD, PECVD or PVD. The first passivation film 7 can include silicon nitride, silicon oxynitride, aluminum oxide, silicon oxide, etc., and can be a single layer or a stack.
[0060] Step 6: Form a paste for the second electrode 2 on the second passivation film 4; the method includes but is not limited to screen printing.
[0061] Step 7: Form a paste for the first electrode 6 on the first passivation film 7; the method includes but is not limited to screen printing.
[0062] Step 8: Sinter to make the second electrode 2 form an electrical connection with the emitter 3, and at the same time the first electrode 6 form an electrical connection with the back surface field 5. High-temperature sintering is used to make the paste form an ohmic contact with the emitter 3.
[0063] Example 2:
[0064] The present application also provides a preparation method of a solar cell structure (the emitter 3 completely covers the side surfaces and the back edge region, see Figure 2 and Figure 4 ), including:
[0065] Step 1: Form a back surface field 5 on the back surface of the semiconductor substrate 1; the method is related to the type of the back surface field 5: if the type of the back surface field 5 is crystalline silicon material and it is directly formed on the back surface of the semiconductor substrate 1, the method is to form the back surface field 5 by diffusing impurities of the same conductivity type to the back surface of the semiconductor substrate 1; if the type of the back surface field 5 is the first tunneling layer 9 + polysilicon layer, the method is by means of vapor deposition, such as LPCVD, PECVD or PVD. First, deposit the first tunneling layer 9 on the back surface of the semiconductor substrate 1, and then deposit a doped polysilicon layer on the first tunneling layer 9.
[0066] Step 2: Form a first mask layer in the central area of the back surface of the semiconductor substrate 1; (the method of forming the first mask layer is by means of vapor deposition, such as LPCVD, PECVD or PVD, and the mask layer can be silicon oxide, silicon nitride, etc.).
[0067] Step 3: Remove the back surface field 5 in the edge area of the back surface of the semiconductor substrate 1 that is not covered by the first mask layer. At this time, the first mask layer in the central area of the back surface of the semiconductor substrate 1 still exists, and the back surface field 5 protected by the first mask layer is below the first mask layer (the removal step can be achieved by laser etching or chemical etching).
[0068] Step 4: Form an emitter 3 on the front surface, side surface and back surface of the semiconductor substrate 1 (formed by means of high-temperature diffusion, etc.).
[0069] Step 5: Form a second mask layer in the edge area of the back surface of the semiconductor substrate 1, and remove the emitter 3 that is not covered by the second mask layer to expose the first mask layer in the central area; (the method of forming the second mask layer is by means of vapor deposition, such as LPCVD, PECVD or PVD, and the second mask layer can be silicon oxide, silicon nitride, etc.; the removal step can be achieved by laser etching or chemical etching).
[0070] Step 6: Remove the first mask layer and the second mask layer on the back surface. (The removal step can be achieved by laser etching or chemical etching. According to the materials in Step 1, it can be selected to remove them in the same process or separately in consecutive different processes.)
[0071] Step 7: Use a laser to form an isolation part 8 between the emitter 3 in the edge area of the back surface and the back surface field 5 in the central area.
[0072] Step 8: Form a second passivation film 4 on the emitter 3 on the front surface and side surface of the semiconductor substrate 1 (by vapor deposition, such as LPCVD, PECVD or PVD).
[0073] Step 9: Form a first passivation film 7 on the back surface field 5, emitter 3 and isolation part 8 on the back surface of the semiconductor substrate 1 by means of vapor deposition, such as LPCVD, PECVD or PVD.
[0074] Step Ten: Form the paste for the second electrode 2 on the second passivation film 4 (by means such as screen printing).
[0075] Step Eleven: Form the paste for the first electrode 6 on the first passivation film 7 in the central area on the back surface of the semiconductor substrate 1 (by means such as screen printing).
[0076] Step Twelve: Sinter to enable the second electrode 2 to form an electrical connection with the emitter 3, and at the same time enable the first electrode 6 to form an electrical connection with the back surface field 5.
[0077] In the above embodiments, the descriptions of each embodiment have their own focuses. For parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0078] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.
Claims
1. A solar cell structure, characterized in that, Comprising: A semiconductor substrate (1) having a first conductivity type; A back surface field (5) located on the back surface of the semiconductor substrate (1) and having a first conductivity type; a first electrode (6) is provided on the back surface field (5); the back surface field (5) includes a polysilicon layer, a polysilicon layer + a first tunneling layer (9), or a heavily doped layer formed by introducing a dopant of the same type on the back surface of the semiconductor substrate (1); An emitter (3) located on the front surface of the semiconductor substrate (1) and extending to the side surface or the back surface of the semiconductor substrate (1), covering at least a part of the side surface, the emitter (3) having a second conductivity type opposite to the first conductivity type; a second electrode (2) is provided on the emitter (3); a second tunneling layer may be selectively provided or not provided between the emitter (3) and the semiconductor substrate (1); and An isolation part (8) located between the back surface field (5) and the emitter (3) to isolate the back surface field (5) from the emitter (3); the isolation part (8) is covered with an insulating passivation film.
2. The solar cell structure according to claim 1, wherein A first passivation film (7) is provided on the back surface field (5), and the first electrode (6) is electrically connected to the back surface field (5) through a window on the first passivation film (7).
3. The solar cell structure according to claim 2, wherein, The outer surface of the emitter (3) is covered with a second passivation film (4), and the second electrode (2) is electrically connected to the emitter (3) through a window on the second passivation film (4); wherein the second passivation film (4) covers the front surface and the side surface of the semiconductor substrate (1); the first passivation film (7) covers the back surface of the semiconductor substrate (1); the first passivation film (7) and the second passivation film (4) are joined along the extension line of the back surface of the semiconductor substrate (1).
4. The solar cell structure according to claim 3, wherein, Both the first passivation film (7) and the second passivation film (4) include any one of silicon nitride, silicon oxynitride, aluminum oxide, and silicon oxide.
5. The solar cell structure according to claim 1, wherein, The emitter (3) partially or completely covers the side surface of the semiconductor substrate (1).
6. The solar cell structure according to claim 1, wherein The emitter (3) simultaneously extends to the back surface edge region of the semiconductor substrate (1).
7. The solar cell structure according to claim 1, wherein, The back surface of the semiconductor substrate (1) is covered with a first tunneling layer (9), the front surface of the semiconductor substrate (1) is covered with a second tunneling layer, and the back surface field (5) and the emitter (3) are respectively formed on the first tunneling layer (9) and the second tunneling layer.
8. The solar cell structure according to claim 1, wherein The thickness of the first tunneling layer (9) ≤ 5 nm; the thickness of the second tunneling layer ≤ 5 nm.