Time synchronization device, terminal equipment and system

By introducing a phase-locked loop module into the time synchronization device to adjust the time synchronization results, the problem of low time synchronization accuracy is solved, and the time synchronization accuracy in picosecond level is achieved, and the communication reliability is improved.

CN223141941UActive Publication Date: 2025-07-22SHENZHEN PANGO MICROSYST CO LTD
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Patent Information

Application Number
CN202421651856.0
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-07-11
Publication Date
2025-07-22
Estimated Expiration
2034-07-11

AI Technical Summary

Technical Problem

The existing time synchronization devices have problems with low time accuracy in real-time Ethernet systems, resulting in communication failure and data loss.

Method used

The time synchronization device is adopted, including a time synchronization module, a second pulse output module and a phase-locking loop module. The time synchronization result is adjusted by the phase-tuning clock signal provided by the phase-locking loop module, and the transmission time of the second pulse output module is changed to compensate for the time deviation.

Benefits of technology

Improves the accuracy of time synchronization, reduces the time deviation to the picosecond level, and ensures the accuracy and stability of communication.

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Patent Text Reader

Abstract

The utility model discloses a time synchronization device, terminal equipment and a system. The device comprises a time synchronization module, a pulse per second output module and a phase-locked loop module, the first end of the phase-locked loop module is connected with the first end of the second pulse output module, and the second end of the second pulse output module is connected with the first end of the time synchronization module; the phase-locked loop module provides a first clock signal supporting phase modulation for the second pulse output module; the time synchronization module performs time synchronization; and the second pulse output module performs phase modulation processing on a time synchronization result according to the first clock signal, and outputs a second pulse signal according to a phase modulation processing result. In the embodiment of the invention, the phase modulation processing is carried out on the time synchronization result according to the phase modulation clock signal provided by the phase-locked loop module, the sending time of the second pulse signal output by the second pulse output module is changed, the purpose of compensating the time deviation is achieved, the time deviation between time synchronization devices can be reduced, and thus the time synchronization precision can be improved.
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Description

Technical Field

[0001] This application relates to the field of electronic circuit technologies, and particularly to a time synchronization device, a terminal device, and a system. Background Art

[0002] In a real-time Ethernet system, the time synchronization accuracy affects the accuracy and stability of data transmission, and high-precision time synchronization provides an important guarantee for high-speed communication. For example, in the case of time asynchronization between two terminal devices, communication failures and data loss may occur.

[0003] Most high-precision clock synchronizations adopt a clock synchronization scheme based on the Precision Time Protocol (PTP). The terminal devices can transmit Pulse Per Second (PPS) signals and time information through an RS422 synchronization interface, and the time accuracy can reach the order of dozens of nanoseconds without cumulative error.

[0004] Currently, the time synchronization device can perform time synchronization according to the PPS signal and then output the PPS signal according to the result of the time synchronization. Since the time of the time synchronization device needs to compensate for link delays, etc., there will still be a certain time deviation after the time synchronization device performs time synchronization through the time synchronization module, resulting in low time accuracy. Summary of the Utility Model

[0005] Embodiments of this application disclose a time synchronization device, a terminal device, and a system for improving time accuracy.

[0006] In a first aspect, embodiments of this application disclose a time synchronization device, including a time synchronization module, a second pulse output module, and a phase-locked loop module;

[0007] A first end of the phase-locked loop module is connected to a first end of the second pulse output module, and a second end of the second pulse output module is connected to a first end of the time synchronization module;

[0008] The phase-locked loop module is configured to provide a first clock signal to the second pulse output module, and the first clock signal supports phase modulation;

[0009] The time synchronization module is configured to perform time synchronization;

[0010] The second pulse output module is configured to perform phase modulation processing on the result of the time synchronization according to the first clock signal and output a second pulse signal according to the result of the phase modulation processing.

[0011] As a possible implementation manner, a second end of the phase-locked loop module is respectively connected to a second end of the time synchronization module and a third end of the second pulse output module;

[0012] The phase-locked loop module is further configured to provide a second clock signal to the time synchronization module and the second pulse output module, and the second clock signal does not support phase modulation;

[0013] The time synchronization module is further configured to determine the second clock signal as the working clock signal;

[0014] The second pulse output module is further configured to determine the second clock signal as the working clock signal.

[0015] As a possible implementation manner, the time synchronization device further includes an edge output module, a first end of the edge output module is connected to a fourth end of the second pulse output module, and a second end of the edge output module is connected to a first end of the phase-locked loop module;

[0016] The phase-locked loop module is further configured to provide the first clock signal to the edge output module;

[0017] The second pulse output module is specifically configured to output a second pulse signal to the edge output module according to the result of the phase modulation process;

[0018] The edge output module is configured to output the second pulse signal according to the first clock signal.

[0019] As a possible implementation manner, the time synchronization device further includes a message processing module, and the message processing module is connected to a third end of the time synchronization module;

[0020] The message processing module is configured to perform message processing;

[0021] The time synchronization module is specifically configured to perform time synchronization according to the result of the message processing.

[0022] As a possible implementation manner, the time synchronization device is a first time synchronization device;

[0023] The time synchronization module is specifically configured to perform time synchronization according to a first time to obtain a second time, and send the second time to the second pulse output module, where the first time is the time of a second time synchronization device;

[0024] The second pulse output module is specifically configured to perform phase modulation processing on the second time according to the first clock signal to obtain a third time, and send the second pulse signal to a third time synchronization device according to the third time.

[0025] As a possible implementation, the second pulse output module is specifically configured to determine a compensation time according to the second time, and perform a phase modulation process on the second time according to the first clock signal and the compensation time to obtain the third time.

[0026] As a possible implementation, the second pulse output module is specifically configured to determine the compensation time according to the second time and a fourth time, where the fourth time is the time of the first time synchronization device.

[0027] As a possible implementation, the message processing module is specifically configured to receive a target message from a second time synchronization device, extract a time from the target message to obtain a first time, and send the first time to the time synchronization module;

[0028] The time synchronization module is specifically configured to perform time synchronization according to the first time.

[0029] In a second aspect, an embodiment of the present application discloses a terminal device, including the time synchronization device disclosed in the first aspect.

[0030] In a third aspect, an embodiment of the present application discloses a time synchronization system, including the time synchronization device, a second time synchronization device, and a third time synchronization device disclosed in the first aspect;

[0031] The second time synchronization device is configured to send a first time to the time synchronization device;

[0032] The third time synchronization device is configured to receive a second pulse signal from the time synchronization device.

[0033] In the embodiment of the present application, the time synchronization device includes a time synchronization module, a second pulse output module, and a phase-locked loop module; a first end of the phase-locked loop module is connected to a first end of the second pulse output module, and a second end of the second pulse output module is connected to a first end of the time synchronization module; the phase-locked loop module provides a first clock signal that supports phase modulation to the second pulse output module; the time synchronization module performs time synchronization; the second pulse output module performs a phase modulation process on the result of time synchronization according to the first clock signal, and outputs a second pulse signal according to the result of the phase modulation process. It can be seen that the second pulse output module does not directly output a second pulse signal according to the result of time synchronization of the time synchronization module, but first performs a phase modulation process on the result of time synchronization according to the phase modulation clock signal provided by the phase-locked loop module, and then outputs a second pulse signal according to the result of the phase modulation process. Since the result of time synchronization is phase-modulated according to the phase modulation clock signal provided by the phase-locked loop module, the transmission time of the second pulse signal output by the second pulse output module can be changed, achieving the purpose of compensating for time deviation, reducing the time deviation between time synchronization devices, and this time deviation can reach the picosecond level, thereby improving the time synchronization accuracy. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0035] Figure 1 is a schematic structural diagram of a time synchronization device disclosed in an embodiment of the present application;

[0036] Figure 2 is a schematic structural diagram of another time synchronization device disclosed in an embodiment of the present application;

[0037] Figure 3 is a schematic structural diagram of yet another time synchronization device disclosed in an embodiment of the present application;

[0038] Figure 4 is a schematic structural diagram of yet another time synchronization device disclosed in an embodiment of the present application;

[0039] Figure 5 is a schematic structural diagram of yet another time synchronization device disclosed in an embodiment of the present application;

[0040] Figure 6 is a schematic structural diagram of yet another time synchronization device disclosed in an embodiment of the present application;

[0041] Figure 7 is a schematic structural diagram of a terminal device disclosed in an embodiment of the present application;

[0042] Figure 8 is a schematic structural diagram of a time synchronization system disclosed in an embodiment of the present application. Detailed Embodiments

[0043] In order to enable those skilled in the art to better understand the solutions of the present application, the following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application.

[0044] The embodiments of the present application disclose a time synchronization device, a terminal device and a system, which are used to improve time accuracy. The following will be described in detail respectively.

[0045] In order to better understand the embodiments of the present application, the related technologies of the embodiments of the present application will be described below first.

[0046] In a real-time Ethernet system, the time synchronization accuracy affects the accuracy and stability of data transmission, and high-precision time synchronization provides an important guarantee for high-speed communication. For example, in the case of time asynchronization between two terminal devices, communication failures and data loss may occur.

[0047] Most high-precision clock synchronization adopts a clock synchronization scheme based on PTP. Between terminal devices, PPS signals and time information can be transmitted through an RS422 synchronization interface, with a time accuracy reaching the order of dozens of nanoseconds and no cumulative error. However, using PPS signals for time synchronization cannot achieve picosecond-level accuracy, resulting in low time accuracy.

[0048] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a time synchronization device disclosed in an embodiment of the present application. As Figure 1 shown, the time synchronization device may include a time synchronization module and a second pulse output module. The time synchronization module is connected to the second pulse output module.

[0049] The time synchronization module can perform time synchronization according to the time of other time synchronization devices, and then send the result of the time synchronization to the second pulse output module. The second pulse output module can output a second pulse signal according to the result of the time synchronization.

[0050] Since the time of the time synchronization device needs to compensate for link delays, etc., after time synchronization through the time synchronization module, there will still be a certain time deviation, resulting in low time accuracy.

[0051] To solve the above problems, the present application designs a time synchronization device, including a time synchronization module, a second pulse output module, and a phase-locked loop module; the first end of the phase-locked loop module is connected to the first end of the second pulse output module, and the second end of the second pulse output module is connected to the first end of the time synchronization module; the phase-locked loop module provides a first clock signal supporting phase modulation to the second pulse output module; the time synchronization module performs time synchronization; the second pulse output module performs phase modulation processing on the result of the time synchronization according to the first clock signal, and outputs a second pulse signal according to the result of the phase modulation processing. It can be seen that the second pulse output module does not directly output a second pulse signal according to the result of the time synchronization of the time synchronization module, but first performs phase modulation processing on the result of the time synchronization according to the phase modulation clock signal provided by the phase-locked loop module, and then outputs a second pulse signal according to the result of the phase modulation processing. Since the result of the time synchronization is phase-modulated according to the phase modulation clock signal provided by the phase-locked loop module, the transmission time of the second pulse signal output by the second pulse output module can be changed, achieving the purpose of compensating for the time deviation, reducing the time deviation between time synchronization devices, which can reach the picosecond level, thereby improving the time synchronization accuracy.

[0052] Please refer toFigure 2 , Figure 2 is a schematic structural diagram of another time synchronization device disclosed in an embodiment of the present application. As Figure 2 shown, the time synchronization device may include a time synchronization module, a second pulse output module, and a phase-locked loop (PLL) module.

[0053] The first end of the phase-locked loop module is connected to the first end of the second pulse output module, and the second end of the second pulse output module is connected to the first end of the time synchronization module.

[0054] The phase-locked loop module can provide a first clock signal to the second pulse output module. The first clock signal supports phase modulation, that is, the first clock signal is a clock signal that supports phase modulation. It can be seen that the phase-locked loop module can provide a phase-modulated clock signal to the second pulse output module.

[0055] The time synchronization module can perform time synchronization. When the time synchronization module performs time synchronization, it can be understood as synchronizing the time of this time synchronization device and other time synchronization devices.

[0056] The second pulse output module can first perform phase modulation processing on the result of time synchronization according to the first clock signal, and then can output a second pulse signal according to the result of the phase modulation processing.

[0057] It can be seen that the second pulse output module can perform phase modulation processing on the result of time synchronization according to the phase-modulated clock signal. Since the phase-locked loop module can provide a stable phase-modulated clock signal, the second pulse output module can perform phase modulation processing on the result of time synchronization according to the phase-modulated clock signal provided by the phase-locked loop module, can change the transmission time of the second pulse signal output by the second pulse output module, achieve the purpose of compensating for time deviation, can reduce the time deviation between time synchronization devices, and this time deviation can reach the picosecond level, thereby improving the time synchronization accuracy.

[0058] In some embodiments, the time synchronization device is a first time synchronization device.

[0059] The time synchronization module can perform time synchronization according to the first time to obtain the second time, and then can send the second time to the second pulse output module. The first time is the time of the second time synchronization device.

[0060] The time synchronization module can receive the first time from the second time synchronization device. The first time is the time of the second time synchronization device. The second time is the time after the first time synchronization device performs time synchronization according to the first time.

[0061] It can be seen that in order to maintain time synchronization with the second time synchronization device, the first time synchronization device can perform time synchronization according to the first time through the time synchronization module.

[0062] After the second pulse output module receives the second time from the time synchronization module, it can first perform phase modulation on the second time according to the first clock signal to obtain the third time, and then send a second pulse signal to the third time synchronization device according to the third time.

[0063] Although the time synchronization module performs time synchronization according to the first time, there is still a time deviation between the second time and the first time, and this time deviation may be less than one clock cycle. To further reduce the time deviation between the first time synchronization device and the second time synchronization device, the second pulse output module can first perform phase modulation on the second time according to the first clock signal to obtain the third time, and then send a second pulse signal to the third time synchronization device according to the third time. It can be seen that the time deviation between the two time synchronization devices can be reduced by phase modulation based on the phase modulation clock signal.

[0064] In some embodiments, the second pulse output module can first determine the compensation time according to the second time, and then perform phase modulation on the second time according to the first clock signal and the compensation time to obtain the third time.

[0065] Before performing phase modulation, the second pulse output module can first determine the compensation time according to the second time, and then perform phase modulation on the second time according to the first clock signal and the compensation time.

[0066] It can be seen that when the second pulse output module performs phase modulation, it does not perform phase modulation randomly or arbitrarily, but performs phase modulation according to the compensation time, and the compensation time is determined according to the second time, which can improve the accuracy of phase modulation, and further reduce the time deviation between the first time synchronization device and the second time synchronization device.

[0067] In some embodiments, the second pulse output module can determine the compensation time according to the second time and the fourth time, and the fourth time is the time of the first time synchronization device.

[0068] The second pulse output module can determine the compensation time according to the time after time synchronization and the time of the first time synchronization device, which can improve the accuracy of determining the compensation time, and further improve the accuracy of phase modulation, thereby improving the time synchronization accuracy.

[0069] In some embodiments, please refer to Figure 3 , Figure 3 which is a schematic structural diagram of another time synchronization device disclosed in the embodiments of the present application. Among them, Figure 3 the time synchronization device shown is optimized from the Figure 2 time synchronization device shown. As Figure 3As shown, the second end of the phase-locked loop module is respectively connected to the second end of the time synchronization module and the third end of the second pulse output module.

[0070] The phase-locked loop module can also provide a second clock signal to the time synchronization module and the second pulse output module. The second clock signal does not support phase modulation, that is, the second clock signal is a clock signal that does not support phase modulation. The first clock signal is different from the second clock signal.

[0071] The time synchronization module can also determine the second clock signal as the working clock signal. The second pulse output module can also determine the second clock signal as the working clock signal.

[0072] It can be seen that the phase-locked loop module can also provide a working clock signal (i.e., the second clock signal) to the time synchronization module and the second pulse output module, which can ensure that the time synchronization module and the second pulse output module work properly according to the second clock signal, so that the time synchronization module can send the time-synchronized result, such as the second time, to the second pulse output module.

[0073] In some embodiments, please refer to Figure 4 , Figure 4 which is a schematic structural diagram of another time synchronization device disclosed in the embodiments of the present application. Among them, Figure 4 the shown time synchronization device is optimized from the time synchronization device shown in Figure 2 . As shown in Figure 4 , the time synchronization device may further include an edge output module. The first end of the edge output module is connected to the fourth end of the second pulse output module, and the second end of the edge output module is connected to the first end of the phase-locked loop module.

[0074] The phase-locked loop module can also provide the first clock signal to the edge output module.

[0075] The second pulse output module can output a second pulse signal to the edge output module according to the result of the phase modulation process.

[0076] The edge output module can output a second pulse signal according to the first clock signal.

[0077] Specifically, the second pulse output module can send a second pulse signal to the edge output module according to the third time. After receiving the second pulse signal, the edge output module can send the second pulse signal to the third time synchronization device according to the first clock signal.

[0078] It can be seen that the second pulse output module does not directly output the second pulse signal to the third time synchronization device, but first outputs the second pulse signal to the edge output module, and then the edge output module outputs it to the third time synchronization device, which can ensure that the second pulse signal is sent at the edge of the chip or device.

[0079] Since the phase-locked loop module provides the first clock signal for the edge output module, the second pulse signal can be sent out from the edge output module (i.e., at the chip pin) at an accurate time.

[0080] It can be seen that by using the high-precision (ps-level) phase shift characteristic of the phase-locked loop module, the output clock phase is changed through the phase modulation clock signal (i.e., the phase modulation function) of the phase-locked loop module to adjust the transmission time of the second pulse signal, so as to achieve the purpose of compensating for time deviation.

[0081] Since the second pulse signal is single-bit (bit) data, by placing the second pulse signal in the edge output module and driving the edge output module through the phase modulation clock signal of the phase-locked loop module to fix the position of the edge output module, the problem of introducing additional delay by using the internal register to output the second pulse signal can be solved.

[0082] In some embodiments, please refer to Figure 5 , Figure 5 which is a schematic structural diagram of another time synchronization device disclosed in the embodiments of the present application. Among them, Figure 5 the shown time synchronization device is optimized from Figure 2 the shown time synchronization device. As Figure 5 shown, the time synchronization device may further include a message processing module, and the message processing module is connected to the third end of the time synchronization module.

[0083] The message processing module can perform message processing. The time synchronization module can perform time synchronization according to the result of the message processing.

[0084] It can be seen that the time transmitted between different time synchronization devices is transmitted in the form of messages, which can avoid situations such as damage and theft of time during the transmission process, and can improve the accuracy and security of time transmission, thereby improving the time synchronization accuracy.

[0085] In some embodiments, the message processing module can receive a target message from a second time synchronization device, then extract the time from the target message to obtain a first time, and further send the first time to the time synchronization module. So that the time synchronization module can receive the first time from the message processing module and further perform time synchronization according to the first time.

[0086] Please refer to Figure 6 , Figure 6 which is a schematic structural diagram of another time synchronization device disclosed in the embodiments of the present application. Among them, Figure 6 the shown time synchronization device is optimized from Figure 3 , Figure 4 and Figure 5 the shown time synchronization devices. As Figure 6As shown in the figure, the time synchronization device may include a message processing module, a phase-locked loop module, a time synchronization module, a second pulse output module, and an edge output module. The time synchronization device is the first time synchronization device.

[0087] The first end of the phase-locked loop module is connected to the first end of the second pulse output module, and the second end of the second pulse output module is connected to the first end of the time synchronization module. The second end of the phase-locked loop module is respectively connected to the second end of the time synchronization module and the third end of the second pulse output module. The first end of the edge output module is connected to the fourth end of the second pulse output module, and the second end of the edge output module is connected to the first end of the phase-locked loop module. The message processing module is connected to the third end of the time synchronization module.

[0088] The working clocks of the message processing module and the phase-locked loop module are the system clock, that is, the message processing module and the phase-locked loop module operate according to the system clock. The message processing module may receive a target message from the second time synchronization device according to the system clock. The phase-locked loop module may generate a first clock signal and a second clock signal according to the system clock.

[0089] Among them, the detailed descriptions of the message processing module, the phase-locked loop module, the time synchronization module, the second pulse output module, and the edge output module may refer to the above relevant descriptions and will not be elaborated here.

[0090] It should be understood that the above time synchronization device may be applied to the 1588 system or other systems.

[0091] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a terminal device disclosed in an embodiment of the present application. As Figure 7 shown, the terminal device may include a time synchronization device.

[0092] Among them, the detailed description of the time synchronization device may refer to the above description and will not be elaborated here.

[0093] Please refer to Figure 8 , Figure 8 which is a schematic structural diagram of a time synchronization system disclosed in an embodiment of the present application. As Figure 8 shown, the time synchronization system may include a time synchronization device (i.e., the first time synchronization device), a second time synchronization device, and a third time synchronization device.

[0094] The second time synchronization device may send the first time to the first time synchronization device. The first time synchronization device may perform time synchronization according to the first time to obtain the second time, perform phase modulation processing on the second time to obtain the third time, and send a second pulse signal to the third time synchronization device according to the third time. The third time synchronization device may receive the second pulse signal from the time synchronization device.

[0095] Among them, the detailed description of the first-time synchronization device can refer to the relevant description above.

[0096] It should be understood that the connections in this application can be understood as electrical connections.

[0097] It should be understood that in different embodiments, the same or corresponding information can be referred to each other.

[0098] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of this application, rather than limiting them; although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of each embodiment of this application.

Claims

1. A time synchronization device, characterized in that, It includes a time synchronization module, a second pulse output module, and a phase-locked loop module; The first end of the phase-locked loop module is connected to the first end of the second pulse output module, and the second end of the second pulse output module is connected to the first end of the time synchronization module; The phase-locked loop module is used to provide a first clock signal to the second pulse output module, and the first clock signal supports phase modulation; The time synchronization module is used to perform time synchronization; The second pulse output module is used to perform phase modulation processing on the result of time synchronization according to the first clock signal, and output a second pulse signal according to the result of the phase modulation processing.

2. The time synchronization device according to claim 1, wherein The second end of the phase-locked loop module is respectively connected to the second end of the time synchronization module and the third end of the second pulse output module; The phase-locked loop module is further used to provide a second clock signal to the time synchronization module and the second pulse output module, and the second clock signal does not support phase modulation; The time synchronization module is further used to determine the second clock signal as the working clock signal; The second pulse output module is further used to determine the second clock signal as the working clock signal.

3. The time synchronization device according to claim 1, characterized in that The time synchronization device further includes an edge output module. The first end of the edge output module is connected to the fourth end of the second pulse output module, and the second end of the edge output module is connected to the first end of the phase-locked loop module; The phase-locked loop module is further used to provide the first clock signal to the edge output module; The second pulse output module is specifically used to output a second pulse signal to the edge output module according to the result of the phase modulation processing; The edge output module is used to output the second pulse signal according to the first clock signal.

4. The time synchronization device according to claim 1, characterized in that, The time synchronization device further includes a message processing module, and the message processing module is connected to the third end of the time synchronization module; The message processing module is used to perform message processing; The time synchronization module is specifically used to perform time synchronization according to the result of the message processing.

5. The time synchronization device according to claim 1, characterized in that The time synchronization device is the first time synchronization device; The time synchronization module is specifically used to perform time synchronization according to the first time to obtain the second time, and send the second time to the second pulse output module. The first time is the time of the second time synchronization device; The second pulse output module is specifically used to perform phase modulation processing on the second time according to the first clock signal to obtain the third time, and send the second pulse signal to the third time synchronization device according to the third time.

6. The time synchronization device according to claim 5, characterized in that The second pulse output module is specifically used to determine the compensation time according to the second time, and perform phase modulation processing on the second time according to the first clock signal and the compensation time to obtain the third time.

7. The time synchronization device according to claim 6, wherein The second pulse output module is specifically used to determine the compensation time according to the second time and the fourth time. The fourth time is the time of the first time synchronization device.

8. The time synchronization device according to claim 4, wherein The message processing module is specifically used to receive the target message from the second time synchronization device, extract the time from the target message to obtain the first time, and send the first time to the time synchronization module; The time synchronization module is specifically used to perform time synchronization according to the first time.

9. A terminal device, characterized in that, Comprising the time synchronization device according to any one of claims 1-8.

10. A time synchronization system, characterized in that, Comprising the time synchronization device according to any one of claims 1-8, a second time synchronization device, and a third time synchronization device; The second time synchronization device is configured to send a first time to the time synchronization device; The third time synchronization device is configured to receive a second pulse signal from the time synchronization device.