UFS packaging structure

Abstract

The utility model relates to the technical field of semiconductor memory packaging, in particular to a UFS packaging structure, which comprises a substrate, a chip and a solder ball array arranged on the substrate, and is characterized in that the substrate comprises a bottom surface and a top surface which are opposite to each other; a base material is arranged in the substrate, and an etched metal circuit layer is arranged on the surface of the base material; an I < O > solder ball is arranged in the center of the bottom surface of the substrate; the chip is packaged in the substrate and is electrically connected with the I O solder balls; the solder ball array is arranged beside the I-O solder balls in a surrounding mode, and the diameter of the solder ball array is smaller than that of the I-O solder balls. The process is simple, low in cost and suitable for batch production and application; the UFS4x performance can be improved, the user experience of equipment can be improved, the probability of heating and heating can be reduced, heat dissipation scheme feasibility is provided for a subsequent new version, and UFS technology development is promoted.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor memory packaging, and particularly relates to a packaging structure of UFS. Background Art

[0002] With the rapid development of mobile computing devices and high-performance intelligent terminals, higher requirements are put forward for the performance, energy efficiency, capacity, and security of storage systems. Due to the design based on parallel signal transmission of traditional embedded multimedia cards (eMMC), it is gradually difficult to meet the market demand for high speed and large capacity. For this reason, the Universal Flash Storage (UFS) technology has emerged. As the next-generation non-volatile storage solution, UFS has significantly improved the data transmission method, changing from parallel signals to a more advanced serial signal transmission. It not only realizes a rapid increase in frequency but also introduces a full-duplex communication mode, greatly improving the data transmission efficiency.

[0003] UFS built based on the Small Computer System Interface (SCSI) structural model not only inherits the efficient command processing mechanism of SCSI but also adds support for SCSI Tagged Command Queuing, making a qualitative leap in the data processing ability of UFS. Especially in high-performance terminal devices such as tablet computers, flagship smartphones, and high-end game consoles, UFS has become a standard configuration, greatly promoting the upgrade of the user experience of these devices.

[0004] Entering the UFS 4.0 era, the storage technology has once again witnessed a major innovation. To achieve a comprehensive leap in speed, energy efficiency, capacity, compatibility, and security, the UFS 4.0 controller chip adopts a more advanced wafer manufacturing process technology, generally reaching or exceeding 12nm, thus laying a foundation for high performance at the physical level. Its sequential read speed is as high as 4200MB / s, showing a significant increase compared with the previous generation UFS 3.1; the energy efficiency ratio is increased by about 46%, greatly extending the device battery life; the storage capacity is directly quadrupled, meeting the growing data storage needs. In addition, UFS 4.0 also introduces heterogeneous storage support. By allowing different types of flash chips to share the same UFS interface, the flexibility and efficiency of the storage system are significantly improved. At the same time, through the Advanced RPMB (Replay Protected Memory Block) technology, UFS 4.0 provides a more secure storage environment for sensitive data such as encryption keys and device identifiers, and the data security is increased by 1.8 times.

[0005] However, with the significant improvement in the functions and performance of UFS 4.0 and higher versions (collectively referred to as UFS 4x), new technical challenges have emerged. In particular, the significant reduction in the wafer area has led to a sharp increase in the density of external IO pads (PADs), exceeding the processing capacity of traditional WB (wire bonding process). For this reason, the controller chip of UFS 4x adopts an advanced flip chip packaging technology, which realizes higher electrical and mechanical connection density by directly installing solder joints or conductive glue on the bottom surface of the chip to connect with the packaging substrate, while optimizing the overall packaging structure. However, the flash memory chip continues to use the packaging method of stepped stacking and wire bonding to meet the high-capacity demand.

[0006] Despite the significant progress made by UFS 4x in terms of performance and functions, its high-speed and large-capacity characteristics also bring heat dissipation problems that cannot be ignored. In the traditional packaging design, only standard IO solder balls are configured at the bottom, and there is a lack of effective heat dissipation design inside, resulting in the difficulty for UFS 4x to maintain an efficient and full-speed operation state for a long time under high-intensity usage scenarios, which affects the stability and reliability of the overall system. Therefore, how to solve the heat dissipation problem of UFS 4x under high-speed and large-capacity operation has become a technical problem that needs to be overcome urgently. Summary of the Utility Model

[0007] In order to overcome the deficiencies of the prior art, the present application provides a packaging structure for UFS, aiming to solve the heat dissipation problem of UFS 4x, reduce the probability of overheating, improve the operation stability and reliability of the system where it is located, and further promote the development of mobile computing and intelligent terminal technologies.

[0008] The technical means adopted by the present utility model to solve its technical problems is: a packaging structure for UFS, which is improved in that it includes a substrate, a chip, and a solder ball array disposed on the substrate, wherein the substrate includes a relative bottom surface and a top surface; the inside of the substrate is a base material, and the surface of the base material is an etched metal circuit layer; an IO solder ball is provided at the center of the bottom surface of the substrate; the chip is packaged in the substrate and is electrically connected to the IO solder ball; the solder ball array is arranged beside the IO solder ball, and the diameter of the solder ball array is smaller than that of the IO solder ball.

[0009] In the above technical solution, the chip includes a controller chip and a flash memory chip, and the controller chip and the flash memory chip are arranged adjacent to each other.

[0010] In the above technical solution, dummy chips are also provided in the substrate, and the dummy chips are made of semiconductor materials.

[0011] In the above technical solution, the substrate is packaged with plastic encapsulant, and a heat dissipation layer is provided on the upper surface of the plastic encapsulant.

[0012] In the above technical solution, positioning grooves or positioning holes are provided at the edge of the substrate.

[0013] In the above technical solution, the metal wiring layer includes a multi-layer interconnect structure to achieve efficient signal transmission between chips and between the chips and external devices.

[0014] In the above technical solution, the solder ball array is treated by gold plating or nickel plating.

[0015] In the above technical solution, the controller chip and the flash memory chip are directly connected through the metal wiring layer on the substrate, and independent power supply and ground channels are provided.

[0016] The beneficial effects of the present utility model are as follows: The process is simple, the cost is low, and it is suitable for mass production applications; it can improve the performance of UFS4x, enhance the user experience of the device, reduce the probability of overheating, provide the feasibility of a heat dissipation solution for subsequent new versions, and promote the development of UFS technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of a packaging structure of a UFS shown in an embodiment of the present utility model;

[0018] Figure 2 It is a schematic diagram of another packaging structure of a UFS shown in an embodiment of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The present utility model will be further described below in conjunction with the drawings and embodiments.

[0020] The concept, specific structure and technical effects of the present utility model will be clearly and completely described below in conjunction with the embodiments and the drawings to fully understand the purpose, features and effects of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative efforts shall fall within the scope of protection of the present utility model. In addition, all the connection / connection relationships involved in the patent do not simply refer to the direct connection of components, but refer to the more optimal connection structure that can be formed by adding or reducing connection accessories according to the specific implementation situation. The various technical features in the creation of the present utility model can be combined with each other without conflict.

[0021] Refer to Figure 1-2As shown in the figure, the present application provides a packaging structure for a UFS, which is characterized by including a substrate 1, a chip 2, and a solder ball array 3 disposed on the substrate 1. Among them, the substrate 1 includes a relative bottom surface and a top surface; the inside of the substrate 1 is a base material, and the surface of the base material is an etched metal circuit layer; an IO solder ball 4 is disposed at the center of the bottom surface of the substrate 1; the chip 2 is packaged in the substrate 1 and electrically connected to the IO solder ball 4; the solder ball array 3 is disposed beside the IO solder ball 4, and the diameter of the solder ball array 3 is smaller than that of the IO solder ball 4.

[0022] In a possible implementation manner, the chip 3 includes a controller chip 21 and a flash memory chip 22, and the controller chip 21 and the flash memory chip 22 are disposed adjacent to each other.

[0023] In an exemplary embodiment, the diameter of the solder ball array 3 is 0.2 - 0.25 mm, the diameter of the IO solder ball is 0.3 - 0.35 mm. Since the diameter of the IO solder ball is larger, it is welded to the application end, and the surrounding solder ball array 3 has a smaller diameter and can be suspended for heat conduction and heat dissipation. This design does not affect the original design of the application end and can be directly applied.

[0024] Optionally, the solder ball array can also be made of aluminum and copper materials, and adaptively become an aluminum ball array or a copper ball array.

[0025] In a possible implementation manner, a dummy chip 5 is further disposed in the substrate 1, and the dummy chip 5 is made of semiconductor material.

[0026] In another possible implementation manner, the substrate 1 is encapsulated with a plastic encapsulant, and a heat dissipation layer is disposed on the upper surface of the plastic encapsulant.

[0027] As Figure 1 shown, there is no stacking between the small - size flash memory chip 22 and the controller chip 21. At this time, in traditional packaging, the controller chip 21 is ground into a thin sheet, while in the present application, the original thickness of the controller chip 21 is retained because the essence of the chip is a semiconductor material, and compared with the plastic encapsulant, the thermal conductivity of the semiconductor is better.

[0028] And Figure 2 in, due to space reasons, the large - size flash memory chip 22 must be stacked with the controller chip 21. Although the controller chip 21 must be ground into a thin sheet for convenient stacking, for the exposed part, the above - mentioned dummy chip 5 can be added. The material of the dummy chip is also semiconductor material, and by using the characteristic that the thermal conductivity of the semiconductor is better than that of the plastic encapsulant, the heat conduction ability is improved.

[0029] In a possible implementation manner, a positioning groove or a positioning hole is disposed at the edge of the substrate 1 to facilitate precise installation and positioning on the circuit board.

[0030] In a possible implementation, the metal wiring layer includes a multi-layer interconnect structure to achieve efficient signal transmission between chips and between the chip and external devices.

[0031] In a possible implementation, the solder ball array 3 is treated by gold plating or nickel plating to improve its corrosion resistance and electrical conductivity.

[0032] In a possible implementation, the controller chip 21 and the flash memory chip 22 are directly connected through the metal wiring layer on the substrate 1, and an independent power supply and ground wire channel are provided to optimize power consumption management and signal integrity.

[0033] The process of this application is simple and has a low cost, making it suitable for mass production applications; it can improve the performance of UFS 4x, enhance the user experience of the device, reduce the probability of overheating, provide the feasibility of a heat dissipation solution for subsequent new versions, and promote the development of UFS technology.

[0034] The above is a specific description of the preferred embodiment of the present utility model, but the present utility model is not limited to the described embodiment. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present utility model, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A packaging structure of UFS, characterized in that It includes a substrate, a chip, and a solder ball array disposed on the substrate. Among them, the substrate includes a relative bottom surface and a top surface; the interior of the substrate is a base material, and the surface of the base material is an etched metal wiring layer; an IO solder ball is provided at the center of the bottom surface of the substrate; the chip is encapsulated in the substrate and electrically connected to the IO solder ball; the solder ball array is surrounded beside the IO solder ball, and the diameter of the solder ball array is smaller than that of the IO solder ball.

2. The encapsulation structure of the UFS according to claim 1, characterized in that, The chip includes a controller chip and a flash memory chip, and the controller chip and the flash memory chip are arranged adjacent to each other.

3. The encapsulation structure of the UFS according to claim 1, wherein A dummy chip is also provided in the substrate, and the dummy chip is made of semiconductor material.

4. The encapsulation structure of the UFS according to claim 1, wherein The substrate is encapsulated with a plastic encapsulant, and a heat dissipation layer is provided on the upper surface of the plastic encapsulant.

5. The encapsulation structure of the UFS according to claim 1, wherein Positioning grooves or positioning holes are provided at the edge of the substrate.

6. The encapsulation structure of the UFS according to claim 1, wherein, The metal wiring layer includes a multi-layer interconnect structure to achieve efficient signal transmission between chips and between the chips and external devices.

7. The encapsulation structure of the UFS according to claim 1, characterized in that, The solder ball array is treated by gold plating or nickel plating.

8. The encapsulation structure of the UFS according to claim 2, wherein, The controller chip and the flash memory chip are directly connected through the metal wiring layer on the substrate, and there are independent power and ground channels.

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