Back contact cell, cell assembly and photovoltaic system

Abstract

The utility model relates to the technical field of solar cells, and provides a back contact cell, a cell assembly and a photovoltaic system, the back surface of a silicon substrate of the back contact cell is provided with a plurality of polishing areas and a plurality of suede areas, and a first passivation layer and a first polarity doping layer are sequentially stacked on the polishing areas; the second passivation layer and the second polarity doping layer are sequentially stacked on the suede area and at least cover the suede area, a first transparent conductive film is arranged on the first polarity doping layer, and a second transparent conductive film is arranged on the second polarity doping layer. And the thickness of the part of the second transparent conductive film corresponding to the suede area is smaller than that of the first transparent conductive film. Thus, the thickness of the part, located on the suede area, of the second transparent conductive thin film is set to be small, parasitic absorption at the suede area can be reduced and the double-sided rate of the back contact cell can be improved when light rays on the back face enter, meanwhile, the partial area of the back face is set to be suede, the reflectivity of the light rays on the back face can be further reduced, and therefore the double-sided rate is further improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular, to a back contact cell, a cell module, and a photovoltaic system. Background Art

[0002] Currently, in solar cells, a hybrid back contact cell is a cell in which both the emitter and base contact electrodes are placed on the back surface (non-light-receiving surface) of the cell. There is no metal electrode shielding on the light-receiving surface of the cell, thereby effectively increasing the short-circuit current of the cell.

[0003] In order to improve the efficiency of the back contact cell, one of the doped layers of the back contact cell can be set as a polysilicon layer, and the other doped layer can be set as different types of doped layers such as an amorphous silicon layer or a microcrystalline silicon layer. Then, a transparent conductive film layer such as TCO is set to form a hybrid back contact cell, that is, the HBC (Hybrid Back Contact) technology. However, the bifaciality of the hybrid back contact cell in the related art is relatively low. Therefore, how to improve the bifaciality of the hybrid back contact cell has become a technical problem studied by those skilled in the art. Summary of the Utility Model

[0004] The present application provides a back contact cell, a cell module, and a photovoltaic system.

[0005] The present application is implemented as follows. The back contact cell of the embodiment of the present application includes:

[0006] A silicon substrate having opposite front and back surfaces, the back surface including a plurality of polished regions and a plurality of textured regions arranged alternately along a first direction, both the polished regions and the textured regions extending along a second direction, and the second direction intersecting the first direction;

[0007] A first passivated contact structure including a first passivation layer and a first polar doping layer sequentially stacked on the polished region;

[0008] A second passivated contact structure including a second passivation layer and a second polar doping layer sequentially stacked on the textured region, and the second passivation layer and the second polar doping layer covering at least the textured region; and

[0009] A first transparent conductive film and a second transparent conductive film, wherein the first transparent conductive film is stacked on the first polar doping layer and covers at least a partial region of the first polar doping layer, the second transparent conductive film is stacked on the second polar doping layer and covers at least a partial region of at least a part of the second polar doping layer corresponding to the matte surface region, the second transparent conductive film is insulated and spaced from the first transparent conductive film, and the thickness of the part of the second transparent conductive film corresponding to the matte surface region is less than the thickness of the first transparent conductive film.

[0010] In some embodiments, the first passivation layer is a tunneling oxide layer, and the first polar doping layer is a doped polysilicon layer;

[0011] The second passivation layer is at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer, and the second polar doping layer is at least one of a doped amorphous silicon layer and doped microcrystalline silicon.

[0012] In some embodiments, the thickness of the part of the second transparent conductive film corresponding to the matte surface region is 75 nm - 85 nm.

[0013] In some embodiments, the thickness of the first transparent conductive film is 90 nm - 155 nm.

[0014] In some embodiments, the ratio between the thickness of the first transparent conductive film and the thickness of the part of the second transparent conductive film corresponding to the matte surface region is 1.2 - 1.8.

[0015] In some embodiments, the first polar doping layer and the second polar doping layer are adjacent in the first direction; or

[0016] The first polar doping layer and the second polar doping layer are spaced apart in the first direction.

[0017] In some embodiments, the first transparent conductive film is only stacked on the first polar doping layer, the second passivation layer and the second polar doping layer are only stacked on the matte surface region, and the second transparent conductive film is only stacked on the second polar doping layer.

[0018] In some embodiments, the first polar doping layer is a base region doping layer, the second polar doping layer is an emitter doping layer, and the sum of the orthographic projection areas of all the second polar doping layers on the silicon substrate is greater than the sum of the orthographic projection areas of all the first polar doping layers on the silicon substrate.

[0019] In some embodiments, the ratio of the sum of the orthographic projection areas of all the second polar doping layers on the silicon substrate to the area of the back surface is 65% - 85%.

[0020] In some embodiments, at a preset position of at least a part of the second passivation contact structure, the second passivation layer has a passivation extension extending to cover a partial area of the first polar doping layer, and the second polar doping layer has a doping extension extending to cover the passivation extension, so as to form a stacked structure on a part of the polishing area, which is sequentially stacked by the first passivation layer, the first polar doping layer, the passivation extension, and the doping layer extension;

[0021] The second transparent conductive film has a film extension extending to at least a partial area of the doping extension, and the first transparent conductive film is at least stacked on the area of the first polar doping layer not covered by the passivation extension and the doping extension.

[0022] In some embodiments, the thickness of the film extension is greater than the thickness of the part of the second transparent conductive film corresponding to the matte area.

[0023] In some embodiments, the thickness of the film extension is the same as the thickness of the first transparent conductive film.

[0024] The present application further provides a battery assembly, and the battery assembly includes a plurality of the back contact batteries described in any one of the above.

[0025] The present application further provides a photovoltaic system, and the photovoltaic system includes the battery assembly described above.

[0026] In the back contact battery, the battery assembly, and the photovoltaic system according to the embodiments of the present application, the back surface of the silicon substrate has a plurality of polishing areas and a plurality of matte areas. The first passivation layer and the first polar doping layer are sequentially stacked on the polishing area. The second passivation layer and the second polar doping layer are sequentially stacked on the matte area and at least cover the matte area. A first transparent conductive film is provided on the first polar doping layer, and a second transparent conductive film is provided on the second polar doping layer, and the two are insulated and spaced apart. The thickness of the part of the second transparent conductive film corresponding to the matte area is less than the thickness of the first transparent conductive film. In this way, the thickness of the part of the second transparent conductive film located on the matte area is set to be smaller, so that when the backlight enters, parasitic absorption at the matte area can be reduced, and the bifaciality of the back contact battery can be improved. At the same time, part of the back surface is set to be matte, which can further reduce the reflectivity of the backlight, thereby further improving the bifaciality.

[0027] The additional aspects and advantages of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present application. Description of the Drawings

[0028] Figure 1It is a schematic diagram of a module of a photovoltaic system provided by an embodiment of the present application;

[0029] Figure 2 It is a schematic diagram of a module of a battery component provided by an embodiment of the present application;

[0030] Figure 3 It is a cross-sectional schematic diagram of a back-contact battery provided by an embodiment of the present application;

[0031] Figure 4 It is another cross-sectional schematic diagram of a back-contact battery provided by an embodiment of the present application;

[0032] Figure 5 It is a planar structure schematic diagram of a back-contact battery provided by an embodiment of the present application;

[0033] Figure 6 It is yet another cross-sectional schematic diagram of a back-contact battery provided by an embodiment of the present application.

[0034] Main element symbol description:

[0035] Photovoltaic system 1000, battery component 200, back-contact battery 100, silicon substrate 10, front surface 11, back surface 12, polished area 121, textured area 122, first passivation contact structure 20, first passivation layer 21, first polar doping layer 22, second passivation contact structure 30, second passivation layer 31, second polar doping layer 32, preset position 320, doping extension 321, first transparent conductive film 40, second transparent conductive film 50. Detailed implementation manners

[0036] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "lateral", "longitudinal", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of this application, "a plurality of" means two or more unless specifically defined otherwise.

[0039] In the description of this application, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" should be construed broadly. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, an electrical connection or a connection capable of mutual communication; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0040] In this application, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but in contact through additional features therebetween. Moreover, the first feature being "above", "over" and "on top of" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly below and obliquely below the second feature, or merely indicating that the first feature has a lower horizontal height than the second feature.

[0041] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure of this application, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit this application. In addition, this application may repeat reference numerals and / or reference letters in different examples. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various embodiments and / or arrangements discussed. In addition, this application provides examples of various specific processes and materials, but those of ordinary skill in the art may be aware of the application of other processes and / or the use scenarios of other materials.

[0042] Please refer to Figure 1 - Figure 2 , the photovoltaic system 1000 in the embodiment of this application may include the battery assembly 200 in the embodiment of this application, and the battery assembly 200 in the embodiment of this application may include a plurality of back-contact batteries 100 in the embodiment of this application.

[0043] In an embodiment of the present application, multiple back-contact batteries 100 in the battery module 200 can be connected in series to form multiple battery strings. Each battery string can be connected in series, in parallel, or in a series-parallel combination to achieve the current confluence output. For example, the connection between each battery cell can be realized by welding a welding tape, and the connection between each battery string can be realized by a bus bar. In some embodiments, each battery string can form a battery cell array, and then be encapsulated together with a front plate, a front encapsulant film, a back encapsulant film, and a back plate to form the battery module 200.

[0044] Please refer to Figure 3 , the back-contact battery 100 in the embodiment of the present application may include a silicon substrate 10, a first passivation contact structure 20, a second passivation contact structure 30, a first transparent conductive thin film 40, and a second transparent conductive thin film 50.

[0045] The silicon substrate 10 has opposite front surface 11 and back surface 12. The back surface 12 includes a plurality of polished regions 121 and a plurality of textured regions 122. The plurality of polished regions 121 and the plurality of textured regions 122 are alternately arranged along a first direction, and both the polished regions 121 and the textured regions 122 extend along a second direction, and the second direction intersects with the first direction.

[0046] Specifically, as Figure 3 shown, the polished regions 121 and the textured regions 122 can be alternately arranged along the lateral direction of the silicon substrate 10 and both extend along the longitudinal direction. That is, the first direction can be the lateral direction of the back-contact battery 100, and the second direction can be the lateral direction of the back-contact battery 100, and the two are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions. For example, the two can be the diagonal directions of the silicon substrate 10 respectively, and specific limitations are not made here.

[0047] The first passivation contact structure 20 may include a first passivation layer 21 and a first polar doping layer 22 that are sequentially stacked on the polished region 121 (the first passivation contact structure 20 is provided on each polished region 121, and the numbers of the two are in one-to-one correspondence). That is, the first passivation layer 21 is stacked on the polished region 121, and the first polar doping layer 22 is stacked on the first passivation layer 21.

[0048] The second passivation contact structure 30 may include a second passivation layer 31 and a second polar doping layer 32 that are sequentially stacked on the textured region 122 (the second passivation contact structure 30 is provided on each textured region 122, and the numbers of the two are in one-to-one correspondence). The second passivation layer 31 and the second polar doping layer 32 at least cover the textured region 122.

[0049] Exemplarily, in some embodiments, the first polar doping layer 22 only overlays the polished area 121, and the second polar doping layer 32 covers at least a part of the textured area 122. The surface of the part of the second polar doping layer 32 corresponding to the textured area 122 facing away from the silicon substrate 10 can be textured. That is to say, in the second passivation contact structure 30, the second passivation layer 31 is disposed on the textured area 122, and the second polar doping layer 32 is stacked on the second passivation layer 31. The back surface of the part of the second polar doping layer 32 corresponding to the textured area 122 can be textured.

[0050] As Figure 3 shown, the first transparent conductive film 40 is stacked on the first polar doping layer 22 and covers at least a part of the first polar doping layer 22. The second transparent conductive film 50 is stacked on the second polar doping layer 32 and covers at least a part of the part of the second polar doping layer 32 corresponding to the textured area 122. The second transparent conductive film 50 and the first transparent conductive film 40 are disposed at an insulating interval.

[0051] Among them, the thickness of the part of the second transparent conductive film 50 corresponding to the textured area 122 is less than the thickness of the first transparent conductive film 40. That is, the thickness of the part of the second transparent conductive film 50 located at the textured area 122 is less than the thickness of the first transparent conductive film 40.

[0052] It should be noted that in this article, when a certain film layer covers or overlays a certain surface or a part of a certain film layer, it can be that the film layer is directly stacked on the surface or a certain film layer, or there may be other film layers between the film layer and the surface or the film layer. The coverage only serves to define the specific setting range of the film layer.

[0053] In addition, in this article, the part of a certain film layer corresponding to a certain area or a certain layer structure refers to the part of the film layer that overlaps with the area or another certain layer structure in the thickness direction. For example, the part of the second transparent conductive film 50 corresponding to the textured area 122 refers to the area of the second transparent conductive film 50 covering the textured area 122. If there are similar descriptions below, the same understanding can be referred to.

[0054] In the back contact battery 100, battery module 200, and photovoltaic system 1000 in the embodiments of the present application, the back surface 12 of the silicon substrate 10 has a plurality of polished regions 121 and a plurality of textured regions 122. The first passivation layer 21 and the first polar doping layer 22 are sequentially stacked on the polished region 121. The second passivation layer 31 and the second polar doping layer 32 are sequentially stacked on the textured region 122 and at least cover the textured region 122. A first transparent conductive thin film 40 is provided on the first polar doping layer 22, and a second transparent conductive thin film 50 is provided on the second polar doping layer 32, and the two are arranged at an insulating interval. The thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122 is less than the thickness of the first transparent conductive thin film 40. In this way, by setting the thickness of the portion of the second transparent conductive thin film 50 located on the textured region 122 to be smaller, when light enters the back surface 12, parasitic absorption at the textured region 122 can be reduced, and the bifaciality of the back contact battery 100 can be improved. At the same time, by setting a portion of the back surface 12 to be textured, the reflectivity of light on the back surface 12 can be further reduced, thereby further improving the bifaciality.

[0055] That is to say, in the present application, a portion of the back surface 12 is set as the textured region 122 and the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122 is set to be smaller. Through such an optimized design, the bifaciality of the back contact battery 100 can be improved.

[0056] Specifically, in the embodiments of the present application, the silicon substrate 10 can be an N-type silicon substrate or a P-type silicon substrate, and specific limitations are not made here. The first polar doping layer 22 can be an N-type doping layer, and the second polar doping layer 32 can be a P-type doping layer, or the first polar doping layer 22 is a P-type doping layer and the second polar doping layer 32 is a P-type doping layer. Specific limitations are not made here, as long as the polarities of the two are opposite. In addition, in the back contact battery of the present application, a first electrode (not shown in the figure) can also be provided on the first transparent conductive thin film 40, and a second electrode (not shown in the figure) can also be provided on the first transparent conductive thin film 40. The collection, confluence, and output of current can be achieved through the first electrode and the second electrode.

[0057] Both the first transparent conductive thin film 40 and the second transparent conductive thin film 50 can be film layers with both light transmission and conductivity, such as TCO film layers. Both can be a single film layer or a multi-layer composite film layer, and specific limitations are not made here.

[0058] In the present application, the back contact battery 100 can be a hybrid back contact battery. The first passivation layer 21 can be a tunneling oxide layer, for example, a tunneling silicon oxide layer. The first polar doping layer 22 can be a doped polysilicon layer. The second passivation layer 31 can be at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer (such as a tunneling silicon oxide layer), and the second polar doping layer 32 is at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer.

[0059] In such a case, the first passivation contact structure 20 is a tunneling passivation contact structure, and the second passivation contact structure 30 is a heterojunction passivation contact structure. In this way, by designing the first polar doping layer 22 as a doped polysilicon layer and the second polar doping layer 32 as at least one of a doped amorphous silicon layer and a doped microcrystalline silicon layer, a hybrid back-contact battery 100 can be formed, improving the efficiency of the back-contact battery 100.

[0060] Meanwhile, the region corresponding to the doped polysilicon is set as a polished region 121, which can avoid a significant reduction in the passivation effect of the region corresponding to the doped polysilicon and affect the efficiency. The passivation effect of the doped amorphous silicon and / or the doped microcrystalline silicon is better. Setting the region corresponding to the doped amorphous silicon and / or the doped microcrystalline silicon as a textured surface can improve the antireflection effect of the back surface 12, thereby improving the bifaciality of the back-contact battery 100. That is to say, in such a case, while ensuring the passivation effect at the region corresponding to the first polar doping layer 22, the bifaciality of the back-contact battery 100 can be further improved.

[0061] In some embodiments, the first polar doping layer 22 may be a P-type doped polysilicon layer, and the second polar doping layer 32 may be at least one of an N-type doped amorphous silicon layer and an N-type doped microcrystalline silicon layer. Of course, in other embodiments, it may also be that the first polar doping layer 22 is an N-type doped polysilicon layer, and the second polar doping layer 32 may be at least one of a P-type doped amorphous silicon layer and a P-type doped microcrystalline silicon layer, which is not specifically limited herein.

[0062] In some embodiments, the thickness of the portion of the second transparent conductive film 50 corresponding to the textured region 122 may be 75 nm - 85 nm.

[0063] Thus, by setting the thickness of the portion of the second transparent conductive film 50 corresponding to the textured region 122 within this reasonable range, it is possible to avoid the thickness of the portion of the second transparent conductive film 50 corresponding to the textured region 122 being too small, which may lead to excessive manufacturing difficulty, and it can also avoid the poor passivation effect on the second polar doping layer 32 due to its small thickness. At the same time, it can also avoid the increase in cost due to excessive thickness. That is to say, setting the thickness within the above reasonable range can reduce the parasitic absorption on the back surface, improve the bifaciality, while reducing the process difficulty, ensuring the passivation effect, and controlling the cost.

[0064] Specifically, in such an embodiment, the thickness of the portion of the second transparent conductive film 50 corresponding to the textured region 122 may be, for example, 75 nm, 76 nm, 77 nm, 78 nm, 79 nm, 80 nm, 81 nm, 82 nm, 83 nm, 84 nm, 85 nm or any value between 75 nm - 85 nm, which is not specifically limited herein.

[0065] In some embodiments, the thickness of the first transparent conductive film 40 may be 90 nm - 155 nm.

[0066] Thus, by setting the thickness of the first transparent conductive film 40 within this reasonable range, it is possible to avoid the situation where the thickness of the part of the first transparent conductive film 40 corresponding to the matte surface area 122 is too small, which may lead to excessive manufacturing difficulty, and it can also avoid the situation where the thickness is too small, resulting in a poor passivation effect on the first polar doping layer 22. At the same time, it can also avoid the situation where the thickness is too large, resulting in increased costs.

[0067] Specifically, in such an embodiment, the thickness of the part of the second transparent conductive film 50 corresponding to the matte surface area 122 may be, for example, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm or any value between 90 nm - 155 nm, and specific values are not limited here.

[0068] In some embodiments, the ratio of the thickness of the first transparent conductive film 40 to the thickness of the part of the second transparent conductive film 50 corresponding to the matte surface area 122 is 1.2 - 1.8.

[0069] Thus, by setting the ratio of the thickness of the first transparent conductive film 40 to the thickness of the part of the second transparent conductive film 50 corresponding to the matte surface area 122 within this reasonable range, it is possible to achieve a better matching effect between the parasitic absorption and passivation effect of the back surface 12.

[0070] Specifically, in such an embodiment, the ratio between the two may be, for example, 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8 or any value between 1.2 - 1.8, and specific values are not limited here.

[0071] Please refer to Figure 3 , in some embodiments, the first polar doping layer 22 and the second polar doping layer 32 are adjacent in the first direction. That is, the polished area 121 and the matte surface area 122 are continuous and adjacent in the first direction, and the first polar doping layer 22 and the second polar doping layer 32 are in contact.

[0072] Thus, it is possible to minimize the area of the back surface 12 of the silicon substrate 10 that is not covered by the first polar doping layer 22 and the second polar doping layer 32 (i.e., the area of the undoped region), thereby improving the efficiency of the back contact battery 100.

[0073] Specifically, in such an embodiment, the first polar doping layer 22 may be a doped polysilicon layer, and the second polar doping layer 32 may be a doped amorphous silicon layer and / or a doped microcrystalline silicon layer. The lateral conductivity of the doped amorphous silicon layer and the doped microcrystalline silicon layer is poor. Therefore, in order to improve the efficiency, the first polar doping layer 22 and the second polar doping layer 32 may be arranged adjacently.

[0074] Of course, as Figure 4 shown, in other embodiments, the first polar doping layer 22 and the second polar doping layer 32 may also be spaced apart in the first direction, and there may be a spacer region between them or they may be separated by other dielectric film layers, which are not specifically limited herein.

[0075] Further, please refer to Figure 3 and Figure 4 , in some embodiments, the first transparent conductive film 40 may be stacked only on the first polar doping layer 22, the second passivation layer 31 and the second polar doping layer 32 may be stacked only on the matte surface region 122, and the second transparent conductive film 50 may be stacked only on the second polar doping layer 32.

[0076] In this way, the insulation performance between the first transparent conductive film 40 and the second transparent conductive film 50 can be improved, and leakage can be avoided.

[0077] Specifically, in such an embodiment, as Figure 3 shown, when the first polar doping layer 22 and the second polar doping layer 32 are adjacent, the first transparent conductive film 40 may cover most of the region of the first polar doping layer 22, and the second transparent conductive film 50 completely covers the second polar doping layer 32 or covers most of the region of the second polar doping layer 32. In such a case, the distance between the two transparent conductive films can be controlled by controlling the sizes of the regions covered by the two transparent conductive films, thereby ensuring their insulation performance.

[0078] As Figure 4 shown, when the first polar doping layer 22 and the second polar doping layer 32 are spaced apart, the first transparent conductive film 40 may completely cover the first polar doping layer 22 or cover most of the region of the first polar doping layer 22, and the second transparent conductive film 50 may completely cover the second polar doping layer 32 or cover most of the region of the second polar doping layer 32. In such a case, the distance between the two transparent conductive films can be controlled by controlling the sizes of the regions covered by the adjacent first polar doping layer 22 and the second polar doping layer 32, thereby ensuring their insulation performance.

[0079] In some embodiments, the first polar doping layer 22 may be a base doping layer, and the second polar doping layer 32 may be an emitter doping layer. The sum of the orthographic projection areas of all the second polar doping layers 32 on the silicon substrate 10 is greater than the sum of the orthographic projection areas of all the first polar doping layers 22 on the silicon substrate 10.

[0080] Thus, the area of the emitter in the back-contact cell 100 can be increased, thereby improving the efficiency of the back contact.

[0081] Specifically, in such an embodiment, when the silicon substrate 10 is an N-type silicon substrate 10, the first polar doping layer 22 is an N-type doping layer, and the second polar doping layer 32 is a P-type doping layer. When the silicon substrate 10 is a P-type silicon substrate 10, the first polar doping layer 22 is a P-type doping layer, and the second polar doping layer 32 is an N-type doping layer.

[0082] Further, in such an embodiment, the ratio of the sum of the orthographic projection areas of all the second polar doping layers 32 on the silicon substrate 10 to the area of the back surface 12 is 65%-85%, and the ratio of the sum of the orthographic projection areas of all the first polar doping layers 22 on the silicon substrate 10 to the area of the back surface 12 is 15%-35%.

[0083] Thus, by setting the area ratios of the first polar doping layer 22 and the second polar doping layer 32 within the above reasonable ranges, the area of the emitter region can be increased while ensuring the area ratio of the base region, further optimizing the efficiency of the back-contact cell 100.

[0084] Specifically, in such an embodiment, the ratio of the sum of the orthographic projection areas of all the second polar doping layers 32 on the silicon substrate 10 to the area of the back surface 12 may be, for example, 65%, 70%, 75%, 80%, 85% or any value between 65%-85%, and is not specifically limited herein. The ratio of the sum of the orthographic projection areas of all the first polar doping layers 22 on the silicon substrate 10 to the area of the back surface 12 may be, for example, 15%, 20%, 25%, 30%, 35% or 15%-35%.

[0085] It can be understood that, in such an embodiment, when the first polar doping layer 21 completely covers the polished area 121 and the second polar doping layer 32 completely covers the textured area 122, the sum of the areas of all the textured areas 122 is greater than the sum of the areas of all the polished areas 121. In such a case, the ratio of the sum of the areas of all the textured areas 122 to the back surface 12 is 65%-85%, and the ratio of the sum of the areas of all the polished areas 121 to the back surface 12 is 15%-35%.

[0086] Please refer to Figure 5 and Figure 6, in some embodiments, at a preset position 320 of at least a part of the second passivation contact structure 30, the second passivation layer 31 has a passivation extension 311 that extends to cover a partial area of the first polar doping layer 22, and the second polar doping layer 32 has a doping extension 321 that extends to cover the passivation extension 311, so as to form a stacked structure 60 that is sequentially stacked by the first passivation layer 21, the first polar doping layer 22, the passivation extension 311, and the doping layer extension on a partial polishing area 121;

[0087] The second transparent conductive film 50 has a film extension 51 that extends to at least a partial area of the doping extension 321, and the first transparent conductive film 40 is at least stacked on an area of the first polar doping layer 22 that is not covered by the passivation extension 311 and the doping extension 321.

[0088] In this way, through the extension arrangement of the stacked structure 60 and the second transparent conductive film 50, the back-contact battery 100 can form a leakage channel at the position of the stacked structure 60, so as to form a leakage point in the thickness direction, which can reduce the reverse breakdown voltage when the back-contact battery 100 is blocked, thereby improving the anti-thermal-spot performance of the back-contact battery 100 and reducing the thermal-spot risk of the battery module 200.

[0089] Specifically, the doping extension 321 forms a leakage contact with the first polar doping layer 22 at the stacked structure 60, and the stacked structure 60 is a leakage contact structure. On the doping extension 321, the area covered by the film extension 51 layer is an effective leakage area, and the area not covered by the second transparent conductive film 50 is an ineffective leakage area. In the back-contact battery 100, only the effective leakage area can function to improve the anti-thermal-spot performance.

[0090] In such an embodiment, the first polar doping layer 22 is a doped polysilicon layer, preferably an N-type doped polysilicon layer, and the second polar doping layer 32 is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, preferably a P-type doped amorphous silicon layer and / or an N-type doped microcrystalline silicon layer.

[0091] In addition, as Figure 5 shown, in the embodiments of the present application, in the back-contact battery 100, all the second polar doping layers 32 may have the preset position 320, that is, all the second polar doping layers may have a doping extension 321 that extends to the first polar doping layer 22 at the preset position 320, or only some of the second polar doping layers 32 may have a doping extension 321 that extends to the first polar doping layer 22 at the preset position 320. There is no specific limitation here, as long as the leakage contact area formed by the doping extension 321 and the first polar doping layer 22 does not cause a large reduction in the efficiency of the back-contact battery 100.

[0092] In addition, for a single second-polarity doping layer 32, a plurality of doping extensions 321 may be provided on the single second-polarity doping layer 32, so as to form a plurality of stacked structures 60 on a single polishing region 121. When the single second-polarity doping layer 32 has a plurality of doping extensions 321, the plurality of doping extensions 321 may be arranged at intervals along the second direction, and specific arrangements are not limited herein.

[0093] In addition, in some embodiments, for a single second-polarity doping layer 32, doping extensions 321 may be formed only on one side, or may be formed on both sides. Specific arrangements are not limited herein. Figure 5 As shown, doping extensions 321 are provided on both sides of the second-polarity doping layer 32. Figure 6 As shown, doping extensions 321 are provided only on one side of the second-polarity doping layer 32, but no limitations are imposed in this application.

[0094] In some embodiments, the thickness of the thin-film extension 51 is greater than the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122. Preferably, the thickness of the thin-film extension 51 may be the same as the thickness of the first transparent conductive thin film 40.

[0095] Thus, by setting the thicknesses of the first transparent conductive thin film 40 and the thin-film extension 51 located on the doped polysilicon layer to be relatively thick, the passivation effect of the corresponding region of the doped polysilicon layer can be improved. While setting the thickness of the portion of the second transparent conductive thin film 50 corresponding to the textured region 122 to be relatively thin can reduce parasitic absorption while efficiently passivating the doped amorphous silicon and / or doped polysilicon, and improve the bifaciality.

[0096] Please refer to Figure 3 , in some embodiments, the length L1 of the doping extension 321 in the first direction may be 10 μm - 600 μm, and the length L2 of the doping extension 321 in the second direction may be 10 μm - 5000 μm.

[0097] Thus, by reasonably setting the lengths of the doping extension 321 in each direction, the area of the doping extension 321 can be controlled within a reasonable range, so as to control the effective leakage contact area of a single doping extension 321 within a reasonable range, avoiding the situation that the anti-thermal-spot performance cannot reach the expected effect due to too small a leakage contact area, and also avoiding too large a leakage contact area resulting in excessive efficiency loss. That is, such a setting can balance the relationship between the anti-thermal-spot performance and efficiency, making it reach a better matching effect.

[0098] Specifically, in such an embodiment, the length L1 of the doped extension portion 321 in the first direction may be, for example, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, or any value between 10 μm and 600 μm.

[0099] The length L2 of the doped extension portion 321 in the second direction may be, for example, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, 550 μm, 600 μm, 650 μm, 700 μm, 750 μm, 800 μm, 850 μm, 900 μm, 950 μm, 1000 μm, 1500 μm, 2000 μm, 2500 μm, 3000 μm, 3500 μm, 4000 μm, 4500 μm, 5000 μm, or any value between 10 μm and 5000 μm.

[0100] Further, in such an embodiment, the length L1 of the doped extension portion 321 in the first direction is preferably 10 μm - 150 μm, and the length L2 of the doped extension portion 321 in the second direction is preferably 20 μm - 500 μm.

[0101] In some embodiments, the length of the thin film extension portion 51 in the first direction is greater than or equal to 10 μm.

[0102] In this way, it is possible to avoid the poor anti - hot - spot performance caused by the too - small extension length of the thin film extension portion 51.

[0103] Further, in such an embodiment, the ratio between the length of the thin film extension portion 51 in the first direction and the length of the doped extension portion 321 in the first direction is greater than 90%, such as 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 99%, etc.

[0104] In this way, by setting the ratio of the length of the thin film extension portion 51 to the length of the doped extension portion 321 within the preferably range greater than 90%, it is possible to effectively improve the anti - hot - spot performance while ensuring the conversion efficiency.

[0105] Specifically, as described above, in some embodiments, the length of the doped extension 321 in the first direction is 10 μm - 600 μm, preferably 10 μm - 150 μm. Then, in this embodiment, the minimum value of the length of the portion of the second transparent conductive thin film 50 extending onto the doped extension 321 in the first direction is greater than 9 μm, and the maximum value can be greater than 540 μm and less than or equal to 600 μm, preferably greater than 135 μm and less than 150 μm.

[0106] Please refer to Figure 5 , in some embodiments, on a single second-polarity doped layer 32, the number of doped extensions 321 can be multiple, and the multiple doped extensions 321 are arranged at intervals in the second direction. That is, on one side of the second-polarity doped layer 32 in the second direction, there are multiple doped extensions 321 arranged at intervals.

[0107] In this way, by providing multiple isolated doped extensions 321 on the second-polarity doped layer 32, it is possible to avoid excessive leakage contact area on a single second-polarity doped layer 32, which may cause excessive efficiency loss.

[0108] It can be understood that, in some embodiments, when the second-polarity doped layer 32 forms leakage contacts with two adjacent first-polarity doped layers 22, doped extensions 321 are formed on both sides of the second-polarity doped layer 32 in the first direction. When the second-polarity doped layer 32 forms a leakage contact with only one first-polarity doped layer 22, a doped extension 321 is formed only on one side of the second-polarity doped layer 32 in the first direction.

[0109] Further, as Figure 5 shown, in some embodiments, in the second direction, the distance H1 between two adjacent doped extensions 321 is 1 cm - 10 cm.

[0110] In this way, it is possible to avoid the distance H1 between two adjacent doped extensions 321 being too small, resulting in over-concentration of leakage points and inability to dissipate heat in time, leading to a significant increase in temperature.

[0111] Specifically, in such an embodiment, the distance H1 between two adjacent doped extensions 321 can be, for example, 1 cm, 1.5 cm, 2 cm, 2.5 cm, 3 cm, 3.5 cm, 4 cm, 4.5 cm, 5 cm, 5.5 cm, 6 cm, 6.5 cm, 7 cm, 7.5 cm, 8 cm, 8.5 cm, 9 cm, 9.5 cm, 10 cm or any value between 1 cm - 10 cm.

[0112] Further, in such an embodiment, in the second direction, the distance H1 between two adjacent doped extensions 321 is preferably greater than or equal to 2 cm and less than 4 cm.

[0113] Thus, through the research and demonstration of the inventors of this application, setting the spacing within this preferred range can avoid excessive heat concentration to the greatest extent while setting a larger number of doped extensions 321. In other words, this can balance the relationship between anti-hot spot performance and excessive heat concentration, so as to achieve the optimal matching effect.

[0114] Specifically, in such an embodiment, the distance H1 between two adjacent doped extensions 321 may preferably be, for example, 2 cm, 2.2 cm, 2.4 cm, 2.6 cm, 2.8 cm, 3 cm, 3.1 cm, 3.2 cm, 3.3 cm, 3.4 cm, 3.5 cm, 3.6 cm, 3.7 cm, 3.9 cm, or 3.95 cm.

[0115] In some embodiments, in the back contact cell 100, the distribution density of the doped extensions 321 is 0.01 per cm 2 -1.5 pieces / cm 2 Thus, by properly controlling the distribution density of the doped extension portion 321 , it is possible to avoid leakage points being too concentrated.

[0116] In such an embodiment, the distribution density of the doped extensions 321 refers to the ratio between the sum of the number of the doped extensions 321 on the back contact cell 100 and the area of the back side 12 of the back contact cell 100. Specifically, the distribution density of the doped extensions 321 can be, for example, 0.01 per cm 2 , 0.05 pieces / cm 2 , 0.1 / cm 2 , 0.2 pieces / cm 2 , 0.3 pieces / cm 2 , 0.4 / cm 2 , 0.5 / cm 2 , 0.6 pieces / cm 2 , 0.7 pieces / cm 2 , 0.8 pieces / cm 2 , 0.9 pieces / cm 2 , 1 piece / cm 2 , 1.1 / cm 2 , 1.2 pieces / cm 2 , 1.3 pieces / cm 2 , 1.4 / cm 2 , 1.5 pieces / cm 2 or 0.01 / cm 2 -1.5 pieces / cm 2 Any value between .

[0117] In some embodiments, in a single doped extension 321, the area of the thin film extension 51 is 100 μm 2 -50000 μm 2 .

[0118] Thus, by controlling the area of the thin film extension 51 within this reasonable range, the anti-thermal spot performance can be improved while ensuring that the efficiency loss is not too large.

[0119] Specifically, in such an embodiment, the area of a single thin film extension 51 can be, for example, 100 μm 2 , 200 μm 2 , 300 μm 2 , 350 μm 2 , 400 μm 2 , 450 μm 2 , 480 μm 2 , 500 μm 2 , 600 μm 2 , 700 μm 2 , 800 μm 2 , 900 μm 2 , 1000 μm 2 , 1100 μm 2 , 1200 μm 2 , 1300 μm 2 , 1400 μm 2 , 1500 μm 2 , 2000 μm 2 , 3000 μm 2 , 4000 μm 2 , 5000 μm 2 , 6000 μm 2 , 7000 μm 2 , 8000 μm 2 , 9000 μm 2 , 10000 μm 2 , 15000 μm 2 , 20000 μm 2 , 25000 μm 2 , 30000 μm 2 , 35000 μm 2 , 40000 μm 2 , 45000 μm 2 , 50000 μm 2 or any value between 100 μm 2 -50000 μm 2 .

[0120] In some embodiments, in the back-contact battery 100, the ratio of the sum of the areas of all the thin-film extensions 51 (i.e., the sum of the effective leakage areas on each doped extension 321 in the back-contact battery 100) to the area of the back surface 12 is 1.5×10 -8 -1.5×10 -5 .

[0121] Thus, by setting the ratio of the sum of the areas of all the thin-film extensions 51 to the area of the back surface 12 within this reasonable range, it is possible to avoid a situation where the proportion of the leakage contact area is too large and seriously affect the efficiency of the back-contact battery 100. That is to say, it is possible to ensure the efficiency of the back-contact battery 100 while ensuring the anti-thermal-spot performance.

[0122] Specifically, in such an embodiment, the ratio of the two areas can be, for example, 1.5×10 -8 , 2×10 -8 , 2.5×10 -8 , 3.5×10 -8 , 4.5×10 -8 , 4.5×10 -8 , 5×10 -8 , 6×10 -8 , 7×10 -8 , 8×10 -8 , 9×10 -8 , 1×10 -7 , 1×10 -6 , 1×10 -5 , 1.5×10 -5 or any other arbitrary value between 4.5×10 -8 -1.5×10 -5 . Specifically, there is no limitation here. In some embodiments, the ratio between the two is preferably greater than 1.5×10 -8 and less than 4.5×10 -8 .

[0123] In the description of this specification, the descriptions referring to terms such as "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials, or characteristics described in connection with the said embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0124] In addition, the above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A back-contact battery, characterized in that, Comprising: A silicon substrate having opposite front and back surfaces, the back surface including a plurality of polished regions and a plurality of textured regions alternately arranged in a first direction, both the polished regions and the textured regions extending in a second direction, the second direction intersecting the first direction; A first passivated contact structure including a first passivation layer and a first polar doping layer sequentially stacked on the polished region; A second passivated contact structure including a second passivation layer and a second polar doping layer sequentially stacked on the textured region, the second passivation layer and the second polar doping layer covering at least the textured region; And A first transparent conductive film and a second transparent conductive film, the first transparent conductive film being stacked on the first polar doping layer and covering at least a partial region of the first polar doping layer, the second transparent conductive film being stacked on the second polar doping layer and covering at least a partial region of at least a part of the second polar doping layer corresponding to the textured region, the second transparent conductive film being insulated and spaced from the first transparent conductive film, and the thickness of the part of the second transparent conductive film corresponding to the textured region being less than the thickness of the first transparent conductive film.

2. The back contact battery according to claim 1, wherein The first passivation layer is a tunneling oxide layer, and the first polar doping layer is a doped polysilicon layer; The second passivation layer is at least one of an intrinsic amorphous silicon layer or a tunneling oxide layer, and the second polar doping layer is at least one of a doped amorphous silicon layer and doped microcrystalline silicon.

3. The back-contact battery according to claim 1, characterized in that, The thickness of the part of the second transparent conductive film corresponding to the textured region is 75 nm - 85 nm.

4. The back-contact battery according to claim 1, characterized in that, The thickness of the first transparent conductive film is 90 nm - 155 nm.

5. The back-contact battery according to claim 1, characterized in that, The ratio of the thickness of the first transparent conductive film to the thickness of the part of the second transparent conductive film corresponding to the textured region is 1.2 - 1.

8.

6. The back-contact battery according to claim 1, characterized in that, The first polar doping layer and the second polar doping layer are adjacent in the first direction; or The first polar doping layer and the second polar doping layer are spaced apart in the first direction.

7. The back-contact battery according to claim 6, wherein, The first transparent conductive film is only stacked on the first polar doping layer, the second passivation layer and the second polar doping layer are only stacked on the textured region, and the second transparent conductive film is only stacked on the second polar doping layer.

8. The back-contact battery according to claim 1, wherein, The first polar doping layer is a base region doping layer, the second polar doping layer is an emitter doping layer, and the sum of the positive projection areas of all the second polar doping layers on the silicon substrate is greater than the sum of the positive projection areas of all the first polar doping layers on the silicon substrate.

9. The back-contact battery according to claim 8, wherein, The ratio of the sum of the positive projection areas of all the second polar doping layers on the silicon substrate to the area of the back surface is 65% - 85%.

10. The back-contact battery according to claim 1, characterized in that, At a preset position of at least a part of the second passivation contact structure, the second passivation layer has a passivation extension extending to cover a partial area of the first polar doping layer, and the second polar doping layer has a doping extension extending to cover the passivation extension, so as to form a stacked structure in which the first passivation layer, the first polar doping layer, the passivation extension, and the doping layer extension are stacked in sequence on a part of the polishing area; The second transparent conductive thin film has a thin film extension extending to at least a partial area of the doping extension, and the first transparent conductive thin film is at least stacked on an area of the first polar doping layer not covered by the passivation extension and the doping extension.

11. The back-contact battery according to claim 10, characterized in that, The thickness of the thin film extension is greater than the thickness of the part of the second transparent conductive thin film corresponding to the matte area.

12. The back-contact battery according to claim 10, wherein, The thickness of the thin film extension is the same as the thickness of the first transparent conductive thin film.

13. A battery assembly, characterized in that, Comprising a back contact battery according to any one of claims 1-12.

14. A photovoltaic system, characterized in that, Comprising a battery assembly according to claim 13.

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