Display panel

Abstract

A display panel is provided. The display panel includes: a base layer; a transistor including a semiconductor pattern, a gate electrode overlapping the semiconductor pattern, a source electrode and a drain electrode connected to the semiconductor pattern; a light-emitting element; a capacitor including a first electrode disposed on the same layer as the semiconductor pattern and a second electrode disposed on the first electrode; an interlayer insulating layer disposed between the semiconductor pattern and the gate electrode; and an intermediate insulating layer disposed between the gate and the source and drain, and including a recess exposing the second electrode. A side surface of the intermediate insulating layer defining the recess includes a first side surface contacting the second electrode, an upper surface overlapping a portion of the first electrode, and a second side surface spaced apart from the first side surface. Therefore, the display panel has a simplified manufacturing process and has a reduced manufacturing cost.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0098769, filed on Jul. 28, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure herein relates to a display panel and a method for manufacturing the display panel, and more particularly, to a display panel manufactured through a simplified process and a method for manufacturing the display panel. Background Art

[0003] The display panel includes a plurality of pixels and a driving circuit (e.g., a scan driving circuit and a data driving circuit) that controls the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel driving circuit that controls the display element. The pixel driving circuit may include a plurality of transistors that are organically connected to each other.

[0004] The scan driving circuit and / or the data driving circuit may be formed by the same process as that of the plurality of pixels. The scan driving circuit and / or the data driving circuit may include a plurality of transistors organically connected to each other. Utility Model Content

[0005] An object of the present invention is to provide a display panel manufactured through a simplified process and a method for manufacturing the display panel.

[0006] An embodiment of the utility model concept provides a display panel including: a base layer; a transistor disposed on the base layer and including a semiconductor pattern, a gate overlapping the semiconductor pattern, and a source and a drain connected to the semiconductor pattern; a light-emitting element connected to the transistor; a capacitor including a first electrode disposed on the same layer as the semiconductor pattern and a second electrode disposed on the first electrode; an interlayer insulating layer disposed between the semiconductor pattern and the gate; and an intermediate insulating layer disposed between the gate and the source electrode and between the gate and the drain electrode, and including a groove exposing the second electrode. Side surfaces of the intermediate insulating layer defining the groove include: a first side surface in contact with the second electrode; an upper surface overlapping a portion of the first electrode; and a second side surface spaced apart from the first side surface.

[0007] In an embodiment, the interlayer insulating layer and the intermediate insulating layer may be disposed on a portion of the first electrode, and the portion of the first electrode may not overlap with the second electrode.

[0008] In an embodiment, the source and drain electrodes may contact the semiconductor pattern through contact holes penetrating the interlayer insulating layer and the intermediate insulating layer.

[0009] In an embodiment, a gate and a second electrode may be disposed on an interlayer insulating layer, and a first thickness of the second electrode may be less than a second thickness of the gate.

[0010] In an embodiment, a difference between the second thickness and the first thickness may be in a range of about 400 angstroms to about 700 angstroms.

[0011] In an embodiment, the display panel may further include a lower insulating layer and an upper insulating layer. The lower insulating layer is disposed on a substrate layer, and a first electrode and a semiconductor pattern are disposed on the lower insulating layer. The upper insulating layer is disposed on an intermediate insulating layer and covers a source electrode and a drain electrode.

[0012] In an embodiment, the upper insulating layer may be disposed in a groove and contact the second electrode.

[0013] In an embodiment, the display panel may further include an upper insulating layer, and a light-emitting element may include an anode connected to a transistor through a contact hole penetrating the upper insulating layer, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode.

[0014] In an embodiment, the first electrode may include polysilicon, and the second electrode may include molybdenum.

[0015] In an embodiment, the semiconductor pattern may include polysilicon.

[0016] In an embodiment, the display panel may further include a thin film encapsulation layer covering the light-emitting element. Description of the Drawings

[0017] The drawings are included to provide a further understanding of the inventive concept, and the drawings are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, are used to explain the principles of the inventive concept. In the drawings:

[0018] Figure 1A is a perspective view of an embodiment of a display panel according to the inventive concept;

[0019] Figure 1B is a perspective view of an embodiment of a curved display panel according to the inventive concept;

[0020] Figure 2 is a cross-sectional view of an embodiment of a display panel according to the inventive concept;

[0021] Figure 3 is a plan view of an embodiment of a display panel according to the inventive concept;

[0022] Figure 4 is an equivalent circuit diagram of an embodiment of a pixel according to the inventive concept;

[0023] Figure 5 is a cross-sectional view of an embodiment of a display panel according to the utility model concept;

[0024] Figure 6 is a cross-sectional view of an embodiment of a display panel according to the utility model concept; and

[0025] Figures 7A to 7M is a cross-sectional view showing an embodiment of a method for manufacturing a display panel according to the utility model concept. Detailed Description

[0026] In this specification, when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, the element can be directly on the other element, directly connected to or directly coupled to the other element, or there can be an intervening element between the element and the other element.

[0027] The same reference numerals or symbols always denote the same elements. Additionally, in the drawings, for an effective description of the technical content, the thickness, ratio, and dimensions of the elements are exaggerated. The term "and / or" includes all combinations in one or more of the combinations that the associated elements can define.

[0028] Although terms such as first, second, etc. may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the utility model concept, the first element can be referred to as the second element, and similarly, the second element can also be referred to as the first element. Unless the context clearly indicates otherwise, the singular form also includes the plural form.

[0029] Additionally, terms such as "below", "beneath", "above", "on" are used to describe the relationship of the elements shown in the drawings. The terms are relative concepts and are described based on the directions indicated in the drawings.

[0030] It will be understood that when terms such as "comprising" or "having" are used herein, it is intended to state the presence of the stated features, wholes, steps, operations, elements, components, or combinations thereof, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, or combinations thereof.

[0031] As used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, the term "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art. Additionally, terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an overly idealized or overly formal sense unless expressly so defined herein.

[0033] Hereinafter, embodiments of the utility model concept will be described with reference to the accompanying drawings.

[0034] Figure 1A is a perspective view of an embodiment of a display panel according to the utility model concept. Figure 1B is a perspective view of an embodiment of a curved display panel according to the utility model concept. Figure 2 is a cross-sectional view of an embodiment of a display panel according to the utility model concept. Figure 3 is a plan view of an embodiment of a display panel according to the utility model concept. Figure 4 is an equivalent circuit diagram of an embodiment of a pixel according to the utility model concept.

[0035] Figure 1A and Figure 1B The display panels DP and DP-1 shown in

[0036] are light-emitting display panels and may be any one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system display panel, an electrowetting display panel, an organic light-emitting display panel, an inorganic light-emitting display panel, and a quantum dot display panel, but the embodiments of the utility model concept are not particularly limited thereto. Figure 1A Figure 2

[0037] ​​The display surface DP-IS is parallel to the plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DP-IS (i.e., the thickness direction of the display panel DP) is represented by the third direction DR3. The front surface (or upper surface) and the rear surface (or lower surface) of each layer or unit to be described below are distinguished based on the third direction DR3.

[0038] The display panel DP may include a display area DA and a non-display area NDA. The light-emitting layer EML of the pixel PX (refer to Figure 5 ) is provided in the display area DA and not provided in the non-display area NDA. The non-display area NDA is defined along the edge of the display surface DP-IS. The non-display area NDA may surround the display area DA. In an embodiment of the utility model concept, the non-display area NDA may be omitted or may be provided only on one side of the display area DA.

[0039] Refer to Figure 1B , in an embodiment, the display panel DP-1 may be bent in the first direction DR1 with respect to the virtual axis AX extending in the second direction DR2. However, the utility model concept is not limited thereto, and the axis may extend in the first direction DR1, or the display panel DP-1 may be bent with respect to a plurality of axes extending in different directions.

[0040] In addition, the display panel DP may be a rollable display panel, a foldable display panel, or a slidable display panel. The display panel DP may have a flexible property and be capable of folding or rolling while being mounted on the display device. Therefore, the display panel DP may include a curved display surface DP-IS or a three-dimensional display surface DP-IS. The three-dimensional display surface DP-IS may include a plurality of display areas indicating different directions.

[0041] Figure 1A And Figure 1B shows the pixel PX provided in the display area DA. The pixel PX may include one or more sub-pixels that provide different lights. In an embodiment, the pixel PX may be an area in which sub-pixels that provide green light, red light, and blue light are provided. The sub-pixels included in the pixel PX may be arranged in, for example, a stripe shape or shape.

[0042] However, the utility model concept is not limited thereto, and sub-pixels that generate different lights may be arranged in a triangular shape. For example, in an embodiment, a light-emitting region of a sub-pixel that provides green light and a light-emitting region of a sub-pixel that provides red light may be spaced apart from each other in a first direction DR1, and a light-emitting region of a sub-pixel that provides blue light may be spaced apart from the light-emitting region of the sub-pixel that provides green light and the light-emitting region of the sub-pixel that provides red light in an oblique direction with respect to each of the first direction DR1 and a second direction DR2. In this case, among the sub-pixels, the sub-pixel that provides red light may have the largest light-emitting region, and the sub-pixel that provides blue light may have the smallest light-emitting region.

[0043] In addition, a shape of a light-emitting region of a sub-pixel that provides green light and a shape of a light-emitting region of a sub-pixel that provides red light may be symmetric with each other. In this case, the light-emitting regions may have similar shapes while having different areas from each other. A light-emitting region of a sub-pixel that provides blue light may be symmetric with respect to a virtual line that intersects the center of the light-emitting region. However, the utility model concept is not limited thereto, and the arrangement of sub-pixels that provide different lights and the area sizes of the light-emitting regions of the sub-pixels are not limited to a specific embodiment.

[0044] Referring to Figure 2 , a display panel DP according to the utility model concept includes a substrate layer BS, a circuit element layer DP-CL disposed on the substrate layer BS, a display element layer DP-OLED, a thin film encapsulation layer TFE, an optical control layer OSL, and a window panel WD. The display panel DP may further include functional layers (such as an antireflection layer or a refractive index adjustment layer). The circuit element layer DP-CL may at least include a plurality of insulating layers and circuit elements. The insulating layers described below may include organic layers and / or inorganic layers.

[0045] The substrate layer BS may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. More specifically, the synthetic resin layer may be a polyimide-based resin layer, but its material is not particularly limited thereto. The synthetic resin layer may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a silicone-based resin, a polyamide-based resin, and a perylene-based resin. In addition, the substrate layer BS may include a glass substrate, a metal substrate, an organic / inorganic composite substrate, etc.

[0046] In the circuit element layer DP-CL, an insulating layer, a semiconductor layer, and a conductive layer are formed through processes such as a coating process or a deposition process. Then, the insulating layer, the semiconductor layer, and the conductive layer can be selectively patterned through a photolithography process and an etching process. Through such processes, semiconductor patterns, conductive patterns, signal lines, etc. are formed. Patterns provided in the same layer are formed through the same process. According to the utility model concept, one or more insulating layers included in the circuit element layer DP-CL can be formed using a halftone mask in which a plurality of slits are defined. Their description will be provided later.

[0047] The circuit element layer DP-CL includes signal lines or a driving circuit for driving the pixel PX. The display element layer DP-OLED may include a pixel defining layer PDL (refer to Figure 5 ) and a light-emitting element OLED (refer to Figure 5 ) included in the pixel PX.

[0048] The thin film encapsulation layer TFE may be provided on the display element layer DP-OLED to protect the light-emitting element OLED. The thin film encapsulation layer TFE may include an inorganic layer and an organic layer provided between the inorganic layers. The inorganic layer may protect the light-emitting element OLED from moisture and oxygen, and the organic layer may protect the light-emitting element OLED from foreign substances (such as dust particles).

[0049] The light control layer OSL may include a color control layer capable of converting the optical properties of the source light generated from the light-emitting element OLED. The color control layer may include quantum dots, and the light control layer OSL may include a color filter that selectively transmits light that has passed through the color control layer.

[0050] In an embodiment, the light control layer OSL may be spaced apart from the thin film encapsulation layer TFE by a predetermined interval between the light control layer OSL and the thin film encapsulation layer TFE. In this case, the light control layer OSL may be formed on a window panel WD serving as a substrate layer. The substrate layer BS to the thin film encapsulation layer TFE may be defined as a lower panel, and the light control layer OSL and the window panel WD may be defined as an upper panel. The lower panel and the upper panel may be joined together with a resin provided in the non-display area NDA.

[0051] However, the utility model concept is not limited thereto, and the light control layer OSL may be directly formed on the thin film encapsulation layer TFE through a continuous process.

[0052] The window panel WD may be provided in the upper part of the display panel DP and may transmit an image provided from the display panel DP to the outside. The window panel WD includes a display area DA and a non-display area NDA. The non-display area NDA may define the boundary of the display area DA and may be defined by a border pattern provided under the window panel WD and absorbing light.

[0053] The window panel WD may include a substrate layer and a functional layer disposed on the substrate layer. The functional layer may include a protective layer, an anti-fingerprint layer, etc. The substrate layer of the window panel WD may include glass, sapphire, plastic, etc.

[0054] Figure 3 The planar arrangement relationship of signal lines SL1 to SLn and DL1 to DLm and pixels PX11 to PXnm included in the display panel DP is shown. Here, n and m are natural numbers greater than 1. The signal lines SL1 to SLn and DL1 to DLm may include a plurality of scan lines SL1 to SLn and a plurality of data lines DL1 to DLm.

[0055] Each of the pixels PX11 to PXnm may be connected to a corresponding scan line among the plurality of scan lines SL1 to SLn and a corresponding data line among the plurality of data lines DL1 to DLm. Each of the pixels PX11 to PXnm may include a pixel driving circuit and a display element. According to the configuration of the pixel driving circuits of the pixels PX11 to PXnm, more types of signal lines may be provided to the display panel DP. In an embodiment, the data lines DL1 to DLm may be respectively connected to pads (or referred to as "bond pads") PD disposed in the non-display area NDA.

[0056] The gate driving circuit GDC may be disposed in the non-display area NDA. The gate driving circuit GDC may be integrated into the display panel DP by an oxide silicon gate ("OSG") driver circuit process or an amorphous silicon gate ("ASG") driver circuit process.

[0057] Figure 4 The circuit diagram of one pixel PXij among the pixels PX11 to PXnm is shown. Here, i and j may be natural numbers greater than 0 and equal to or less than n and m, respectively.

[0058] Referring to Figure 4 , the pixel PXij may include a pixel circuit PC and a light-emitting element OLED. The pixel circuit PC may include a plurality of transistors T1 to T3 and a capacitor Cst.

[0059] The plurality of transistors T1 to T3 may be formed by a low-temperature polycrystalline silicon ("LTPS") process or a low-temperature polycrystalline oxide ("LTPO") process. Each of the first transistor T1 to the third transistor T3 may include any one of a silicon semiconductor and an oxide semiconductor. In this case, the oxide semiconductor may include a crystalline oxide semiconductor or an amorphous oxide semiconductor, and the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc., and the utility model concept is not limited thereto.

[0060] Hereinafter, the first transistor T1 to the third transistor T3 are described as N-type transistors, but the inventive concept is not limited thereto, and each of the first transistor T1 to the third transistor T3 may be a P-type transistor or an N-type transistor according to the signal applied thereto. In this case, the source and drain of the P-type transistor may correspond to the drain and source of the N-type transistor, respectively.

[0061] In an embodiment, the capacitor Cst included in the pixel circuit PC may include two electrodes spaced apart from each other. In this case, the electrode disposed on the lower side compared to the other electrode may be doped with a P-type dopant. Their description will be provided later.

[0062] Figure 4 A pixel PXij connected to the i-th scan line SCLi, the i-th sense line SSLi, the j-th data line DLj, and the j-th reference line RLj is shown.

[0063] The pixel circuit PC may include a first transistor T1 (driving transistor), a second transistor T2 (switching transistor), a third transistor T3 (sensing transistor), and a capacitor Cst. However, the pixel circuit PC may further include additional transistors and additional capacitors, and the inventive concept is not limited thereto.

[0064] The first transistor T1 to the third transistor T3 may respectively include sources S1, S2, and S3, drains D1, D2, and D3, and gates G1, G2, and G3.

[0065] The light-emitting element OLED may be an organic light-emitting element or an inorganic light-emitting element including an anode (first electrode) and a cathode (second electrode). The anode of the light-emitting element OLED may receive a first voltage ELVDD through the first transistor T1, and the cathode of the light-emitting element OLED may receive a second voltage ELVSS. When the first voltage ELVDD and the second voltage ELVSS are received, the light-emitting element OLED may emit light.

[0066] The first transistor T1 may include a drain D1 that receives the first voltage ELVDD, a source S1 connected to the anode of the light-emitting element OLED, and a gate G1 connected to the capacitor Cst. The first transistor T1 may control the driving current flowing through the light-emitting element OLED from the first voltage ELVDD in response to the voltage value stored in the capacitor Cst.

[0067] The second transistor T2 may include a drain D2 connected to the j-th data line DLj, a source S2 connected to the capacitor Cst, and a gate G2 that receives the i-th write scan signal SCi. The second transistor T2 provides a data voltage Vd to the first transistor T1 in response to the i-th write scan signal SCi.

[0068] The third transistor T3 may include a source S3 connected to the j-th reference line RLj, a drain D3 connected to the anode of the light-emitting element OLED, and a gate G3 receiving the i-th sampled scan signal SSi. The j-th reference line RLj may receive a reference voltage Vr.

[0069] The capacitor Cst may store voltage differences of various values according to an input signal. For example, in an embodiment, the capacitor Cst may store a voltage equal to the difference between the voltage transmitted from the second transistor T2 and the first voltage ELVDD.

[0070] In the utility model concept, the equivalent circuit of the pixel PXij is not limited to Figure 4 the equivalent circuit shown in. In other embodiments of the utility model concept, the pixel PXij may be implemented in various forms to cause the light-emitting element OLED to emit light.

[0071] Figure 5 is a cross-sectional view of an embodiment of a display panel according to the utility model concept. Figure 6 is a cross-sectional view of an embodiment of a display panel according to the utility model concept. Figure 5 Only Figure 2 some components of the display panel DP shown in are shown, that is, the substrate layer BS to the thin film encapsulation layer TFE.

[0072] Referring to Figure 5 , in an embodiment, the display panel DP may include a substrate layer BS, a circuit element layer DP-CL disposed on the substrate layer BS, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0073] The first insulating layer 10 (or the lower insulating layer) may be disposed on the substrate layer BS. In an embodiment, the first insulating layer 10 may be a buffer layer and include an inorganic layer having a single-layer or multi-layer structure.

[0074] The first electrode C1 of the capacitor Cst and the semiconductor pattern A1 may be disposed on the first insulating layer 10. The first electrode C1 and the semiconductor pattern A1 may be formed by the same process and may include the same material as each other. For example, in an embodiment, the first electrode C1 and the semiconductor pattern A1 may include polysilicon. A P-type doping process may be performed on the first electrode C1 and the semiconductor pattern A1. After the doping process, the first electrode C1 and the semiconductor pattern A1 may be impregnated with boron. Its description will be given later.

[0075] The second insulating layer 20 (or interlayer insulating layer) may be disposed on the first insulating layer 10 and cover the first electrode C1 and the semiconductor pattern A1. The second insulating layer 20 may include an inorganic layer having a single-layer or multi-layer structure.

[0076] The gate G1 may be disposed on the second insulating layer 20. The gate G1 may be stacked with the semiconductor pattern A1. In an embodiment, the gate G1 may be used as a mask in the doping process of the semiconductor pattern A1. Accordingly, the region of the semiconductor pattern A1 stacked with the gate G1 may be defined as a channel region.

[0077] The second electrode C2 of the capacitor Cst may be disposed on the second insulating layer 20. The second electrode C2 may be stacked with the first electrode C1. In an embodiment, the second electrode C2 may not be stacked with a part of the first electrode C1. The second electrode C2 and the gate G1 may be formed by the same process and may include the same material as each other.

[0078] The third insulating layer 30 (or intermediate insulating layer) may be disposed on the second insulating layer 20 and cover the gate G1. In an embodiment, the third insulating layer 30 may include an organic layer. Contact holes 30-CN1 and 30-CN2 may be defined in the third insulating layer 30 by penetrating the third insulating layer 30. Each of the contact holes 30-CN1 and 30-CN2 may expose the doped region of the semiconductor pattern A1. The source S1 may be disposed in the first contact hole 30-CN1 and may be connected to one region of the semiconductor pattern A1. The drain D1 may be disposed in the second contact hole 30-CN2 and may be connected to another region of the semiconductor pattern A1.

[0079] According to the utility model concept, a groove 30-H exposing at least a part of the second electrode C2 may be defined in the third insulating layer 30. The groove 30-H may be defined by penetrating the third insulating layer 30. The groove 30-H may be defined by one side surface SM1 and the other side surface SM2 of the third insulating layer 30 exposed by being penetrated. One side surface SM1 and the other side surface SM2 may face each other in a cross section.

[0080] In an embodiment, one side surface SM1 may include a first side surface 30-S1, a second side surface 30-Sx2, and an upper surface 30-U.

[0081] The first side surface 30-S1 may contact one side of the second electrode C2. The top surface 30-U may extend from the first side surface 30-S1 and may be connected to the second side surface 30-S2. The upper surface 30-U may be stacked with the part of the first electrode C1 exposed from the second electrode C2. The other side of the second electrode C2 opposite to the one side may be disposed in the other side surface SM2.

[0082] According to the utility model concept, the width from the first side surface 30-S1 to the other side surface SM2 can be smaller than the width from the second side surface 30-S2 to the other side surface SM2. Therefore, the second insulating layer 20 and the third insulating layer 30 can be disposed on the portion of the first electrode C1 exposed from the second electrode C2.

[0083] In an embodiment, the display panel DP may further include a conductive pattern SD, which is disposed in the groove 30-H adjacent to the other side surface SM2 and contacts the other side surface SM2, the upper surface of the third insulating layer 30, and the second electrode C2. The conductive pattern SD, the source S1, and the drain D1 can be formed by the same process and can include the same materials as each other. In an embodiment, the conductive pattern SD can branch from a part of the source S1 or the drain D1.

[0084] The fourth insulating layer 40 (or the upper insulating layer) can be disposed on the third insulating layer 30 and cover the gate G1. In an embodiment, the fourth insulating layer 40 can include an organic layer. The contact hole 40-CN can be defined in the fourth insulating layer 40 by penetrating the fourth insulating layer 40.

[0085] The first electrode AE of the light-emitting element OLED is disposed on the fourth insulating layer 40. The first electrode AE can be an anode. The first electrode AE can be connected to the source S1 through the contact hole 40-CN. The pixel defining film PDL is disposed on the fourth insulating layer 40. An opening exposing at least a part of the first electrode AE can be defined in the pixel defining film PDL. The opening of the pixel defining film PDL can be defined as a light-emitting region for providing light. The light-emitting layer EML is disposed on the first electrode AE. In an embodiment, the light-emitting layer EML can be disposed only in the region corresponding to the opening. The light-emitting layer EML can be separately formed in each of the plurality of pixels PX.

[0086] Although the patterned light-emitting layer EML is shown in the illustrated embodiment, the light-emitting layer EML can be commonly disposed in the plurality of pixels PX. The commonly disposed light-emitting layer EML can generate white light or blue light. Additionally, the light-emitting layer EML can have a multilayer structure. The second electrode CE is disposed on the light-emitting layer EML. The electron control layer and the second electrode CE can be commonly disposed in the plurality of pixels PX.

[0087] In an embodiment, the display panel DP may further include a hole control layer disposed between the first electrode AE and the light-emitting layer EML and an electron control layer disposed between the light-emitting layer EML and the second electrode CE. The hole control layer can include a hole transport layer and a hole injection layer, and the electron control layer can include an electron transport layer and an electron injection layer. The hole control layer and the electron control layer can be common layers commonly disposed in the plurality of pixels PX.

[0088] The thin film encapsulation layer TFE includes at least one of an inorganic layer and an organic layer. In an embodiment, the inorganic layer may be provided as a plurality of layers, and may be provided on and under the organic layer. Additionally, either the inorganic layer or the organic layer may include two or more layers, and the utility model concept is not limited thereto.

[0089] According to the utility model concept, the process of defining contact holes 30-CN1 and 30-CN2 for connecting the source S1 and the drain D1 to the semiconductor pattern A1, and the process of doping the first electrode C1 of the capacitor Cst can be performed in the same mask process. Therefore, the manufacturing cost of the display panel DP can be reduced, and the manufacturing process of the display panel DP can be simplified. Their descriptions will be provided later.

[0090] Referring to Figure 6 , in an embodiment, the display panel DP-A may include a substrate layer BS, a circuit element layer DP-CL provided on the substrate layer, a display element layer DP-OLED provided on the circuit element layer DP-CL, and a thin film encapsulation layer TFE provided on the display element layer DP-OLED. The differences between the display panel DP described with reference to Figure 5 and the display panel DP-A will be mainly described.

[0091] The display panel DP-A may include a capacitor Cst, and the capacitor Cst includes a first electrode C1 and a second electrode C2. The first electrode C1 may be spaced apart from the second electrode C2, and a second insulating layer 20 is between the first electrode C1 and the second electrode C2. The first electrode C1 and the semiconductor pattern A1 may be formed by the same process and may include the same materials as each other. The second electrode C2 and the gate G1 may be formed by the same process and may include the same materials as each other.

[0092] In an embodiment, the second electrode C2 may have a first thickness TH1, and the gate G1 may have a second thickness TH2. The first thickness TH1 may be less than the second thickness TH2. The difference between the second thickness TH2 and the first thickness TH1 may be in the range of about 400 angstroms to about . The reason may be that during the etching process for defining the groove 30-H in the third insulating layer 30, since the upper part of the second electrode C2 is partially etched, the second electrode C2 has a thickness less than that of the gate G1.

[0093] Figures 7A to 7M is a cross-sectional view showing an embodiment of a method for manufacturing a display panel according to the utility model concept. The method for manufacturing the display panel DP described with reference to Figures 7A to 7M will be described with reference to Figure 5 .

[0094] Referring to Figure 7A , in an embodiment, a method for manufacturing a display panel may include forming a first insulating layer 10 (or a lower insulating layer) on a substrate layer BS. The first insulating layer 10 may be formed by applying an inorganic material to the entire surface of the substrate layer BS.

[0095] Then, the method may include forming a first electrode C1 and a semiconductor pattern A1 on the substrate layer BS. The first electrode C1 and the semiconductor pattern A1 may be formed by applying a polysilicon-containing material to the entire surface of the first insulating layer 10 and patterning the polysilicon-containing material through a first mask MS1.

[0096] Then, referring to Figure 7B , in an embodiment, a method for manufacturing a display panel may include forming a second insulating layer 20 (or an interlayer insulating layer) on the first insulating layer 10. The second insulating layer 20 may be formed by applying an inorganic material to the entire surface of the first insulating layer 10.

[0097] Hereinafter, the method may include forming a second electrode C2 and a gate G1 on the second insulating layer 20. The second electrode C2 and the gate G1 may be formed by applying a metal to the entire surface of the second insulating layer 20 and patterning the metal through a second mask MS2. In an embodiment, the metal may include molybdenum.

[0098] The second electrode C2 may be patterned to overlap with the first electrode C1, and the gate G1 may be patterned to overlap with the semiconductor pattern A1. In the illustrated embodiment, the second electrode C2 may expose at least a portion of the first electrode C1.

[0099] Subsequently, referring to Figure 7C , in an embodiment, a method for manufacturing a display panel may include doping the first electrode C1 and the semiconductor pattern A1. According to the doping process, a first portion C-P of the first electrode C1 that does not overlap with the second electrode C2 may be doped, and a second portion C-I of the first electrode C1 that overlaps with the second electrode C2 may not be doped. A region of the semiconductor pattern A1 that does not overlap with the gate G1 may be doped. Thus, a region of the semiconductor pattern A1 that overlaps with the gate G1 may be defined as a channel region. In the illustrated embodiment, a portion of each of the first electrode C1 and the semiconductor pattern A1 may be doped with a P-type dopant.

[0100] Then, referring to Figure 7D, in an embodiment, a method of manufacturing a display panel may include forming a third insulating layer 30 (or an intermediate insulating layer) on a second insulating layer 20. The third insulating layer 30 may be formed by applying an organic material to the second insulating layer 20. Thereafter, the method may include forming a photoresist layer PR on the third insulating layer 30. The photoresist layer PR may serve as a mask for patterning the third insulating layer 30. The photoresist layer PR may be patterned through a third mask MS3. In an embodiment, a portion of the third mask MS3 may be a halftone mask HM. A plurality of slits that overlap with a first portion C-P of the first electrode C1 and are spaced apart from each other may be defined in the halftone mask HM. A stepped region HF may be defined in a portion of the photoresist layer PR that overlaps with the halftone mask HM. The stepped region HF may overlap with an end portion of the second electrode C2.

[0101] Light contact holes P-CN1 and P-CN2 may be defined in a region that overlaps with an opening of the third mask MS3. Each of the light contact holes P-CN1 and P-CN2 may overlap with a semiconductor pattern A1.

[0102] According to the utility model concept, an opening that overlaps with at least a portion of the second electrode C2 may be defined in the photoresist layer PR. The opening may be defined by one side surface PM1 that defines the stepped region HF and another side surface PM2 that is opposite to the one side surface PM1. The one side surface PM1 may have a first side surface P-S1 facing the other side surface PM2, an upper surface P-U connected to the first side surface P-S1 and parallel to an upper surface of the third insulating layer 30, and a second side surface P-S2 connected to the upper surface P-U and spaced apart from the first side surface P-S1. The stepped region HF may be defined by the first side surface P-S1, the upper surface P-U, and the second side surface P-S2.

[0103] Then, referring to Figure 7E , in an embodiment, a method of manufacturing a display panel may include patterning the third insulating layer 30. A groove 30-H that overlaps with the opening of the photoresist layer PR and preliminary contact holes 30-H1 and 30-H2 that overlap with the light contact holes P-CN1 and P-CN2 may be defined in the third insulating layer 30. The groove 30-H may be defined by penetrating the third insulating layer 30 to expose the second electrode C2. The preliminary contact holes 30-H1 and 30-H2 may be defined by removing portions of the third insulating layer 30. In an embodiment, the groove 30-H and the preliminary contact holes 30-H1 and 30-H2 may be defined through a dry etching process.

[0104] Hereinafter, referring to Figure 7F, in an embodiment, a method of manufacturing a display panel may include removing a stepped region HF of a photoresist layer PR. Since the stepped region HF of the photoresist layer PR is removed, an upper surface 30-E of the third insulating layer 30 that overlaps a first portion C-P of the first electrode C1 may be exposed.

[0105] Subsequently, referring to Figure 7G and Figure 7H , in an embodiment, a method of manufacturing a display panel may include patterning the third insulating layer 30. In this operation, a portion of the third insulating layer 30 that overlaps the upper surface 30-E already described with reference to Figure 7F may be removed. As a side surface SM1 defining a groove 30-H, a first side surface 30-S1, a second side surface 30-S2, and an upper surface 30-U defining a step may be formed.

[0106] The first side surface 30-S1 may contact one side of the second electrode C2. The upper surface 30-U may extend from the first side surface 30-S1 and may be connected to the second side surface 30-S2. The upper surface 30-U may overlap a portion of the first electrode C1 exposed from the second electrode C2.

[0107] According to the utility model concept, since the halftone mask HM is used as the third mask MS3, after patterning of the third insulating layer 30, the second insulating layer 20 and the third insulating layer 30 may remain on the first portion C-P. Accordingly, the first portion C-P may be protected by the second insulating layer 20 and the third insulating layer 30 in subsequent processes.

[0108] In addition, in the step of patterning the third insulating layer 30, contact holes 30-CN1 and 30-CN2 exposing the semiconductor pattern A1 may be defined by further etching the third insulating layer 30 and the second insulating layer 20 exposed through preliminary contact holes 30-H1 and 30-H2 defined in Figure 7E .

[0109] According to the utility model concept, the method may include doping a second portion C-I of the first electrode C1 during the same process as the process for defining the contact holes 30-CN1 and 30-CN2 exposing the semiconductor pattern A1.

[0110] As used herein, "the same process" may be defined as a process performed before using a fourth mask MS4 (refer to Figure 7D ) different from the third mask MS3 used in Figure 7I .

[0111] In referring to Figure 7CIn the described doping process, since the second part C-I is stacked with the second electrode C2, the second part C-I may not be doped. As referred to Figure 7E As described, in the process for defining the groove 30-H, a part of the second electrode C2 and the third insulating layer 30 may be etched simultaneously by an etchant, and the thickness of the second electrode C2 may become smaller. Therefore, the doping material can easily penetrate the second part C-I. In an embodiment, the doping material may be boron. Thus, after the doping process, the first electrode C1 may be impregnated with boron.

[0112] According to the utility model concept, since the halftone mask HM is used, disconnection of the first electrode C1 can be prevented, and the process for doping the first electrode C1 and the process for defining the contact holes 30-CN1 and 30-CN2 can be performed in the same process. In addition, the number of masks used in the manufacturing process of the display panel can be reduced. Therefore, a display panel manufactured by a simplified process at a reduced manufacturing cost and a method for manufacturing the display panel can be provided.

[0113] Then, referring to Figure 7I , in an embodiment, the method for manufacturing a display panel may include forming a source electrode S1 and a drain electrode D1. Additionally, the method may further include forming a conductive pattern SD. The source electrode S1 and the drain electrode D1 may be formed by forming a conductive material on the third insulating layer 30 and patterning the conductive material through a fourth mask MS4. The source electrode S1 may be disposed in the first contact hole 30-CN1 to contact a part of the semiconductor pattern A1, and the drain electrode D1 may be disposed in the second contact hole 30-CN2 to contact another part of the semiconductor pattern A1. The conductive pattern SD and the source electrode S1 and the drain electrode D1 may be formed using the same mask and may include the same material. The conductive pattern SD may branch from the source electrode S1 or the drain electrode D1 and may be disposed in the groove 30-H to contact the second electrode C2.

[0114] Hereinafter, referring to Figure 7J , in an embodiment, the method for manufacturing a display panel may include forming a fourth insulating layer 40 (or an upper insulating layer) on the third insulating layer 30. The fourth insulating layer 40 may be formed by applying an organic material to the entire surface of the third insulating layer 30. A contact hole 40-CN may be defined in the fourth insulating layer 40 through a fifth mask MS5. The contact hole 40-CN may expose the source electrode S1.

[0115] Next, referring to Figure 7K, in an embodiment, a method for manufacturing a display panel may include forming a first electrode AE. The first electrode AE may be formed by applying a conductive material to a fourth insulating layer 40 and patterning the conductive material through a sixth mask MS6. The first electrode AE may be disposed in a contact hole 40-CN to contact a source electrode S1.

[0116] Then, referring to Figure 7L , in an embodiment, a method for manufacturing a display panel may include forming a pixel defining layer PDL. The pixel defining layer PDL may be formed by applying an organic material to the fourth insulating layer 40. An opening may be defined in the pixel defining layer PDL through a seventh mask MS7. The opening may expose at least a portion of the first electrode AE.

[0117] Then, referring to Figure 7M , in an embodiment, a method for manufacturing a display panel may further include forming a thin film encapsulation layer TFE. The thin film encapsulation layer TFE may include an inorganic layer and an organic layer disposed between the inorganic layers. The inorganic layer may be formed by a chemical vapor deposition (“CVD”) method.

[0118] In an embodiment of the inventive concept, the manufacturing process of the display panel may be simplified, and the manufacturing cost of the display panel may be reduced.

[0119] Although embodiments of the inventive concept have been described, it is understood that the inventive concept should not be limited to these embodiments, but various changes and modifications may be made by those skilled in the art within the spirit and scope of the inventive concept as claimed.

[0120] Therefore, the technical scope of the inventive concept is not limited to the content described in the detailed description of the specification, but should be defined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: a substrate layer; a transistor disposed on the substrate layer and including a semiconductor pattern, a gate overlapping the semiconductor pattern, and a source and a drain connected to the semiconductor pattern; a light-emitting element connected to the transistor; a capacitor including a first electrode disposed on the same layer as the semiconductor pattern and a second electrode disposed on the first electrode; an interlayer insulating layer disposed between the semiconductor pattern and the gate; and an intermediate insulating layer disposed between the gate and the source and between the gate and the drain, the intermediate insulating layer including side surfaces defining a groove exposing the second electrode, the side surfaces including: a first side surface in contact with the second electrode; an upper surface overlapping a portion of the first electrode; and a second side surface spaced apart from the first side surface.

2. The display panel according to claim 1, wherein The interlayer insulating layer and the intermediate insulating layer are disposed on the portion of the first electrode, and the portion of the first electrode does not overlap the second electrode.

3. The display panel according to claim 1, wherein The source and the drain contact the semiconductor pattern through contact holes penetrating the interlayer insulating layer and the intermediate insulating layer.

4. The display panel according to claim 1, characterized in that, The gate and the second electrode are disposed on the interlayer insulating layer, and a first thickness of the second electrode is less than a second thickness of the gate.

5. The display panel according to claim 4, characterized in that, A difference between the second thickness and the first thickness is in a range of 400 angstroms to 700 angstroms.

6. The display panel according to claim 1, wherein The display panel further includes a lower insulating layer and an upper insulating layer, the lower insulating layer is disposed on the substrate layer and the first electrode and the semiconductor pattern are disposed on the lower insulating layer, and the upper insulating layer is disposed on the intermediate insulating layer and covers the source and the drain.

7. The display panel according to claim 6, wherein The upper insulating layer is disposed in the groove and contacts the second electrode.

8. The display panel according to claim 1, wherein The display panel further includes an upper insulating layer, wherein the light-emitting element includes an anode connected to the transistor through a contact hole penetrating the upper insulating layer, a cathode disposed on the anode, and a light-emitting layer disposed between the anode and the cathode.

9. The display panel according to claim 1, wherein The first electrode includes polysilicon, and the second electrode includes molybdenum.

10. The display panel according to claim 9, characterized in that, The semiconductor pattern includes polysilicon.

11. The display panel according to claim 1, wherein, The display panel further includes a thin film encapsulation layer covering the light-emitting element.

Images