Driving interlocking circuit and voltage regulating device

Abstract

The utility model discloses a drive interlocking circuit and a voltage regulating device, and relates to the technical field of power conversion. Comprising a DSP module used for generating multiple paths of driving instruction signals; the driving channel is used for transmitting a driving instruction signal; the DSP module is electrically connected with the driving channels, and each path of driving instruction signal corresponds to one driving channel; the logic interlocking module is used for interlocking the driving channels according to the driving instruction signal; the logic interlocking module is electrically connected to the driving channel; according to the scheme, the logic interlocking module is arranged in the driving circuit, and the driving channel is interlocked according to the driving instruction signal, so that the driving circuit has good electrical isolation performance, isolation between the main circuit and the control circuit is achieved, the driving circuit has high anti-interference capability, and interference of the power level circuit on the control signal is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of power conversion, in particular to a drive interlocking circuit and a voltage regulating device. Background Art

[0002] In direct current transmission equipment, it is often necessary to drive semiconductor components to convert electrical energy. However, in the traditional chip driving process, due to the high operating frequency and input impedance of IGBT, it is easy to be interfered with, causing the power stage circuit to bring greater interference to the control signal; it is easy to cause the equipment to be mis-conducted, resulting in reduced power conversion quality or even short circuit, etc., making it difficult for the equipment to perform low-voltage management of the power grid more stable and high-quality. Utility Model Content

[0003] The technical problem to be solved by the present invention is: since the operating frequency and input impedance of IGBT are high and easily interfered with, the power stage circuit brings greater interference to the control signal, which easily causes the equipment to be mis-conducted, resulting in reduced power conversion quality or even short circuit, etc., resulting in the equipment to perform low voltage management of the power grid more stably and with high quality; the purpose is to provide a drive interlocking circuit and a voltage regulating device, a logic interlocking module is set in the drive circuit, and the drive channel is interlocked according to the drive instruction signal, so that the drive circuit has good electrical isolation performance, so as to realize isolation between the main circuit and the control circuit, so that it has strong anti-interference ability, and avoids interference of the power stage circuit on the control signal.

[0004] The utility model is achieved through the following technical solutions:

[0005] This solution provides a drive interlock circuit, including:

[0006] DSP module, used to generate multi-channel driving command signals;

[0007] The driving channel is used to transmit the driving instruction signal; the DSP module is electrically connected to the driving channel, and each driving instruction signal corresponds to one driving channel;

[0008] The logic interlocking module is used to interlock the driving channel according to the driving instruction signal; the logic interlocking module is electrically connected to the driving channel.

[0009] Working principle of this solution: Since the operating frequency and input impedance of IGBT are high, they are easily interfered with, causing the power stage circuit to bring greater interference to the control signal, which can easily cause the equipment to be misconnected, resulting in reduced power conversion quality or even short circuit, etc., so that the equipment can perform low-voltage management of the power grid more stably and with high quality; this solution provides a drive interlocking circuit and a voltage regulating device, and sets a logic interlocking module in the drive circuit to interlock the drive channel according to the drive command signal, so that the drive circuit has good electrical isolation performance, so as to achieve isolation between the main circuit and the control circuit, so that it has strong anti-interference ability, and avoids interference of the power stage circuit on the control signal.

[0010] A further optimized solution is to further include an amplification module and a response module; the amplification module is used to amplify the drive instruction signal; the response module is used to respond to the drive instruction signal;

[0011] The amplifying module is electrically connected to the driving channel and the output end of the logic interlocking module; the responding module is electrically connected to the output end of the amplifying module.

[0012] A further optimized solution is that the DSP module includes four drive instruction output ports: a first drive instruction port, a second drive instruction port, a third drive instruction port and a fourth drive instruction port.

[0013] A further optimized solution is that the logic interlock module includes: a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate;

[0014] The first drive instruction port is electrically connected to the first input terminal of the third AND gate, and the first drive instruction port is electrically connected to the first NOT gate and then respectively connected to the first input terminal of the fourth AND gate and the first input terminal of the second AND gate;

[0015] The second driving instruction port is electrically connected to the second input terminal of the fourth AND gate, and the second driving instruction port is electrically connected to the second NOT gate and then to the first input terminal of the first AND gate;

[0016] The third driving instruction port is electrically connected to the first input terminal of the fifth AND gate, and the third driving instruction port is electrically connected to the third NOT gate and then to the second input terminal of the second AND gate;

[0017] The fourth drive instruction port is electrically connected to the second input terminal of the sixth AND gate, and the fourth drive instruction port is electrically connected to the fourth NOT gate and then respectively connected to the second input terminal of the first AND gate and the second input terminal of the fourth AND gate;

[0018] The output end of the first AND gate is connected to the second input end of the third AND gate, and the output end of the second AND gate is connected to the first input end of the sixth AND gate.

[0019] A further optimization solution is that the output end of the third AND gate serves as the output end of the drive channel corresponding to the first drive instruction, the output end of the fourth AND gate serves as the output end of the drive channel corresponding to the second drive instruction, the output end of the fifth AND gate serves as the output end of the drive channel corresponding to the third drive instruction, and the output end of the sixth AND gate serves as the output end of the drive channel corresponding to the fourth drive instruction.

[0020] A further optimized solution is that the amplification module includes a plurality of amplification units with the same circuit structure; each amplification unit is used to amplify two drive instruction signals simultaneously;

[0021] The amplifying unit includes: a first input terminal, a second input terminal, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a U44 chip, a first output terminal and a second output terminal;

[0022] The first input end is connected to the INA port of the U44 chip after being connected in series with the resistor R1, and the second input end is connected to the INB port of the U44 chip after being connected in series with the resistor R2;

[0023] One end of capacitor C1 is connected to the INA port of U44 chip, and the other end is grounded; one end of capacitor C2 is connected to the INB port of U44 chip, and the other end is grounded;

[0024] Capacitor C3 is connected between the GND port and VDD port of the U44 chip, capacitor C4 is connected in parallel on both sides of capacitor C3, the GND port of the U44 chip is grounded, and the VDD port of the U44 chip is connected to a 12V power supply;

[0025] The OUTA port of the U44 chip serves as the first output port, and the OUTB port of the U44 chip serves as the second output port;

[0026] The two drive command signals are input into the first input terminal and the second input terminal respectively, and are output from the first output terminal and the second output terminal accordingly.

[0027] A further optimization solution is that the resistor R1 is 100Ω, the resistor R2 is 100Ω, the capacitor C1 is 100pF, the capacitor C2 is 100pF, the capacitor C3 is 1μF, and the capacitor C4 is 1μF.

[0028] A further optimized solution is that the response module includes a semiconductor device, and the semiconductor device responds to the driving instruction signal by switching on and off; each driving channel corresponds to one or more semiconductor devices.

[0029] This solution also provides a voltage regulating device, which includes the above-mentioned drive interlocking circuit.

[0030] A further optimization solution is that the voltage regulating device realizes flexible DC voltage regulation of the low-voltage distribution network system.

[0031] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0032] This solution provides a drive interlock circuit and a voltage regulating device. A logic interlock module is set in the drive circuit to interlock the drive channels according to the drive command signal, so that the drive circuit has good electrical isolation performance, thereby achieving isolation between the main circuit and the control circuit, giving it strong anti-interference ability and avoiding interference of the power stage circuit on the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the accompanying drawings:

[0034] Figure 1 It is a schematic diagram of the drive interlock circuit structure;

[0035] Figure 2 It is a schematic diagram of the DSP module structure;

[0036] Figure 3 It is a schematic diagram of the logic interlock module structure;

[0037] Figure 4 This is a schematic diagram of the amplification module structure;

[0038] Figure 5 This is a schematic diagram of the pressure regulating device structure. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0040] Since the IGBT has a high operating frequency and input impedance, it is easily interfered with, causing the power stage circuit to cause significant interference to the control signal, which can easily cause the device to be mis-conducted, resulting in reduced power conversion quality or even short circuit, etc., making it difficult for the device to perform low-voltage control work on the power grid more stable and high-quality. In view of this, the utility model provides the following embodiments to solve the above technical problems:

[0041] Example 1

[0042] This embodiment provides a driving interlock circuit, such as Figure 1 Shown, including:

[0043] DSP module, used to generate multi-channel driving command signals;

[0044] The driving channel is used to transmit the driving instruction signal; the DSP module is electrically connected to the driving channel, and each driving instruction signal corresponds to one driving channel;

[0045] The logic interlocking module is used to interlock the driving channel according to the driving instruction signal; the logic interlocking module is electrically connected to the driving channel.

[0046] It also includes an amplification module and a response module; the amplification module is used to amplify the driving instruction signal; the response module is used to respond to the driving instruction signal;

[0047] The amplifying module is electrically connected to the driving channel and the output end of the logic interlocking module; the responding module is electrically connected to the output end of the amplifying module.

[0048] like Figure 2 As shown, the DSP module includes four drive instruction output ports: a first drive instruction port, a second drive instruction port, a third drive instruction port, and a fourth drive instruction port. In this embodiment, the DSP module is a 28377D chip; ports A46, A44, A42, and A40 correspond to the first drive instruction port, the second drive instruction port, the third drive instruction port, and the fourth drive instruction port, respectively.

[0049] like Figure 3 As shown, the logic interlock module includes: a first NOT gate F1, a second NOT gate F2, a third NOT gate F3, a fourth NOT gate F4, a first AND gate Y1, a second AND gate Y2, a third AND gate Y3, a fourth AND gate Y4, a fifth AND gate Y5 and a sixth AND gate Y6;

[0050] The first drive instruction port is electrically connected to the first input terminal of the third AND gate, and the first drive instruction port is electrically connected to the first NOT gate and then respectively connected to the first input terminal of the fourth AND gate and the first input terminal of the second AND gate;

[0051] The second driving instruction port is electrically connected to the second input terminal of the fourth AND gate, and the second driving instruction port is electrically connected to the second NOT gate and then to the first input terminal of the first AND gate;

[0052] The third driving instruction port is electrically connected to the first input terminal of the fifth AND gate, and the third driving instruction port is electrically connected to the third NOT gate and then to the second input terminal of the second AND gate;

[0053] The fourth drive instruction port is electrically connected to the second input terminal of the sixth AND gate, and the fourth drive instruction port is electrically connected to the fourth NOT gate and then respectively connected to the second input terminal of the first AND gate and the second input terminal of the fourth AND gate;

[0054] The output end of the first AND gate is connected to the second input end of the third AND gate, and the output end of the second AND gate is connected to the first input end of the sixth AND gate.

[0055] The output end of the third AND gate serves as the output end of the drive channel corresponding to the first drive instruction, the output end of the fourth AND gate serves as the output end of the drive channel corresponding to the second drive instruction, the output end of the fifth AND gate serves as the output end of the drive channel corresponding to the third drive instruction, and the output end of the sixth AND gate serves as the output end of the drive channel corresponding to the fourth drive instruction.

[0056] like Figure 4 As shown, the amplification module includes multiple amplification units with the same circuit structure; each amplification unit is used to amplify two drive instruction signals at the same time;

[0057] The amplifying unit includes: a first input terminal, a second input terminal, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a U44 chip, a first output terminal and a second output terminal;

[0058] The first input end is connected to the INA port of the U44 chip after being connected in series with the resistor R1, and the second input end is connected to the INB port of the U44 chip after being connected in series with the resistor R2;

[0059] One end of capacitor C1 is connected to the INA port of U44 chip, and the other end is grounded; one end of capacitor C2 is connected to the INB port of U44 chip, and the other end is grounded;

[0060] Capacitor C3 is connected between the GND port and VDD port of the U44 chip, capacitor C4 is connected in parallel on both sides of capacitor C3, the GND port of the U44 chip is grounded, and the VDD port of the U44 chip is connected to a 12V power supply;

[0061] The OUTA port of the U44 chip serves as the first output port, and the OUTB port of the U44 chip serves as the second output port;

[0062] The two drive command signals are input into the first input terminal and the second input terminal respectively, and are output from the first output terminal and the second output terminal accordingly.

[0063] The resistor R1 is 100Ω, the resistor R2 is 100Ω, the capacitor C1 is 100pF, the capacitor C2 is 100pF, the capacitor C3 is 1μF, and the capacitor C4 is 1μF.

[0064] The response module includes a semiconductor device, and the semiconductor device responds to the driving instruction signal by switching on and off; each driving channel corresponds to one or more semiconductor devices.

[0065] This solution only uses NOT gates and AND gates. By driving and interlocking the fully controlled IGBT device, precise control can be achieved, the probability of system false start-up can be reduced, and system stability can be improved. It can achieve high-quality and highly stable power output, and can also achieve efficient power transmission over long distances. At the same time, it can significantly reduce circuit line losses, increase the grid voltage at the end of the device, and bring a good power consumption environment to users at the end of the line.

[0066] Example 2

[0067] This embodiment provides a voltage regulating device, which includes the drive interlock circuit described in Example 1.

[0068] The voltage regulating device realizes flexible DC voltage regulation of the low-voltage distribution network system.

[0069] like Figure 5 In the voltage regulator shown, the rectifier input is a three-phase, four-wire system. It is boosted to 750V DC through AC / DC conversion and transmitted over long distances to the inverter. The inverter then converts the voltage back to AC through DC / AC conversion and feeds it into the end of the grid line to manage the voltage there. The distribution network flexible DC voltage regulator is a device that manages low voltage in low-voltage distribution networks. The device consists of a rectifier and an inverter, which are installed at the front end and the end of the power grid respectively. The line between the rectifier and the inverter adopts 750V DC flexible DC transmission to reduce the loss of the AC line. The entire device is connected in parallel in the power grid, which is safer and has functions such as low terminal voltage, voltage imbalance, and bus bias. The drive interlocking circuit of Example 1 is used in the voltage regulating device to drive the IGBT in the voltage regulating device. In each cycle, four drive command signals (A, B, C, D) correspond to four outputs, and a single one is output normally. If multiple outputs are output simultaneously, there are: 1 and 2 are interlocked; 3 and 4 are interlocked; 1 and 4 are interlocked, and once the interlocking circuits are input simultaneously, the outputs are all low.

[0070] The function logic formula corresponding to the logic interlock module is:

[0071] The simplification is:

[0072]

[0073] From the formula, there are only logical relationships of NOT and AND, so only NOT gates and AND gates need to be used in the logic interlock module.

[0074] The logic interlock module described above utilizes a minimal number of components, making certain logical design changes based on the number of channels covered by the chip, ultimately achieving interlocking with the minimum number of chips. Adding interlock circuits to the drive circuit ensures its reliability, significantly improving device stability and guaranteeing output power quality, ensuring power conversion across the entire device and managing low voltage at the end of the grid.

[0075] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of the utility model in detail. It should be understood that the above description is only a specific implementation method of the utility model and is not intended to limit the scope of protection of the utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the utility model should be included in the scope of protection of the utility model.

Claims

1. A drive interlock circuit, characterized in that: include: DSP module, used to generate multi-channel driving command signals; Drive channel, used for transmitting drive command signals; The DSP module is electrically connected to the drive channel, and each drive command signal corresponds to a drive channel; The logic interlocking module is used to interlock the driving channel according to the driving instruction signal; the logic interlocking module is electrically connected to the driving channel.

2. A drive interlock circuit according to claim 1, characterized in that: It also includes an amplification module and a response module; the amplification module is used to amplify the driving instruction signal; the response module is used to respond to the driving instruction signal; The amplifying module is electrically connected to the driving channel and the output end of the logic interlocking module; the responding module is electrically connected to the output end of the amplifying module.

3. A drive interlock circuit according to claim 2, characterized in that: The DSP module includes four drive instruction output ports: a first drive instruction port, a second drive instruction port, a third drive instruction port and a fourth drive instruction port.

4. A drive interlock circuit according to claim 3, characterized in that: The logic interlock module includes: a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate; The first drive instruction port is electrically connected to the first input terminal of the third AND gate, and the first drive instruction port is electrically connected to the first NOT gate and then respectively connected to the first input terminal of the fourth AND gate and the first input terminal of the second AND gate; The second driving instruction port is electrically connected to the second input terminal of the fourth AND gate, and the second driving instruction port is electrically connected to the second NOT gate and then to the first input terminal of the first AND gate; The third driving instruction port is electrically connected to the first input terminal of the fifth AND gate, and the third driving instruction port is electrically connected to the third NOT gate and then to the second input terminal of the second AND gate; The fourth drive instruction port is electrically connected to the second input terminal of the sixth AND gate, and the fourth drive instruction port is electrically connected to the fourth NOT gate and then respectively connected to the second input terminal of the first AND gate and the second input terminal of the fourth AND gate; The output end of the first AND gate is connected to the second input end of the third AND gate, and the output end of the second AND gate is connected to the first input end of the sixth AND gate.

5. A drive interlock circuit according to claim 4, characterized in that: The output end of the third AND gate serves as the output end of the drive channel corresponding to the first drive instruction, the output end of the fourth AND gate serves as the output end of the drive channel corresponding to the second drive instruction, the output end of the fifth AND gate serves as the output end of the drive channel corresponding to the third drive instruction, and the output end of the sixth AND gate serves as the output end of the drive channel corresponding to the fourth drive instruction.

6. A drive interlock circuit according to claim 4, characterized in that: The amplification module includes a plurality of amplification units with the same circuit structure; each amplification unit is used to amplify two drive instruction signals simultaneously; The amplifying unit includes: a first input terminal, a second input terminal, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a U44 chip, a first output terminal and a second output terminal; The first input end is connected to the INA port of the U44 chip after being connected in series with the resistor R1, and the second input end is connected to the INB port of the U44 chip after being connected in series with the resistor R2; One end of capacitor C1 is connected to the INA port of U44 chip, and the other end is grounded; one end of capacitor C2 is connected to the INB port of U44 chip, and the other end is grounded; Capacitor C3 is connected between the GND port and VDD port of the U44 chip, capacitor C4 is connected in parallel on both sides of capacitor C3, the GND port of the U44 chip is grounded, and the VDD port of the U44 chip is connected to a 12V power supply; The OUTA port of the U44 chip serves as the first output port, and the OUTB port of the U44 chip serves as the second output port; The two drive command signals are input into the first input terminal and the second input terminal respectively, and are output from the first output terminal and the second output terminal accordingly.

7. A drive interlock circuit according to claim 6, characterized in that: The resistor R1 is 100Ω, the resistor R2 is 100Ω, the capacitor C1 is 100pF, the capacitor C2 is 100pF, the capacitor C3 is 1μF, and the capacitor C4 is 1μF.

8. A drive interlock circuit according to claim 2, characterized in that: The response module includes a semiconductor device, and the semiconductor device responds to the driving instruction signal by switching on and off; each driving channel corresponds to one or more semiconductor devices.

9. A voltage regulating device, characterized in that: The voltage regulating device includes the drive interlock circuit according to any one of claims 1 to 8.

10. A voltage regulating device according to claim 9, characterized in that: The voltage regulating device realizes flexible DC voltage regulation of the low-voltage distribution network system.

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