SiC transistor with extended short circuit tolerance time

Abstract

The utility model relates to a SiC transistor capable of prolonging short-circuit tolerance time. Relates to the technical field of semiconductors. Comprising a SiC Sub layer, a SiC Drift layer, an N region, an isolation dielectric layer and a front electrode metal layer which are sequentially arranged from bottom to top, a P region extending downwards from the top surface is arranged in the SiC Drift layer; the N region is provided with a Pwell region which extends downwards from the top surface of the N region; the NP region extends downwards from the top surface of the Pwell region; the section of the gate oxide layer is of a U-shaped structure, and the gate oxide layer extends downwards into the P region from the top surface of the NP region; the Poly layer is filled in the gate oxide layer; the bottom surface of the isolation dielectric layer is respectively connected with the NP region, the gate oxide layer and the Poly layer, and the side part of the isolation dielectric layer is provided with a front ohmic contact alloy layer connected with the NP region. According to the utility model, advanced breakdown failure of the gate oxide layer at the corner at the bottom of the channel is avoided, and the use reliability of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC transistor with extended short-circuit withstand time. Background Art

[0002] After decades of development, semiconductor materials have evolved from first-generation traditional Si materials to second-generation GaAs and InP, and even to the currently popular third-generation materials SiC and GaN. All of these efforts have been driven by the goal of achieving higher power levels with smaller chip areas, resulting in ever-increasing power density. Wide-bandgap SiC (WBG) materials are particularly prominent, boasting numerous physical performance advantages, including a wide bandgap, high critical breakdown electric field, low intrinsic carrier concentration, fast saturation drift velocity, high melting point, and high thermal conductivity. Consequently, SiC-based power devices offer significant advantages in the high-voltage and high-power arena, and have already begun widespread use, such as in SiC diodes and SiC MOSFETs.

[0003] Although SiC MOSFET power devices have begun to gradually replace Si IGBT devices in high-voltage and high-power applications, the smaller chip area and thickness of SiC MOSFET devices also present certain risks in use, which is insufficient compared to Si IGBTs. Si IGBT devices typically have a short-circuit withstand time of approximately 10µs, while SiC MOSFET devices, due to their greater power density, have a short-circuit withstand time of only approximately 3µs. This places more stringent requirements on system circuit design. Improper design can easily cause the device to short-circuit and breakdown, damaging the entire system. Therefore, improving short-circuit characteristics is crucial to the long-term safe and stable use of SiC MOSFET devices. Utility Model Content

[0004] In response to the above problems, the present invention provides a SiC transistor with extended short-circuit withstand time, which avoids the breakdown failure of the gate oxide layer at the corner of the channel bottom, and at the same time prolongs the short-circuit withstand time of the device, thereby improving the short-circuit characteristics.

[0005] The technical solution of the utility model is:

[0006] A SiC transistor with extended short-circuit withstand time includes a SiC sub layer, a SiC drift layer, an N region, an isolation dielectric layer, and a front electrode metal layer arranged sequentially from bottom to top;

[0007] The SiC Drift layer is provided with a P region extending downward from the top surface;

[0008] The N region is provided with:

[0009] A Pwell region extending downward from the top surface of the N region;

[0010] an NP region extending downward from the top surface of the Pwell region;

[0011] A gate oxide layer having a U-shaped cross section extending downward from the top surface of the NP region into the P region;

[0012] A Poly layer filled in the gate oxide layer;

[0013] The bottom surface of the isolation dielectric layer is connected to the NP region, the gate oxide layer and the Poly layer respectively, and a front ohmic contact alloy layer connected to the NP region is provided on the side.

[0014] Specifically, the depth between the bottom surface of the P region and the top surface of the SiC Drift layer is 0.4 μm-1 μm.

[0015] Specifically, the thickness of the N region is 0.6um-2um.

[0016] Specifically, the thickness of the Pwell region is 0.4um-1.8um.

[0017] Specifically, the gate oxide layer has a thickness of 30 nm to 80 nm.

[0018] Beneficial effects of the utility model:

[0019] 1. Improve the short-circuit characteristics of the device:

[0020] The utility model is aimed at trench gate SiC MOSFET, and forms a JFET structure (P region, N region and Pwell region in the structure) inside the device. When the device is short-circuited, the short-circuit current must flow through the JFET region to reach the other electrode. The JFET region suppresses the short-circuit current, thereby extending the short-circuit withstand time of the device and improving the short-circuit characteristics of the SiC MOSFET.

[0021] 2. Protect the gate oxide layer of the device and improve the reliability of use:

[0022] Although trench-gate SiC MOSFETs can be manufactured to extremely small dimensions, the electric field concentration in the gate oxide layer at the bottom corners of the trench can easily lead to premature breakdown failure, damaging the device. This has always been a major challenge for trench-gate SiC MOSFETs. The present utility model addresses this issue by designing P regions on both sides of the bottom corners of the trench in the trench-gate SiC MOSFET, completely enclosing the bottom corners within the P regions to protect them. This prevents premature breakdown failure of the gate oxide layer at the bottom corners of the trench, thereby improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1This is a schematic diagram of the structure of the trench gate SiC MOSFET of the utility model;

[0024] Figure 2 It is a structural diagram of step S100 of the present utility model;

[0025] Figure 3 It is a structural diagram of step S200 of the present utility model;

[0026] Figure 4 It is a structural diagram of step S300 of the present utility model;

[0027] Figure 5 It is a structural diagram of step S400 of the present utility model;

[0028] Figure 6 It is a structural diagram of step S500 of the present utility model;

[0029] Figure 7 It is a structural diagram of step S700 of the present utility model;

[0030] Figure 8 It is a structural diagram of step S800 of the present utility model;

[0031] Figure 9 It is a structural diagram of step S900 of the present utility model;

[0032] Figure 10 It is a structural diagram of step S1000 of the present utility model;

[0033] Figure 11 It is a structural diagram of step S1100 of the present utility model;

[0034] Figure 12 It is a structural diagram of step S1200 of the present utility model;

[0035] In the figure, 1 is the SiC Sub layer, 2 is the SiCDrift layer, 3 is the P region, 4 is the N region, 5 is the Pwell region, 6 is the NP region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the isolation dielectric layer, 10 is the front ohmic contact alloy layer, and 11 is the front electrode metal layer. DETAILED DESCRIPTION

[0036] The present invention will be described in detail below with reference to specific practical cases. Examples of the embodiments are shown in the accompanying drawings. The schematic implementations of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0037] In the description of this utility model, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this utility model. They do not indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limiting this utility model. In the description of this utility model, unless otherwise specified, "plurality" means two or more.

[0038] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0039] A SiC transistor with extended short-circuit withstand time includes the following steps:

[0040] S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition;

[0041] The SiC Sub layer 1 in step S100 is heavily doped with a doping concentration of 5E18-2E19cm -2 , SiC Drift layer 2 is lightly doped with a doping concentration of 1E15-5E16cm -2 .

[0042] S200, forming a P region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation;

[0043] The P region 3 in step S200 is heavily doped, with a doping concentration of 5E17-1E19 cm -2 The depth from the bottom surface to the top surface of the SiC Drift layer 2 is 0.4um-1um.

[0044] S300 , forming an N region 4 on the top surface of the SiC Drift layer 2 by epitaxial deposition;

[0045] The N region 4 in step S300 is lightly doped with a doping concentration of 5E16-5E17cm -2 , thickness is 0.6um-2um.

[0046] S400 , forming a Pwell region 5 on the top surface of the N region 4 by Al ion implantation;

[0047] The Pwell region 5 in step S400 is lightly doped with a doping concentration of 1E17-3E18 cm -2 , thickness is 0.4um -1.8um.

[0048] S500 , forming a NP region 6 on the top surface of the Pwell region 5 by N ion implantation;

[0049] The NP region 6 in step S500 is heavily doped, with a doping concentration of 1E18-1E19 cm -2 , the bottom depth is 0.2um-1.5um.

[0050] S600, activating the implantation regions of the P region 3, the Pwell region 5 and the NP region 6 by high temperature ion annealing;

[0051] The high temperature ion annealing condition in step S600 is a temperature of 1600° C.-1900° C.

[0052] S700 , forming a trench on the top surface of the NP region 6 by etching downward, wherein the bottom surface of the trench coincides with the bottom surface of the P region 3 ;

[0053] The depth of the bottom of the trench in step S700 is 0 μm-0.3 μm less than the bottom depth of the P region 3 , and the P region 3 must wrap around the bottom corners on both sides of the trench.

[0054] S800, forming a gate oxide layer 7 on the inner wall of the trench by dry oxygen oxidation by introducing oxygen;

[0055] The thickness of the gate oxide layer 7 in step S800 is 30 nm to 80 nm.

[0056] S900 , forming a Poly layer 8 inside the trench by depositing polysilicon;

[0057] S1000, forming an isolation dielectric layer 9 on top of the NP region 6 and the Poly layer 8 by oxide deposition;

[0058] S1100, forming a front ohmic contact alloy layer 10 on the top surface of the NP region 6 by Ni metal sputtering followed by rapid thermal annealing;

[0059] The thickness of the Ni metal in step S1100 is 0.3um-1um.

[0060] S1200, forming a front electrode metal layer 11 on the top of the device by sputtering Ti and AlCu metals;

[0061] In step S1200 , the thickness of the Ti metal is 0.1 um to 0.6 um, and the thickness of the AlCu metal is 2 um to 5 um.

[0062] A SiC transistor with extended short-circuit withstand time, comprising a SiC Sub layer (1), a SiCDrift layer (2), an N region (4), an isolation dielectric layer (9), and a front electrode metal layer (11) arranged in sequence from bottom to top;

[0063] The SiC Drift layer (2) is provided with a P region (3) extending downward from the top surface;

[0064] The N region (4) is provided with:

[0065] A Pwell region (5) extending downward from the top surface of the N region (4) and having a spacing therebetween from the bottom surface of the N region (4);

[0066] an NP region (6) extending downward from the top surface of the Pwell region (5);

[0067] The gate oxide layer (7) has a U-shaped cross-section and extends downward from the top surface of the NP region (6) to the inside of the P region (3); the P region 3 wraps around the bottom corners on both sides of the gate oxide layer 7;

[0068] A Poly layer (8) is filled in the gate oxide layer (7), and the top surface of the Poly layer (8) is flush with the top surface of the gate oxide layer (7);

[0069] The bottom surface of the isolation dielectric layer (9) is respectively connected to the NP region (6), the gate oxide layer (7) and the Poly layer (8), and a front ohmic contact alloy layer (10) connected to the NP region (6) is provided on the side.

[0070] The bottom surface of the N region (4) is connected to the P region (3) and the SiC Drift layer (2) respectively.

[0071] The bottom surface of the front electrode metal layer (11) is respectively connected to the front ohmic contact alloy layer (10) and the isolation dielectric layer (9).

[0072] The utility model is as follows Figure 1 In the trench-gate SiC MOSFET device shown, P regions 3 are designed on both sides of the bottom corner of the trench, completely enclosing the bottom corner within P region 3 to protect the corner and prevent breakdown failure of the gate oxide layer at the bottom corner of the trench. At the same time, P region 3, N region 4, and Pwell region 5 above it form the JFET structure represented by the dashed box in the figure. When the device is short-circuited, the short-circuit current ID indicated by the arrow in the figure must flow through the JFET region before reaching the other electrode. The JFET region, in turn, suppresses the short-circuit current ID, thereby extending the device's short-circuit withstand time and improving its short-circuit characteristics.

Claims

1. A SiC transistor with extended short-circuit withstand time, characterized in that: It includes a SiC Sub layer (1), a SiC Drift layer (2), an N region (4), an isolation dielectric layer (9), and a front electrode metal layer (11) arranged in sequence from bottom to top; The SiC Drift layer (2) is provided with a P region (3) extending downward from the top surface; The N region (4) is provided with: A Pwell region (5) extending downward from the top surface of the N region (4); an NP region (6) extending downward from the top surface of the Pwell region (5); A gate oxide layer (7) having a U-shaped cross-section, extending downward from the top surface of the NP region (6) to the inside of the P region (3); A Poly layer (8) filled in the gate oxide layer (7); The bottom surface of the isolation dielectric layer (9) is respectively connected to the NP region (6), the gate oxide layer (7) and the Poly layer (8), and a front ohmic contact alloy layer (10) connected to the NP region (6) is provided on the side.

2. The SiC transistor with extended short-circuit withstand time according to claim 1, wherein: The depth between the bottom surface of the P region (3) and the top surface of the SiC Drift layer (2) is 0.4 μm-1 μm.

3. The SiC transistor with extended short-circuit withstand time according to claim 1, wherein: The thickness of the N region (4) is 0.6um-2um.

4. The SiC transistor with extended short-circuit withstand time according to claim 1, wherein: The thickness of the Pwell region (5) is 0.4um-1.8um.

5. The SiC transistor with extended short-circuit withstand time according to claim 1, wherein: The gate oxide layer (7) has a thickness of 30 nm to 80 nm.

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