Display substrate and display device

Abstract

According to the display substrate and the display device, the first metal wire is arranged on the side, away from the substrate, of the channel structure, and the first orthographic projection, on the substrate, of the first metal wire is overlapped with the second orthographic projection, on the substrate, of the first pixel defining structure; the ratio of the overlapping area to the second orthographic projection is larger than the preset threshold value, light rays irradiating from the pixel defining structure to the channel structure can irradiate on the first metal wires, and the first metal wires are made of metal and can reflect the light rays, so that the light rays can be reflected by the first metal wires. The light rays irradiated from the pixel defining structure to the channel structure direction can be reflected to the light emitting direction, the light rays irradiated to the IGZO film layer channel region are reduced, the shading performance is improved, and the phenomenon that Vth negative drift occurs to an afterimage due to the fact that a TFT is affected by illumination is avoided.

Description

Technical Field

[0001] The utility model relates to the field of display technology, in particular to a display substrate and a display device. Background Art

[0002] Recently, large-scale OLEDs (Organic Light-Emitting Diodes) have been used to create transparent displays, for example, for subway station announcements and advertising. These large-scale OLEDs allow for visibility inside and outside the vehicle, and the display content can be switched freely. Large-scale OLEDs are becoming a new growth area in the display industry. Among these large-scale OLEDs, top-gate oxide thin-film transistors (TFTs) have attracted attention due to their higher Ion (on-state current), higher aperture ratio, and improved TFT stability compared to bottom-gate oxide TFTs. However, the channel structure of the oxide TFTs commonly used in mass production, IGZO (indium gallium zinc oxide), is highly susceptible to light exposure, leading to a negative Vth (initial threshold voltage) shift. Currently, light reflects multiple times off the gate (gate line) or SD (source / drain) anode metal traces, striking the IGZO film channel region and causing a negative Vth shift in the TFT. Utility Model Content

[0003] The purpose of the present invention is to provide a display substrate and a display device. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present invention provides a display substrate, wherein the display substrate includes a plurality of pixel regions, each of the pixel regions includes a plurality of sub-pixels;

[0005] The display substrate includes: a substrate, a channel structure, an anode structure, a pixel defining structure and a first metal wiring;

[0006] The first metal wiring is arranged on a side of the channel structure away from the substrate, the pixel defining structure and the anode structure are arranged on a side of the first metal wiring away from the substrate, and the pixel defining structure is arranged between two adjacent anode structures to define anode structures of different sub-pixels;

[0007] A first orthographic projection of the first metal trace on the substrate overlaps with a second orthographic projection of the first pixel defining structure on the substrate, and a ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, wherein the first pixel defining structure is used to define the anode structures of different sub-pixels in the same pixel area.

[0008] In a possible implementation, the sub-pixels in the same pixel region have different light emission wavelengths;

[0009] The first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the second pixel defining structure on the substrate; the second pixel defining structure is the first pixel defining structure adjacent to the first anode structure, and the first anode structure is the anode structure of the sub-pixel with the shortest light-emitting wavelength.

[0010] In a possible implementation manner, the first metal trace includes VSS and / or VDD.

[0011] In a possible implementation, each of the pixel regions includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged in a "T-shaped" pattern.

[0012] In a possible implementation, each of the pixel regions includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged in a line in a row direction;

[0013] The first metal traces are arranged along the column direction, and the first orthographic projection of the first metal traces on the substrate overlaps with the third orthographic projection of the third pixel defining structure on the substrate; the third pixel defining structure is used to define the anode structure of the blue sub-pixel and another sub-pixel in the same pixel area.

[0014] In a possible implementation, the blue sub-pixel is disposed between a first sub-pixel and a second sub-pixel in the same pixel region, and the first metal trace includes VSS or VDD;

[0015] The first orthographic projection of the first metal trace on the substrate overlaps with the fourth orthographic projection of the fourth pixel defining structure on the substrate. The fourth pixel defining structure is used to define a blue sub-pixel and a first sub-pixel, or to define a blue sub-pixel and a second sub-pixel.

[0016] In a possible implementation, the blue sub-pixel is disposed between a first sub-pixel and a second sub-pixel in the same pixel region, and the first metal trace includes VSS and VDD;

[0017] The fifth orthographic projection of the VSS on the substrate overlaps with the fifth orthographic projection of the fifth pixel defining structure on the substrate, and the fifth pixel defining structure is used to define the blue sub-pixel and the first sub-pixel.

[0018] A sixth orthographic projection of the VDD on the substrate overlaps with a sixth orthographic projection of a sixth pixel defining structure on the substrate. The sixth pixel defining structure is used to define a blue sub-pixel and a second sub-pixel.

[0019] In a possible implementation, the display substrate further includes VSS and VDD, sensing lines;

[0020] The first metal routing is a metal routing between VSS and VDD, and the second metal routing is a metal routing between VSS and VDD other than the first metal routing;

[0021] The sensing line is arranged on a side of the channel structure away from the substrate;

[0022] The sensing line and the second metal wiring are respectively arranged on two sides of the pixel area.

[0023] In a possible embodiment, the display substrate further includes a light shielding layer, a buffer layer, a gate insulation structure, a gate structure, an interlayer dielectric layer, a source electrode, a passivation layer, a planarization layer, an encapsulation layer, a light shielding layer, a color filter layer, and a glass cover plate;

[0024] The light shielding layer, the buffer layer, the gate insulation structure, the gate structure, the interlayer dielectric layer, the passivation layer, the planar layer, the anode structure, the encapsulation layer, the color filter layer, and the glass cover are sequentially arranged away from the substrate.

[0025] An embodiment of a second aspect of the present invention provides a display device, comprising a display substrate according to any embodiment of the first aspect.

[0026] Beneficial effects of the embodiments of the present utility model:

[0027] An embodiment of the present invention provides a display substrate and a display device, in which a first metal trace is arranged on a side of a channel structure away from a substrate, and a first orthographic projection of the first metal trace on the substrate overlaps with a second orthographic projection of a first pixel defining structure on the substrate, and a ratio of the overlapping area to the second orthographic projection is greater than a preset threshold value. Light irradiated from the pixel defining structure in the direction of the channel structure will first irradiate the first metal trace. Since the first metal trace is made of metal and can reflect light, the light irradiated from the pixel defining structure in the direction of the channel structure can be reflected in the light emitting direction, thereby reducing the light irradiating the channel region of the IGZO film layer, improving the light shielding performance, and preventing the TFT from being affected by light and causing a negative Vth drift to cause an afterimage.

[0028] Of course, it is not necessary to achieve all the advantages described above simultaneously when implementing any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0030] Figure 1 A schematic diagram of the driving principle of a 3T1C pixel circuit structure provided by an embodiment of the present utility model;

[0031] Figure 2 A first schematic diagram of a display substrate provided by an embodiment of the present utility model;

[0032] Figure 3 A second schematic diagram of a display substrate provided by an embodiment of the present utility model;

[0033] Figure 4 A third schematic diagram of a display substrate provided by an embodiment of the present utility model;

[0034] Figure 5 A fourth schematic diagram of a display substrate provided by an embodiment of the present utility model;

[0035] Figure 6-1 A fifth schematic diagram of a display substrate provided by an embodiment of the present utility model;

[0036] Figure 6-2 A sixth schematic diagram of a display substrate provided by an embodiment of the present utility model;

[0037] Figure 7 This is a seventh schematic diagram of a display substrate provided by an embodiment of the present utility model. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field based on the present invention are within the scope of protection of the present invention.

[0039] An embodiment of the present invention provides a display substrate, the display substrate comprising a plurality of pixel regions, each of the pixel regions comprising a plurality of sub-pixels;

[0040] The display substrate includes: a substrate, a channel structure, an anode structure, a pixel defining structure and a first metal wiring;

[0041] The first metal wiring is arranged on a side of the channel structure away from the substrate, the pixel defining structure and the anode structure are arranged on a side of the first metal wiring away from the substrate, and the pixel defining structure is arranged between two adjacent anode structures to define anode structures of different sub-pixels;

[0042] A first orthographic projection of the first metal trace on the substrate overlaps with a second orthographic projection of the first pixel defining structure on the substrate, and a ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, wherein the first pixel defining structure is used to define the anode structures of different sub-pixels in the same pixel area.

[0043] A top-gate oxide thin film transistor (Oxide Thin Film Transistor, Oxide TFT) is a TFT structure in which the gate is above the channel structure. The solution of the present utility model is applicable to the top-gate oxide thin film transistor.

[0044] like Figure 1 As shown, Figure 1 This is a schematic diagram of the 3T1C pixel circuit structure driving principle. The figure includes three TFTs (T1, T2, T3) and one capacitor (Cst). The pixel circuit includes power supply voltages (OVDD, OVSS), a data signal (Data), and a sense signal (Sense). T2 is turned on or off by the control signal Switch Scan, and T3 is turned on or off by the control signal SenseScan. G is the gate of the driving transistor T1, D is the drain of the driving transistor T1, and S is the gate of the driving transistor T1.

[0045] like Figure 1 As shown in , for OLED products, if the OLED is to be lit, at least a gate, a source, a drain, a data signal, and a power supply voltage signal are required. In addition, if the pixel circuit needs to be tested, a sensing signal is also required.

[0046] Each pixel area includes a plurality of sub-pixels, wherein the light-emitting wavelengths of the sub-pixels may be the same or different. In one example, the light-emitting wavelengths of the sub-pixels included in each pixel area are different. In one example, each pixel area includes 3 sub-pixels, for example, the 3 sub-pixels are: red sub-pixel (R sub-pixel), green sub-pixel (G sub-pixel), and blue sub-pixel (blue sub-pixel). Alternatively, each pixel area includes 4 sub-pixels, for example, the 4 sub-pixels are: red sub-pixel (R sub-pixel), green sub-pixel (G sub-pixel), blue sub-pixel (blue sub-pixel), and white sub-pixel (W sub-pixel). The sub-pixels emit light of the corresponding color through the corresponding color filter layer. For example, the red sub-pixel corresponds to the red color filter layer, and the red light is emitted through the red color filter layer. The same applies to sub-pixels of other colors.

[0047] The display substrate includes a gate, a source, a drain, a channel structure and an anode structure. Each sub-pixel corresponds to an anode structure. Each sub-pixel corresponds to an anode structure, and a pixel defining structure is provided between two adjacent anode structures. The display substrate includes a variety of metal traces, for example, data lines, VDD (positive power line), VSS (negative power line), etc. The first metal trace can be any metal trace. Figure 2 As shown, Figure 2 In the figure, 011 and 012 represent the glass cover, 10 represents the channel structure, 20 represents the gate, 30 and 60 represent metal traces, 40 represents the anode structure, 50 represents the pixel definition structure, 70 represents the color filter layer, 80 represents the light shielding layer, and 90 represents the interlayer dielectric (ILD). Metal traces can be SD (source / drain), VDD (positive power supply), VSS (negative power supply), data lines, or sensing lines. The specific settings can be customized based on actual needs.

[0048] A channel structure is disposed on a substrate, a gate of the display substrate is disposed on a side of the channel structure away from the substrate, an anode structure is disposed on a side of the gate away from the substrate, and a pixel defining structure is disposed between two adjacent anode structures. The anode structure is a metal layer that can reflect light. If the pixel defining structure cannot reflect light, some light will be irradiated from the pixel defining structure to the channel structure. A first metal trace is disposed on a side of the channel structure away from the substrate, and a first orthographic projection of the first metal trace on the substrate overlaps with a second orthographic projection of the first pixel defining structure on the substrate, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold. That is, when the width of the first metal trace reaches a certain level, the first metal trace can reflect light so that the light does not need to irradiate the channel structure. The preset threshold can be set based on actual conditions. In one example, the first orthographic projection completely overlaps the second orthographic projection, that is, the ratio of the overlapping area to the second orthographic projection is 1.

[0049] In other words, light directed from the pixel-defining structure toward the channel structure will first strike the first metal trace. Because the first metal trace is made of metal and can reflect light, it can reflect light from the pixel-defining structure toward the channel structure back toward the light output direction, reducing the amount of light reaching the channel region of the IGZO film. This improves light-shielding performance and prevents the TFT from being affected by light and causing negative Vth drift and residual images. This improves the TFT's NBTIS (Negative bias Temperature Illμmination stress, stress under negative voltage, temperature, and light conditions, also known as negative voltage high-temperature light stability) characteristics and enhances the reliability of the display substrate.

[0050] Generally speaking, power lines (VDD, VSS) are used to provide power supply voltage. If these lines need to carry large currents, they should be relatively wide. Therefore, the first metal traces can be used for VDD and VSS. Alternatively, the first metal traces can also be sensing traces, as sensing traces are only used to detect signals and carry relatively low currents. To reduce the amount of light reaching the channel region of the IGZO film and improve light-shielding performance, the sensing traces can be widened so that the first orthographic projection of the sensing trace on the substrate overlaps with the second orthographic projection of the first pixel-defining structure on the substrate, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold.

[0051] In one possible embodiment, Figure 3 As shown, 4001 and 4002 are anode structures corresponding to different sub-pixels, and the two anode structures are separated, wherein AC is the edge of the cross section of the anode structure 4002, point A and point C are two points of the cross section of the anode structure 4002, wherein point A is the upper vertex and point C is the lower base, BD is the edge of the cross section of the anode structure 4001, point B and point D are two points of the cross section of the anode structure 4001, wherein point B is the upper vertex and point D is the lower base, the extension line of the AD line intersects with the first metal wiring, and the extension line of the BC line intersects with the first metal wiring, indicating that the first metal wiring can reflect all light irradiated from the pixel defining structure to the channel structure, and no light will be irradiated to the channel structure.

[0052] That is, the line width of the first metal trace can be determined based on the quadrilateral ABCD, which is the partition area between the anode structures, and the extension line of the diagonal side of the quadrilateral ABCD intersects with the cross section of the first metal trace.

[0053] In a possible implementation, the sub-pixels in the same pixel region have different light emission wavelengths;

[0054] The first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the second pixel defining structure on the substrate; the second pixel defining structure is the first pixel defining structure adjacent to the first anode structure, and the first anode structure is the anode structure of the sub-pixel with the shortest light-emitting wavelength.

[0055] When the pixel area includes multiple sub-pixels, the light emission wavelength of each sub-pixel is different. The shorter the wavelength, the higher the energy. If the light is irradiated on the channel area of the IGZO film layer, it is easy to cause the TFT Vth negative drift phenomenon. Therefore, the first metal trace is set at a position close to the anode structure of the sub-pixel with the shortest light emission wavelength.

[0056] like Figure 4 As shown, the pixel area includes multiple sub-pixels, among which 7001 is the color filter layer corresponding to the blue sub-pixel, 7002 is the color filter layer corresponding to the red sub-pixel, 7003 is the color filter layer corresponding to the green sub-pixel, 4001 is the anode structure of the blue sub-pixel, 4002 is the anode structure of the red sub-pixel, 4003 is the anode structure of the green sub-pixel, the blue light-emitting wavelength is the shortest, 4001 is the first anode structure, the second pixel defining structure adjacent to 4001 is 5001, 5002 is the pixel defining structure adjacent to 4002 and 4003, and the first metal routing can be set at a position close to 5001, such as 3001 shown in the figure.

[0057] Because the first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the second pixel defining structure on the substrate, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, the first metal trace can reduce the area of the IGZO film channel region where light with the shortest wavelength and highest energy is exposed, thereby improving the light-shielding performance and preventing the TFT from being affected by light and causing a negative Vth drift and an afterimage.

[0058] In a possible implementation manner, the first metal trace includes VSS and / or VDD.

[0059] The display substrate includes a first power supply line (VDD) and a second power supply line (VSS). Among them, VDD is the positive power supply line, and VSS is the negative power supply line. VDD and VSS are used to provide power supply voltage. The lines need to carry large currents, so VDD and VSS are relatively wide. Therefore, VSS and / or VDD can be arranged on the side of the channel structure away from the substrate. The first orthographic projection of VDD and VSS on the substrate overlaps with the second orthographic projection of the first pixel defining structure on the substrate. In this way, the limited space of the display substrate can be fully utilized, the light incident on the channel region of the IGZO film layer can be reduced, the light shielding performance can be improved, and the TFT can be prevented from being affected by light and causing a negative shift of Vth and image sticking. The NBTIS (Negative bias Temperature Illumination stress, stress under negative voltage, temperature and illumination conditions, also known as negative voltage high temperature illumination stability) characteristics of the TFT are improved, and the reliability of the display substrate is enhanced.

[0060] In a possible implementation manner, each pixel region includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged in a cross shape.

[0061] The pixel region can include four sub-pixels. For example, each pixel region includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged in a cross shape.

[0062] Because the 4 sub-pixels are arranged in a cross shape and the pixel defining structure is located between two sub-pixels, the first metal trace can be arranged in the middle of adjacent sub-pixels.

[0063] As Figure 5 shown, Figure 5 FIG. is a plan view of a pixel region. The pixel region 01 includes four sub-pixels (710, 720, 730, 740), and the four sub-pixels are arranged in a cross shape. The pixel region includes an edge region and a middle position. The first metal trace is arranged at the middle position (such as 3012 in the figure), and traces can also be arranged in the edge region (such as 3011 and 3013 in the figure). The first metal trace can be arranged in the middle of adjacent sub-pixels, that is, at the middle position of the pixel region. As Figure 5 shown, 3012 is the first metal trace, and other metal traces (3011, 3013) are arranged in the edge region. For example, sensing lines, etc. In one example, VDD is arranged at 3012, VSS is arranged at 3011, and a sensing line is arranged at 3013. Or, VSS is arranged at 3012, VDD is arranged at 3011, and a sensing line is arranged at 3013. Specifically, it can be set based on the actual situation and is not limited here.

[0064] In order to reduce the light reaching the channel area of the IGZO film layer, improve the light shielding performance, and prevent the TFT from being affected by light and causing Vth negative drift and afterimage.

[0065] In a possible implementation, the display substrate further includes VSS and VDD, sensing lines;

[0066] The first metal routing is a metal routing between VSS and VDD, and the second metal routing is a metal routing between VSS and VDD other than the first metal routing;

[0067] The sensing line is arranged on a side of the channel structure away from the substrate;

[0068] The sensing line and the second metal wiring are respectively arranged on two sides of the pixel area.

[0069] In one example, the display substrate includes a first power line (VDD) and a second power line (VSS), wherein VDD is a positive power line and VSS is a negative power line. VDD and VSS are used to provide power supply voltage. The lines need to have large currents, and VDD and VSS are relatively wide. In one example, VDD can be set at 3012, and VSS and sensing lines can be set on both sides of the pixel area, for example, 3013 is VSS and 3011 is a sensing line; or, 3011 is VSS and 3013 is a sensing line. In another example, VSS can be set at 3012, and VDD and sensing lines can be set on both sides of the pixel area, for example, 3013 is VDD and 3011 is a sensing line; or, 3011 is VDD and 3013 is a sensing line. Specifically, Figure 6-1 to Figure 6-2 shown.

[0070] In a possible implementation, each of the pixel regions includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged in a line in a row direction;

[0071] The first metal routing is arranged along the column direction, and the first orthographic projection of the first metal routing on the substrate overlaps with the third orthographic projection of the third pixel defining structure on the substrate; the third pixel defining structure is used to define the anode structure of the blue sub-pixel and another sub-pixel in the same pixel area.

[0072] The pixel region may include four sub-pixels. For example, each pixel region includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. The red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels may be arranged in a straight line in the row direction, with the first metal trace arranged in the column direction. Because the blue sub-pixel has the shortest wavelength and the highest energy, the first metal trace is disposed near the anode structure of the blue sub-pixel. Because the first metal trace overlaps with the second orthographic projection of the first pixel-defining structure on the substrate, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, the first metal trace can reduce the amount of light with the shortest wavelength and the highest energy that reaches the channel region of the IGZO film layer, thereby improving light shielding performance and preventing the TFT from being affected by light and causing a negative Vth drift and residual image.

[0073] In a possible implementation, the blue sub-pixel is disposed between a first sub-pixel and a second sub-pixel in the same pixel region, and the first metal trace includes VSS or VDD;

[0074] The first orthographic projection of the first metal trace on the substrate overlaps with the fourth orthographic projection of the fourth pixel defining structure on the substrate. The fourth pixel defining structure is used to define a blue sub-pixel and a first sub-pixel, or to define a blue sub-pixel and a second sub-pixel.

[0075] If the blue sub-pixel is located at the edge of the pixel area, or the pixel area is arranged so that there is a pixel-defining structure on one side of the anode structure of the blue sub-pixel and no pixel-defining structure on the other side, the first metal trace can be set only on the side with the pixel-defining structure. The first metal trace can be VSS or VDD. In an example, the first metal trace is VSS, and VDD can be set at other locations based on actual conditions.

[0076] In one possible embodiment, each pixel region includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixels, the green sub-pixels, the blue sub-pixels, and the white sub-pixels are arranged in a "T-shaped" pattern. A VDD may be provided in the center of the pixel region, with VSS and sensing lines provided on either side of the pixel region. Alternatively, a VSS may be provided in the center of the pixel region, with VDD and sensing lines provided on either side of the pixel region.

[0077] In this way, because the blue sub-pixel has the shortest emission wavelength and the highest energy, the first metal trace is arranged in the anode structure close to the blue sub-pixel. Because the second orthographic projection of the first metal trace and the first pixel-defining structure on the substrate overlaps, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, the first metal trace can reduce the area of light with the shortest emission wavelength and the highest energy that reaches the channel region of the IGZO film layer, thereby improving the light-shielding performance and preventing the TFT from being affected by light and causing a negative Vth drift and an afterimage.

[0078] In a possible implementation, the blue sub-pixel is disposed between a first sub-pixel and a second sub-pixel in the same pixel region, and the first metal trace includes VSS and VDD;

[0079] The fifth orthographic projection of the VSS on the substrate overlaps with the fifth orthographic projection of the fifth pixel defining structure on the substrate, and the fifth pixel defining structure is used to define the blue sub-pixel and the first sub-pixel.

[0080] A sixth orthographic projection of the VDD on the substrate overlaps with a sixth orthographic projection of a sixth pixel defining structure on the substrate. The sixth pixel defining structure is used to define a blue sub-pixel and a second sub-pixel.

[0081] If the blue sub-pixel is located in the middle of the pixel area, that is, there are pixel-defining structures on both sides of the anode structure of the blue sub-pixel, a first metal trace can be set on both sides of the pixel-defining structure, for example, one side is set to VSS and the other side is set to VDD.

[0082] In this way, because the blue sub-pixel has the shortest emission wavelength and the highest energy, the first metal trace is arranged in the anode structure close to the blue sub-pixel. Because the second orthographic projection of the first metal trace and the first pixel-defining structure on the substrate overlaps, and the ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, the first metal trace can reduce the area of light with the shortest emission wavelength and the highest energy that reaches the channel region of the IGZO film layer, thereby improving the light-shielding performance and preventing the TFT from being affected by light and causing a negative Vth drift and an afterimage.

[0083] In a possible embodiment, the display substrate further includes a light shielding layer, a buffer layer, a gate insulation structure, a gate structure, an interlayer dielectric layer, a source electrode, a passivation layer, a planarization layer, an encapsulation layer, a light shielding layer, a color filter layer, and a glass cover plate;

[0084] The light shielding layer, the buffer layer, the gate insulation structure, the gate structure, the interlayer dielectric layer, the passivation layer, the planar layer, the anode structure, the encapsulation layer, the color filter layer, and the glass cover are sequentially arranged away from the substrate.

[0085] like Figure 7As shown, the display substrate includes a substrate 101, a light-shielding layer 201, a buffer layer 301, a channel structure 401, a gate insulation structure 501, a gate structure 601, an interlayer dielectric layer 701, a source 801, a passivation layer 901, a planarization layer 1001, an anode structure 1101, a pixel defining structure 1201, various layers of the OLED 1301, an encapsulation layer 1401, a light-shielding layer 1501, a color filter layer (1601, 1701), a columnar spacer 1901, a glass cover 2001, various capacitor electrodes (2101, 2103), and metal traces (2201, 2202, 2203).

[0086] The pixel area includes a plurality of sub-pixels, wherein 1601 is a color filter layer corresponding to the blue sub-pixel, and 1701 is a color filter layer corresponding to the red sub-pixel.

[0087] The utility model also provides a method for preparing a display substrate, which is used to prepare Figure 7 The display substrate in the embodiment.

[0088] Figure 7 The process flow of the display substrate in the embodiment is as follows:

[0089] Step 10: providing a transparent substrate and performing photolithography on the transparent substrate to obtain a pattern of the light-shielding layer.

[0090] The substrate can be a transparent substrate, such as a 50-1000 μm thick Corning or Asahi Glass or other materials such as quartz glass. Metal is deposited on the substrate using a sputtering device, and patterned by photolithography and wet etching. The photoresist on the metal surface is then stripped off to obtain the pattern of the light-shielding layer.

[0091] Step 20: Prepare CNT (carbon nanotube) vias and grooves for Vdd and Data wiring.

[0092] The buffer layer film is deposited by PECVD (vapor phase electrolytic deposition). The buffer layer film can be composed of one or more overlapping components of SiNx, SiOx or SiOxNy. The thickness of the buffer layer film is 150 to 500 nm. The buffer layer is then patterned by photolithography and dry etching, and the photoresist on the surface of the buffer layer is stripped off to obtain CNT vias and grooves for Vdd and Data routing.

[0093] Step 30: depositing an active layer.

[0094] A sputter device is used to deposit oxide on the buffer layer as an active layer. After photolithography and wet etching patterning, the photoresist on the metal surface is stripped off. The oxide can be an amorphous oxide such as IGZO, ZnON, ITZO, etc.

[0095] Step 40: depositing a gate insulating layer.

[0096] The gate insulating layer, referred to as GI layer, is deposited by CVD (chemical vapor deposition) method.

[0097] Use a sputter device to deposit a gate metal layer on the insulating layer. The thickness of the gate metal layer can be 200nm-1000nm. The material of the gate metal layer can be Al, Mo, Cr, Cu, Ti, etc. The gate pattern is defined through photo and wet etching processes. At the same time, the photoresist is retained without being stripped. The photoresist on the gate metal layer is continued as a mask to dry-etch the GI pattern.

[0098] Step 50: depositing an interlayer dielectric layer.

[0099] The exposed IGZO is treated with a conductive process using any of NH3, N2, or H2 gases to reduce the ohmic contact resistance with the SD. The ILD layer is deposited using PECVD. Contact vias between the SD and the active layer are formed through dry etching, as are vias connecting the SD to the shield layer. Grooves are also dry-etched for the data traces in the light-emitting area. The ILD can be made of a single or multilayer SiNx or SiOx film.

[0100] Step 60: depositing source and drain electrodes.

[0101] The source and drain (SD) are deposited using a sputtering process. The source and drain materials can be Al, Mo, Cr, Cu, Ti, etc., with a thickness of 200-1000nm. The SD pattern is obtained through photolithography and wet etching processes.

[0102] Step 70: depositing a passivation layer using a CVD method. The material of the passivation layer may be SiO 2 .

[0103] Step 80: depositing a planarization layer.

[0104] The planarization material is deposited using a slit method. After pre-baking, exposure, and development, the pattern of the solidified pixel area is exposed. After post-baking at 230°C, water and organic solvents are removed. The thickness of the planarization layer can be 2.0μm to 3.5μm.

[0105] Step 90: depositing an anode.

[0106] The reflective anode is deposited using a sputtering process. The anode material can be metal, such as Cu, MoNb, ITO, Al, Mo, ITO, etc. The anode thickness is 2000nm-6000nm. The anode and auxiliary electrode patterns are obtained through photolithography and wet etching processes.

[0107] Step 100: depositing a pixel definition layer.

[0108] The pixel definition layer material is deposited using the slit method. After pre-baking, exposure, and development, the pattern of the solidified pixel area is exposed. After post-baking at 230°C, water and organic solvents are removed. The thickness of the pixel definition layer is 1.8μm to 2.0μm.

[0109] Step 110: manufacturing a top-emitting OLED display.

[0110] The evaporation process is used to form each OLED layer and the transparent cathode layer in sequence, and then the encapsulation layer is deposited using the CVD process. The array substrate and the CF cover are aligned to make a top-emitting OLED display.

[0111] Step 120: Prepare a color filter layer pattern.

[0112] The CF cover is coated with BM (black matrix) material using the slit method and a half-tone process. After pre-baking, exposure, and development, the pattern of the solidified color film in the pixel area is exposed. After post-baking at 230°C, water and organic solvents are removed. The thickness of the color film layer is 2.0μm to 2.5μm.

[0113] Step 130: preparing a color filter layer.

[0114] The blue color film material is coated using the slit method. After pre-baking, exposure, and development, the pattern of the solidified pixel area color film is exposed. After post-baking at 230°C to remove water and organic solvents, the thickness is 2.0μm to 3.5μm. The green and red color film patterns are formed in sequence according to the same process.

[0115] The present utility model also provides a display device, comprising the display substrate of any embodiment of the first aspect.

[0116] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0117] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0118] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention are included in the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that: The display substrate includes a plurality of pixel areas, and each of the pixel areas includes a plurality of sub-pixels; The display substrate includes: a substrate, a channel structure, an anode structure, a pixel defining structure and a first metal wiring; The first metal wiring is arranged on a side of the channel structure away from the substrate, the pixel defining structure and the anode structure are arranged on a side of the first metal wiring away from the substrate, and the pixel defining structure is arranged between two adjacent anode structures to define anode structures of different sub-pixels; A first orthographic projection of the first metal trace on the substrate overlaps with a second orthographic projection of the first pixel defining structure on the substrate, and a ratio of the overlapping area to the second orthographic projection is greater than a preset threshold, wherein the first pixel defining structure is used to define the anode structures of different sub-pixels in the same pixel area.

2. The display substrate according to claim 1, wherein: The light emission wavelengths of the sub-pixels in the same pixel area are different; The first orthographic projection of the first metal trace on the substrate overlaps with the second orthographic projection of the second pixel defining structure on the substrate; the second pixel defining structure is the first pixel defining structure adjacent to the first anode structure, and the first anode structure is the anode structure of the sub-pixel with the shortest light-emitting wavelength.

3. The display substrate according to claim 1, wherein The first metal trace includes VSS and / or VDD.

4. The display substrate according to claim 1, wherein Each of the pixel regions includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged in a "T-shaped" pattern.

5. The display substrate according to claim 1, wherein Each of the pixel regions includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged in a line in a row direction; The first metal routing is arranged along the column direction, and the first orthographic projection of the first metal routing on the substrate overlaps with the third orthographic projection of the third pixel defining structure on the substrate; the third pixel defining structure is used to define the anode structure of the blue sub-pixel and another sub-pixel in the same pixel area.

6. The display substrate according to claim 5, wherein: The blue sub-pixel is arranged between the first sub-pixel and the second sub-pixel in the same pixel region, and the first metal trace includes VSS or VDD; The first orthographic projection of the first metal trace on the substrate overlaps with the fourth orthographic projection of the fourth pixel defining structure on the substrate. The fourth pixel defining structure is used to define a blue sub-pixel and a first sub-pixel, or to define a blue sub-pixel and a second sub-pixel.

7. The display substrate according to claim 5, wherein: The blue sub-pixel is arranged between a first sub-pixel and a second sub-pixel in the same pixel region, and the first metal trace includes VSS and VDD; The fifth orthographic projection of the VSS on the substrate overlaps with the fifth orthographic projection of the fifth pixel defining structure on the substrate, and the fifth pixel defining structure is used to define the blue sub-pixel and the first sub-pixel. A sixth orthographic projection of the VDD on the substrate overlaps with a sixth orthographic projection of a sixth pixel defining structure on the substrate. The sixth pixel defining structure is used to define a blue sub-pixel and a second sub-pixel.

8. The display substrate according to claim 4, wherein: The display substrate further includes VSS and VDD, sensing lines; The first metal routing is a metal routing between VSS and VDD, and the second metal routing is a metal routing between VSS and VDD other than the first metal routing; The sensing line is arranged on a side of the channel structure away from the substrate; The sensing line and the second metal wiring are respectively arranged on two sides of the pixel area.

9. The display substrate according to claim 1, wherein: The display substrate further includes a light shielding layer, a buffer layer, a gate insulating structure, a gate structure, an interlayer dielectric layer, a source electrode, a passivation layer, a flat layer, an encapsulation layer, a light shielding layer, a color filter layer, and a glass cover plate; The light shielding layer, the buffer layer, the gate insulation structure, the gate structure, the interlayer dielectric layer, the passivation layer, the planar layer, the anode structure, the encapsulation layer, the color filter layer, and the glass cover are sequentially arranged away from the substrate.

10. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 9.

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