Test card for boundary scan test
By designing a test card that supports Boundary-Scan test, the server motherboard has solved the problem of low test coverage under high temperature, high frequency and high speed conditions, and achieved accurate positioning and convenient maintenance of faulty connection locations, improving testing efficiency.
Patent Information
- Application Number
- CN202421324604.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-12
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2034-06-12
AI Technical Summary
The prior art cannot effectively cover the connector welding test of server motherboards, especially under high temperature, high frequency and high speed conditions, and traditional testing methods are difficult to improve test coverage and locate faulty connection locations.
Design a test card including JTAG signal input interface, power control module, differential signal acquisition unit, signal acquisition module and gold finger. It supports Boundary-Scan testing method, can perform data storage and fault detection under high temperature, high frequency and high speed conditions, supports step by step self-test and conduction, and is tested through the IEEE 1149.1 protocol.
It improves the test coverage of the server motherboard, can accurately locate the fault connection location under high temperature, high frequency and high speed conditions, facilitates maintenance, supports cascade of multiple test cards, and realizes boundary scanning testing with simple structure and convenient operation.
Smart Images
Figure CN223205602U_ABST
Abstract
Description
Technical Field
[0001] The utility model is applied to the technical field of printed circuit board testing, and particularly relates to a test card for boundary scan testing. Background Art
[0002] As the functionality of server motherboards in the manufacturing industry continues to increase, the performance requirements for testing memory modules are also gradually increasing. With the continuous advancement of CPU architectures and the continuous upgrade of server motherboards under test, M.2 test cards, E1.S test cards, and Slimline test cards have been developed to meet the requirements of Boundary-Scan test methods. These new technology cards, such as the M.2 test card, MCIO_74P test card, and Slimline test card, offer high performance, larger capacity, enhanced data integrity, and easier maintenance. Traditional ICT in-circuit testing in the manufacturing industry involves designing fixtures to connect test points on the PCBA to a large, programmable digital tester. The tester then measures the electronic components and captures digital signals on the PCBA, enabling SMT soldering process testing of components, including basic components like capacitors and resistors, as well as analog and digital chips. However, with the increasing compactness of components, the reduction in test points, the increasing integration density of chips, and the increase in high-speed signals, ICT testing has shown limitations, such as the inability to cover connector soldering on the board. Therefore, it is necessary to provide an M.2 test card for boundary scan testing that has a simple structure, is easy to operate, easy to maintain, supports multiple test methods of Boundary-Scan testing, can improve the test coverage of server motherboards, supports step-by-step self-test conduction, realizes data storage under high temperature, high frequency, and high speed conditions, and detects and locates the location of faulty connections. Utility Model Content
[0003] The technical problem to be solved by the utility model is to overcome the deficiencies of the prior art and provide a test card for boundary scan testing that is simple in structure, easy to operate, easy to maintain, supports a variety of boundary-scan test methods, can improve the test coverage of server motherboards, supports step-by-step self-check conduction, realizes data storage under high temperature, high frequency and high speed conditions, and detects and locates fault connection positions.
[0004] The technical solution adopted by the present invention is: the present invention includes a JTAG signal input interface, a power control module, a differential signal acquisition unit, a signal acquisition module and a gold finger, the differential signal acquisition unit is connected to the power control module and the signal acquisition module, the power control module and the signal acquisition module are both connected to the JTAG signal input interface, and the gold finger is connected to the signal acquisition module.
[0005] As can be seen from the above scheme, the test card for boundary scan testing supports M.2 test cards, MCIO_74P test cards, and Slimline test cards using the Boundary-Scan test method, thereby improving test coverage for server motherboards. It supports step-by-step self-testing to detect and locate faulty connections for easy maintenance. The gold finger end features an upward-facing anti-stuck notch, resulting in a simple structure and easy operation. It can store data under high-temperature, high-frequency, and high-speed conditions. It supports cascading, allowing multiple test cards to be cascaded into a chain for testing. It supports the IEEE 1149.1 protocol for Boundary-Scan testing and has a programming function. Information is transmitted via the JTAG (FCP connector) communication interface.
[0006] A preferred solution is that the test card for boundary scan testing further includes a cascade indicator light, and the cascade indicator light is connected to the differential signal acquisition unit.
[0007] A preferred solution is that the test card for boundary scan testing further includes a power indicator light, and the power indicator light is connected to the gold finger.
[0008] A preferred solution is that the ENABLE_JTAG_NEXT pin of the differential signal acquisition unit is connected to the corresponding pin of the power control module.
[0009] A preferred solution is that the MCU_SCL pin and the MCU_SDA pin of the differential signal acquisition unit are connected to the corresponding pins of the signal acquisition module.
[0010] A preferred solution is that the JTAG signal input interface JTAG_TDO pin, TDI_OUT pin, and TDO_OUT pin are all connected to corresponding pins of the power control module.
[0011] A preferred solution is that the M2 pin of the signal acquisition module is connected to the pin corresponding to the gold finger.
[0012] A preferred solution is that the token_out_next pin of the cascade indicator light is connected to the corresponding pin of the differential signal acquisition unit. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 It is a structural block diagram of the utility model;
[0014] Figure 2 is a circuit schematic diagram of the JTAG signal input interface;
[0015] Figure 3 is a circuit schematic diagram of the power control module;
[0016] Figure 4 is a circuit schematic diagram of the differential signal acquisition unit;
[0017] Figure 5 is a circuit schematic diagram of the cascade indicator light;
[0018] Figure 6 is a circuit schematic diagram of the signal acquisition module;
[0019] Figure 7 1 is a circuit schematic diagram of the power supply control module. DETAILED DESCRIPTION
[0020] like Figure 1 As shown, in this embodiment, the utility model includes a JTAG signal input interface 1, a power control module 2, a differential signal acquisition unit 3, a signal acquisition module 5, and a gold finger 6. The differential signal acquisition unit 3 is connected to the power control module 2 and the signal acquisition module 5, and the power control module 2 and the signal acquisition module 5 are both connected to the JTAG signal input interface 1. The gold finger 6 is connected to the signal acquisition module 5. When the test card is being inserted into the motherboard, the cascade test card is connected through the JTAG signal input interface 1. After the motherboard is powered on, a 3.3V voltage is connected through the gold finger 6. When performing a Boundary-Scan test, a program is run. The signal collected through the gold finger 6 is transmitted to the signal acquisition module 5, and compared with the signal transmitted from the JTAG signal input interface 1 to obtain the difference between the actual value and the expected value, so that the actual signal is transmitted stably.
[0021] like Figure 1 As shown, in this embodiment, the test card for boundary scan test further includes a cascade indicator light 4, which is connected to the differential signal acquisition unit 3. When performing the boundary scan test, the program is run and the cascade indicator light 4 lights up, indicating that the cascade is on.
[0022] In this embodiment, the test card for boundary scan testing further includes a power indicator light, which is connected to the gold finger 6. When a 3.3V voltage is connected to the gold finger 6, the power indicator light lights up.
[0023] like Figure 1 、 Figure 3 as well as Figure 4 As shown, in this embodiment, the ENABLE_JTAG_NEXT pin of the differential signal acquisition unit 3 is connected to the corresponding pin of the power control module 2. The model of the differential signal acquisition unit 3 is STM8L152K6U6TR*, and the model of the power control module 2 is 74CBTLV3257.
[0024] like Figure 4 、 Figure 6 As shown, in this embodiment, the MCU_SCL pin and the MCU_SDA pin of the differential signal acquisition unit 3 are connected to the corresponding pins of the signal acquisition module 5. The model of the signal acquisition module 5 is LCMXO256C-100TQFP.
[0025] like Figure 2 and Figure 3 As shown, in this embodiment, the JTAG_TDO pin, TDI_OUT pin, and TDO_OUT pin of the JTAG signal input interface 1 are all connected to corresponding pins of the power control module 2. The model of the JTAG signal input interface 1 is XH2.54*6.
[0026] like Figure 6 and Figure 7 As shown, in this embodiment, the M2 pin of the signal acquisition module 5 is connected to the corresponding pin of the gold finger 6. The model of the gold finger 6 is GF-NGFF-75P.
[0027] like Figure 4 and Figure 5 As shown, Figure 1 As shown, in this embodiment, the token_out_next pin of the cascade indicator light 4 is connected to the corresponding pin of the differential signal acquisition unit 3 .
[0028] The working principle of the present invention is as follows: when the test card is being inserted into the main board, the cascade test card is connected via the JTAG signal input interface. After the main board is powered on, the 3.3V voltage is connected via the gold finger, and the power indicator light is on. When performing a Boundary-Scan test, the program is run, and the cascade indicator light is on, indicating that the cascade is turned on. The signal collected via the gold finger is transmitted to the signal acquisition module, and compared with the signal transmitted from the JTAG signal input interface to obtain the difference between the actual value and the expected value, so that the actual signal is stably transmitted.
Claims
1. A test card for boundary scan testing, characterized in that: It comprises a JTAG signal input interface (1), a power control module (2), a differential signal acquisition unit (3), a signal acquisition module (5) and a gold finger (6), wherein the differential signal acquisition unit (3) is connected to the power control module (2) and the signal acquisition module (5), the power control module (2) and the signal acquisition module (5) are both connected to the JTAG signal input interface (1), and the gold finger (6) is connected to the signal acquisition module (5).
2. The test card for boundary scan testing according to claim 1, wherein: The test card for boundary scan testing further comprises a cascade indicator light (4), and the cascade indicator light (4) is connected to the differential signal acquisition unit (3).
3. The test card for boundary scan testing according to claim 1, wherein: The test card for boundary scan testing also includes a power indicator light, which is connected to the gold finger (6).
4. The test card for boundary scan testing according to claim 1, wherein: The ENABLE_JTAG_NEXT pin of the differential signal acquisition unit (3) is connected to the corresponding pin of the power control module (2).
5. The test card for boundary scan testing according to claim 1, wherein: The MCU_SCL pin and the MCU_SDA pin of the differential signal acquisition unit (3) are connected to corresponding pins of the signal acquisition module (5).
6. The test card for boundary scan testing according to claim 1, wherein: The JTAG_TDO pin, the TDI_OUT pin, and the TDO_OUT pin of the JTAG signal input interface (1) are all connected to corresponding pins of the power control module (2).
7. The test card for boundary scan testing according to claim 1, wherein: The M2 pin of the signal acquisition module (5) is connected to the corresponding pin of the gold finger (6).
8. The test card for boundary scan testing according to claim 2, wherein: The token_out_next pin of the cascade indicator light (4) is connected to the corresponding pin of the differential signal acquisition unit (3).