Serial port fault automatic offline circuit
Through the automatic offline circuit of serial port fault, resistors, capacitors and logic gate circuits are used to control the level changes, which solves the communication error problem caused by TXD pin failure in serial port communication, and realizes automatic offline processing.
Patent Information
- Application Number
- CN202422394903.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2034-09-30
AI Technical Summary
In existing serial communication, when the TXD pin of one device continues to go low, it may cause the RXD pin of another device to continue to receive errors, affecting normal operation.
Design a serial port fault automatic offline circuit, including resistor R1, capacitor C1, diode D1, OR gate U1 and NAND gate U2, to realize the level change of the TXD pin by controlling the charging and discharging of capacitor C1, automatically offline the faulty device to avoid communication errors.
It realizes automatic offline failure of the device when the TXD pin is continuously low, preventing communication errors and ensuring normal communication.
Smart Images
Figure CN223205859U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of serial port communication, in particular to an automatic offline circuit for serial port failure. Background Art
[0002] Among the existing communication methods between different devices, serial communication has become the preferred communication method due to its simplicity and ubiquitous availability.
[0003] The way two different devices communicate via serial ports is as follows:
[0004] When there is no data transmission, the TXD pin and RXD pin of the two devices are both high level and in communication standby state;
[0005] When data needs to be transmitted, the device sending the data will first pull the TXD pin low, then send 1 byte of data, and then pull the TXD pin high after the data is sent.
[0006] When one of the two devices fails, the TXD pin of the failed device may continue to be at a low level, causing the RXD pin of the other device to continuously trigger a serial port receive error or continuously receive data 0, affecting the normal operation of the other device.
[0007] In view of the existence of the above problems, it is necessary to study a serial port fault automatic offline circuit, which can realize that when the TXD pin of one of the two devices performing serial communication fails continues to become a low level, the other device will automatically go offline for the faulty device, avoiding communication errors and affecting the operation of the other device. Utility Model Content
[0008] The purpose of the utility model is to provide a serial port fault automatic offline circuit, which can realize that when the TXD pin of one of the two devices performing serial communication fails continuously becomes a low level, the other device is automatically offline for the failed device, thereby avoiding communication errors affecting the operation of the other device.
[0009] In order to achieve the above objectives, the solution of the present invention is:
[0010] A serial port fault automatic offline circuit includes a resistor R1, a capacitor C1, a diode D1, an OR gate U1 and a NOT gate U2; a first input end of the OR gate U1 and an input end of the NOT gate U2 are connected to the input end of the serial port fault automatic offline circuit, an output end of the NOT gate U2 is connected to the cathode of the diode D1, an anode of the diode D1 is connected to the first end of the resistor R1, the first end of the capacitor C1 and the second input end of the OR gate U1, a second end of the resistor R1 is connected to a control power supply VCC, a second end of the capacitor C1 is grounded, and an output end of the OR gate U1 is connected to the output end of the serial port fault automatic offline circuit.
[0011] The serial port fault automatic offline circuit further includes a resistor R2, and the output end of the OR gate U1 is connected to the output end of the serial port fault automatic offline circuit via the resistor R2.
[0012] After adopting the above solution, the serial port fault automatic offline circuit of the utility model is connected in series between two devices when in use. The input end of the serial port fault automatic offline circuit is connected to the TXD pin of the first device, and the output end of the serial port fault automatic offline circuit is connected to the RXD pin of the second device. The working principle of the utility model is as follows:
[0013] When the TXD pin of the first device is always at a high level, the NOT gate U2 outputs a low level. At this time, the voltage on the capacitor C1 is released through the diode D1. The cathode voltage of the diode D1 is the output voltage of the NOT gate U2 (0V), and the anode voltage of the diode D1 is the forward voltage drop of the diode D1 (0.3V). Since the anode of the diode D1 is also connected to the second input terminal of the OR gate U1, the second input terminal level of the OR gate U1 is low at this time, and the first input terminal level of the OR gate U1 is high at this time. At this time, the output of the OR gate U1 is high to the second device, that is, the RXD pin of the second device is set to a high level, making the second device in a data waiting state;
[0014] When the first device needs to send data, since the data consists of data 0 and data 1, the TXD pin of the first device outputs a series of high or low levels. When the TXD pin of the first device outputs a low level, the output of the NOT gate U2 is high. At this time, the diode D1 is cut off, and the control power supply VCC charges the capacitor C1 through the resistor R1. The capacitor C1 takes about 0.7 seconds to charge to the rated voltage of the capacitor C1, so that the level of the second input terminal of the OR gate U1 is raised to a high level. When the TXD pin of the first device outputs a high level, the output of the NOT gate U2 becomes a low level. At this time, the diode D1 discharges the capacitor C1. At this time, since there is no current limiting by any resistor, the capacitor C1 discharges quickly, causing the level of the second input terminal of the OR gate U1 to quickly become a low level. As can be seen from the foregoing, during the data transmission process of the first device, when the TXD pin of the first device outputs a low level, it takes 0.7 seconds for capacitor C1 to be charged to the rated voltage of capacitor C1. When the TXD pin of the first device outputs a high level, capacitor C1 is immediately discharged. However, since the time it takes for the first device to send each byte of data is much less than 0.7 seconds, capacitor C1 is never able to be charged to the rated voltage of capacitor C1 during the transmission process of the first device. This causes the second input terminal of the NOT gate U2 to be always at a low level. In this way, the output level of the NOT gate U2 depends on the output level of the TXD pin of the first device, that is, the output level of the NOT gate U2 is the same as the output level of the TXD pin of the first device. In this way, the first device and the second device can communicate normally.
[0015] When the TXD pin of the first device is continuously at a low level due to a fault, after 0.7 seconds, the capacitor C1 is charged to the rated voltage of the capacitor C1. At this time, the second input terminal level of the OR gate U1 is continuously at a high level. In this way, no matter whether the first input terminal level of the OR gate U1 is high or low, the OR gate U1 outputs a high level, that is, the RXD pin of the second device is always at a high level, and the second device is always in a state of waiting for data reception. In this way, the second device realizes automatic offline processing of the first device, thereby preventing the second device from working due to communication errors. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 This is a schematic diagram of the use of the present utility model. DETAILED DESCRIPTION
[0017] In order to further explain the technical solution of the present invention, the present invention will be described in detail below through specific embodiments.
[0018] like Figure 1As shown, the utility model discloses a serial port fault automatic offline circuit, which includes a resistor R1, a capacitor C1, a diode D1, an OR gate U1 and a NOT gate U2; the first input end of the OR gate U1 and the input end of the NOT gate U2 are connected to the input end of the serial port fault automatic offline circuit, the output end of the NOT gate U2 is connected to the cathode of the diode D1, the anode of the diode D1 is connected to the first end of the resistor R1, the first end of the capacitor C1 and the second input end of the OR gate U1, the second end of the resistor R1 is connected to the control power supply VCC, the second end of the capacitor C1 is grounded, and the output end of the OR gate U1 is connected to the output end of the serial port fault automatic offline circuit.
[0019] Cooperate Figure 1 As shown, the serial port fault automatic offline circuit of the present invention is connected in series between two devices when in use. The input end of the serial port fault automatic offline circuit is connected to the TXD pin of the first device, and the output end of the serial port fault automatic offline circuit is connected to the RXD pin of the second device. The working principle of the present invention is as follows:
[0020] When the TXD pin of the first device is always at a high level, the NOT gate U2 outputs a low level. At this time, the voltage on the capacitor C1 is released through the diode D1. The cathode voltage of the diode D1 is the output voltage of the NOT gate U2 (0V), and the anode voltage of the diode D1 is the forward voltage drop of the diode D1 (0.3V). Since the anode of the diode D1 is also connected to the second input terminal of the OR gate U1, the second input terminal level of the OR gate U1 is low at this time, and the first input terminal level of the OR gate U1 is high at this time. At this time, the output of the OR gate U1 is high to the second device, that is, the RXD pin of the second device is set to a high level, making the second device in a data waiting state;
[0021] When the first device needs to send data, since the data consists of data 0 and data 1, the TXD pin of the first device outputs a series of high or low levels. When the TXD pin of the first device outputs a low level, the output of the NOT gate U2 is high. At this time, the diode D1 is cut off, and the control power supply VCC charges the capacitor C1 through the resistor R1. The capacitor C1 takes about 0.7 seconds to charge to the rated voltage of the capacitor C1, so that the level of the second input terminal of the OR gate U1 is raised to a high level. When the TXD pin of the first device outputs a high level, the output of the NOT gate U2 becomes a low level. At this time, the diode D1 discharges the capacitor C1. At this time, since there is no current limiting by any resistor, the capacitor C1 discharges quickly, causing the level of the second input terminal of the OR gate U1 to quickly become a low level. As can be seen from the foregoing, during the data transmission process of the first device, when the TXD pin of the first device outputs a low level, it takes 0.7 seconds for capacitor C1 to be charged to the rated voltage of capacitor C1. When the TXD pin of the first device outputs a high level, capacitor C1 is immediately discharged. However, since the time it takes for the first device to send each byte of data is much less than 0.7 seconds, capacitor C1 is never able to be charged to the rated voltage of capacitor C1 during the transmission process of the first device. This causes the second input terminal of the NOT gate U2 to be always at a low level. In this way, the output level of the NOT gate U2 depends on the output level of the TXD pin of the first device, that is, the output level of the NOT gate U2 is the same as the output level of the TXD pin of the first device. In this way, the first device and the second device can communicate normally.
[0022] When the TXD pin of the first device is continuously at a low level due to a fault, after about 0.7 seconds, the capacitor C1 is charged to the rated voltage of the capacitor C1. At this time, the second input terminal level of the OR gate U1 is continuously at a high level. In this way, no matter whether the first input terminal level of the OR gate U1 is high or low, the OR gate U1 outputs a high level, that is, the RXD pin of the second device is always at a high level, and the second device is always in a state of waiting for data reception. In this way, the second device realizes automatic offline processing of the first device, thereby preventing the second device from working due to communication errors.
[0023] In an embodiment of the present invention, the serial port fault automatic offline circuit of the present invention may further include a resistor R2. The output end of the OR gate U1 is connected to the output end of the serial port fault automatic offline circuit via the resistor R2. The resistor R2 may function as a current limiting protection.
[0024] In an embodiment of the present invention, the rated voltage of capacitor C1 can be 2.2V, the capacitance of capacitor C1 can be 10uF, the voltage of control power supply VCC can be 5V, the resistance of resistor R1 can be 100KΩ, and the resistance of resistor R2 can be 1KΩ.
[0025] The above embodiments and drawings do not limit the product form and style of the present invention. Any appropriate changes or modifications made by ordinary technicians in the relevant technical field should be deemed to be within the patent scope of the present invention.
Claims
1. A serial port fault automatic offline circuit, characterized by: It includes resistor R1, capacitor C1, diode D1, OR gate U1 and NOT gate U2; A first input terminal of the OR gate U1 and an input terminal of the NOT gate U2 are connected to an input terminal of the serial port fault automatic offline circuit, an output terminal of the NOT gate U2 is connected to a cathode of a diode D1, an anode of the diode D1 is connected to a first terminal of a resistor R1, a first terminal of a capacitor C1, and a second input terminal of the OR gate U1, a second terminal of the resistor R1 is connected to a control power supply VCC, a second terminal of the capacitor C1 is grounded, and an output terminal of the OR gate U1 is connected to an output terminal of the serial port fault automatic offline circuit.
2. The serial port fault automatic offline circuit according to claim 1, characterized in that: It also includes a resistor R2, and the output end of the OR gate U1 is connected to the output end of the serial port fault automatic offline circuit through the resistor R2.