SoC chip pin multiplexing circuit

Abstract

The utility model discloses an SoC chip pin multiplexing circuit. An SoC chip is provided with a first multiplexing pin and a second multiplexing pin. The pin multiplexing circuit comprises a first GPI O circuit, a second GPI O circuit, an XTAL circuit and a voltage clamping circuit. The first multiplexing pin is connected with the input end of the first GPI O circuit and the input end of the XTAL circuit. The second multiplexing pin is connected with the output end of the second GPI O circuit and the output end of the XTAL circuit. The first GPI O circuit comprises a first phase inverter, a second phase inverter, a first switch and a second switch; the second GPI O circuit comprises a third phase inverter, a fourth phase inverter, a third switch and a fourth switch; and the XTAL circuit comprises a fifth resistor Rf and a fifth phase inverter. According to the SoC chip pin multiplexing circuit provided by the utility model, the requirement on the output resistance when the multiplexing pin is in a turn-off state can be reduced, so that the working frequency of a GPI O (General Purpose Interface Output) can be improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of electronic circuits and relates to a pin multiplexing circuit, in particular to a SoC chip pin multiplexing circuit. Background Art

[0002] It is a common practice to use XTAL to provide a stable and reliable clock for SoC. Generally speaking, the input and output of XTAL each need to occupy a pin of the SoC chip. Pin resources are an important resource in SoC chips. They can connect chips and external devices (including sensors, memories, and communication interfaces, etc.). Usually the chip will allocate as many pin configurations as possible to GPIO to enrich the functions of the chip. If the SoC chip has an internal clock source or other clock source and does not need to use the clock provided by XTAL, then the two pins occupied by XTAL will be wasted. In this case, the input / output of XTAL and the input / output of GPIO can be connected to the same pin, and two functions can be achieved through different chip configurations:

[0003] Two pins are used as XTAL input / output

[0004] Two pins are used as two GPIO input / output

[0005] This design needs to avoid the influence of GPIO on the normal operation of XTAL. The general practice is to configure GPIO to high impedance when the pin is used as XTAL input / output to avoid affecting XTAL. Figure 1 As shown in the figure, setting SW1 / SW2 in GPIO1 and GPIO2 to open can reduce the influence of GPIO on XTAL.

[0006] like Figure 2 The figure shows the equivalent circuit at the XTAL input. R1 represents the open-circuit resistance of SW1, and R2 represents the open-circuit resistance of SW2. According to Kirchhoff's current law, the voltage at the XTAL input is given by equation (1).

[0007] Vxtal_in=(Vout / Rf+Vdd / R1) / (1 / R1+1 / R2+1 / Rf) Formula (1)

[0008] To maximize the XTAL's drive capability, the DC voltage at the XTAL input and output must be equal. The resistance values of R1 and R2 vary significantly under different temperatures, voltages, and process corners. To ensure that the DC voltage at the XTAL input is not affected by GPIO1, R1 and R2 generally need to be at least ten times the value of Rf. Because the open-circuit resistance of SW1 / SW2 cannot be too small, the minimum closed resistance is also limited. This results in a high output impedance when the GPIO drives off-chip devices, limiting the maximum operating frequency.

[0009] In view of this, there is an urgent need to design a new SoC chip pin multiplexing method to overcome at least some of the above-mentioned defects of the existing SoC chip pin multiplexing method. Utility Model Content

[0010] The utility model provides a SoC chip pin multiplexing circuit, which can reduce the requirement on the output resistance of the multiplexed pin when it is in an off state, thereby increasing the frequency of GPIO operation.

[0011] In order to solve the above technical problems, according to one aspect of the present invention, the following technical solutions are adopted:

[0012] A SoC chip pin multiplexing circuit, wherein the SoC chip is provided with a first multiplexing pin and a second multiplexing pin; the pin multiplexing circuit comprises: a first GPIO circuit, a second GPIO circuit, an XTAL circuit and a voltage clamping circuit;

[0013] The first multiplexed pin is connected to the input end of the first GPIO circuit and the XTAL circuit respectively, and the second multiplexed pin is connected to the output end of the second GPIO circuit and the XTAL circuit respectively;

[0014] The first GPIO circuit includes a first inverter, a second inverter, a first switch, and a second switch; the output end of the first inverter is connected to the first multiplexing pin and the input end of the second inverter respectively, the third end of the first inverter is connected to the second end of the first switch, and the fourth end of the first inverter is grounded;

[0015] The second GPIO circuit includes a third inverter, a fourth inverter, a third switch, and a fourth switch; the output end of the third inverter is connected to the second multiplexing pin and the input end of the fourth inverter respectively, the third end of the third inverter is connected to the second end of the third switch, and the fourth end of the third inverter is grounded;

[0016] The XTAL circuit includes a fifth resistor Rf and a fifth inverter, wherein the first end of the fifth resistor Rf is respectively connected to the input end of the fifth inverter and the first multiplexing pin; the second end of the fifth resistor Rf is respectively connected to the output end of the fifth inverter and the second multiplexing pin.

[0017] As an embodiment of the present invention, the voltage clamping circuit includes a first voltage clamping unit and a second voltage clamping unit, and the first voltage clamping unit and the second voltage clamping unit are respectively connected to the input end of the XTAL circuit;

[0018] The first voltage clamping unit includes a fifth switch, a first resistor, and a first component group, the first component group including at least one first component; a first end of the fifth switch is connected to a power supply voltage, a second end of the fifth switch is connected to a first end of the first resistor, a second end of the first resistor is connected to the first component group, and the first component group is connected to the first multiplexed pin;

[0019] The second voltage clamping unit includes a second element group, a second resistor, and a sixth switch, and the second element group includes at least one second element; the first end of the second element group is connected to the first multiplexed pin, the second end of the second element group is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the sixth switch, and the second end of the sixth switch is grounded.

[0020] As an embodiment of the present invention, the first element is a MOS tube or a diode, and the first elements are connected in sequence; when the first element is an NMOS tube, the gate and drain of each NMOS tube are connected; when the first element is a PMOS tube, the gate and drain of each PMOS tube are connected;

[0021] The second element is a MOS tube or a diode, and each second element is connected in sequence; when the second element is an NMOS tube, the gate and drain of each NMOS tube are connected; when the second element is a PMOS tube, the gate and drain of each PMOS tube are connected.

[0022] As an embodiment of the present invention, the first element is a first NMOS transistor, and the first NMOS transistors are sequentially labeled as the first-NMOS transistor M11, the second-NMOS transistor M12, the third-NMOS transistor M13, ..., the first-n NMOS transistor M1n, where n is an integer greater than or equal to 2; the second end of the first-first resistor is connected to the gate and drain of the first-NMOS transistor M11; the source of the first-NMOS transistor M11 is connected to the gate and source of the first-second NMOS transistor; the drain of the NMOS transistor M1(i-1) is connected to the gate and drain of the NMOS transistor M1i, where i is an integer between 2 and n; and the source of the first-n NMOS transistor M1n is connected to the first multiplexing pin;

[0023] The second elements are second NMOS transistors, which are sequentially labeled as a second-first NMOS transistor M21, a second-second NMOS transistor M22, a second-third NMOS transistor M23, ..., a second-mth NMOS transistor M2m, where m is an integer greater than or equal to 2; the drain of the first nNMOS transistor M1n is connected to the gate and source of the second-first NMOS transistor M21; the drain of the NMOS transistor M1(j-1) is connected to the gate and source of the NMOS transistor M1j, where j is an integer between 2 and m; and the drain of the second-mth NMOS transistor M1m is connected to the first end of the second-first resistor.

[0024] As an embodiment of the present invention, the first element is a first PMOS transistor, and the first PMOS transistors are sequentially labeled as the first-PMOS transistor M11, the first-second PMOS transistor M12, the first-third PMOS transistor M13, ..., the first-n PMOS transistor M1n, where n is an integer greater than or equal to 2; the second end of the first resistor is connected to the source of the first-PMOS transistor M11; the drain of the first-PMOS transistor M11 is respectively connected to the gate of the first-PMOS transistor M11 and the source of the first-second PMOS transistor; the drain of the PMOS transistor M1(i-1) is respectively connected to the gate of the PMOS transistor M1(i-1) and the source of the PMOS transistor M1i, where i is an integer between 2 and n; the drain of the first-n PMOS transistor M1n is respectively connected to the gate of the first-n PMOS transistor M1n and the first multiplexing pin;

[0025] The second element is a second PMOS transistor, and the second PMOS transistors are sequentially labeled as a second-first PMOS transistor M21, a second-second PMOS transistor M22, a second-third PMOS transistor M23, ..., a second-mth PMOS transistor M2m, where m is an integer greater than or equal to 2; the source of the first nPMOS transistor M1n is connected to the first multiplexed pin; the drain of the PMOS transistor M1(j-1) is respectively connected to the gate of the PMOS transistor M1(j-1) and the source of the PMOS transistor M1j; and the drain of the second-mth PMOS transistor M1m is respectively connected to the gate of the second-mth PMOS transistor M1m and the first end of the second-first resistor.

[0026] As an embodiment of the present invention, the first element is a first diode, and the second element is a second diode;

[0027] The first diodes are labeled as diode 1-1 D11, diode 1-2 D12, diode 1-3 D13, ..., diode 1-n D1n. The second end of the first resistor is connected to the anode of diode 1-1 D11, and the anode of diode D1(i-1) is connected to the cathode of diode D1i. Where i is an integer between 2 and n. The cathode of diode D1n is connected to the first multiplexed pin.

[0028] The second diodes are labeled as the second-first diode D21, the second-second diode D22, the second-third diode D23, ..., the second-mth diode D2m in sequence; the anode of the second-first diode D21 is connected to the first multiplexed pin; the anode of the diode D1(j-1) is connected to the cathode of the diode D1j; where j is an integer between 2 and m; and the cathode of the diode D1m is connected to the first end of the second-first resistor.

[0029] As an embodiment of the present invention, the voltage clamping circuit includes a first voltage clamping unit and a second voltage clamping unit, and the first voltage clamping unit and the second voltage clamping unit are respectively connected to the input end of the XTAL circuit;

[0030] The first voltage clamping unit includes a fifth switch, a first resistor, and a first component group, the first component group including at least one first component; a first end of the fifth switch is connected to a power supply voltage, a second end of the fifth switch is connected to a first end of the first resistor, a second end of the first resistor is connected to the first component group, and the first component group is connected to the first multiplexed pin;

[0031] The second voltage clamping unit includes a second component group, a second resistor, and a sixth switch, wherein the second component group includes at least one second component; a first end of the second component group is connected to the first multiplexed pin, a second end of the second component group is connected to the first end of the second resistor, a second end of the second resistor is connected to the first end of the sixth switch, and a second end of the sixth switch is grounded;

[0032] When the multiplexing pin is configured as the XTAL function, the pin multiplexing circuit controls the first switch, the second switch, the third switch, and the fourth switch to be in the open state, and the fifth switch and the sixth switch to be in the closed state;

[0033] When the multiplexed pin is configured as a GPIO function, the pin multiplexing circuit controls the fifth switch and the sixth switch to be in an open state, and the first switch, the second switch, the third switch, and the fourth switch to be in a closed state.

[0034] The beneficial effect of the present invention is that the SoC chip pin multiplexing circuit proposed by the present invention can reduce the requirement on the output resistance when the multiplexed pin is in the off state, thereby increasing the frequency of GPIO operation.

[0035] The utility model is not only applicable to applications when XTAL and GPIO multiplex pins, but also can be used when XTAL and other circuits share pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a circuit diagram for reusing pins on an existing SoC chip.

[0037] Figure 2This is the equivalent circuit diagram of the XTAL input pin of the existing SoC chip.

[0038] Figure 3 This is a circuit diagram of a SoC chip pin multiplexing circuit in one embodiment of the present invention.

[0039] Figure 4 a is a circuit diagram of a voltage clamping circuit in one embodiment of the present invention.

[0040] Figure 4 b is a circuit diagram of a voltage clamping circuit in an embodiment of the present invention.

[0041] Figure 4 c is a circuit diagram of a voltage clamping circuit in an embodiment of the present invention.

[0042] Figure 5 This is a circuit diagram of a SoC chip pin multiplexing circuit in one embodiment of the present invention. DETAILED DESCRIPTION

[0043] The preferred embodiments of the present utility model are described in detail below with reference to the accompanying drawings.

[0044] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0045] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar existing technical means and some technical features of the embodiments are interchangeable and fall within the scope of the description and protection of the present invention.

[0046] The description of the steps in each embodiment in the specification is only for the convenience of explanation, and the implementation method of this application is not limited by the order of implementation of the steps.

[0047] The term "connection" as used in this specification includes both direct connection and indirect connection, such as connection through active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices that are well known to those skilled in the art and can achieve the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.

[0048] The utility model discloses a SoC chip pin multiplexing circuit. Figure 3 、 Figure 5 This is a circuit diagram of a SoC chip pin multiplexing circuit in one embodiment of the present invention; please refer to Figure 3 、 Figure 5The SoC chip has a first multiplexing pin 11 and a second multiplexing pin 12. The pin multiplexing circuit includes a first GPIO circuit 1, a second GPIO circuit 2, an XTAL circuit 3, and a voltage clamp circuit 4. The first multiplexing pin 11 is connected to the input terminals of the first GPIO circuit 1 and the XTAL circuit 3, respectively. The second multiplexing pin 12 is connected to the output terminals of the second GPIO circuit 2 and the XTAL circuit 3, respectively.

[0049] like Figure 3 、 Figure 5 As shown, in one embodiment of the present invention, the first GPIO circuit 1 includes a first inverter, a second inverter, a first switch and a second switch; the output end of the first inverter is respectively connected to the first multiplexing pin and the input end of the second inverter, the third end of the first inverter is connected to the second end of the first switch, and the fourth end of the first inverter is grounded. The second GPIO circuit includes a third inverter, a fourth inverter, a third switch and a fourth switch; the output end of the third inverter is respectively connected to the second multiplexing pin and the input end of the fourth inverter, the third end of the third inverter is connected to the second end of the third switch, and the fourth end of the third inverter is grounded. The XTAL circuit includes a fifth resistor Rf and a fifth inverter, the first end of the fifth resistor Rf is respectively connected to the input end of the fifth inverter and the first multiplexing pin; the second end of the fifth resistor Rf is respectively connected to the output end of the fifth inverter and the second multiplexing pin.

[0050] In one embodiment of the present invention, the voltage clamping circuit includes a first voltage clamping unit and a second voltage clamping unit, the first voltage clamping unit and the second voltage clamping unit being respectively connected to the input end of the XTAL circuit. The first voltage clamping unit includes a fifth switch, a first resistor, and a first element group, the first element group including at least one first element; the first end of the fifth switch is connected to the power supply voltage, the second end of the fifth switch is connected to the first end of the first resistor, the second end of the first resistor is connected to the first element group, and the first element group is connected to the first multiplexing pin. The second voltage clamping unit includes a second element group, a second resistor, and a sixth switch, the second element group including at least one second element; the first end of the second element group is connected to the first multiplexing pin, the second end of the second element group is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the sixth switch, and the second end of the sixth switch is grounded.

[0051] In one use scenario of the present invention, when the multiplexed pin of the SoC chip is configured as an XTAL function, the voltage clamping circuit 4 is connected to the first multiplexed pin 11 to clamp the voltage of the first multiplexed pin 11 to a set voltage. When the multiplexed pin of the SoC chip is configured as a GPIO function, the voltage clamping circuit 4 is disconnected from the first multiplexed pin 11 without affecting the operation of the first GPIO circuit 1 and the second GPIO circuit 2.

[0052] When the multiplexed pin is configured as the XTAL function, the pin multiplexing circuit controls the first switch, the second switch, the third switch, and the fourth switch to be in the open state, and the fifth switch and the sixth switch to be in the closed state; when the multiplexed pin is configured as the GPIO function, the pin multiplexing circuit controls the fifth switch and the sixth switch to be in the open state, and the first switch, the second switch, the third switch, and the fourth switch to be in the closed state.

[0053] The first element may be a MOS tube or a diode, and each first element is connected in sequence; when the first element is an NMOS tube, the gate and drain of each NMOS tube are connected; when the first element is a PMOS tube, the gate and drain of each PMOS tube are connected; the second element may be a MOS tube or a diode, and each second element is connected in sequence; when the second element is an NMOS tube, the gate and drain of each NMOS tube are connected; when the second element is a PMOS tube, the gate and drain of each PMOS tube are connected.

[0054] Figure 4 a is a circuit diagram of a voltage clamping circuit in one embodiment of the present invention; please refer to Figure 4 a. In one embodiment of the present invention, the first component is a first NMOS transistor, and the first NMOS transistors are sequentially labeled as the first-NMOS transistor M11, the second-NMOS transistor M12, the third-NMOS transistor M13, ..., the n-th NMOS transistor M1n, where n is an integer greater than or equal to 2; the second end of the first-first resistor is connected to the gate and drain of the first-NMOS transistor M11; the source of the first-NMOS transistor M11 is connected to the gate and source of the second-NMOS transistor; the drain of the NMOS transistor M1(i-1) is connected to the gate and drain of the NMOS transistor M1i, where i is an integer between 2 and n; and the source of the n-th NMOS transistor M1n is connected to the first multiplexed pin.

[0055] The second elements are second NMOS transistors, which are sequentially labeled as a second-first NMOS transistor M21, a second-second NMOS transistor M22, a second-third NMOS transistor M23, ..., a second-mth NMOS transistor M2m, where m is an integer greater than or equal to 2; the drain of the first nNMOS transistor M1n is connected to the gate and source of the second-first NMOS transistor M21; the drain of the NMOS transistor M1(j-1) is connected to the gate and source of the NMOS transistor M1j, where j is an integer between 2 and m; and the drain of the second-mth NMOS transistor M1m is connected to the first end of the second-first resistor.

[0056] Figure 4 b is a circuit diagram of a voltage clamping circuit in an embodiment of the present invention; please refer to Figure 4b. In one embodiment of the present invention, as an implementation manner of the present invention, the first component is a first PMOS transistor, and the first PMOS transistors are sequentially labeled as the first-PMOS transistor M11, the first-second PMOS transistor M12, the first-third PMOS transistor M13, ..., the first-nPMOS transistor M1n, where n is an integer greater than or equal to 2; the second end of the first-first resistor is connected to the source of the first-first PMOS transistor M11; the drain of the first-first PMOS transistor M11 is respectively connected to the gate of the first-first PMOS transistor M11 and the source of the first-second PMOS transistor; the drain of the PMOS transistor M1(i-1) is respectively connected to the gate of the PMOS transistor M1(i-1) and the source of the PMOS transistor M1i, where i is an integer between 2 and n; and the drain of the first-n PMOS transistor M1n is respectively connected to the gate of the first-n PMOS transistor M1n and the first multiplexing pin.

[0057] The second element is a second PMOS transistor, and the second PMOS transistors are sequentially labeled as a second-first PMOS transistor M21, a second-second PMOS transistor M22, a second-third PMOS transistor M23, ..., a second-mth PMOS transistor M2m, where m is an integer greater than or equal to 2; the source of the first nPMOS transistor M1n is connected to the first multiplexed pin; the drain of the PMOS transistor M1(j-1) is respectively connected to the gate of the PMOS transistor M1(j-1) and the source of the PMOS transistor M1j; and the drain of the second-mth PMOS transistor M1m is respectively connected to the gate of the second-mth PMOS transistor M1m and the first end of the second-first resistor.

[0058] Figure 4 c is a circuit diagram of a voltage clamping circuit in an embodiment of the present invention; please refer to Figure 4 c. In one embodiment of the present invention, the first component is a first diode, and the second component is a second diode. The first diodes are sequentially labeled as diode D11, diode D12, diode D13, ..., diode D1n. The second end of the first resistor is connected to the anode of diode D11, and the anode of diode D1(i-1) is connected to the cathode of diode D1i. Where i is an integer between 2 and n, the cathode of diode D1n is connected to the first multiplexed pin.

[0059] The second diodes are labeled as the second-first diode D21, the second-second diode D22, the second-third diode D23, ..., the second-mth diode D2m in sequence; the anode of the second-first diode D21 is connected to the first multiplexed pin; the anode of the diode D1(j-1) is connected to the cathode of the diode D1j; where j is an integer between 2 and m; and the cathode of the diode D1m is connected to the first end of the second-first resistor.

[0060] The present invention further discloses a pin multiplexing control method for the SoC chip pin multiplexing circuit. The pin multiplexing control method includes:

[0061] When the multiplexed pin of the SoC chip is configured as an XTAL function, the voltage clamping circuit is connected to the first multiplexed pin to clamp the voltage of the first multiplexed pin to a set voltage;

[0062] When the multiplexed pin of the SoC chip is configured as a GPIO function, the voltage clamping circuit is disconnected from the first multiplexed pin without affecting the operation of the first GPIO circuit and the second GPIO circuit.

[0063] The utility model provides a circuit which can reduce the requirement for the open-circuit resistance of SW1 / SW2, so that the GPIO pin multiplexed with the XTAL pin can operate at a higher frequency.

[0064] like Figure 3 As shown in the figure, a new voltage clamp module (Vc l amp) is added at the XTAL input Xtal_in, whose characteristics are as follows: when the Vxtal_in voltage is between vth l and vthh, the Vc l amp output impedance is much larger than Rf, R1 and R2; when the Vxtal_in voltage is greater than vthh, or less than vth l, the Vc l amp output impedance is much smaller than Rf, R1 and R2. When the Vxtal_in voltage is greater than vthh, the Vc L amp's output impedance is much smaller than Rf, R1, and R2, so the voltage at Vxtal_in is primarily determined by Vc L amp. At this point, Vxtal_in is only slightly higher than vthh, denoted as vthh2. When the Vxtal_in voltage is less than vthl, the Vc L amp's output impedance is much smaller than Rf, R1, and R2, so the voltage at Vxtal_in is primarily determined by Vc L amp. At this point, Vxtal_in is only slightly lower than vthl, denoted as vthl2. Due to this Vc L amp characteristic, the open-circuit resistance of SW1 and SW2 can be smaller, increasing the GPIO operating frequency. At the same time, the voltage at Xtal_in is limited between vthl2 and vthh2, allowing the inverter driving XTAL to provide a larger gm.

[0065] like Figure 4 a. Figure 4 b. Figure 4Figure c shows several Vclamp circuits that meet the above characteristics; the circuit shown in Figure a is used as an example for illustration. The upper half of the circuit consists of resistor R11 and multiple NMOS transistors M11…M1n, while the lower half consists of resistor R21 and M21…M2n. The gate and drain of the NMOS transistors in the circuit are connected together, forming a diode connection. The gate-source voltage difference of M11 is Vgs_M11, and the gate-source voltage difference of M21 is Vgs_M21. The output voltage is clamped between Vgs_M21+…+Vgs_M2n and Vdd-Vgs_M12-…-Vgs_M2n. The number of cascaded NMOS transistors connected in diode fashion in the upper half of the circuit determines the minimum output voltage; the number of cascaded NMOS transistors connected in diode fashion in the lower half of the circuit determines the maximum output voltage. By properly selecting the number of cascaded transistors M11…M1n and M21…M2n and the device sizes, Vgs_M21+…+Vgs_M2n>Vdd-Vgs_M12-…-Vgs_M2n. Resistors R11 and R21 prevent the Vclamp output impedance from becoming too low, which would disrupt the XTAL's oscillation conditions. Figure 4 (b) and (c) show alternative implementations of circuit (a), replacing the diode-connected NMOS with a diode-connected PMOS and diode, respectively. In addition to implementations (b) and (c), a diode-connected BJT can also be used instead of a diode-connected NMOS, or a combination of these devices can be used in a single circuit.

[0066] like Figure 5 The figure shows an implementation of the XTAL and GPIO pin multiplexing proposed by the present invention. The following describes its working status:

[0067] When the pin is configured as XTAL function, SW1-SW4 are in the open state and SW5 / SW6 are in the closed state:

[0068] Under different voltages, temperatures, and process conditions, the voltage at Xtal_in ranges from Vdd - Vgs_M12 - ... - Vgs_M2n to Vgs_M21 + ... + Vgs_M2n. At this point, M11 ... M1n, M21 ... M2n are all off, and the equivalent circuit structure is the same as Figure 1. By selecting Vgs_M12 ... Vgs_M1n, Vgs_M21 ... Vgs_M2n, the inverter's gm can be increased.

[0069] Under different voltages, temperatures, and process conditions, when SW1's on-resistance is very low, without a Vcl amp circuit, the voltage at Xtal_in is pulled up to close to Vdd, and the inverter in XTAL cannot provide negative resistance. With a Vcl amp circuit, since M21...M2n are all diode-connected, the Xtal_in voltage is clamped to a voltage slightly higher than Vgs_M21+...+Vgs_M2n. This increases the inverter's gm, allowing it to provide sufficient negative resistance.

[0070] Under different voltages, temperatures, and process conditions, when the on-resistance of SW2 is very small, without a Vcl amp circuit, the voltage at Xtal_in is pulled down to near zero, and the inverter in XTAL cannot provide negative resistance. With a Vcl amp circuit, since M11…M1n are all diode-connected, the Xtal_in voltage is clamped to a voltage slightly lower than Vdd-Vgs_M12-…-Vgs_M2n. This increases the inverter gm, allowing it to provide sufficient negative resistance.

[0071] When the pin is configured as a GPIO, SW5 / SW6 is configured to be disconnected. At this time, the impact of the Vcl amp circuit on the GPIO operation is only to increase some parasitic capacitance, which will not affect the GPIO operation.

[0072] In summary, the SoC chip pin multiplexing circuit proposed in the present invention can reduce the requirement for the output resistance of the multiplexed pin when it is in the off state, thereby increasing the frequency of GPIO operation.

[0073] The utility model is not only applicable to applications when XTAL and GPIO multiplex pins, but also can be used when XTAL and other circuits share pins.

[0074] It should be noted that the present application can be implemented in software and / or a combination of software and hardware; for example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium; for example, a RAM memory, a magnetic or optical drive, or a floppy disk and the like. In addition, some steps or functions of the present application can be implemented in hardware; for example, as a circuit that cooperates with a processor to perform various steps or functions.

[0075] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The description and application of the present invention here are illustrative and are not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the embodiments may not be reflected in the embodiments due to interference from various factors, and the description of the effects or advantages is not used to limit the embodiments. Variations and changes to the embodiments disclosed here are possible, and replacements and various equivalent components of the embodiments are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that, without departing from the spirit or essential characteristics of the present invention, the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts. Other variations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A SoC chip pin multiplexing circuit, characterized in that: The SoC chip is provided with a first multiplexing pin and a second multiplexing pin; the pin multiplexing circuit includes: a first GPIO circuit, a second GPIO circuit, an XTAL circuit and a voltage clamping circuit; The first multiplexed pin is connected to the input end of the first GPIO circuit and the XTAL circuit respectively, and the second multiplexed pin is connected to the output end of the second GPIO circuit and the XTAL circuit respectively; The first GPIO circuit includes a first inverter, a second inverter, a first switch, and a second switch; the output end of the first inverter is connected to the first multiplexing pin and the input end of the second inverter respectively, the third end of the first inverter is connected to the second end of the first switch, and the fourth end of the first inverter is grounded; The second GPIO circuit includes a third inverter, a fourth inverter, a third switch, and a fourth switch; the output end of the third inverter is connected to the second multiplexing pin and the input end of the fourth inverter respectively, the third end of the third inverter is connected to the second end of the third switch, and the fourth end of the third inverter is grounded; The XTAL circuit includes a fifth resistor Rf and a fifth inverter, wherein the first end of the fifth resistor Rf is respectively connected to the input end of the fifth inverter and the first multiplexing pin; the second end of the fifth resistor Rf is respectively connected to the output end of the fifth inverter and the second multiplexing pin.

2. The SoC chip pin multiplexing circuit according to claim 1, characterized in that: The voltage clamping circuit includes a first voltage clamping unit and a second voltage clamping unit, and the first voltage clamping unit and the second voltage clamping unit are respectively connected to the input end of the XTAL circuit; The first voltage clamping unit includes a fifth switch, a first resistor, and a first component group, the first component group including at least one first component; a first end of the fifth switch is connected to a power supply voltage, a second end of the fifth switch is connected to a first end of the first resistor, a second end of the first resistor is connected to the first component group, and the first component group is connected to the first multiplexed pin; The second voltage clamping unit includes a second element group, a second resistor, and a sixth switch, and the second element group includes at least one second element; the first end of the second element group is connected to the first multiplexed pin, the second end of the second element group is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the sixth switch, and the second end of the sixth switch is grounded.

3. The SoC chip pin multiplexing circuit according to claim 2, characterized in that: The first element is a MOS tube or a diode, and each first element is connected in sequence; when the first element is an NMOS tube, the gate and drain of each NMOS tube are connected; when the first element is a PMOS tube, the gate and drain of each PMOS tube are connected.

4. The SoC chip pin multiplexing circuit according to claim 3, characterized in that: The first element is a first NMOS transistor, and the first NMOS transistors are sequentially labeled as the first-NMOS transistor M11, the second-NMOS transistor M12, the third-NMOS transistor M13, ..., the n-th NMOS transistor M1n, where n is an integer greater than or equal to 2; the second end of the first-first resistor is connected to the gate and drain of the first-NMOS transistor M11; the source of the first-NMOS transistor M11 is connected to the gate and source of the second-NMOS transistor; the drain of the NMOS transistor M1(i-1) is connected to the gate and drain of the NMOS transistor M1i, where i is an integer between 2 and n; and the source of the n-th NMOS transistor M1n is connected to the first multiplexed pin.

5. The SoC chip pin multiplexing circuit according to claim 2, characterized in that: The second element is a MOS tube or a diode, and each second element is connected in sequence; when the second element is an NMOS tube, the gate and drain of each NMOS tube are connected; when the second element is a PMOS tube, the gate and drain of each PMOS tube are connected.

6. The SoC chip pin multiplexing circuit according to claim 5, characterized in that: The second elements are second NMOS transistors, and the second NMOS transistors are sequentially labeled as a 2nd-1 NMOS transistor M21, a 2nd-2 NMOS transistor M22, a 2nd-3 NMOS transistor M23, ..., a 2nd-mth NMOS transistor M2m, where m is an integer greater than or equal to 2; the drain of the 1st-nth NMOS transistor M1n is connected to the gate and source of the 2nd-1st NMOS transistor M21; the drain of the NMOS transistor M1(j-1) is connected to the gate and source of the NMOS transistor M1j, where j is an integer between 2 and m; and the drain of the 2nd-mth NMOS transistor M1m is connected to the first end of the 2nd-1st resistor.

7. The SoC chip pin multiplexing circuit according to claim 2, characterized in that: The first element is a first PMOS transistor, and the first PMOS transistors are sequentially labeled as the first-PMOS transistor M11, the second-PMOS transistor M12, the third-PMOS transistor M13, ..., the first-n PMOS transistor M1n, where n is an integer greater than or equal to 2; the second end of the first-resistor is connected to the source of the first-PMOS transistor M11; the drain of the first-PMOS transistor M11 is respectively connected to the gate of the first-PMOS transistor M11 and the source of the first-second PMOS transistor; the drain of the PMOS transistor M1(i-1) is respectively connected to the gate of the PMOS transistor M1(i-1) and the source of the PMOS transistor M1i, where i is an integer between 2 and n; the drain of the first-n PMOS transistor M1n is respectively connected to the gate of the first-nPMOS transistor M1n and the first multiplexing pin; The second element is a second PMOS transistor, and the second PMOS transistors are sequentially labeled as a second-first PMOS transistor M21, a second-second PMOS transistor M22, a second-third PMOS transistor M23, ..., a second-m PMOS transistor M2m, where m is an integer greater than or equal to 2; the source of the first-n PMOS transistor M1n is connected to the first multiplexed pin; the drain of the PMOS transistor M1(j-1) is respectively connected to the gate of the PMOS transistor M1(j-1) and the source of the PMOS transistor M1j; and the drain of the second-m PMOS transistor M1m is respectively connected to the gate of the second-m PMOS transistor M1m and the first end of the second-first resistor.

8. The SoC chip pin multiplexing circuit according to claim 2, characterized in that: The first element is a first diode, and the second element is a second diode; The first diodes are labeled as diode 1-1 D11, diode 1-2 D12, diode 1-3 D13, ..., diode 1-n D1n. The second end of the first resistor is connected to the anode of diode 1-1 D11, and the anode of diode D1(i-1) is connected to the cathode of diode D1i. Where i is an integer between 2 and n. The cathode of diode D1n is connected to the first multiplexed pin. The second diodes are labeled as the second-first diode D21, the second-second diode D22, the second-third diode D23, ..., the second-mth diode D2m in sequence; the anode of the second-first diode D21 is connected to the first multiplexed pin; the anode of the diode D1(j-1) is connected to the cathode of the diode D1j; where j is an integer between 2 and m; and the cathode of the diode D1m is connected to the first end of the second-first resistor.

9. The SoC chip pin multiplexing circuit according to claim 1, characterized in that: The voltage clamping circuit includes a first voltage clamping unit and a second voltage clamping unit, and the first voltage clamping unit and the second voltage clamping unit are respectively connected to the input end of the XTAL circuit; The first voltage clamping unit includes a fifth switch, a first resistor, and a first component group, the first component group including at least one first component; a first end of the fifth switch is connected to a power supply voltage, a second end of the fifth switch is connected to a first end of the first resistor, a second end of the first resistor is connected to the first component group, and the first component group is connected to the first multiplexed pin; The second voltage clamping unit includes a second component group, a second resistor, and a sixth switch, wherein the second component group includes at least one second component; a first end of the second component group is connected to the first multiplexed pin, a second end of the second component group is connected to the first end of the second resistor, a second end of the second resistor is connected to the first end of the sixth switch, and a second end of the sixth switch is grounded; When the multiplexing pin is configured as the XTAL function, the pin multiplexing circuit controls the first switch, the second switch, the third switch, and the fourth switch to be in the open state, and the fifth switch and the sixth switch to be in the closed state; When the multiplexed pin is configured as a GPIO function, the pin multiplexing circuit controls the fifth switch and the sixth switch to be in an open state, and the first switch, the second switch, the third switch, and the fourth switch to be in a closed state.

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