Solar cell and photovoltaic module
By providing a tunneled oxide layer passivation contact structure between the second surface of the silicon substrate of the solar cell, the light absorption effect problem caused by the thickness of the doped polysilicon layer is solved, and the efficiency of the battery is improved.
Patent Information
- Application Number
- CN202422209323.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2025-08-08
- Estimated Expiration
- 2034-09-09
AI Technical Summary
The doped polysilicon layer of the existing TOPCon batteries is consistent and thick, resulting in strong light absorption effect on the back, poor long-band response, serious current loss, and reduced battery efficiency.
A plurality of tunneling oxide layer passivation contact structures are arranged at intervals between the second surface of the silicon substrate of the solar cell, and a tunneling oxide layer passivation contact structure is arranged only in the metal area, combining the back passivation layer and the anti-reflection layer to reduce the area of the doped polysilicon layer.
By reducing the light absorption effect of the doped polysilicon layer, the current loss is reduced, and the efficiency of the battery is improved.
Smart Images
Figure CN223207457U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of photovoltaics, in particular to a solar cell and a photovoltaic module. Background Art
[0002] With the continuous development of solar cell technology, carrier-selective passivation contacts have become one of the key approaches to improving solar cell efficiency. This is the core process for tunnel oxide passivated contact (TOPCon) cells. When preparing TOPCon cells, a tunnel oxide layer and a doped polysilicon layer are typically formed on the back of the cell. This not only provides a good interfacial passivation contact on the back of the cell, but also forms an electron-selective tunneling structure on the back of the cell, thereby improving cell performance.
[0003] However, the thickness of the doped polysilicon layer of the current TOPCon cell is consistent and relatively thick, which makes the doped polysilicon layer on the back have a strong light absorption effect, resulting in poor long-waveband response and current loss on the back of the cell, thereby reducing the efficiency of the TOPCon cell. Utility Model Content
[0004] In view of this, an object of the present invention is to provide a solar cell and a photovoltaic module that can improve the efficiency of the cell.
[0005] The utility model provides a solar cell, comprising:
[0006] A silicon substrate, comprising a first surface and a second surface disposed opposite to each other, wherein the first surface is a light-receiving surface and the second surface is a backlight surface;
[0007] A plurality of tunneling oxide layer passivation contact structures are arranged at intervals on the second surface, each tunneling oxide layer passivation contact structure is used to connect to a back electrode;
[0008] Each of the tunneling oxide layer passivation contact structures includes a tunneling oxide layer and a doped polysilicon layer that are stacked; wherein the tunneling oxide layer is close to the second surface.
[0009] In a possible implementation manner, the thickness of the tunnel oxide layer passivation contact structure is 80 nm to 150 nm.
[0010] In a possible implementation manner, a back passivation layer is further deposited on the second surface, and the back passivation layer wraps the tunnel oxide layer passivation contact structure.
[0011] In a possible implementation manner, the back passivation layer is an aluminum oxide layer.
[0012] In a possible implementation, the second surface is formed by polishing the back surface of the silicon substrate, and a portion of the second surface where the tunneling oxide layer passivation contact structure is not provided is recessed toward the first surface to form a groove.
[0013] In a possible implementation manner, the depth of the groove is 2 μm to 4 μm.
[0014] In a possible implementation manner, a back anti-reflection layer is further provided on the side of the back passivation layer facing away from the second surface.
[0015] In a possible implementation, the back anti-reflection layer is a silicon nitride layer.
[0016] In a possible implementation manner, a boron diffusion layer, a front passivation layer, and a front anti-reflection layer are sequentially stacked on the first surface.
[0017] The utility model provides a photovoltaic assembly, comprising the solar cell described in any one of the possible embodiments above.
[0018] The solar cell and photovoltaic module provided by the embodiments of the present invention have multiple tunneling oxide layer passivation contact structures arranged at intervals on the second surface of the silicon substrate, and each tunneling oxide layer passivation contact structure is used to connect to a back electrode. That is, the tunneling oxide layer passivation contact structure is only provided in the metal area, while it is not provided in other parts of the second surface. This can reduce the area of the doped polysilicon layer, thereby reducing the light absorption effect of the doped polysilicon layer, which is beneficial to reducing current loss and thus beneficial to improving the efficiency of the battery.
[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 A schematic structural diagram of a solar cell provided by an embodiment of the present utility model is shown;
[0022] Figure 2 A schematic structural diagram of another solar cell provided by an embodiment of the present utility model is shown;
[0023] Figure 3 A schematic diagram of a silicon substrate after texturing provided by an embodiment of the present utility model is shown;
[0024] Figure 4 A schematic diagram of a silicon substrate after boron diffusion treatment provided by an embodiment of the present invention is shown;
[0025] Figure 5 A schematic diagram showing a backside polished silicon substrate provided by an embodiment of the present invention is shown;
[0026] Figure 6 A schematic diagram showing a silicon substrate provided by an embodiment of the present invention after a tunneling oxide layer and an amorphous silicon layer are deposited on the back side thereof;
[0027] Figure 7 A schematic diagram showing a method of selective crystallization and selective oxidation of an amorphous silicon layer provided by an embodiment of the present utility model is shown;
[0028] Figure 8 A schematic diagram of a silicon substrate after alkaline etching provided by an embodiment of the present utility model is shown;
[0029] Figure 9 A schematic diagram of another silicon substrate after alkaline etching provided by an embodiment of the present utility model is shown;
[0030] Figure 10 A schematic diagram showing a silicon substrate provided by an embodiment of the present invention after a passivation film and an anti-reflection film are deposited;
[0031] Figure 11 A principle block diagram of a photovoltaic module provided by an embodiment of the present utility model is shown.
[0032] Description of reference numerals:
[0033] Solar cell 10; silicon substrate 1; tunneling oxide passivation contact structure 2; tunneling oxide layer 21; doped amorphous silicon layer 22a; doped polycrystalline silicon layer 22; back electrode 3; back passivation layer 4; back anti-reflection layer 5; boron diffusion layer 7; front passivation layer 8; front anti-reflection layer 9; front electrode 6; first surface a; second surface b; groove c; crystallized region d; oxidized region e; photovoltaic module 100. DETAILED DESCRIPTION
[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The components of the embodiments of the present invention generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the utility model for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.
[0035] Research has found that the thickness of the doped polysilicon layer of the current TOPCon cell is consistent and relatively thick, which makes the doped polysilicon layer on the back have a strong light absorption effect, which in turn leads to poor long-waveband response and current loss on the back of the cell, thereby reducing the efficiency of the TOPCon cell.
[0036] Based on the above research, the present invention provides a solar cell, see Figure 1 The figure shows a schematic diagram of the structure of a solar cell provided by an embodiment of the present invention. The solar cell 10 comprises a silicon substrate 1, which comprises a first surface a and a second surface b disposed opposite to each other, wherein the first surface a is a light-receiving surface and the second surface b is a light-receiving surface. A plurality of tunneling oxide passivation contact structures 2 are spaced apart on the second surface b, each tunneling oxide passivation contact structure 2 being configured to connect to a back electrode 3. Each tunneling oxide passivation contact structure 2 comprises a stacked tunneling oxide layer 21 and a doped polysilicon layer 22, wherein the tunneling oxide layer 21 is adjacent to the second surface b.
[0037] Exemplarily, the silicon substrate 1 is an N-type silicon substrate, and the doped polysilicon layer 22 is a phosphorus-doped polysilicon layer.
[0038] In the embodiment of the present disclosure, the thickness of the tunnel oxide layer passivation contact structure 2 is 80 nm to 150 nm, where nm represents nanometers. Of course, in other embodiments, the thickness of the tunnel oxide layer passivation contact structure 2 can be thicker or thinner, which is not specifically limited here.
[0039] Furthermore, a back passivation layer 4 is deposited on the second surface b, and the back passivation layer 4 encapsulates the tunnel oxide layer passivation contact structure 2. Optionally, the back passivation layer 4 is an aluminum oxide layer. In this way, the aluminum oxide layer not only achieves passivation but also provides anti-UVID (ultraviolet attenuation) performance.
[0040] In some embodiments, see Figure 2 As shown, the second surface b is formed by polishing the back side of the silicon substrate 1. The portion of the second surface b not provided with the tunneling oxide layer passivation contact structure 2 is recessed toward the first surface a to form a groove c. The depth of the groove c is 2 μm to 4 μm, where μm represents micrometers. Of course, in other embodiments, the depth of the groove c can be deeper or shallower, and this is not specifically limited here.
[0041] In the embodiment of the present invention, since the thickness of the tunneling oxide layer passivation contact structure 2 is at the nanometer level and the depth of the groove c is at the micrometer level, in the process of using laser to prepare local passivation contact, the damage caused by the laser to the battery cell is at the micrometer level. Therefore, alkaline etching is used to perform alkaline polishing on the laser-treated area and form a groove c with a depth of 2um-4um. This can not only remove the laser damage in the manufacturing process, but also increase the tower base of the laser-treated area to 1-3 times the original size during the alkaline etching process, making the surface smoother. This can also improve the passivation performance of aluminum oxide, thereby increasing the open circuit voltage of the battery.
[0042] Furthermore, a back anti-reflection layer 5 is provided on the side of the back passivation layer 4 facing away from the second surface b. Specifically, the back anti-reflection layer 5 is a silicon nitride layer.
[0043] In addition, a boron diffusion layer 7 , a front passivation layer 8 , and a front anti-reflection layer 9 are sequentially stacked on the first surface a. Furthermore, the solar cell 10 further includes a front electrode 6 .
[0044] The following is a detailed introduction to the method for manufacturing a solar cell provided by an embodiment of the present invention.
[0045] See also Figure 3 As shown, first, the front and back sides of the silicon substrate 1 can be double-sided textured. The textured front side is the first side a mentioned above. Specifically, the original N-type silicon substrate 1 can be immersed in a KOH or NaOH solution with a mass fraction of 1% to 3% at a temperature of 60°C to 85°C for 20 to 30 minutes to perform double-sided texture.
[0046] Then, the silicon substrate 1 after double-sided texturing is subjected to boron diffusion treatment, such as Figure 4 As shown, a boron diffusion layer 7 is obtained. Specifically, in this step, the silicon substrate 1 obtained after double-sided texturing can be loaded into a tubular low-pressure boron diffusion furnace to complete the front surface (front) boron diffusion doping process, with BCl3 being used as the boron diffusion source, the diffusion temperature being 900°C to 1100°C, the diffusion time being 2 hours to 3 hours, the diffusion square resistance being 150Ω / sq to 180Ω / sq, and the junction depth being 0.5um to 1um.
[0047] Then the back of the silicon substrate 1 obtained by texturing is polished. Figure 5 As shown, the second side b is obtained. The specific process may include the following:
[0048] First, a chain etching machine is used to perform single-sided HF cleaning on the N-type silicon substrate 1 to remove the BSG layer on the back and side of the N-type silicon substrate 1, while retaining the BSG layer on the front of the N-type silicon substrate 1. Then, a slot machine is used to perform alkaline polishing on the back of the N-type silicon substrate 1. Generally, a mixed solution of KOH and additives is used to polish the back surface. In this way, on the one hand, the boron doping layer that has spread to the back during the boron diffusion process is removed, thereby insulating the front and back surfaces. On the other hand, the polished surface is conducive to the deposition of a more uniform tunnel oxide layer and polysilicon layer.
[0049] Then, if Figure 6 As shown, a tunneling oxide layer 21 and a doped amorphous silicon layer 22a (in-situ phosphorus doping) are sequentially deposited on the second surface b. Specifically, a PECVD (Plasma Enhanced Chemical Vapor Deposition) device or a PVD (Physical Vapor Deposition) device can be used to deposit the tunneling oxide layer 21 and the phosphorus-doped amorphous silicon layer 22a on the second surface b at a temperature of 400°C to 500°C.
[0050] See also Figure 7 As shown, the doped amorphous silicon layer 22a is then subjected to regional selective laser crystallization treatment to obtain a crystallized region d, which is a metallized region. The width of the crystallized region d is 200um to 500um, the wavelength of the laser used is 193nm to 1300nm, the average power of the laser used is 15kw / cm2 to 50kw / cm2, and the process time is 5ms to 60s.
[0051] Here, it should be noted that after the amorphous silicon layer 22a is crystallized, it becomes the doped polysilicon layer 22. That is, the crystallized region d corresponds to the doped polysilicon layer 22.
[0052] The crystallized region d is then subjected to a region-selective laser oxidation treatment to obtain an oxidized region e. A SiOx thin film layer is formed on the surface of the crystallized phosphorus-doped polysilicon. This SiOx thin film layer is a mask layer, which is mainly used to protect the crystallized phosphorus-doped polysilicon layer during the alkaline etching process in the subsequent steps. The width of the oxidized region e is 200um to 500um. The wavelength of the laser used in this process is 193nm to 1300nm, the average power of the laser used is 2W to 15W, and the laser frequency used is 10kHz to 2000kHz.
[0053] Please also see Figure 8 and Figure 9 ,right Figure 7 The back surface of the processed result is subjected to alkali etching or alkali polishing to form a tunnel oxide passivation contact structure 2. Specifically, the alkali etching can be performed using a tank machine to remove the back phosphorus-doped amorphous silicon layer 22a and the surrounding phosphorus-doped amorphous silicon layer. The crystallized phosphorus-doped polysilicon layer 22 is not etched by the alkali because the surface is protected by the SiOx mask.
[0054] For example, a mixed solution of KOH and additives can be used to remove the amorphous silicon layer 22a; then, the N-type silicon substrate 1 is cleaned with HF using a tank machine to remove the tunneling oxide layer (made of SiOx) and BSG on the front side and the SiOx mask layer on the back side.
[0055] Here, it should be noted that during the alkali etching process, the second surface can be further etched to form Figure 9 The groove c shown in .
[0056] See also Figure 10 As shown, after obtaining the tunnel oxide layer passivation contact structure 2, a passivation film and an anti-reflection film can be sequentially deposited on both sides to obtain a front passivation layer 8, a back passivation layer 4, a front anti-reflection film 9, and a back anti-reflection film 5. The passivation film can play a passivation role, and the anti-reflection film plays an anti-reflection role.
[0057] Finally, a metallization sintering process is performed, and the front electrode 6 and the back electrode 3 are screen-printed on the front and back sides of the battery.
[0058] See also Figure 11 As shown, in some embodiments, the present invention further provides a photovoltaic assembly 100 , which may include the solar cell described in any of the above embodiments.
[0059] The solar cell 10 and photovoltaic module 100 provided by the embodiment of the present invention have multiple tunneling oxide layer passivation contact structures 2 arranged at intervals on the second surface b of the silicon substrate 1, and each tunneling oxide layer passivation contact structure 2 is used to connect to a back electrode 3. That is, the tunneling oxide layer passivation contact structure 2 is only provided in the metal area, while other parts of the second surface b are not provided. This can reduce the area of the doped polysilicon layer, thereby reducing the light absorption effect of the doped polysilicon layer, which is beneficial to reducing current loss and thus beneficial to improving the efficiency of the battery.
[0060] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.
[0061] The embodiments described above are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present invention.
[0062] In the description of the embodiments of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships typically placed when the disclosed product is in use. These terms are intended solely to facilitate the description of the present invention and simplify the description, and are not intended to indicate or imply that the electric photovoltaic assembly or component referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0063] It should also be noted that, in the description of this utility model, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.
[0064] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, intended to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can, within the technical scope disclosed by the present invention, modify or easily conceive of variations to the technical solutions described in the above-described embodiments, or substitute equivalent features for some of the technical features thereof. Such modifications, variations, or substitutions do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. They should all be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.
Claims
1. A solar cell, characterized in that: include: A silicon substrate, comprising a first surface and a second surface disposed opposite to each other, wherein the first surface is a light-receiving surface and the second surface is a backlight surface; A plurality of tunneling oxide layer passivation contact structures are arranged at intervals on the second surface, each tunneling oxide layer passivation contact structure is used to connect to a back electrode; Each of the tunneling oxide layer passivation contact structures includes a tunneling oxide layer and a doped polysilicon layer that are stacked; wherein the tunneling oxide layer is close to the second surface.
2. The solar cell according to claim 1, wherein The thickness of the tunnel oxide layer passivation contact structure is 80nm to 150nm.
3. The solar cell according to claim 1, wherein A back passivation layer is also deposited on the second surface, and the back passivation layer wraps the tunnel oxide layer passivation contact structure.
4. The solar cell according to claim 3, characterized in that The back passivation layer is an aluminum oxide layer.
5. The solar cell according to claim 1, wherein The second surface is formed by polishing the back surface of the silicon substrate, and a portion of the second surface where the tunneling oxide layer passivation contact structure is not provided is recessed toward the first surface to form a groove.
6. The solar cell according to claim 5, characterized in that The depth of the groove is 2 μm to 4 μm.
7. The solar cell according to claim 3, characterized in that A back anti-reflection layer is further provided on the side of the back passivation layer facing away from the second surface.
8. The solar cell according to claim 7, characterized in that The back anti-reflection layer is a silicon nitride layer.
9. The solar cell according to claim 1, wherein A boron diffusion layer, a front passivation layer and a front anti-reflection layer are sequentially stacked on the first surface.
10. A photovoltaic module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 9.