Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a plurality of repetitive units, and insertion columns are arranged between adjacent repetitive unit columns. The at least one repetitive unit comprises a plurality of circuit units, and the at least one circuit unit comprises a pixel driving circuit and a data signal line; the driving structure layer further comprises a first connecting line, a second connecting line, first constant-voltage wires and second constant-voltage wires, the first end of the first connecting line is connected with the data signal line, the second end of the first connecting line is connected with the second connecting line, the at least one second constant-voltage wire is connected with the at least one first constant-voltage wire, and the second constant-voltage wires are connected with the at least one second constant-voltage wire. A net-shaped communication structure for transmitting a constant-voltage signal is formed; and the second connecting line and the second constant-voltage routing line are arranged in the insertion column.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Currently, existing display substrates have problems such as a large border width. Utility Model Content

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the present disclosure is to provide a display substrate and a display device to overcome the problems of the existing display substrate such as the large border width.

[0006] On the one hand, the present disclosure provides a display substrate, comprising a driving structure layer arranged on a base; the driving structure layer comprises a plurality of repeating units forming a plurality of repeating unit rows and a plurality of repeating unit columns, and an insertion column is arranged between adjacent repeating unit columns; at least one repeating unit comprises a plurality of circuit units arranged in sequence along a first direction, at least one circuit unit comprises a pixel driving circuit and a data signal line extending along a second direction, the data signal line is connected to the pixel driving circuit, and the data signal line is configured to provide a data signal to the pixel driving circuit, and the first direction and the second direction intersect; the driving structure layer also comprises at least one first connecting line and at least one first constant voltage line extending along the first direction, and at least one second connecting line and at least one second constant voltage line extending along the second direction, the first end of the first connecting line is connected to the data signal line, the second end of the first connecting line is connected to the second connecting line, and at least one second constant voltage line is connected to at least one first constant voltage line to form a mesh connection structure for transmitting a constant voltage signal; the second connecting line and the second constant voltage line are arranged in the insertion column.

[0007] In an exemplary embodiment, at least one repeating unit includes three circuit units.

[0008] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor, a first transistor serving as a first initialization transistor, and a second transistor serving as a compensation transistor, the first transistor including at least a first gate electrode and a first active layer, the second transistor including at least a second gate electrode and a second active layer, the storage capacitor including a first plate and a second plate, the orthographic projection of the second plate on the substrate at least partially overlapping with the orthographic projection of the first plate on the substrate, the first plate being connected to the second region of the first active layer and the first region of the second active layer, and the second plate being connected to a first power line; at least one circuit unit further includes a shielding electrode connected to the second plate, the orthographic projection of the shielding electrode on the substrate at least partially overlapping with the orthographic projection of the first active layer between the two gate electrodes of the first transistor on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlapping with the orthographic projection of the second active layer between the two gate electrodes of the second transistor on the substrate; and the orthographic projection of at least one second connecting line on the substrate at least partially overlapping with the orthographic projection of the shielding electrode on the substrate.

[0009] In an exemplary embodiment, the pixel driving circuit further includes a third transistor serving as a driving transistor and a fourth transistor serving as a data writing transistor, the third transistor including at least a third active layer, the fourth transistor including at least a fourth active layer, the first region of the third active layer being connected to the second region of the fourth active layer; at least one circuit unit further includes a compensation electrode connected to the second electrode plate, an orthographic projection of the compensation electrode on the substrate at least partially overlapping with an orthographic projection of a connection region between the first region of the third active layer and the second region of the fourth active layer on the substrate.

[0010] In an exemplary embodiment, the pixel driving circuit further includes a fourth transistor serving as a data writing transistor, the second gate electrode being connected to the first scanning signal line extending along the first direction, the gate electrode of the fourth transistor being connected to the second scanning signal line extending along the first direction, the first electrode of the fourth transistor being connected to the data signal line, and the second scanning signal line being arranged on a side of the first scanning signal line away from the second electrode plate; in the second direction, the first connecting line and the first constant voltage routing are arranged between the first scanning signal line and the second electrode plate, or the first connecting line and the first constant voltage routing are arranged between the first scanning signal line and the second scanning signal line.

[0011] In an exemplary embodiment, at least one circuit unit further includes a data connection electrode, the data signal line is connected to the data connection electrode through a via, and the data connection electrode is connected to the first electrode of the fourth transistor through a via; at least one repeating unit further includes a data connection block, the data connection block is respectively connected to the first connection line and the data connection electrode in a circuit unit, and the data connection block is arranged on a side of the first scan signal line close to the second electrode plate.

[0012] In an exemplary embodiment, at least one repeating unit further includes a data connection block connected to the first connection line, the data connection block is connected to the first electrode of the fourth transistor in a circuit unit through a via, the data signal line is connected to the data connection block through a via, and the data connection block is arranged on a side of the first scan signal line away from the second electrode plate.

[0013] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor serving as a first light-emitting control transistor, a gate electrode of the fifth transistor being connected to a light-emitting signal line, a first electrode of the fifth transistor being connected to the first power line, and the light-emitting signal line being arranged on one side of the second electrode plate in the second direction; in the second direction, the first connecting line and the first constant voltage trace are arranged on a side of the light-emitting signal line away from the second electrode plate.

[0014] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the light-emitting structure layer including at least a red light-emitting unit, a green light-emitting unit, and a blue light-emitting unit, the red light-emitting unit including at least a first anode, the green light-emitting unit including at least a second anode, and the blue light-emitting unit including at least a third anode; the orthographic projection of at least one first anode and at least one second anode on the substrate at least partially overlaps with the orthographic projection of the second connecting line or the second constant voltage trace on the substrate, and the orthographic projection of at least one third anode on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate.

[0015] In an exemplary embodiment, at least one third anode is provided with an anode groove having a strip shape extending along the second direction, and an orthographic projection of the anode groove on the substrate at least partially overlaps with an orthographic projection of the data signal line on the substrate.

[0016] In an exemplary embodiment, at least one insertion column is further provided with at least one constant voltage connection line extending along the second direction; in the first direction, the constant voltage connection line is arranged between the second connection line and the data signal line, or the constant voltage connection line is arranged between the second constant voltage routing line and the data signal line.

[0017] In an exemplary embodiment, at least one circuit unit further includes a first initial signal line, a second initial signal line, and a third initial signal line extending along the first direction, the pixel driving circuit is connected to the first initial signal line, the second initial signal line, and the third initial signal line, respectively, and the first initial signal line, the second initial signal line, and the third initial signal line are configured to provide the first initial signal, the second initial signal, and the third initial signal to the pixel driving circuit, respectively; at least one of the constant voltage connection lines is connected to the first initial signal line, the second initial signal line, or the third initial signal line.

[0018] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the light-emitting structure layer including a plurality of light-emitting units, at least one light-emitting unit including a light-emitting device, the light-emitting device being connected to a second power line, the second power line being configured to provide a second power signal to the light-emitting device; at least one circuit unit further includes a first initial signal line, a second initial signal line, a third initial signal line extending along the first direction, and a first power line extending along the second direction, the pixel driving circuit being connected to the first initial signal line, the second initial signal line, the third initial signal line, and the first power line, respectively, the first initial signal line, the second initial signal line, and the third initial signal line being configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively, the first power line being configured to provide a first power signal to the pixel driving circuit; the second constant voltage trace being connected to any one or more of the following: the first initial signal line, the second initial signal line, the third initial signal line, the first power line, or the second power line.

[0019] In an exemplary embodiment, the display substrate is divided into a plurality of sub-areas, the second constant voltage routing in one sub-area is connected to the first initial signal line, the second constant voltage routing in another sub-area is connected to the second initial signal line, and the second constant voltage routing in yet another sub-area is connected to the third initial signal line, thereby forming a meshed connectivity structure for transmitting the first initial signal, a meshed connectivity structure for transmitting the second initial signal, and a meshed connectivity structure for transmitting the third initial signal.

[0020] In an exemplary embodiment, a plurality of second constant voltage routings are respectively connected to the first initial signal line, the second initial signal line, and the third initial signal line. In the first direction, the second constant voltage routing connected to the first initial signal line, the second constant voltage routing connected to the second initial signal line, and the second constant voltage routing connected to the third initial signal line are periodically arranged.

[0021] In an exemplary embodiment, a plurality of second constant voltage traces are respectively connected to the first initial signal line, the second initial signal line, the third initial signal line and the second power line. In the first direction, the second constant voltage trace connected to the first initial signal line, the second constant voltage trace connected to the second power line, the second constant voltage trace connected to the second initial signal line, the second constant voltage trace connected to the second power line, the second constant voltage trace connected to the third initial signal line, and the second constant voltage trace connected to the second power line are periodically arranged.

[0022] In an exemplary embodiment, the second constant voltage line located in the same insertion column as the second connecting line is connected to the first power line or the second power line, and the second constant voltage line separately arranged in the insertion column is connected to the first initial signal line, the second initial signal line or the third initial signal line.

[0023] In an exemplary embodiment, in a direction perpendicular to the base, the display substrate includes multiple conductive layers, the second constant voltage trace, the first constant voltage trace and at least one initial signal line are arranged in different conductive layers, a portion of the second constant voltage trace is connected to the first constant voltage trace, and another portion of the second constant voltage trace is connected to the initial signal line.

[0024] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0025] The present disclosure provides a display substrate and a display device. By arranging a first connecting line and a second connecting line in a display area, the first end of the first connecting line is connected to a data signal line, and the second end of the first connecting line is connected to the second connecting line, the width of the lower frame can be reduced, the screen-to-body ratio can be increased, and full-screen display can be achieved.

[0026] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0028] Figure 1 is a structural schematic diagram of a display device;

[0029] Figure 2 It is a structural schematic diagram of a display substrate;

[0030] Figure 3A and Figure 3B This is a schematic diagram of the planar structure of a display area in a display substrate;

[0031] Figure 4 A schematic diagram of the cross-sectional structure of a display area in a display substrate;

[0032] Figure 5A and Figure 5B is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0033] Figure 6 This is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 This is a schematic diagram of the arrangement of data connection lines according to an exemplary embodiment of the present disclosure;

[0035] Figure 8 This is a schematic structural diagram of a data connection line and a constant voltage line according to an exemplary embodiment of the present disclosure;

[0036] 9A to 9D This is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0037] Figure 10 This is a schematic diagram of a display substrate disclosed herein after a semiconductor layer pattern is formed;

[0038] Figure 11A and Figure 11B This is a schematic diagram of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0039] Figure 12A and Figure 12B This is a schematic diagram of a display substrate after a second conductive layer pattern is formed in the present disclosure;

[0040] Figure 13 This is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed in the present disclosure;

[0041] 14A to 14D This is a schematic diagram of a display substrate disclosed herein after a third conductive layer pattern is formed;

[0042] Figure 15A and Figure 15B This is a schematic diagram of a display substrate after a first flat layer pattern is formed in the present disclosure;

[0043] 16A to 16D This is a schematic diagram of a display substrate after a fourth conductive layer pattern is formed on the substrate according to the present disclosure;

[0044] Figure 17 This is a schematic diagram of a display substrate after a second flat layer pattern is formed on the substrate according to the present disclosure;

[0045] Figure 18A and Figure 18B This is a schematic diagram of a display substrate after an anode conductive layer pattern is formed in the present disclosure;

[0046] Figure 19 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0047] Figure 20 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0048] Figure 21 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0049] Figure 22 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0050] Figure 23 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0051] Figure 24 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0052] Figure 25 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0053] Figure 26 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0054] Figure 27 This is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0055] Figure 28 This is a schematic structural diagram of another data connection line and constant voltage wiring according to an exemplary embodiment of the present disclosure;

[0056] Figure 29 This is a structural diagram of another data connection line and constant voltage wiring according to an exemplary embodiment of the present disclosure;

[0057] Figure 30 Schematic diagram of the structure of another data connection line and constant voltage line according to an exemplary embodiment of the present disclosure.

[0058] Description of the accompanying drawings:

[0059] 10—first active connection line; 11—first active layer; 12—second active layer;

[0060] 13—third active layer; 14—fourth active layer; 15—fifth active layer;

[0061] 16—sixth active layer; 17—seventh active layer; 18—eighth active layer;

[0062] 19—active connecting strip; 21—first gate electrode; 22—second gate electrode;

[0063] 24—fourth gate electrode; 25—first electrode plate; 26—second electrode plate;

[0064] 27—compensation electrode; 28—shielding electrode; 30—third active connecting line;

[0065] 31—first scanning signal line; 32—second scanning signal line; 33—third scanning signal line;

[0066] 34—fourth scanning signal line; 35—light emitting control line; 36—scanning connection line;

[0067] 37—repair line; 41—first initial signal line; 42—second initial signal line;

[0068] 43—third initial signal line; 51—first connection electrode; 52—second connection electrode;

[0069] 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode;

[0070] 56—sixth connecting electrode; 57—seventh connecting electrode; 58—eighth connecting electrode;

[0071] 61—first power line; 62—power connection line; 63—anode connection electrode;

[0072] 70—data signal line; 80—data connection line; 81—first connection line;

[0073] 82—second connection line; 83—dummy connection block; 84—data connection block;

[0074] 90—horizontal routing; 91—first constant voltage routing; 92—second constant voltage routing;

[0075] 93—constant voltage connecting line; 94—fourth connecting block; 95—fifth connecting block;

[0076] 100—display area; 101—substrate; 102—driving structure layer;

[0077] 103 —light-emitting structure layer; 104 —encapsulation structure layer; 110 —first region;

[0078] 120—second area; 200—binding area; 300—border area. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0080] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the figures.

[0081] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0082] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0083] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0084] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0085] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0086] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0087] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0088] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0089] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0090] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0091] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, a display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, the pixel driving circuit being connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values and control signals received from a timing controller. For example, the data driver can sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0092] Figure 2 Schematic diagram of the structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij forming a pixel array. The plurality of sub-pixels Pxij are configured to display dynamic or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled.

[0093] In an exemplary embodiment, the binding area 200 may include a lead area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area. The lead area is connected to the display area 100 and includes at least a data lead. The bending area is connected to the lead area and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include a binding pad (BondingPad), which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0094] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove respectively.

[0095] In an exemplary embodiment, the lead line area in the binding area 200 and the power line area in the border area 300 can be provided with an isolation dam, and the isolation dam can extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100. The edge of the display area is the edge of one side of the display area binding area or the border area.

[0096] Figure 3AFIG. 1 is a schematic diagram of the planar structure of a display area in a display substrate. Figure 3A As shown, the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0097] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a green subpixel (G) that emits green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the three subpixels may be arranged in a Real RGB format.

[0098] Figure 3B FIG. 1 is a schematic diagram of the planar structure of the display area in another display substrate. Figure 3B As shown, the pixel unit P may include four sub-pixels, the first sub-pixel P1 may be a red sub-pixel emitting red light, the second sub-pixel P2 and the fourth sub-pixel P4 may be green sub-pixels (G) emitting green light, and the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light. The four sub-pixels may be arranged in an RGBG manner.

[0099] Figure 4 FIG. 1 is a schematic diagram of the cross-sectional structure of a display area in a display substrate, illustrating the structure of three sub-pixels in the display area. Figure 4 As shown, on a plane perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0100] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0101] Figure 5A is an equivalent circuit diagram of a pixel driving circuit. Figure 5A As shown, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light-emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power line VDD).

[0102] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the second electrode of the first transistor T2, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0103] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0104] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor is connected to the first node N1 .

[0105] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0106] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0107] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the second scan signal line S2 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0108] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0109] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0110] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the third scan signal line S3 , a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0111] In an exemplary embodiment, a gate electrode of the eighth transistor T8 is connected to the third scan signal line S3 , a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3 , and a second electrode of the eighth transistor T8 is connected to the second node N2 .

[0112] In an exemplary embodiment, the pixel driving circuit may further include a second node capacitor C N2 , the second node capacitance C N2 One end of the capacitor is connected to the second node N2, and the second node capacitor C N2 The other end of the second node capacitor C is connected to the first power line VDD. N2 It can have the function of stabilizing the voltage of the second node N2.

[0113] In an exemplary embodiment, the pixel driving circuit can realize normal driving and low-frequency driving. In the scene where the refresh rate requirement is not high, low-frequency refresh can be used to save power consumption. During normal driving, the driving timing of the pixel driving circuit can include four stages such as initialization, compensation, data writing and light emission. During low-frequency driving, the driving timing of the pixel driving circuit can include six stages such as initialization, compensation, data writing, light emission, adjustment and light emission again. In the adjustment stage, the eighth transistor T8 is used to write the third initial signal (bias voltage) to the first pole of the third transistor T3, so that the bias state of the third transistor T3 is maintained consistent with the bias state when the data signal is just written. This can not only improve the stability of the working state of the driving transistor and improve low-frequency flicker (Fliker), but also effectively improve the hysteresis of the third transistor, which is beneficial to improving the afterimage and improving the display effect.

[0114] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0115] In an exemplary embodiment, the first power line VDD is configured to provide a constant first power signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second power signal to the light-emitting device. The voltage of the first power signal is higher than the voltage of the second power signal, the first power signal is a high-level signal, and the second power signal is a low-level signal. The first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 are configured to provide a constant first initial signal, a second initial signal, and a third initial signal, respectively, to the pixel driving circuit, although this disclosure is not limited thereto. In an exemplary embodiment, the third initial signal may be referred to as a reference signal, and the third initial signal line INIT3 may be referred to as a reference signal line.

[0116] In an exemplary embodiment, the first to eighth transistors T1 to T8 in the pixel driving circuit may be P-type transistors or N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to eighth transistors T1 to T8 may include P-type transistors and N-type transistors.

[0117] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0118] Figure 5B is an equivalent circuit diagram of another pixel driving circuit. Figure 5B As shown, the pixel driving circuit can be a 9T2C structure, which can include 9 transistors (the eleventh transistor T11 to the nineteenth transistor T19) and 2 storage capacitors (the first capacitor C1 and the second capacitor C2). The pixel driving circuit is respectively connected to 12 signal lines (the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, the fourth scanning signal line S4, the first light-emitting signal line EM1, the second light-emitting signal line EM2, the first initial signal line INIT1, the second initial signal line INIT2, the first reference signal line REF1, the second reference signal line REF2, the data signal line D and the first power line VDD).

[0119] In an exemplary embodiment, the pixel driving circuit may include an eleventh node N11, a twelfth node N12, a thirteenth node N13, a fourteenth node N14, and a fifteenth node N15. The eleventh node N11 is connected to the second electrode of the eleventh transistor T11, the first electrode of the twelfth transistor T12, the gate electrode of the thirteenth transistor T13, and the first end of the first capacitor C1, respectively. The twelfth node N12 is connected to the second electrode of the fourteenth transistor T14, the second electrode of the eighteenth transistor T18, the second end of the first capacitor C1, and the second end of the second capacitor C2, respectively. The thirteenth node N13 is connected to the first electrode of the thirteenth transistor T13, the second electrode of the fifteenth transistor T15, and the second electrode of the nineteenth transistor T19, respectively. The fourteenth node N14 is connected to the second electrode of the twelfth transistor T12, the second electrode of the thirteenth transistor T13, and the first electrode of the sixteenth transistor T16, respectively. The fifteenth node N15 is connected to the second electrode of the sixteenth transistor T16 and the second electrode of the seventeenth transistor T17, respectively.

[0120] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the eleventh node N11, a second end of the first capacitor C1 is connected to the twelfth node N12, a first end of the second capacitor C2 is connected to the first power line VDD, and a second end of the second capacitor C2 is connected to the twelfth node N12.

[0121] In an exemplary embodiment, a gate electrode of the eleventh transistor T11 is connected to the fourth scan signal line S4 , a first electrode of the eleventh transistor T11 is connected to the first initial signal line INIT1 , and a second electrode of the eleventh transistor T11 is connected to the eleventh node N11 .

[0122] In an exemplary embodiment, a gate electrode of the twelfth transistor T12 is connected to the second scan signal line S2 , a first electrode of the twelfth transistor T12 is connected to the eleventh node N11 , and a second electrode of the twelfth transistor T12 is connected to the fourteenth node N14 .

[0123] In an exemplary embodiment, a gate electrode of the thirteenth transistor T13 is connected to the eleventh node N11 , a first electrode of the thirteenth transistor T13 is connected to the thirteenth node N13 , and a second electrode of the thirteenth transistor T13 is connected to the fourteenth node N14 .

[0124] In an exemplary embodiment, a gate electrode of the fourteenth transistor T14 is connected to the third scan signal line S3 , a first electrode of the fourteenth transistor T14 is connected to the data signal line DATA, and a second electrode of the fourteenth transistor T14 is connected to the twelfth node N12 .

[0125] In an exemplary embodiment, a gate electrode of the fifteenth transistor T15 is connected to the first light emitting signal line EM1 , a first electrode of the fifteenth transistor T15 is connected to the first power line VDD, and a second electrode of the fifteenth transistor T15 is connected to the thirteenth node N13 .

[0126] In an exemplary embodiment, a gate electrode of the sixteenth transistor T16 is connected to the second light emitting signal line EM2 , a first electrode of the sixteenth transistor T16 is connected to the fourteenth node N14 , and a second electrode of the sixteenth transistor T16 is connected to the fifteenth node N15 .

[0127] In an exemplary embodiment, a gate electrode of the seventeenth transistor T17 is connected to the first scan signal line S1 , a first electrode of the seventeenth transistor T17 is connected to the second initial signal line INIT2 , and a second electrode of the seventeenth transistor T17 is connected to the fifteenth node N15 .

[0128] In an exemplary embodiment, a gate electrode of the eighteenth transistor T18 is connected to the second scan signal line S2 , a first electrode of the eighteenth transistor T18 is connected to the first reference signal line REF1 , and a second electrode of the eighteenth transistor T18 is connected to the twelfth node N12 .

[0129] In an exemplary embodiment, a gate electrode of the nineteenth transistor T19 is connected to the first scan signal line S1 , a first electrode of the nineteenth transistor T19 is connected to the second reference signal line REF2 , and a second electrode of the nineteenth transistor T19 is connected to the thirteenth node N13 .

[0130] In an exemplary embodiment, a first electrode of the light emitting device EL is connected to the fifteenth node N15 , and a second electrode of the light emitting device EL is connected to the second power line VSS.

[0131] In an exemplary embodiment, the eleventh transistor T11 to the nineteenth transistor T19 may all be P-type transistors, or may all be N-type transistors, or may include P-type transistors and N-type transistors. The pixel driving circuit can improve the hysteresis of the driving transistor, which is beneficial to improving the display effect.

[0132] With the development of OLED display technology, consumers are increasingly demanding higher display effects and quality. Narrow bezels have become a new trend in display product development. Consequently, narrower or even borderless bezels are gaining increasing attention in OLED display product design. In one display substrate, the data signals from the integrated circuits in the bonding area must be introduced to the wider display area via data lead wires in a fan-out manner. This occupies a large area in the lead wire area, resulting in a larger bottom bezel width, which has been maintained at approximately 2.0mm.

[0133] To reduce the width of the lower bezel, exemplary embodiments of the present disclosure provide a display substrate employing a fanout in panel (FIP) structure. Multiple data connection lines are arranged in the display area. One end of each of the multiple data connection lines is connected to a plurality of data signal lines in the display area. The other ends of the multiple data connection lines extend to a binding area and are connected to the integrated circuit via a plurality of data lead lines in a lead area. Because the lead area does not require fan-shaped diagonal lines, the width of the lead area is reduced, thereby reducing the width of the lower bezel.

[0134] An exemplary embodiment of the present disclosure provides a display substrate, comprising a driving structure layer disposed on a base; the driving structure layer comprises a plurality of repeating units forming a plurality of repeating unit rows and a plurality of repeating unit columns, with an intervening column disposed between adjacent repeating unit columns; at least one repeating unit comprises a plurality of circuit units disposed sequentially along a first direction, at least one circuit unit comprising a pixel driving circuit and a data signal line extending along a second direction, the data signal line being connected to the pixel driving circuit and configured to provide a data signal to the pixel driving circuit, the first direction and the second direction intersecting; the driving structure layer further comprises at least one first connecting line and at least one first constant voltage trace extending along the first direction, and at least one second connecting line and at least one second constant voltage trace extending along the second direction, a first end of the first connecting line being connected to the data signal line, a second end of the first connecting line being connected to the second connecting line, and at least one second constant voltage trace being connected to the at least one first constant voltage trace to form a meshed connection structure for transmitting a constant voltage signal; the second connecting line and the second constant voltage trace being disposed in the intervening column.

[0135] In an exemplary embodiment, at least one repeating unit includes three circuit units.

[0136] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the light-emitting structure layer including a plurality of light-emitting units, at least one light-emitting unit including a light-emitting device, the light-emitting device being connected to a second power line, the second power line being configured to provide a second power signal to the light-emitting device; at least one circuit unit further includes a first initial signal line, a second initial signal line, a third initial signal line extending along the first direction, and a first power line extending along the second direction, the pixel driving circuit being connected to the first initial signal line, the second initial signal line, the third initial signal line, and the first power line, respectively, the first initial signal line, the second initial signal line, and the third initial signal line being configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively, the first power line being configured to provide a first power signal to the pixel driving circuit; the second constant voltage trace being connected to any one or more of the following: the first initial signal line, the second initial signal line, the third initial signal line, the first power line, or the second power line.

[0137] Figure 6 FIG. 1 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 6As shown, in a plane parallel to the display substrate, the display substrate may include at least a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a base, a light-emitting structure layer disposed on a side of the driving structure layer away from the base, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the base.

[0138] In an exemplary embodiment, the driving structure layer of the display area 100 may include a plurality of pixel driving circuits, a plurality of data signal lines 70, and a plurality of data connection lines 80. The pixel driving circuits are configured to output corresponding currents to the connected light-emitting devices. The light-emitting structure layer of the display area 100 may include a plurality of light-emitting devices, each of which is connected to a corresponding pixel driving circuit and configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0139] In an exemplary embodiment, at least one data signal line 70 is connected to at least one pixel driving circuit, and the data signal line 70 is configured to provide a data signal to the connected pixel driving circuit. One end of at least one data connection line 80 is connected to the corresponding data signal line 70, and the other end is connected to the data lead line 80A in the binding area 200, thereby realizing the connection between the data signal line 70 and the data lead line 80A.

[0140] In an exemplary embodiment, the binding region 200 may include a lead region, a bend region, a driver chip region, and a binding pin region, arranged sequentially along a direction away from the display region. The lead region is connected to the display region 100, and the bend region is connected to the lead region. The lead region may be provided with at least a plurality of data lead lines 80A, extending in a direction away from the display region. The first ends of some of the data lead lines 80A are connected to the data connection lines 80 in the display region 100, while the first ends of another portion of the data lead lines are connected to the data signal lines 70 in the display region 100. The second ends of all data lead lines 80A extend along a second direction Y and cross the bend region to connect to the integrated circuit in the driver chip region. Data signals from the integrated circuit are applied to the data signal lines 70 via the data lead lines 80A and the data connection lines 80. Since the data connection lines 80 are arranged in the display region, the length of the lead region in the second direction Y can be effectively reduced, significantly reducing the width of the lower bezel, and increasing the screen-to-body ratio, facilitating full-screen display.

[0141] In an exemplary embodiment, the plurality of data signal lines 70 in the display area can be divided into a first data signal line group and a second data signal line group according to whether they are connected to the data connection lines 80. The data signal lines 70 in the first data signal line group are connected to the data connection lines 80, while the data signal lines 70 in the second data signal line group are not connected to the data connection lines 80. The plurality of data lead lines 80A in the lead area can be divided into a first lead line group and a second lead line group according to whether they are connected to the data connection lines 80. The data lead lines 80A in the first lead line group are connected to the data connection lines 80, while the data lead lines 80A in the second lead line group are not connected to the data connection lines 80. The plurality of data signal lines 70 in the first data signal line group are connected to one end of the plurality of data connection lines 80, and the other ends of the plurality of data connection lines 80 are connected to the plurality of data lead lines 80A in the first lead line group. The plurality of data signal lines 70 in the second data signal line group are connected to the plurality of data lead lines 80A in the second lead line group.

[0142] In an exemplary embodiment, the display area 100 may have a center line O, and the multiple data signal lines 70, the multiple data connection lines 80 in the display area 100 and the multiple data lead lines 80A in the lead area 201 may be symmetrically arranged relative to the center line O. The center line O may be a straight line that bisects the display area 100 in the first direction X and extends along the second direction Y.

[0143] Figure 7 FIG. 1 is a schematic diagram of the arrangement of data connection lines according to an exemplary embodiment of the present disclosure. Figure 7 As shown, the data connection line 80 may include at least a first connection line 81 and a second connection line 82. The first connection line 81 may be in the shape of a straight line or a zigzag line extending along a first direction X. The data signal line 70 and the second connection line 82 may be in the shape of a straight line or a zigzag line extending along a second direction Y. The first direction X intersects the second direction Y. The first end of the first connection line 81 may be connected to the data signal line 70 through a first connection hole. The second end of the first connection line 81 may extend along the first direction X or a direction opposite to the first direction X and then be connected to the first end of the second connection line 82 through a second connection hole. The second end of the second connection line 82 may extend along the second direction Y toward the lead area and then be connected to the data lead line.

[0144] In an exemplary embodiment, the data lead lines and the data signal lines 70 , and the data lead lines and the data connection lines 80 may be directly connected, or may be connected through connection holes, which is not limited in the present disclosure.

[0145] In an exemplary embodiment, since the data connection lines include a first connection line 81 extending along a first direction X and a second connection line 82 extending along a second direction Y, and are provided in a portion of the display area, the display area can be divided into a first area 110 and a second area 120 based on the presence or absence of the data connection lines. The first area 110 may be an area where the first connection line 81 or the second connection line 82 is provided, and may be referred to as a FIP area. The second area 120 may be an area where the first connection line 81 and the second connection line 82 are not provided, and may be referred to as a non-FIP area.

[0146] The present invention provides data connection lines in the display area, so that the data lead lines in the binding area are connected to the data signal lines through the data connection lines, so that there is no need to set fan-shaped oblique lines in the lead area, which effectively reduces the length of the lead area, greatly reduces the width of the lower frame, and improves the screen-to-body ratio, which is conducive to achieving full-screen display.

[0147] Figure 8 FIG. 1 is a structural diagram of a data connection line and a constant voltage line according to an exemplary embodiment of the present disclosure. Figure 8 As shown, in an exemplary embodiment, the driving structure layer of the display area 100 may include a plurality of repeating units Q forming a plurality of repeating unit rows and a plurality of repeating unit columns. The repeating unit Q is a basic unit constituting the driving structure layer and is formed by being repeatedly and continuously arranged along a first direction X and a second direction Y. At least one repeating unit Q may include a plurality of circuit units sequentially arranged along the first direction X, and at least one circuit unit may include a pixel driving circuit. The light-emitting structure layer of the display area 100 may include a plurality of light-emitting units, and at least one light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the corresponding circuit unit.

[0148] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0149] In an exemplary embodiment, a plurality of repeating units sequentially arranged along a first direction X may be referred to as a repeating unit row, and a plurality of repeating units sequentially arranged along a second direction Y may be referred to as a repeating unit column. A plurality of circuit units sequentially arranged along the first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along the second direction Y may be referred to as a unit column.

[0150] In an exemplary embodiment, one repeating unit row may include one unit row, ie, one unit row and one repeating unit row are the same concept, and one repeating unit column may include three unit columns.

[0151] In an exemplary embodiment, the driving structure layer of the display area 100 may further include a plurality of insertion columns, each of which is disposed between adjacent repeating unit columns. The insertion columns are configured to provide vertical traces, such as second connecting lines or second constant voltage traces. The insertion columns referred to in this disclosure may be such that the distance between two circuit units having the insertion columns is greater than the distance between two circuit units not having the insertion columns.

[0152] In an exemplary embodiment, the driving structure layer of the display area 100 may further include a plurality of data signal lines 70, a plurality of first connection lines 81, a plurality of second connection lines 82, a plurality of first constant voltage traces 91, and a plurality of second constant voltage traces 92. The first connection lines 81 and the first constant voltage traces 91 may be in the shape of a straight line or a broken line extending along the first direction X, and the data signal lines 70, the second connection lines 82, and the second constant voltage traces 92 may be in the shape of a straight line or a broken line extending along the second direction Y.

[0153] In an exemplary embodiment, a plurality of data signal lines 70 may be respectively arranged in each unit column and arranged sequentially along the first direction X, and the data signal lines 70 are connected to the pixel driving circuits of the plurality of circuit units in the unit column. A plurality of first connection lines 81 and a plurality of second connection lines 82 may be arranged in the first region 110, and the plurality of first connection lines 81 may be respectively arranged in corresponding repeating unit rows and arranged sequentially along the second direction Y, and the plurality of second connection lines 82 may be respectively arranged in corresponding intervening columns and arranged sequentially along the first direction X. A plurality of first constant voltage traces 91 and a plurality of second constant voltage traces 92 may be arranged in the second region 120, and the plurality of first constant voltage traces 91 may be respectively arranged in corresponding repeating unit rows and arranged sequentially along the second direction Y, and the plurality of second constant voltage traces 92 may be respectively arranged in corresponding intervening columns and arranged sequentially along the first direction X. In an exemplary embodiment, some of the first constant voltage traces 91 and some of the second constant voltage traces 92 may extend into the first region 110.

[0154] In an exemplary embodiment, a repeating unit (three circuit units) may be spaced between two adjacent second connecting lines 82 in the first direction X, and a repeating unit (three circuit units) may be spaced between two adjacent second constant voltage lines 92 in the first direction X, that is, the second connecting line 82 and the second constant voltage line 92 are a three-in-one structure.

[0155] In an exemplary embodiment, three data signal lines 70 may be provided between two adjacent second connection lines 82 in the first direction X, and three data signal lines 70 may be provided between two adjacent second constant voltage traces 92 in the first direction X.

[0156] In an exemplary embodiment, the driving structure layer of the display substrate may include multiple conductive layers in a direction perpendicular to the display substrate. The first connecting line 81 and the second connecting line 82 may be arranged in different conductive layers. The first connecting line 81 and the data signal line 70 may be arranged in different conductive layers. The first end of the first connecting line 81 may be connected to the data signal line 70 through the first connecting hole K1. The second end of the first connecting line 81 extends along the first direction X or the opposite direction of the first direction X, and then connects to the first end of the second connecting line 82 through the second connecting hole K2. The second end of the second connecting line 82 extends along the second direction Y toward the lead area and then connects to the data lead line.

[0157] In an exemplary embodiment, the first constant voltage trace 91 and the second constant voltage trace 92 can be set in different conductive layers, and at least one second constant voltage trace 92 can be connected to at least one first constant voltage trace 91 through a third connection hole K3, forming a mesh connection structure for transmitting a constant voltage signal in the display area.

[0158] In an exemplary embodiment, the first constant voltage trace 91 and the first connecting line 81 can be set on the same layer and formed synchronously through the same patterning process, and the data signal line 70, the second connecting line 82 and the second constant voltage trace 92 can be set on the same layer and formed synchronously through the same patterning process.

[0159] In an exemplary embodiment, at least one repeating unit row may include at least one first connection line 81 and at least one first constant voltage trace 91. A first break DF1 may be provided between the first connection line 81 and the first constant voltage trace 91. The first break DF1 is configured to achieve mutual insulation between the first connection line 81 and the first constant voltage trace 91. In an exemplary embodiment, the unit row may include a first region 110 and a second region 120.

[0160] In an exemplary embodiment, at least one repeating unit row may be provided with only one first constant voltage trace 91 , and the unit row may not be provided with a first connection line 81 . In an exemplary embodiment, the unit row may be a unit row in the second region 120 .

[0161] In an exemplary embodiment, at least one second connection line 82 and at least one second constant-voltage trace 92 may be provided in at least one insertion column. A second break DF2 may be provided between the second connection line 82 and the second constant-voltage trace 92. The second break DF2 is configured to achieve mutual insulation between the second connection line 82 and the second constant-voltage trace 92. In an exemplary embodiment, the insertion column may be an insertion column including the first region 110 and the second region 120.

[0162] In an exemplary embodiment, at least one insertion column may be provided with only one second constant voltage trace 92 , and the insertion column may not be provided with a second connection line 82 . In an exemplary embodiment, the insertion column may be an insertion column in the second region 120 .

[0163] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D Schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure. Figure 9A for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 9B for Figure 9A Schematic diagram of the first connecting line and the second connecting line, Figure 9C for Figure 8 Schematic diagram of the structure of area B in the middle. Figure 9D for Figure 9C Schematic diagram of the first constant voltage trace and the second constant voltage trace. Figure 9A and Figure 9B The structure of six circuit units in one unit row (Mth unit row) and six unit columns (Nth to N+5th unit columns) in the first region is shown. Figure 9C and Figure 9D The structure of six circuit cells in one cell row (M-4th cell row) and six cell columns (N+9th cell column to N+14th cell column) in the second region is illustrated.

[0164] In an exemplary embodiment, the display substrate may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, in a direction perpendicular to the display substrate. In a plane parallel to the substrate, the driving structure layer may include a plurality of repeating units Q forming a plurality of repeating unit rows and a plurality of repeating unit columns, with an intervening column IN disposed between adjacent repeating unit columns. At least one repeating unit Q may include three circuit units sequentially arranged along a first direction X, and at least one circuit unit may include a pixel driving circuit. The pixel driving circuit may be connected to a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a fourth scan signal line 34, a light-emitting signal line 35, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a first power line 61, and a data signal line 70, respectively.

[0165] In an exemplary embodiment, the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, and the fourth scan signal line 34 are configured to respectively provide a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the pixel driving circuit; the light emission signal line 35 is configured to provide a light emission control signal to the pixel driving circuit; the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to respectively provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit; the first power line 61 is configured to provide a first power signal to the pixel driving circuit; and the data signal line 70 is configured to provide a data signal to the pixel driving circuit. The plurality of signal lines connected to the pixel driving circuit may be located within the circuit unit.

[0166] In an exemplary embodiment, the shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the fourth scan signal line 34, the light-emitting signal line 35, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the first power line 61 and the data signal line 70 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0167] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0168] In an exemplary embodiment, the pixel driving circuit may include a storage capacitor and eight transistors. The storage capacitor may include a first plate and a second plate stacked together, wherein the orthographic projection of the second plate on the substrate at least partially overlaps the orthographic projection of the first plate on the substrate. The eight transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor. In an exemplary embodiment, the eight transistors may all be low-temperature polysilicon transistors (P-type transistors).

[0169] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 34, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is respectively connected to the first electrode and the first plate of the second transistor T2 (which also serves as the gate electrode of the third transistor T3). The gate electrode of the second transistor T2 is connected to the first scan signal line 31, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the second scan signal line 32, the first electrode of the fourth transistor T4 is connected to the first data signal line 70, and the second electrode of the fourth transistor T4 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8. The gate electrode of the fifth transistor T5 is connected to the light emission signal line 35, and the first electrode of the fifth transistor T5 is connected to the first power supply line 61. The gate electrode of the sixth transistor T6 is connected to the light emission signal line 35, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the third scanning signal line 33, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the third scanning signal line 33, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0170] In an exemplary embodiment, in at least one circuit unit, the first scan signal line 31 may be disposed on a side of the storage capacitor opposite to the second direction Y, the second scan signal line 32 may be disposed on a side of the first scan signal line 31 away from the storage capacitor, the fourth scan signal line 34 may be disposed on a side of the second scan signal line 32 away from the storage capacitor, and the first initial signal line 41 may be disposed on a side of the fourth scan signal line 34 away from the storage capacitor. The light-emitting signal line 35 may be disposed on a side of the storage capacitor in the second direction Y, the third scan signal line 33 may be disposed on a side of the light-emitting signal line 35 away from the storage capacitor, the second initial signal line 42 may be disposed on a side of the third scan signal line 33 away from the storage capacitor, and the third initial signal line 43 may be disposed on a side of the second initial signal line 42 away from the storage capacitor.

[0171] In an exemplary embodiment, the driving structure layer may further include at least one power connection line 62. The power connection line 62 may be in the shape of a zigzag line extending along the first direction X and may be disposed between the first scanning signal line 31 and the light emitting signal line 35. The power connection line 62 is connected to the second electrode plate through a via hole, and the first power line 61 is connected to the power connection line 62 through a via hole. The first power line 61 and the power connection line 62 form a meshed connection structure for transmitting the first power signal.

[0172] In an exemplary embodiment, the drive structure layer may further include at least one first connecting line 81, at least one second connecting line 82, at least one first constant voltage trace 91, and at least one second constant voltage trace 92. The first connecting line 81 and the first constant voltage trace 91 may be in the shape of a straight line or a broken line extending along the first direction X, and the second connecting line 82 and the second constant voltage trace 92 may be in the shape of a straight line or a broken line extending along the second direction Y. The first connecting line 81 is configured to be connected to the data signal line 70 and the second connecting line 82, respectively, to form a structure in which the data connecting line is located in the display area. The first constant voltage trace 91 and the second constant voltage trace 92 are configured to be interconnected to form a meshed connection structure for transmitting constant voltage signals.

[0173] In an exemplary embodiment, the display substrate may include a plurality of conductive layers disposed on a base in a direction perpendicular to the display substrate. The first connecting line 81 and the second connecting line 82 may be disposed in different conductive layers. The first connecting line 81 and the first constant voltage trace 91 may be disposed in the same layer, and the second connecting line 82 and the second constant voltage trace 92 may be disposed in the same layer.

[0174] like Figure 9A and Figure 9BAs shown, in the first region, the first connection line 81 can be arranged between the first scan signal line 31 and the second electrode plate, and the second connection line 82 can be arranged in the insertion column IN. Three first power lines 61 and three data signal lines 70 can be arranged between two adjacent second connection lines 82, that is, three circuit units (one repeating unit Q) can be spaced between two adjacent second connection lines 82.

[0175] In an exemplary embodiment, in the first direction X, at least one first power line 61 may be disposed between the data signal line 70 and the second connection line 82 .

[0176] In an exemplary embodiment, at least one repeating unit row may be provided with at least one first connection line 81 and at least one first constant-voltage trace 91, and a first break DF1 may be provided between the first connection line 81 and the first constant-voltage trace 91. The first break DF1 is configured to achieve mutual insulation between the first connection line 81 and the first constant-voltage trace 91. At least one insertion column IN may be provided with at least one second connection line 82 and at least one second constant-voltage trace 92. A second break DF2 may be provided between the second connection line 82 and the second constant-voltage trace 92. The second break DF2 is configured to achieve mutual insulation between the second connection line 82 and the second constant-voltage trace 92.

[0177] In an exemplary embodiment, each circuit cell in the first region may be provided with a third connection electrode 53, which serves as the data connection electrode of the present disclosure, and the data signal line 70 may be connected to the third connection electrode 53 through a via. At least one circuit cell in the first region may be provided with a data connection block 84. The data connection block 84 may be provided between the first connection line 81 and the third connection electrode 53, with both ends of the data connection block 84 connected to the first connection line 81 and the third connection electrode 53, respectively, thereby connecting the first end of the first connection line 81 to the data signal line 70. For example, the data connection block 84 may be provided in the circuit cell in the Mth cell row and the N+1th cell column, connecting the first connection line 81 in the Mth cell row with the data signal line 70 in the N+1th cell column.

[0178] In an exemplary embodiment, in at least one repeating unit row, the data connection block 84 can be arranged on a side of the first scan signal line 31 close to the second electrode plate, and the third connection electrodes 53 of the plurality of circuit units can be arranged on a side of the first scan signal line 31 close to the second electrode plate and located on the same straight line extending along the first direction X.

[0179] In an exemplary embodiment, in at least one intervening column of the first region, the second connection line 82 may be connected to the first connection line 81 through a via, thereby achieving a connection between the second end of the first connection line 81 and the second connection line 82. For example, in the intervening column between the (N+3)th cell column and the (N+4)th cell column, the second connection line 82 is connected to the first connection line 81 in the (M)th cell row through a via.

[0180] like Figure 9C and Figure 9D As shown, in the second region, the first constant voltage trace 91 can be disposed between the first scan signal line 31 and the second electrode plate, and the second constant voltage trace 92 can be disposed in the insertion column IN. Three first power lines 61 and three data signal lines 70 can be disposed between two adjacent second constant voltage traces 92, that is, three circuit units (one repeating unit Q) can be spaced between two adjacent second constant voltage traces 92.

[0181] In an exemplary embodiment, in the first direction X, at least one first power line 61 may be disposed between the data signal line 70 and the second constant voltage trace 92 .

[0182] In an exemplary embodiment, at least one repeating unit row may include only first constant voltage traces 91 without first connection lines, and at least one insertion column IN may include only second constant voltage traces 92 without second connection lines 82 .

[0183] In an exemplary embodiment, in at least one inserted column in the second region, the second constant voltage trace 92 can be connected to the first constant voltage trace 91 through a via, thereby achieving a connection between the first constant voltage trace 91 and the second constant voltage trace 92, forming a meshed connectivity structure for transmitting constant voltage signals. For example, in the inserted column between the N+9th cell column and the N+10th cell column, the second constant voltage trace 92 is connected to the first constant voltage trace 91 in the M-4th cell row through a via. For another example, in the inserted column between the N+12th cell column and the N+13th cell column, the second constant voltage trace 92 is connected to the first constant voltage trace 91 in the M-4th cell row through a via.

[0184] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a first conductive layer disposed on a base, a second conductive layer disposed on a side of the first conductive layer away from the base, a third conductive layer disposed on a side of the second conductive layer away from the base, and a fourth conductive layer disposed on a side of the third conductive layer away from the base. The first connection line 81 and the first constant voltage trace 91 may be disposed in the third conductive layer, and the second connection line 82 and the second constant voltage trace 92 may be disposed in the fourth conductive layer.

[0185] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating an organic material, mask exposure, and development for organic materials. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be achieved by any one or more of spraying, spin coating, and inkjet printing; and etching can be achieved by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0186] In an exemplary embodiment, taking six circuit units in a repeating unit row as an example, the preparation process of the substrate shown in this embodiment may include the following operations: wherein a repeating unit Q includes three circuit units.

[0187] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as Figure 10 shown. Figure 10 for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 8 The semiconductor layer pattern in area B is Figure 8 The middle A area is basically the same.

[0188] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the eighth active layer 18 of the eighth transistor T8, and the first active layer 11 to the seventh active layer 17 may be an integrated structure connected to each other, and the eighth active layer 18 may be provided separately.

[0189] In an exemplary embodiment, the first active layer 11, the second active layer 12 and the fourth active layer 14 can be located on the side of the third active layer 13 in the opposite direction Y of the second direction Y of the present circuit unit, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 can be located on the side of the third active layer 13 in the second direction Y of the present circuit unit.

[0190] In an exemplary embodiment, the first active layer 11, the fourth active layer 14, the fifth active layer 15, the seventh active layer 17, and the eighth active layer 18 may have a strip shape extending along the second direction Y, the second active layer 12 and the sixth active layer 16 may have an "L" shape, and the third active layer 13 may have an inverted "Ω" shape.

[0191] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer 13, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 12-2 of the second active layer may serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be provided separately.

[0192] In an exemplary embodiment, the eighth active layer 18 can be separately disposed on the side of the seventh active layer 17 in the opposite direction of the first direction X, the first region 18-1 of the eighth active layer can be disposed on the side of the channel region of the eighth active layer away from the third active layer 13, and the second region 18-2 of the eighth active layer can be disposed on the side of the channel region of the eighth active layer close to the third active layer 13.

[0193] In an exemplary embodiment, a first active block 11A may be disposed on the first active layer 11 . The first active block 11A may be in a strip shape extending along the first direction X and may be disposed on one side of the first active layer 11 in the first direction X and connected to the first active layer 11 .

[0194] In an exemplary embodiment, in at least one circuit unit, the first active layer 11 and the first active block 11A may be an integral structure connected to each other.

[0195] In an exemplary embodiment, a second active block 12A may be disposed on the second active layer 12 . The second active block 12A may be block-shaped (eg, trapezoidal), disposed at a corner of the L-shape, and connected to the second active layer 12 .

[0196] In an exemplary embodiment, in at least one circuit unit, the second active layer 12 and the second active block 12A may be an integral structure connected to each other.

[0197] In exemplary embodiments, the semiconductor layer may further include a first active connection line 10 and a third active connection line 30 .

[0198] In an exemplary embodiment, the first active connection line 10 may be in the shape of a straight line or a broken line extending along the first direction X. It may be disposed on a side of the first active layer 11 away from the third active layer 13 and connected to the first region 11-1 of the first active layer of each circuit unit. The first active connection line 10 may be reused as a first initial trace extending along the first direction X, ensuring that the first regions of multiple first active layers in a cell row have the same potential.

[0199] In an exemplary embodiment, in at least one repeating unit, a first active connection block 10A may be provided on the first active connection line 10. The first active connection block 10A may be block-shaped (e.g., rectangular) and may be provided on a side of the first active connection line 10 away from the third active layer 13 and connected to the first active connection line 10. The first active connection block 10A is configured to be connected to the first initial signal line via a subsequently formed sixth connection electrode, so that the first active connection line and the first initial signal line form a signal line with a double-layer structure.

[0200] In an exemplary embodiment, the first active connection block 10A may be disposed at the boundary region between the (N+1)th unit column and the (N+2)th unit column, and may be disposed at the boundary region between the (N+4)th unit column and the (N+5)th unit column. In at least one repeating unit, the first active connection line 10 and the first active connection block 10A may be an integral structure connected to each other.

[0201] In an exemplary embodiment, the third active connection line 30 may be in the shape of a straight line or a zigzag line extending along the first direction X. It may be disposed on a side of the seventh active layer 17 away from the third active layer 13 and connected to the first region 17-1 of the seventh active layer of each circuit unit. The third active connection line 30 may be reused as a third initial trace extending along the first direction X, thereby ensuring that the first regions of multiple seventh active layers in a cell row have the same potential.

[0202] In an exemplary embodiment, in at least one repeating unit, a third active connection block 30A may be provided on the third active connection line 30. The third active connection block 30A may be in a block shape (e.g., rectangular) and may be provided on a side of the third active connection line 30 close to the third active layer 13 and connected to the third active connection block 30A. The third active connection block 30A is configured to be connected to the third initial signal line via a subsequently formed seventh connection electrode, so that the third active connection line and the third initial signal line form a signal line with a double-layer structure.

[0203] In an exemplary embodiment, the third active connection blocks 30A may be provided in the circuit units of the N+1th unit column and the N+4th unit column, respectively. In at least one repeating unit, the third active connection line 30 and the third active connection block 30A may be connected to each other as an integral structure.

[0204] In an exemplary embodiment, in at least one repetition unit, the eighth active layer 18 may be disposed on a side of the third active connection block 30A close to the third active layer 13 and connected to the third active connection block 30A.

[0205] In an exemplary embodiment, the second region 12-2 of the second active layer may serve as the second electrode of the second transistor T2, the second region 13-2 of the third active layer may serve as the second electrode of the third transistor (driving transistor) T3, and the first region 16-1 of the sixth active layer may serve as the first electrode of the sixth transistor T6. A connection region where the second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer are connected to each other serves as a third node N3 of the pixel driving circuit. The second region 16-2 of the sixth active layer may serve as the second electrode of the sixth transistor T6, and the second region 17-2 of the seventh active layer may serve as the second electrode of the seventh transistor T7. A connection region where the second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer are connected to each other serves as a fourth node N4 of the pixel driving circuit.

[0206] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Figure 11A and Figure 11B As shown, Figure 11B for Figure 11A Schematic plan view of the first conductive layer in FIG. Figure 11A for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 8 The first conductive layer pattern in area B Figure 8 In example embodiments, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0207] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first gate electrode 21 , a second gate electrode 22 , a fourth gate electrode 24 , a first plate 25 of a storage capacitor, a light emitting control line 35 and a scan connection line 36 .

[0208] In an exemplary embodiment, the shape of the first electrode plate 25 of the storage capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the first electrode plate 25 on the substrate at least partially overlaps with the orthographic projection of the third active layer 13 on the substrate. The first electrode plate 25 can serve as a plate of the storage capacitor and a gate electrode of the third transistor T3 at the same time.

[0209] In an exemplary embodiment, the first gate electrode 21 may be shaped like a "C" and may be disposed on a side of the first electrode 25 in the opposite direction of the second direction Y. The orthographic projection of the first gate electrode 21 on the substrate at least partially overlaps with the orthographic projection of the first active layer 11 on the substrate. The two overlapping regions of the first gate electrode 21 and the first active layer 11 may serve as two gate electrodes of the first transistor T1 of the dual-gate structure.

[0210] In an exemplary embodiment, in the second direction Y, the first active block 11A may be located between two gate electrodes of the first transistor T1 .

[0211] In an exemplary embodiment, a first gate connection block 21-1 may be provided on the first gate electrode 21. The first gate connection block 21-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the first gate electrode 21 away from the third active layer 13 and connected to the first gate electrode 21. The first gate connection block 21-1 is configured to be connected to a fourth scan signal line formed subsequently.

[0212] In an exemplary embodiment, in at least one circuit unit, the first gate electrode 21 and the first gate connection block 21 - 1 may be an integral structure connected to each other.

[0213] In an exemplary embodiment, the second gate electrode 22 may be in an "L" shape and may be disposed on a side of the first electrode 25 in the opposite direction of the second direction Y. The orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps with the orthographic projection of the second active layer 12 on the substrate. The two overlapping regions of the second gate electrode 22 and the second active layer 12 may serve as two gate electrodes of the second transistor T2 of the dual-gate structure.

[0214] In exemplary embodiments, the second active block 12A may be located between two gate electrodes of the second transistor T2 .

[0215] In an exemplary embodiment, a second gate connection block 22-1 may be provided on the second gate electrode 22. The second gate connection block 22-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the second gate electrode 22 away from the third active layer 13 and connected to the second gate electrode 22. The second gate connection block 22-1 is configured to be connected to a first scan signal line formed subsequently.

[0216] In an exemplary embodiment, in at least one circuit unit, the second gate electrode 22 and the second gate connection block 22 - 1 may be an integral structure connected to each other.

[0217] In an exemplary embodiment, the fourth gate electrode 24 may be in an "L" shape and may be disposed on a side of the first electrode 25 in the opposite direction of the second direction Y. The orthographic projection of the fourth gate electrode 24 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer 14 on the substrate. The overlapping region between the fourth gate electrode 24 and the fourth active layer 14 may serve as the gate electrode of the fourth transistor T4.

[0218] In an exemplary embodiment, a fourth gate connection block 24-1 may be provided on the fourth gate electrode 24. The fourth gate connection block 24-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the fourth gate electrode 24 away from the third active layer 13 and connected to the fourth gate electrode 24. The fourth gate connection block 24-1 is configured to be connected to a second scan signal line formed subsequently.

[0219] In an exemplary embodiment, in at least one circuit unit, the fourth gate electrode 24 and the fourth gate connection block 24 - 1 may be an integral structure connected to each other.

[0220] In an exemplary embodiment, the light emission control line 35 may be in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The light emission control line 35 may be disposed on one side of the first electrode plate 25 in the second direction Y. The orthographic projection of the light emission control line 35 on the substrate at least partially overlaps with the orthographic projection of the fifth active layer 15 on the substrate, and the overlapping region may serve as the gate electrode of the fifth transistor T5. The orthographic projection of the light emission control line 35 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer 16 on the substrate, and the overlapping region may serve as the gate electrode of the sixth transistor T6.

[0221] In an exemplary embodiment, the scan connection line 36 may be in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The scan connection line 36 may be disposed on a side of the light-emitting control line 35 away from the first electrode plate 25. The orthographic projection of the scan connection line 36 on the substrate at least partially overlaps with the orthographic projection of the seventh active layer 17 on the substrate, and the overlapping region may serve as the gate electrode of the seventh transistor T7. The orthographic projection of the scan connection line 36 on the substrate at least partially overlaps with the orthographic projection of the eighth active layer 18 on the substrate, and the overlapping region may serve as the gate electrode of the eighth transistor T8.

[0222] In an exemplary embodiment, in at least one repeating unit, a connection line break DF0 may be provided on the scan connection line 36 , and the connection line break DF0 cuts off the scan connection line 36 to reduce static electricity accumulation.

[0223] In an exemplary embodiment, the connection line break DF0 may be provided in the circuit cells of the (N+2)th cell column and the (N+5)th cell column.

[0224] In an exemplary embodiment, in at least one repeating unit, a scan connection block 36-1 may be provided on the scan connection line 36. The scan connection block 36-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the scan connection line 36 away from the first electrode plate 25 and connected to the scan connection line 36. The scan connection block 36-1 is configured to be connected to a third scan signal line formed subsequently.

[0225] In an exemplary embodiment, the first scan connection block 36 - 1 may be provided in the circuit units of the N+1th unit column and the N+4th unit column. In at least one repeating unit, the scan connection line 36 and the first scan connection block 36 - 1 may be an integral structure connected to each other.

[0226] In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer can be conductorized using the first conductive layer as a shield. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the eighth transistor T8, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first and second areas of the first to eighth active layers, the first active connecting line, and the third active connecting line are all conductorized.

[0227] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Figure 12A and Figure 12B As shown, Figure 12B for Figure 12A Schematic plan view of the second conductive layer in FIG. Figure 12A for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 8 The second conductive layer pattern in area B Figure 8 In example embodiments, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0228] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a second plate 26 of the storage capacitor, a compensation electrode 27 , a shielding electrode 28 , a repair line 37 , a first initial signal line 41 , and a third initial signal line 43 .

[0229] In an exemplary embodiment, the contour shape of the second plate 26 of the storage capacitor can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the second plate 26 on the substrate at least partially overlaps with the orthographic projection of the first plate 25 on the substrate. The second plate 26 can serve as another plate of the storage capacitor, and the first plate 25 and the second plate 26 constitute the storage capacitor of the pixel driving circuit.

[0230] In an exemplary embodiment, the shape of the compensation electrode 27 can be a block (such as a rectangle) and can be arranged on the side of the second electrode plate 26 in the opposite direction of the first direction X and connected to the second electrode plate 26. The orthographic projection of the compensation electrode 27 on the substrate at least partially overlaps with the orthographic projection of the connection area of the first area of the third active layer and the second area of the fourth active layer on the substrate (i.e., the second node N2 of the pixel driving circuit). In an exemplary embodiment, the connection area of the first area of the third active layer and the second area of the fourth active layer can serve as a capacitor plate and can have the potential of the second node N2. The compensation electrode 27 can serve as another capacitor plate. Since the second electrode plate 26 is configured to be connected to the first power line formed later, the compensation electrode 27 has the potential of the first power line. The compensation electrode 27 forms a second node capacitor C with the second node N2 of the pixel driving circuit. N2 , the second node capacitance C N2 It can have the function of stabilizing the voltage of the second node N2.

[0231] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 26 and the compensation electrode 27 may be an integrated structure connected to each other.

[0232] In an exemplary embodiment, a plate connection line 26-1 may be provided on the second plate 26. The plate connection line 26-1 may be in the shape of a strip extending along the first direction X and may be provided on one side of the second plate 26 in the first direction X. A first end of the plate connection line 26-1 is connected to the second plate 26 of the circuit unit in question, and a second end of the plate connection line 26-1 extends along the first direction X and is connected to the compensation electrode 27 of an adjacent circuit unit, thereby interconnecting the second plates 26 of adjacent circuit units in a unit row via the compensation electrode 27 and the plate connection line 26-1.

[0233] In an exemplary embodiment, in at least one unit row, the second plates 26, compensation electrodes 27 and plate connecting lines 26-1 of multiple circuit units can be an integrated structure connected to each other. The second plates 26, compensation electrodes 27 and plate connecting lines 26-1 of the integrated structure can be reused as power signal connecting lines to ensure that the multiple second plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0234] In an exemplary embodiment, an opening 26-2 may be provided on the second electrode plate 26. The opening 26-2 may be located in the middle of the second electrode plate 26. The opening 26-2 may be block-shaped (e.g., rectangular), so that the second electrode plate 26 forms a ring structure. The opening 26-2 exposes the third insulating layer covering the first electrode plate 25, and the orthographic projection of the first electrode plate 25 on the substrate includes the orthographic projection of the opening 26-2 on the substrate. In an exemplary embodiment, the opening 26-2 is configured to accommodate a subsequently formed eleventh via. The eleventh via is located within the opening 26-2 and exposes the first electrode plate 25, allowing a subsequently formed first connecting electrode to be connected to the first electrode plate 25.

[0235] In an exemplary embodiment, the shielding electrode 28 may be L-shaped and may be located on a side of the second plate 26 opposite the second direction Y. The orthographic projection of the shielding electrode 28 on the substrate at least partially overlaps with the orthographic projection of the first active block 11A on the substrate, and at least partially overlaps with the orthographic projection of the second active block 12A on the substrate. The shielding electrode 28 is connected to the second plate 26 at one end proximal to the second plate 26. Since the first active block 11A is disposed between the two gate electrodes of the first transistor T1, the shielding electrode 28 can effectively prevent data voltage jumps from affecting the first active layer between the two gate electrodes of the first transistor T1, thereby preventing data voltage jumps from affecting the normal operation of the pixel driving circuit and improving display quality. Since the second active block 12A is disposed between the two gate electrodes of the second transistor T2, the shielding electrode 28 can effectively prevent data voltage jumps from affecting the second active layer between the two gate electrodes of the second transistor T2 and preventing data voltage jumps from affecting the normal operation of the pixel driving circuit, thereby reducing crosstalk and improving display quality.

[0236] In an exemplary embodiment, in at least one circuit unit, the second electrode plate 26 and the shielding electrode 28 may be an integrated structure connected to each other, that is, the shielding electrode 28 is a portion of the second electrode plate 26 extending along the second direction Y.

[0237] In an exemplary embodiment, the length and width of the shielding electrode 28 can be adjusted accordingly according to the layout space conditions, and the shielding electrode 28 can also be used to form a capacitor, etc., which is not limited in this disclosure.

[0238] In an exemplary embodiment, the shape of the repair line 37 can be a straight line or a broken line with the main part extending along the first direction X, and can be arranged between the light-emitting control line 35 and the scanning connection line 36. The repair line 37 is configured as a repair line for a large-size display substrate. In the event of a defect in the pixel driving circuit, the repair line 37 can be connected to a light-emitting device separated from the pixel driving circuit to quickly repair the light-emitting device that cannot be lit, which can effectively improve the yield.

[0239] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line with the main part extending along the first direction X, and can be arranged on the side of the first gate electrode 21 away from the first electrode plate 26, and the orthographic projection of the first initial signal line 41 on the substrate at least partially overlaps with the orthographic projection of the first active connection line 10 on the substrate.

[0240] In an exemplary embodiment, in at least one repeating unit, the first initial signal line 41 may include a first initial connection portion 41-1 and a first initial bend portion 41-2. The first initial connection block 41-1 may be block-shaped (e.g., rectangular) and may be disposed on a side of the first initial signal line 41 away from the second electrode plate 26. The orthographic projection of the first initial connection block 41-1 on the substrate at least partially overlaps with the orthographic projection of the first active connection block 10A on the substrate. The first initial connection block 41-1 is configured to connect to the first active connection block 10A via a subsequently formed sixth connection electrode. The first initial bend portion 41-2 may be arc-shaped, convex toward the second electrode plate 26, and form a first groove 41-3 that exposes the first active connection block 10A. The first groove 41-3 is configured to accommodate a subsequently formed thirteenth via.

[0241] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line with the main part extending along the first direction X, and can be arranged on the side of the first connecting line 81 away from the light-emitting control line 35, and the positive projection of the third initial signal line 43 on the substrate at least partially overlaps with the positive projection of the third active connecting line 30 on the substrate.

[0242] In an exemplary embodiment, in at least one repeating unit, the third initial signal line 43 may include a third initial connection portion 43-1 and a third initial bend portion 43-2. The third initial connection portion 43-1 may be block-shaped (e.g., rectangular) and may be disposed on a side of the third initial signal line 43 away from the second electrode plate 26. The orthographic projection of the third initial connection portion 43-1 on the substrate at least partially overlaps the orthographic projection of the third active connection block 30A on the substrate. The third initial connection portion 43-1 is configured to connect to the third active connection block 30A via a subsequently formed seventh connection electrode. The third initial bend portion 43-2 may be arc-shaped, convex toward the second electrode plate 26, and may form a third groove 43-3 that exposes the third active connection block 30A. The third groove 43-3 is configured to accommodate a subsequently formed fifteenth via.

[0243] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, and providing a plurality of vias in each circuit unit, such as Figure 13 shown. Figure 13 for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 8 The via structure in area B is Figure 8 The middle A area is basically the same.

[0244] In an exemplary embodiment, the multiple vias of each circuit unit in the display area include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11 and a twelfth via V12.

[0245] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away to expose the surface of the second region of the first active layer (also the first region of the second active layer), and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the second region of the first active layer (also the first region of the second active layer) through the via hole.

[0246] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first area of the third active layer (also the second area of the fourth active layer and the second area of the fifth active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first area of the third active layer (also the second area of the fourth active layer and the second area of the fifth active layer), and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the first area of the third active layer (also the second area of the fourth active layer and the second area of the fifth active layer) through the via hole.

[0247] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the third via hole V3 are etched away to expose the surface of the first area of the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first area of the fourth active layer through the via hole.

[0248] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is within the range of the orthographic projection of the first area of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via hole V4 are etched away to expose the surface of the first area of the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed fifth connecting electrode to the first area of the fifth active layer through the via hole.

[0249] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of the sixth active layer (also the second area of the seventh active layer), and the fifth via hole V5 is configured to connect the subsequently formed fourth connecting electrode to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole.

[0250] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via V6 are etched away to expose the surface of the first region of the seventh active layer, and the sixth via V6 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via.

[0251] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second region of the eighth active layer, and the seventh via hole V7 is configured to connect a subsequently formed second connecting electrode to the second region of the eighth active layer through the via hole.

[0252] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first gate connection block 21-1 of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer in the eighth via V8 are etched away to expose the surface of the first gate connection block 21-1, and the eighth via V8 is configured to connect the subsequently formed fourth scan signal line to the first gate connection block 21-1 through the via.

[0253] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second gate connection block 22-1 of the second gate electrode 22 on the substrate, the fourth insulating layer and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the second gate connection block 22-1, and the ninth via hole V9 is configured to connect the subsequently formed first scan signal line to the second gate connection block 22-1 through the via hole.

[0254] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the fourth gate connection block 24-1 of the fourth gate electrode 24 on the substrate, the fourth insulating layer and the third insulating layer in the tenth via hole V10 are etched away to expose the surface of the fourth gate connection block 24-1, and the tenth via hole V10 is configured to connect the subsequently formed second scan signal line to the fourth gate connection block 24-1 through the via hole.

[0255] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the opening 26-2 of the second electrode plate 26 on the substrate, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away, exposing the surface of the first electrode plate 25, and the eleventh via hole V11 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 25 through the via hole.

[0256] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the compensation electrode 27 on the substrate, the fourth insulating layer in the twelfth via hole V12 is etched away to expose the surface of the compensation electrode 27, and the twelfth via hole V12 is configured to connect a subsequently formed power connection line to the compensation electrode 27 through the via hole.

[0257] In an exemplary embodiment, at least one repeating unit may further include a thirteenth via hole V13 , a fourteenth via hole V14 , a fifteenth via hole V15 , a sixteenth via hole V16 , and a seventeenth via hole V17 .

[0258] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the first active connection block 10A of the first active connection line 10 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first active connection block 10A, and the thirteenth via hole V13 is configured to connect a subsequently formed sixth connection electrode to the first active connection block 10A through the via hole.

[0259] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first initial connection portion 41-1 of the first initial signal line 41 on the substrate, the fourth insulating layer in the fourteenth via V14 is etched away, exposing the surface of the first initial connection portion 41-1, and the fourteenth via V14 is configured to connect the subsequently formed sixth connection electrode to the first initial connection portion 41-1 through the via.

[0260] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the third active connection block 30A of the third active connection line 30 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fifteenth via V15 are etched away to expose the surface of the third active connection block 30A, and the fifteenth via V15 is configured to connect the subsequently formed seventh connection electrode to the third active connection block 30A through the via.

[0261] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the third initial connection portion 43-1 of the third initial signal line 43 on the substrate, the fourth insulating layer in the sixteenth via V16 is etched away, exposing the surface of the third initial connection portion 43-1, and the sixteenth via V16 is configured to connect the subsequently formed seventh connection electrode to the third initial connection portion 43-1 through the via.

[0262] In an exemplary embodiment, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the first scan connection block 36-1 of the scan connection line 36 on the substrate, the fourth insulating layer and the third insulating layer in the seventeenth via hole V17 are etched away, exposing the surface of the first scan connection block 36-1, and the seventeenth via hole V17 is configured to connect the subsequently formed third scan signal line to the first scan connection block 36-1 through the via hole.

[0263] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, such as Figure 14A 、 Figure 14B 、 Figure 14C and Figure 14D As shown, Figure 14A for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 14B for Figure 14A A plan view of the third conductive layer in FIG. Figure 14C for Figure 8 Schematic diagram of the structure of area B in the middle. Figure 14D for Figure 14C In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0264] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display area includes: a first scan signal line 31, a second scan signal line 32, a third scan signal line 33, a fourth scan signal line 34, a second initial signal line 42, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55 and a power connection line 62.

[0265] In an exemplary embodiment, the first scan signal line 31 may be in the shape of a straight line or a zigzag line, with its main portion extending along the first direction X. It may be disposed on the side of the second electrode plate 26 opposite the second direction Y. The first scan signal line 31 is connected to the second gate connection block 22-1 in each circuit unit via a ninth via V9. Since the second gate connection block 22-1 is connected to the second gate electrode 22, the first scan signal line 31 is connected to the gate electrode of the second transistor T2 in each circuit unit. The second gate electrode 22 in the first conductive layer and the first scan signal line 31 in the third conductive layer form a dual-layer, parallel structure. The first scan signal line 31 can control the conduction or disconnection of the second transistor T2 in each circuit unit.

[0266] In an exemplary embodiment, the second scan signal line 32 may be in the shape of a straight line or a zigzag line, with its main portion extending along the first direction X. It may be disposed on a side of the first scan signal line 31 away from the second electrode plate 26 . The second scan signal line 32 is connected to the fourth gate connection block 24 - 1 via a tenth via hole V10 . Because the fourth gate connection block 24 - 1 is connected to the fourth gate electrode 24 , the fourth gate electrode 24 in the first conductive layer and the second scan signal line 32 in the third conductive layer form a dual-layer, parallel structure. This allows the second scan signal line 32 to be connected to the gate electrode of the fourth transistor T4 in each circuit unit. The second scan signal line 32 can control the conduction or disconnection of the fourth transistor T4 in each circuit unit.

[0267] In an exemplary embodiment, the shape of the third scanning signal line 33 can be a straight line or a broken line with the main part extending along the first direction X, and can be set on the side of the repair line 37 away from the second electrode plate 26, and the positive projection of the third scanning signal line 33 on the substrate at least partially overlaps with the positive projection of the scanning connection line 36 on the substrate.

[0268] In an exemplary embodiment, a second scan connection block 33-1 may be provided on the third scan signal line 33 in at least one repeating unit. The second scan connection block 33-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the third scan signal line 33 away from the second electrode plate 26 and connected to the third scan signal line 33. The orthographic projection of the second scan connection block 33-1 on the substrate at least partially overlaps with the orthographic projection of the scan connection block 36-1 on the substrate. The second scan connection block 33-1 is connected to the scan connection block 36-1 via a seventeenth via V17. Since the scan connection block 36-1 is connected to the scan connection line 36 and the second scan connection block 33-1 is connected to the third scan signal line 33, the third scan signal line 33 is connected to the gate electrode of the seventh transistor T7 and the gate electrode of the eighth transistor T8 in each circuit unit. The third scan signal line 33 can control the conduction or disconnection of the seventh transistor T7 and the eighth transistor T8 in each circuit unit.

[0269] In an exemplary embodiment, the scan connection line 36 and the third scan signal line 33 form a double-layer and parallel structure of scan signal lines, which can effectively reduce the resistance of the third scan signal line 33, reduce the voltage drop of the third scan signal, and improve the performance of the pixel driving circuit.

[0270] In an exemplary embodiment, the second scan connection block 33-1 may be provided in the circuit units of the N+1th unit column and the N+4th unit column. In at least one repeating unit, the third scan signal line 33 and the second scan connection block 33-1 may be an integral structure connected to each other.

[0271] In an exemplary embodiment, the fourth scan signal line 34 may be in the shape of a straight line or a zigzag line, with its main portion extending along the first direction X. It may be disposed on a side of the second scan signal line 32 away from the second electrode plate 26 . The fourth scan signal line 34 is connected to the first gate connection block 21 - 1 via an eighth via V8 . Because the first gate connection block 21 - 1 is connected to the first gate electrode 21 , the first gate electrode 21 in the first conductive layer and the fourth scan signal line 34 in the third conductive layer form a dual-layer, parallel structure. This allows the fourth scan signal line 34 to be connected to the gate electrode of the first transistor T1 in each circuit unit. The fourth scan signal line 34 can control the conduction or disconnection of the first transistor T1 in each circuit unit.

[0272] The present disclosure can effectively reduce the resistance of the scanning signal lines, reduce the voltage drop of the scanning signals, and improve the performance of the pixel driving circuit by setting the first scanning signal line 31, the second scanning signal line 32, the third scanning signal line 33, and the fourth scanning signal line 34 in the third conductive layer.

[0273] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main portion extending along the first direction X, and can be arranged on the side of the third scanning signal line 33 away from the second electrode plate 26. The second initial signal line 42 is connected to the first area of the seventh active layer in each circuit unit through the sixth via V6, thereby enabling the second initial signal line 42 to write the second initial signal into the first electrode of the seventh transistor T7 in each circuit unit.

[0274] In an exemplary embodiment, the power connection line 62 can be shaped like a zigzag line extending along the first direction X, and can be arranged between the first scanning signal line 31 and the third scanning signal line 33. The power connection line 62 is connected to the compensation electrode 27 in each circuit unit through the twelfth via V12. The power connection line 62 is configured to connect the first power line formed subsequently.

[0275] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip extending along the second direction Y. A first end of the first connection electrode 51 is connected to the first electrode plate 25 via an eleventh via hole V11, and a second end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) via a first via hole V1. In an exemplary embodiment, since the first electrode plate 25 can serve as the gate electrode of the third transistor T3, the first connection electrode 51 interconnects the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 25, forming a first node N1 of the pixel driving circuit.

[0276] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip extending along the second direction Y. A first end of the second connection electrode 52 is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) via a second via hole V2, and a second end of the second connection electrode 52 is connected to the second region of the eighth active layer via a seventh via hole V7. In an exemplary embodiment, the second connection electrode 52 interconnects the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, forming a second node N2 of the pixel driving circuit.

[0277] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (e.g., a rectangular shape). The third connection electrode 53 is connected to the first region of the fourth active layer through a third via hole V3. The third connection electrode 53 is configured to be connected to a subsequently formed data signal line. In an exemplary embodiment, the third connection electrode 53 may serve as a data connection electrode of the present disclosure.

[0278] In an exemplary embodiment, in at least one repeating unit, the third connection electrodes 53 of the plurality of circuit units may all be disposed on a side of the first scan signal line 31 close to the second electrode plate 26 , and the plurality of third connection electrodes 53 may be located on the same straight line extending along the first direction X.

[0279] In an exemplary embodiment, the shape of the fourth connecting electrode 54 can be block-shaped (such as rectangular), and the fourth connecting electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fifth via V5. The fourth connecting electrode 54 is configured to be connected to the subsequently formed anode connecting electrode.

[0280] In an exemplary embodiment, the fifth connection electrode 55 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the power connection line 62 away from the first scan signal line 31. A first end of the fifth connection electrode 55 is connected to the first region of the fifth active layer via a fourth via hole V4, and a second end of the fifth connection electrode 55 is connected to the power connection line 62. Because the power connection line 62 is connected to a first power line formed later, the fifth connection electrode 55 enables the first power line to write the first power signal to the first electrode of the fifth transistor T5.

[0281] In an exemplary embodiment, in at least one circuit unit, the fifth connection electrode 55 and the power connection line 62 may be an integral structure connected to each other.

[0282] In an exemplary embodiment, in at least one repeating unit, the third conductive layer may further include a sixth connection electrode 56 and a seventh connection electrode 57 .

[0283] In an exemplary embodiment, the sixth connection electrode 56 may be in the shape of a strip extending along the first direction X and may be disposed on a side of the fourth scan signal line 34 away from the second electrode plate 26. A first end of the sixth connection electrode 56 is connected to the first active connection block 10A via a thirteenth via hole V13, and a second end of the sixth connection electrode 56 is connected to the first initial connection portion 41-1 via a fourteenth via hole V14. Because the first active connection block 10A is connected to the first active connection line 10 and the first initial connection portion 41-1 is connected to the first initial signal line 41, the sixth connection electrode 56 connects the first initial signal line 41 to the first active connection line 10, forming a double-layer, parallel structure for the first initial signal line. This effectively reduces the resistance of the first initial signal line, reduces the voltage drop of the first initial signal, and effectively improves the uniformity of the first initial signal, thereby effectively improving display uniformity and enhancing display quality.

[0284] In the exemplary embodiment, since the first active connection line 10 is connected to the first region of the first active layer in each circuit unit, the first initial signal line 41 writes the first initial signal into the first electrode of the first transistor T1 in each circuit unit.

[0285] In an exemplary embodiment, the seventh connection electrode 57 may be in the shape of a strip extending along the first direction X and may be disposed on a side of the second initial signal line 42 away from the second electrode plate 26. A first end of the seventh connection electrode 57 is connected to the third active connection block 30A via a fifteenth via hole V15, and a second end of the seventh connection electrode 57 is connected to the third initial connection portion 43-1 via a sixteenth via hole V16. Because the third active connection block 30A is connected to the third active connection line 30, and the third initial connection portion 43-1 is connected to the third initial signal line 43, the seventh connection electrode 57 connects the third initial signal line 43 to the third active connection line 30, forming a double-layer, parallel structure for the third initial signal line. This effectively reduces the resistance of the third initial signal line, reduces the voltage drop of the third initial signal, and effectively improves the uniformity of the third initial signal, thereby effectively improving display uniformity and enhancing display quality.

[0286] In an exemplary embodiment, since the third active connection line 30 is connected to the first region of the eighth active layer in each circuit unit, the third initial signal line 43 writes the third initial signal into the first electrode of the eighth transistor T8 in each circuit unit.

[0287] In an exemplary embodiment, the sixth connection electrode 56 can be respectively arranged at the junction area of the N+1th unit column and the N+2th unit column, and the junction area of the N+4th unit column and the N+5th unit column, and the seventh connection electrode 57 can be respectively arranged in the circuit units of the N+1th unit column and the N+4th unit column.

[0288] like Figure 14A and Figure 14B As shown, the third conductive layer in the first area (FIP area) may further include a first connecting line 81 and a first constant voltage trace 91 .

[0289] In an exemplary embodiment, the shape of the first connecting line 81 and the first constant voltage line 91 can be a straight line or a broken line extending along the first direction X, and can be arranged between the first scanning signal line 31 and the second electrode 26 (also between the first scanning signal line 31 and the power connection line 62).

[0290] In an exemplary embodiment, a first connection block 81-1 may be provided on the first connection line 81. The first connection block 81-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the first connection line 81 close to the second electrode plate 26 and connected to the first connection line 81. The first connection block 81-1 is configured to be connected to a second connection line formed subsequently.

[0291] In an exemplary embodiment, the first connection block 81-1 may be disposed in an insertion column, and the first connection line 81 and the first connection block 81-1 may be an integral structure connected to each other. For example, the first connection block 81-1 may be disposed in an insertion column between the N+3th unit column and the N+4th unit column.

[0292] In an exemplary embodiment, at least one dummy connection block 83 may be further provided on the first connection line 81. The dummy connection block 83 may be block-shaped (e.g., rectangular) and may be provided on a side of the first connection line 81 close to the second electrode plate 26 and connected to the first connection line 81.

[0293] In an exemplary embodiment, the dummy connection block 83 may be provided in an insertion column, and the first connection line 81 and the dummy connection block 83 may be an integral structure connected to each other. For example, the dummy connection block 83 may be provided in an insertion column between the Nth unit column and the N+1th unit column.

[0294] In an exemplary embodiment, the position and shape of the dummy connection block 83 in one insertion column can be substantially identical to the position and shape of the first connection block 81-1 in another insertion column, with the difference being that the first connection block 81-1 is configured to connect to a subsequently formed second connection line, while the dummy connection block 83 is neither connected to the second connection line nor to any other traces. The present disclosure utilizes a uniform design for the transition region, which not only improves the uniformity of the subsequent etching process but also enables different locations to achieve the same display effect under both transmitted and reflected light, improving display uniformity and achieving shadow elimination, effectively avoiding poor display substrate appearance and the occurrence of off-screen watermarks (mura), and improving display quality.

[0295] In an exemplary embodiment, at least one circuit unit may further include a data connection block 84. The data connection block 84 may be block-shaped (e.g., rectangular) and may be disposed between the first connection line 81 and the third connection electrode 53. A first end of the data connection block 84 may be connected to the first connection line 81, and a second end of the data connection block 84 may be connected to the third connection electrode 53.

[0296] In an exemplary embodiment, the data connection block 84 may be provided in the circuit unit of the Mth unit row and the N+1th unit column, and the first connection line 81 , the data connection block 84 and the third connection electrode 53 may be an integrated structure connected to each other.

[0297] In an exemplary embodiment, at least one repeating unit row may be provided with at least one first connection line 81 and at least one first constant voltage trace 91. A first break DF1 may be provided between the first connection line 81 and the first constant voltage trace 91 to achieve mutual insulation between the first connection line 81 and the first constant voltage trace 91.

[0298] In one exemplary embodiment, the width of the first constant voltage trace 91 may be equal to the width of the first connecting line 81. In another exemplary embodiment, the widths of the first connecting line 81 and the first constant voltage trace 91 may be different. The widths of the first connecting line 81 and the first constant voltage trace 91 are dimensions in the second direction Y.

[0299] like Figure 14C and Figure 14D As shown, the third conductive layer in the second area (non-FIP area) may further include a first constant voltage trace 91 .

[0300] In an exemplary embodiment, the first constant voltage trace 91 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed between the first scan signal line 31 and the second electrode plate 26 (also between the first scan signal line 31 and the power connection line 62 ).

[0301] In an exemplary embodiment, at least one repeating unit row may be provided with only the first constant voltage trace 91 but not the first connection line.

[0302] In an exemplary embodiment, at least one first constant voltage connection block 91-1 may be provided on the first constant voltage trace 91. The first constant voltage connection block 91-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the first constant voltage trace 91 close to the second electrode plate 26 and connected to the first constant voltage trace 91. The first constant voltage connection block 91-1 is configured to be connected to a subsequently formed second constant voltage trace.

[0303] In an exemplary embodiment, the first constant voltage connection block 91-1 may be provided in an insertion column, and the first constant voltage trace 91 and the first constant voltage connection block 91-1 may be an integral structure connected to each other. For example, the first constant voltage connection block 91-1 may be provided in the insertion column between the (N+9)th unit column and the (N+10)th unit column, and in the insertion column between the (N+12)th unit column and the (N+13)th unit column, respectively.

[0304] In an exemplary embodiment, a frame constant voltage lead may be provided in the frame area, and the frame constant voltage lead may transmit a first power signal or a second power signal. At least one first constant voltage trace 91 may extend into the frame area and connect to the frame constant voltage lead, so that the first constant voltage trace 91 is a trace that transmits the first power signal or the second power signal.

[0305] (16) Forming a first flat layer pattern. In an exemplary embodiment, forming the first flat layer pattern may include: coating a first flat film on the substrate on which the aforementioned pattern is formed, patterning the first flat film using a patterning process to form a first flat layer covering the third conductive layer, wherein a plurality of via holes are provided on the first flat layer, such as Figure 15A and Figure 15B As shown, Figure 15A for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 15B for Figure 8 Schematic diagram of the structure of area B in the middle.

[0306] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display area includes a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 .

[0307] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the power connection line 62 on the substrate, the first flat layer in the twenty-first via V21 is removed, exposing the surface of the power connection line 62, and the twenty-first via V21 is configured to connect the subsequently formed first power line to the power connection line 62 through the via.

[0308] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer in the twenty-second via hole V22 is removed, exposing the surface of the fourth connecting electrode 54, and the twenty-second via hole V22 is configured to connect the subsequently formed anode connecting electrode to the fourth connecting electrode 54 through the via hole.

[0309] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-third via hole V23 is removed, exposing the surface of the third connecting electrode 53, and the twenty-third via hole V23 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.

[0310] In an exemplary embodiment, since the third connection electrode 53 in the circuit unit of the Mth unit row and the N+1th unit column is connected to the first connection line 81 through the data connection block 84, the twenty-third via V23 in the circuit unit of the Mth unit row and the N+1th unit column can serve as the first connection hole of the present disclosure.

[0311] like Figure 15A As shown, the first flat layer of the first region may further include a twenty-fourth via V24. In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the orthographic projection of the first connection block 81-1 of the first connection line 81 on the substrate. The first flat layer within the twenty-fourth via V24 is removed, exposing the surface of the first connection block 81-1. The twenty-fourth via V24 is configured to connect a subsequently formed second connection line to the first connection block 81-1 through this via. In an exemplary embodiment, the twenty-fourth via V24 may serve as the second connection hole of the present disclosure.

[0312] like Figure 15B As shown, the first flat layer of the second region may further include a twenty-fifth via V25. In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the first constant voltage connection block 91-1 of the first constant voltage trace 91 on the substrate. The first flat layer within the twenty-fifth via V25 is removed, exposing the surface of the first constant voltage connection block 91-1. The twenty-fifth via V25 is configured to connect the subsequently formed second constant voltage trace to the first constant voltage connection block 91-1 through the via. In an exemplary embodiment, the twenty-fifth via V25 may serve as the third connection hole of the present disclosure.

[0313] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on the first flat layer, such as Figure 16A 、 Figure 16B 、 Figure 16C and Figure 16D As shown, Figure 16A for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 16B for Figure 16A A plan view of the fourth conductive layer in FIG. Figure 16C for Figure 8 Schematic diagram of the structure of area B in the middle. Figure 16D for Figure 16C In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0314] In an exemplary embodiment, the fourth conductive layer pattern of each circuit unit in the display area includes at least a first power supply line 61 , an anode connection electrode 63 , and a data signal line 70 .

[0315] In an exemplary embodiment, the shape of the first power line 61 can be a straight line or a broken line with the main portion extending along the second direction Y. The first power line 61 is connected to the power connection line 62 through the twenty-first via V21, thereby realizing the mutual connection between the power connection line 62 extending along the first direction X and the first power line 61 extending along the second direction Y. The power connection line 62 and the first power line 61 form a mesh connection structure for transmitting the first power signal, which can effectively reduce the resistance of the first power line, effectively reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0316] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. Because the first connection electrode 51 serves as the first node N1 in the pixel driving circuit, the first power line 61, which has a constant voltage, can effectively shield the first node N1 from the effects of other signals in the pixel driving circuit. This prevents other signals (such as data voltage jumps) from affecting the potential of the first node N1 of the pixel driving circuit, reduces crosstalk, and improves display quality.

[0317] In an exemplary embodiment, an orthographic projection of the first power line 61 on the substrate may include an orthographic projection of the first connection electrode 51 on the substrate.

[0318] In an exemplary embodiment, the first power lines 61 may be designed with unequal widths. The unequal width design of the first power lines 61 not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power lines and the data signal lines.

[0319] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate may include the orthographic projection of the first break DF1 on the first connecting line 81 on the substrate, so that the first power line 61 can block the first break DF1 from above, which can effectively eliminate the film layer differences in different areas, is conducive to shadow elimination, and avoids poor appearance of the display substrate.

[0320] In an exemplary embodiment, the anode connection electrode 63 may be in the shape of a strip extending along the first direction X. The anode connection electrode 63 is connected to the fourth connection electrode 54 through the twenty-second via hole V22. The anode connection electrode 63 is configured to be connected to a subsequently formed anode. Since the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the via hole, the pixel driving circuit is enabled to drive the light-emitting device to emit light.

[0321] In an exemplary embodiment, the data signal line 70 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 70 is connected to the third connection electrode 53 through the twenty-third via hole V23. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 70 writes the data signal to the first electrode of the fourth transistor T4.

[0322] In an exemplary embodiment, since the third connection electrode 53 in the circuit unit of the Mth unit row and the N+1th unit column is connected to the first connection line 81 through the data connection block 84, the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column is achieved.

[0323] like Figure 16A and Figure 16B As shown, the fourth conductive layer in the first region may further include a second connection line 82 and a second constant voltage trace 92. The second connection line 82 and the second constant voltage trace 92 may be in the shape of a straight line or a broken line with the main portion extending along the second direction Y, and may be respectively arranged in the insertion column.

[0324] In an exemplary embodiment, a second connection block 82-1 may be provided on the second connection line 82. The second connection block 82-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the second connection line 82 opposite to the first direction X. The second connection block 82-1 is connected to the second connection line 82. The second connection block 82-1 is connected to the first connection block 81-1 via the twenty-fourth via V24. Since the first connection block 81-1 is connected to the first connection line 81 and the second connection block 82-1 is connected to the second connection line 82, a connection is established between the first connection line 81 in the Mth cell row and the second connection line 82 located in the intervening column between the N+3th cell column and the N+4th cell column. Due to the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column, the second connection line 82 in the inserted column, the first connection line 81 in the Mth unit row, and the data signal line 70 in the N+1th unit column are connected in sequence, and the data signal in the binding area can be transmitted to the data signal line 70 through the first connection line 81 and the second connection line 82.

[0325] In an exemplary embodiment, at least one second connecting line 82 and at least one second constant voltage line 92 may be provided in at least one insertion column, and a second break DF2 may be provided between the second connecting line 82 and the second constant voltage line 92 so that the second connecting line 82 and the second constant voltage line 92 located on both sides of the second break DF2 are insulated from each other.

[0326] In an exemplary embodiment, the orthographic projection of the second fracture DF2 on the substrate can be located within the range of the orthographic projection of the first initial signal line 41 on the substrate, so that the first initial signal line 41 can pad the second fracture DF2 from the bottom, which can effectively eliminate the film layer differences in different areas, is conducive to eliminating shadows, and avoids poor appearance of the display substrate.

[0327] In some possible embodiments, the orthographic projection of the second break DF2 on the substrate may be within the range of the orthographic projection of the second initial signal line 42 on the substrate, or the orthographic projection of the second break DF2 on the substrate may be within the range of the orthographic projection of the third initial signal line 43 on the substrate, or the orthographic projection of the second break DF2 on the substrate may be within the range of the orthographic projection of the power connection line 62 on the substrate.

[0328] In some other possible implementations, the orthographic projection of the second fracture DF2 on the substrate may be located within the range of the orthographic projection of the first connection line 81 on the substrate, which is not limited in the present disclosure.

[0329] In an exemplary embodiment, in at least one repeating unit, an orthographic projection of the second connection block 82 - 1 on the substrate at least partially overlaps with an orthographic projection of the dummy connection block 83 on the substrate.

[0330] In one exemplary embodiment, the width of the second constant voltage trace 92 may be equal to the width of the second connecting line 82. In another exemplary embodiment, the widths of the second connecting line 82 and the second constant voltage trace 92 may be different. The widths of the second connecting line 82 and the second constant voltage trace 92 are dimensions in the first direction X.

[0331] like Figure 16C and Figure 16D As shown, the fourth conductive layer in the second region may further include a second constant voltage trace 92 . The second constant voltage trace 92 may be in the shape of a straight line or a broken line with the main portion extending along the second direction Y, and may be arranged in a corresponding insertion column.

[0332] In an exemplary embodiment, at least one second constant voltage connection block 92-1 may be provided on the second constant voltage trace 92. The second constant voltage connection block 92-1 may be block-shaped (e.g., rectangular) and may be provided on a side opposite to the first direction X of the second constant voltage trace 92, and connected to the second constant voltage trace 92. The second constant voltage connection block 92-1 is connected to the first constant voltage connection block 91-1 via the twenty-fifth via V25. Since the first constant voltage connection block 91-1 is connected to the first constant voltage trace 91, and the second constant voltage connection block 92-1 is connected to the second constant voltage trace 92, the first constant voltage trace 91 extending along the first direction X and the second constant voltage trace 92 extending along the second direction Y are interconnected. The first constant voltage trace 91 and the second constant voltage trace 92 form a meshed interconnected structure for transmitting a constant voltage signal, which can effectively reduce the resistance of the constant voltage signal line, effectively reduce the voltage drop of the constant voltage signal, effectively improve the uniformity of the constant voltage signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0333] In an exemplary embodiment, at least one insertion column may be provided with only the second constant voltage trace 92 without any second connection line.

[0334] In an exemplary embodiment, in at least one repeating unit, an orthographic projection of the second constant voltage connection block 92 - 1 on the substrate at least partially overlaps with an orthographic projection of the dummy connection block 83 on the substrate.

[0335] In an exemplary embodiment, at least one first power line 61 may be disposed between the data signal line 70 and the second connection line 82 , or at least one first power line 61 may be disposed between the data signal line 70 and the second constant voltage trace 92 .

[0336] In an exemplary embodiment, the orthographic projection of at least one second connecting line 82 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 28 on the substrate, or the orthographic projection of at least one second constant voltage trace 92 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 28 on the substrate.

[0337] In an exemplary embodiment, the binding region may be provided with a binding constant voltage lead, which may transmit a first power signal or a second power signal. At least one second constant voltage trace 92 may extend to the binding region and connect to the binding constant voltage lead, thereby transmitting the first power signal or the second power signal.

[0338] In an exemplary embodiment, the first constant voltage trace 91 and the second constant voltage trace 92 are both traces for transmitting the first power signal, forming a meshed connection structure for transmitting the first power signal.

[0339] In an exemplary embodiment, the first constant voltage trace 91 and the second constant voltage trace 92 are both traces for transmitting the second power signal, forming a meshed connection structure for transmitting the second power signal.

[0340] In some possible implementations, the second constant voltage trace 92 may be directly connected to the first power line 61 via a connecting bar, which is not limited in the present disclosure.

[0341] (18) Forming a second flat layer pattern. In an exemplary embodiment, forming the second flat layer pattern may include: coating a second flat film on the substrate formed with the aforementioned pattern, patterning the second flat film using a patterning process to form a second flat layer covering the fourth conductive layer, and providing a plurality of via holes on the second flat layer, such as Figure 17 shown. Figure 17 for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 8 The via structure in area B is Figure 8 The middle A area is basically the same.

[0342] In an exemplary embodiment, the plurality of via holes of each circuit unit in the display area may include an anode via hole V30 .

[0343] In an exemplary embodiment, the orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connecting electrode 63 on the substrate, the second flat layer in the anode via V30 is removed to expose the surface of the anode connecting electrode 63, and the anode via V30 is configured to connect a subsequently formed anode to the anode connecting electrode 63 through the via.

[0344] At this point, the drive structure layer is prepared on the substrate. In a plane parallel to the display substrate, the drive structure layer may include a plurality of circuit units, each circuit unit may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light emitting control line, a first initial signal line, a second initial signal line, a third initial signal line, a first power line and a data signal line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive structure layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first flat layer, a fourth conductive layer and a second flat layer stacked in sequence on the substrate.

[0345] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0346] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of an organic material, such as a resin. The active layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0347] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0348] (19) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate having the aforementioned pattern formed thereon, patterning the anode conductive film using a patterning process, and forming an anode conductive layer disposed on the second flat layer, such as Figure 18A and Figure 18B As shown, Figure 18B for Figure 18A Schematic plan view of the anode conductive layer. Figure 18A for Figure 8 Schematic diagram of the structure of area A in the middle. Figure 8 The anode conductive layer pattern in the B area Figure 8 The middle A area is basically the same.

[0349] In an exemplary embodiment, the anode conductive layer may include at least a plurality of anode patterns. The plurality of anode patterns may include a first anode 130A for a red light-emitting unit, a second anode 130B for a green light-emitting unit, and a third anode 130C for a blue light-emitting unit. The first anodes 130A and the second anodes 130B may be alternately arranged along the second direction Y, and the third anode 130C may be arranged on one side of the second anode 130B in the first direction X. The first anode 130A, the second anode 130B, and the third anode 130C may be connected to the anode connection electrode 63 of the corresponding circuit unit through the anode via V30.

[0350] In an exemplary embodiment, at least one of the first anode 130A, the second anode 130B and the third anode 130C may include an anode main body and an anode connecting portion that are connected to each other. The shape of the anode main body may be rectangular, and the corners of the rectangle may be chamfered. The shape of the anode connecting portion may be block-shaped (such as a rectangle), and the anode connecting portion is connected to the anode connecting electrode 63 through the anode via V30.

[0351] In an exemplary embodiment, the orthographic projections of the anode body portions of at least one first anode 130A and at least one second anode 130B on the substrate at least partially overlap with the orthographic projections of the first power line 61 and the second connecting line 82 on the substrate, or the orthographic projections of the anode body portions of at least one first anode 130A and at least one second anode 130B on the substrate at least partially overlap with the orthographic projections of the first power line 61 and the second constant voltage trace 92 on the substrate.

[0352] In an exemplary embodiment, an orthographic projection of an anode body portion of at least one third anode 130C on the substrate at least partially overlaps with an orthographic projection of one data signal line 70 and two first power lines 61 on the substrate, and in the first direction X, the data signal line 70 is disposed between the two first power lines 61.

[0353] In an exemplary embodiment, an anode groove 131 may be provided on the anode body of at least one third anode 130C. The anode groove 131 may be in the shape of a strip extending along the second direction Y and may be provided in a central region of the anode body of the third anode 130C in the first direction X. The orthographic projection of the anode groove 131 on the substrate at least partially overlaps with the orthographic projection of the data signal line 70 on the substrate. That is, the anode body of the third anode 130C has a bifurcated structure, and the bifurcated position avoids the data signal line 70. This can effectively reduce the impact of data voltage jumps on the data signal line on the anode potential, thereby improving the display effect.

[0354] In an exemplary embodiment, the anode body portion of the third anode 130C may have a first length L1, and the anode groove 131 may have a second length L2. The ratio of the second length L2 to the first length L1 may be 0.3 to 0.7. The first length L1 is the average dimension of the anode body portion of the third anode 130C in the second direction Y, and the second length L2 is the average dimension of the anode groove 131 in the second direction Y.

[0355] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0356] In an exemplary embodiment, the subsequent preparation process may include: first forming a pixel definition layer pattern, then using an evaporation or inkjet printing process to form an organic light-emitting layer, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0357] The exemplary embodiments of the present disclosure provide a display substrate. By setting data connection lines in the display area, the data lead lines in the binding area are connected to the data signal lines through the data connection lines, thereby realizing a FIP structure. This eliminates the need for fan-shaped oblique lines in the lead line area, effectively reducing the length of the lead line area, greatly reducing the width of the lower frame, and improving the screen-to-body ratio, which is conducive to achieving full-screen display. The present disclosure adopts a multi-plug 1 (such as 3 plugs 1) design for FIP routing, in which the second connection line is set in an insertion column between the repeating units. This can reduce the density of the longitudinal routing while reducing the width of the lower frame, reducing defects and improving the yield rate.

[0358] The present disclosure provides a first constant voltage line and a second constant voltage line for transmitting a first power signal or a second power signal within a display area, and forms a meshed connection structure for transmitting the first power signal or the second power signal. This effectively reduces the resistance of the first power signal or the second power line, effectively reduces the voltage drop of the first power signal or the second power signal, and achieves low power consumption. It also effectively improves the uniformity of the first power signal or the second power signal in the display substrate, effectively improving display uniformity, and improving display quality.

[0359] The present disclosure realizes the VSS inpixel structure by forming a mesh connection structure for transmitting the second power supply signal in the display area, which can greatly reduce the width of the constant voltage lead of the frame, greatly reduce the width of the left and right frames, improve the screen-to-body ratio, and facilitate the realization of full-screen display.

[0360] The present disclosure arranges the data connection line in the first area and the constant voltage line in the second area, so that the first area and the second area have basically the same routing structure. Different areas can achieve basically the same display effect under transmitted light and reflected light, effectively avoiding the poor appearance of the display substrate and improving the display quality.

[0361] The present disclosure provides a double-layer structure for the first initial signal line and the third initial signal line, which can effectively reduce the resistance of the first initial signal line and the third initial signal line, reduce the voltage drop of the first initial signal and the third initial signal, effectively improve the uniformity of the first initial signal and the third initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0362] The present disclosure arranges multiple scanning signal lines in the third conductive layer, and the third scanning signal line has a double-layer structure, which can effectively reduce the resistance of the scanning signal line, reduce the voltage drop of the scanning signal, and improve the performance of the pixel driving circuit.

[0363] The present disclosure sets a repair line in the display area. When a defect occurs in the pixel driving circuit, the repair line can be connected to the light-emitting device separated from the pixel driving circuit to quickly repair the light-emitting device that cannot be illuminated, thereby effectively improving the yield.

[0364] The present disclosure sets the third anode as a bifurcated structure, and the bifurcated position avoids the data signal line, which can effectively reduce the influence of the data voltage jump on the data signal line on the anode potential and improve the display effect.

[0365] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0366] Figure 19This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8 In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The illustrated embodiments are substantially the same, except that the first connection line 81 may be provided between the first scan signal line 31 and the second scan signal line 32 .

[0367] In an exemplary embodiment, in at least one repeating unit row in the first region, the shapes of the fourth active layers 14 of multiple circuit units are differentiated, and the first area of the fourth active layer of at least one circuit unit is arranged between the first scanning signal line 31 and the second scanning signal line 32, while the first areas of the fourth active layers of other circuit units are arranged between the first scanning signal line 31 and the second electrode plate, and are located on the same straight line extending along the first direction X.

[0368] In an exemplary embodiment, in at least one repeating unit row in the first region, the first connection line 81 may be disposed between the first scan signal line 31 and the second scan signal line 32. A data connection block 84 may also be disposed in one circuit unit. The data connection block 84 may be block-shaped (e.g., rectangular) and may be disposed on a side of the first connection line 81 close to the first scan signal line 31 and connected to the first connection line 81. The data connection block 84 may be connected to the first region of the fourth active layer in the circuit unit through a via hole, while other circuit units still adopt a structure in which the third connection electrode is connected to the first region of the fourth active layer through a via hole.

[0369] In an exemplary embodiment, in at least one repeating unit row, the data connection block 84 may be disposed on a side of the first scan signal line 31 away from the second electrode plate, and the first connection line 81 and the data connection block 84 may be an integrated structure connected to each other.

[0370] In an exemplary embodiment, the data connection block 84 can be set in the circuit unit of the Mth unit row and the N+1th unit column, and the data signal line in the N+1th unit column can be connected to the data connection block 84 through a via, thereby realizing the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column.

[0371] In some possible embodiments, the first regions of the fourth active layers of multiple circuit units in a repeating unit row may be arranged between the first scan signal line 31 and the second scan signal line 32 , which is not limited in the present disclosure.

[0372] Figure 20 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The embodiments shown are basically the same, except that the first connection line 81 and the first power line 91 can be arranged on the side of the luminous signal line 25 away from the power connection line 62, that is, the luminous signal line 25 can be located between the power connection line 62 and the first connection line 81.

[0373] In an exemplary embodiment, in at least one repeating unit row in the first region, the first connection line 81 and the first power trace 91 can be arranged on a side of the second initial signal line 42 away from the power connection line 62, and in at least one repeating unit row in the second region, the first power trace 91 can be arranged on a side of the second initial signal line 42 away from the power connection line 62.

[0374] In an exemplary embodiment, the orthographic projection of the first connecting line 81 or the first power supply line 91 on the substrate at least partially overlaps with the orthographic projection of the third initial signal line 43 on the substrate. The third initial signal line 43 with a constant voltage can effectively shield the influence of the data voltage jump in the first connecting line 81 on the pixel driving circuit and reduce crosstalk.

[0375] In an exemplary embodiment, at least one repeating unit row in the first region may also be provided with a data connection block 84. The data connection block 84 may be in the shape of a block (such as a rectangle) and may be provided on the side of the first connection line 81 away from the second initial signal line 42 and connected to the first connection line 81. The data signal line 70 may be connected to the data connection block 84 through a via, thereby realizing the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column.

[0376] Figure 21 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8 In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The illustrated embodiments are substantially the same, except that the first connection line 81 and the first power supply line 91 may be arranged on a side of the luminous signal line 25 away from the power supply connection line 62 , and the second initial signal line 42 may be arranged in the second conductive layer.

[0377] In an exemplary embodiment, in at least one repeating unit row in the first area, the first connecting line 81 and the first power supply line 91 can be set between the luminous signal line 25 and the third initial signal line 43, and in at least one repeating unit row in the second area, the first power supply line 91 can be set between the luminous signal line 25 and the third initial signal line 43.

[0378] In an exemplary embodiment, the orthographic projection of the first connecting line 81 or the first power supply line 91 on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 on the substrate. Not only can the second initial signal line 42 with a constant voltage effectively shield the impact of the data voltage jump in the first connecting line 81 on the pixel driving circuit and reduce crosstalk, but it can also save wiring space as much as possible, which is conducive to achieving a higher resolution (PPI).

[0379] In an exemplary embodiment, a data connection block 84 may be provided in at least one repeating unit row in the first region. The data connection block 84 may be in the shape of a block (such as a rectangle) and may be provided on the side of the first connection line 81 away from the third initial signal line 43 and connected to the first connection line 81. The data signal line 70 may be connected to the data connection block 84 through a via, thereby realizing the connection between the first connection line 81 in the Mth unit row and the data signal line 70 in the N+1th unit column.

[0380] In an exemplary embodiment, this example shows the preparation process of the substrate. 9A to 9D The illustrated embodiments are substantially the same, except that the second conductive layer further includes a second initial signal line, and the second initial signal line 42 can be disposed between the third scanning signal line 33 and the third initial signal line 43 .

[0381] In an exemplary embodiment, the positions of the third scan signal line 33 and the scan connection line 36 can be appropriately moved upward according to the layout space. For example, the repair line can be removed to leave space for the second initial signal line 42.

[0382] Figure 22 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8 In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The illustrated embodiment is substantially the same, except that a constant voltage connection line 93 is further provided in the insertion column.

[0383] In an exemplary embodiment, at least one insertion column may be provided with two vertical lines, which may be the second connection line 82 and the constant voltage connection line 93 , or the second power supply line 92 and the constant voltage connection line 93 .

[0384] In an exemplary embodiment, the constant voltage connection line 93 may be in the shape of a straight line or a broken line, with the main portion extending along the second direction Y. The constant voltage connection line 93 may be disposed between the second connection line 82 and the adjacent data signal line 70, or the constant voltage connection line 93 may be disposed between the second power supply line 92 and the adjacent data signal line 70. By disposing the constant voltage connection line 93 between the second connection line 82 and the data signal line 70, the present disclosure can effectively avoid crosstalk of data signals.

[0385] In an exemplary embodiment, the second connection line 82 , the second power supply line 92 , and the constant voltage connection line 93 may be disposed in the same conductive layer and simultaneously formed through the same patterning process.

[0386] In an exemplary embodiment, at least one fourth connection block 94 may be provided on the constant voltage connection line 93. The fourth connection block 94 may be block-shaped (e.g., rectangular) and may be provided on one side of the constant voltage connection line 93 in the first direction X or on a side opposite to the first direction X, and connected to the constant voltage connection line 93. The fourth connection block 94 may be connected to the second initial signal line 42 via a via, thereby achieving interconnection between the second initial signal line 42 extending along the first direction X and the constant voltage connection line 93 extending along the second direction Y. The second initial signal line 42 and the constant voltage connection line 93 form a meshed interconnected structure for transmitting the second initial signal, which can effectively reduce the resistance of the second initial signal line, effectively reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal, effectively improve display uniformity, and improve display quality and display quality.

[0387] In some possible embodiments, the constant voltage connection line 93 can be connected to the first initial signal line 41, thereby realizing the mutual connection between the first initial signal line 41 extending along the first direction X and the constant voltage connection line 93 extending along the second direction Y. The first initial signal line 41 and the constant voltage connection line 93 form a mesh connection structure for transmitting the first initial signal, which can effectively reduce the resistance of the first initial signal line, effectively reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0388] In other possible embodiments, a constant voltage connection line 93 inserted in a column can be connected to the third initial signal line 43, thereby realizing the interconnection of the third initial signal line 43 extending along the first direction X and the constant voltage connection line 93 extending along the second direction Y. The third initial signal line 43 and the constant voltage connection line 93 form a mesh connection structure for transmitting the third initial signal, which can effectively reduce the resistance of the third initial signal line, effectively reduce the voltage drop of the third initial signal, effectively improve the uniformity of the third initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0389] In some other possible embodiments, the constant voltage connection line 93 in one insertion column can be connected to the first initial signal line 41, the constant voltage connection line 93 in another insertion column can be connected to the second initial signal line 42, and the constant voltage connection line 93 in yet another insertion column can be connected to the third initial signal line 43, thereby simultaneously forming a meshed connection structure for transmitting the first initial signal, a meshed connection structure for transmitting the second initial signal, and a meshed connection structure for transmitting the third initial signal on the display substrate. For example, in the first direction X, the constant voltage connection line 93 connected to the first initial signal line 41, the constant voltage connection line 93 connected to the second initial signal line 42, and the constant voltage connection line 93 connected to the third initial signal line 43 can be arranged periodically.

[0390] Figure 23 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8 In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The illustrated embodiments are substantially the same, except that a constant voltage connection line 93 is further provided in the cell column.

[0391] In an exemplary embodiment, three vertical lines may be provided in at least one cell column, and the three vertical lines may be a first power line 61 , a data signal line 70 , and a constant voltage connection line 93 .

[0392] In an exemplary embodiment, the second connection line 82 , the second power supply line 92 , and the constant voltage connection line 93 may be disposed in the same conductive layer and simultaneously formed through the same patterning process.

[0393] In an exemplary embodiment, at least one connection block may be connected to the constant voltage connection line 93, and the connection block is configured to be connected to the first initial signal line 41, the second initial signal line 42 or the third initial signal line 43 through a via to form a mesh connection structure for transmitting the first initial signal, the second initial signal or the third initial signal.

[0394] In some possible embodiments, the constant voltage connection line 93 in one unit column can be connected to the first initial signal line 41, the constant voltage connection line 93 in another unit column can be connected to the second initial signal line 42, and the constant voltage connection line 93 in yet another unit column can be connected to the third initial signal line 43, thereby simultaneously forming a meshed connection structure for transmitting the first initial signal, a meshed connection structure for transmitting the second initial signal, and a meshed connection structure for transmitting the third initial signal on the display substrate. For example, in the first direction X, the constant voltage connection line 93 connected to the first initial signal line 41, the constant voltage connection line 93 connected to the second initial signal line 42, and the constant voltage connection line 93 connected to the third initial signal line 43 can be arranged periodically.

[0395] In some other possible implementations, Figure 22 The illustrated embodiments and Figure 23 The shown embodiments can be combined into a new scheme, in which two vertical lines (a second connection line 82 and a constant voltage connection line 93) are provided in the insertion column, and three vertical lines (a first power line 61, a data signal line 70 and a constant voltage connection line 93) are provided in the unit column, that is, the second connection line 82 is a 3-in-1 structure, and the constant voltage connection line is a 1-in-1 structure, which can further stabilize the constant voltage signal and further reduce power consumption.

[0396] Figure 24 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8 In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The illustrated embodiments are substantially the same, except that the second constant voltage trace 92 is connected to the first initial signal line 41 .

[0397] In an exemplary embodiment, at least one circuit unit may further include an active connection bar 19 and an eighth connection electrode 58. The active connection bar 19 may be in the shape of a bar extending along the second direction Y and may be disposed on a side of the first active connection line 10 close to the power connection line 62. A first end of the active connection bar 19 is connected to the first active connection line 10, and a second end of the active connection bar 19 extends in a direction close to the power connection line 62. The eighth connection electrode 58 may be in the shape of a block (e.g., a rectangle) and may be disposed on a side of the first active connection line 10 close to the power connection line 62. The eighth connection electrode 58 may be connected to the second end of the active connection bar 19 through a via.

[0398] In an exemplary embodiment, in at least one circuit unit, the first active connection line 10 and the active connection bar 19 may be disposed in the same layer and be an integrated structure connected to each other.

[0399] In exemplary embodiments, the eighth connection electrode 58 may be provided in the third conductive layer.

[0400] In an exemplary embodiment, at least one fifth connection block 95 may be further provided on at least one second constant-voltage trace 92. The fifth connection block 95 may be block-shaped (e.g., rectangular) and may be provided on one side of the second constant-voltage trace 92 in the first direction X. The fifth connection block 95 may be connected to the sixth connection electrode 56 via a via. Since the first active connection line 10 is connected to the first initial signal line 41, the first initial signal line 41 extending along the first direction X and the second constant-voltage trace 92 extending along the second direction Y are interconnected. The first initial signal line 41 and the second constant-voltage trace 92 form a meshed connection structure for transmitting the first initial signal.

[0401] In some possible implementations, the first constant voltage trace 91 or the second constant voltage trace 92 may extend to the frame area and be connected to a lead that transmits the first initial signal, which is not limited in the present disclosure.

[0402] Figure 25 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8 In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The illustrated embodiments are substantially the same, except that the second constant voltage trace 92 is connected to the second initial signal line 42 .

[0403] In an exemplary embodiment, at least one fifth connection block 95 may be further provided on at least one second constant-voltage trace 92. The fifth connection block 95 may be block-shaped (e.g., rectangular) and may be provided on a side of the second constant-voltage trace 92 opposite to the first direction X, and connected to the second constant-voltage trace 92. The fifth connection block 95 may be connected to the second initial signal line 42 via a via, thereby interconnecting the second initial signal line 42 extending along the first direction X and the second constant-voltage trace 92 extending along the second direction Y. The second initial signal line 42 and the second constant-voltage trace 92 form a meshed connection structure for transmitting the second initial signal.

[0404] In some possible implementations, the first constant voltage trace 91 or the second constant voltage trace 92 may extend to the frame area and be connected to a lead that transmits the second initial signal, which is not limited in the present disclosure.

[0405] Figure 26 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8 In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The illustrated embodiments are substantially the same, except that the second constant voltage trace 92 is connected to the third initial signal line 43 .

[0406] In an exemplary embodiment, at least one fifth connection block 95 may be further provided on at least one second constant-voltage trace 92. The fifth connection block 95 may be block-shaped (e.g., rectangular) and may be provided on a side of the second constant-voltage trace 92 opposite to the first direction X, and connected to the second constant-voltage trace 92. The fifth connection block 95 may be connected to the third initial signal line 43 via a via, thereby interconnecting the third initial signal line 43 extending along the first direction X and the second constant-voltage trace 92 extending along the second direction Y. The third initial signal line 43 and the second constant-voltage trace 92 form a meshed connection structure for transmitting the third initial signal.

[0407] In some possible implementations, the first constant voltage trace 91 or the second constant voltage trace 92 may extend to the frame area and be connected to a lead that transmits the third initial signal, which is not limited in the present disclosure.

[0408] In some possible implementations, Figures 24 to 26 In the illustrated embodiment, a second constant voltage trace 92 is provided to be connected to the first constant voltage trace 91 through a via, and the initial signal line (the first initial signal line 41, the second initial signal line 42 or the third initial signal line 43) extending along the first direction X and the first constant voltage trace 91 and the second constant voltage trace 92 extending along the second direction Y form a mesh connection structure for transmitting the initial signal.

[0409] In some other possible implementations, Figures 24 to 26 In the illustrated embodiment, there is no connection between the first constant voltage trace 91 and the second constant voltage trace 92, and the first constant voltage trace 91 and the second constant voltage trace 92 respectively transmit different constant voltage signals. For example, the first constant voltage trace 91 can transmit the first power signal or the second power signal, and the second constant voltage trace 92 connected to the initial signal line (the first initial signal line 41, the second initial signal line 42, or the third initial signal line 43) can transmit the initial signal.

[0410] In some other possible implementations, Figures 24 to 26 In the illustrated embodiment, a portion of the second constant voltage trace 92 is connected to a portion of the first constant voltage trace 91 through a via, while another portion of the first constant voltage trace 91 is not connected to another portion of the second constant voltage trace 92. The two portions of the second constant voltage trace 92 transmit different constant voltage signals respectively.

[0411] For example, the second constant voltage trace 92 in the same insertion column as the second connection line 82 can be connected to the first power line or the second power line, and connected to the first constant voltage trace 91 separately arranged in the repeating unit row through a via, forming a meshed connectivity structure for transmitting the first power signal or the second power signal. The second constant voltage trace 92 separately arranged in the insertion column can be connected to the initial signal line (the first initial signal line 41, the second initial signal line 42 or the third initial signal line 43) to form a meshed connectivity structure for transmitting the initial signal. This connection method can realize the formation of different constant potential traces in a network, make full use of the wiring space, and significantly reduce power consumption.

[0412] For another example, a first constant voltage trace 91 provided on the same layer as the first connection line 81 can transmit a first power signal or a second power signal, a portion of a second constant voltage trace 92 provided on the same layer as the second connection line 82 can be connected to the first constant voltage trace 91, and another portion of the second constant voltage trace 92 can be connected to the first initial signal line 41 or the third initial signal line 43 located in the second conductive layer. The two portions of the second constant voltage trace 92 can be alternately arranged in the first direction X. This connection method enables routing of different film layers, increases available space, enables more potential grids, and reduces power consumption.

[0413] Figure 27 This is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure. Figure 8 In the exemplary embodiment, this embodiment shows the main structure of the substrate and 9A to 9D The illustrated embodiments are substantially the same, except that the second constant voltage trace 92 is connected to the first initial signal line 41 and the second initial signal line 42 , respectively.

[0414] In an exemplary embodiment, one second constant voltage trace 92 can be connected to the first initial signal line 41 to form a meshed connection structure for transmitting the first initial signal, and another second constant voltage trace 92 can be connected to the second initial signal line 42 to form a meshed connection structure for transmitting the second initial signal. Figure 24 The embodiment shown is basically the same, and the connection structure between the second constant voltage trace 92 and the second initial signal line 42 can be the same as Figure 25 The embodiments shown are basically the same and will not be described again here.

[0415] In an exemplary embodiment, a third break DF3 may be provided on at least one first constant voltage trace 91, and the first constant voltage traces 91 located on both sides of the third break DF3 are insulated from each other, thereby cutting off the connection between the mesh connection structure transmitting the first initial signal and the mesh connection structure transmitting the second initial signal.

[0416] In some possible embodiments, the display substrate can be divided into multiple sub-areas, and the multiple second constant voltage traces 92 in one sub-area can be connected to the first initial signal line 41, the multiple second constant voltage traces 92 in another sub-area can be connected to the second initial signal line 42, and the multiple second constant voltage traces 92 in yet another sub-area can be connected to the third initial signal line 43, and a meshed interconnected structure for transmitting the first initial signal, a meshed interconnected structure for transmitting the second initial signal, and a meshed interconnected structure for transmitting the third initial signal are simultaneously formed on the display substrate. For example, in the first direction X or the second direction Y, the meshed interconnected structure for transmitting the first initial signal, the meshed interconnected structure for transmitting the second initial signal, and the meshed interconnected structure for transmitting the third initial signal can be periodically arranged.

[0417] In other possible implementations, the plurality of second constant voltage traces 92 in the second region may be respectively connected to the first initial signal line 41, the second initial signal line 42, the third initial signal line 43, and the second power line. For example, the second constant voltage trace 92 connected to the first initial signal line 41, the second constant voltage trace 92 connected to the second power line, the second constant voltage trace 92 connected to the second initial signal line 42, the second constant voltage trace 92 connected to the second power line, the second constant voltage trace 92 connected to the third initial signal line 43, and the second constant voltage trace 92 connected to the second power line may be periodically arranged.

[0418] In some other possible embodiments, the multiple second constant voltage lines 92 in the first area can be connected to the first power line or the second power line to form a mesh connectivity structure for transmitting the first power signal or the second power signal, and the multiple second constant voltage lines 92 in the second area can be connected to the first initial signal line 41, the second initial signal line 42 or the third initial signal line 43 to form a mesh connectivity structure for transmitting the first initial signal, the second initial signal or the third initial signal.

[0419] In some other possible embodiments, the second constant voltage line 92 located in the same insertion column as the second connecting line 82 can be connected to the first initial signal line 41, the second initial signal line 42 or the third initial signal line 43, and the second constant voltage line 92 separately arranged in the insertion column can be connected to the first power line or the second power line. This disclosure does not limit this.

[0420] Figure 28 FIG. 1 is a structural diagram of another data connection line and constant voltage line according to an exemplary embodiment of the present disclosure. Figure 28 As shown, the main structure of the data connection line and the constant voltage line in this embodiment is similar to Figure 8 The illustrated embodiments are substantially the same, except that the line widths of the constant voltage traces in the first area (FIP area) and the second area (non-FIP area) are different.

[0421] In an exemplary embodiment, the width of the first constant voltage trace 91 in the first region may be greater than the width of the first constant voltage trace 91 in the second region, or the width of the second constant voltage trace 92 in the first region may be greater than the width of the second constant voltage trace 92 in the second region, or the width of the first constant voltage trace 91 in the first region may be greater than the width of the first constant voltage trace 91 in the second region, and the width of the second constant voltage trace 92 in the first region may be greater than the width of the second constant voltage trace 92 in the second region. The width of the first constant voltage trace 91 may be the dimension in the second direction Y, and the width of the second constant voltage trace 92 may be the dimension in the first direction X.

[0422] In an exemplary embodiment, the first constant voltage trace 91 and the second constant voltage trace 92 can be respectively arranged in the first area and the second area. The first constant voltage trace 91 and the first connecting line 81 arranged in the first area are arranged in the same repeating unit row, the second constant voltage trace 92 and the second connecting line 82 arranged in the first area are arranged in the same insertion column, and only the first constant voltage trace 91 and the second constant voltage trace 92 are arranged in the second area, and the first connecting line 81 and the second connecting line 82 are not arranged. In this way, the grid density formed by the first constant voltage trace 91 and the second constant voltage trace 92 in the first area is lower than the grid density formed by the first constant voltage trace 91 and the second constant voltage trace 92 in the second area. The present disclosure can not only improve the display uniformity of the two areas, but also reduce the resistance of the constant voltage trace in the first area by setting the line width of the constant voltage trace in the first area to be greater than the line width of the constant voltage trace in the second area.

[0423] Figure 29 FIG. 1 is a structural diagram of another data connection line and constant voltage line according to an exemplary embodiment of the present disclosure. Figure 29 As shown, the main structure of the data connection line and the constant voltage line in this embodiment is similar to Figure 8 The illustrated embodiments are substantially the same, except that the second constant voltage trace 92 can transmit different constant voltage signals.

[0424] In an exemplary embodiment, the plurality of second constant voltage traces 92 can be divided into two groups. The second constant voltage traces 92 in the first group can be connected to the first constant voltage traces 91 through vias, and the second constant voltage traces 92 in the second group can be connected to the lateral traces 90 through vias. In the first direction X, the second constant voltage traces 92 in the first group and the second constant voltage traces 92 in the second group can be alternately arranged, forming a structure in which the second constant voltage traces 92 alternately transmit different constant voltage signals.

[0425] In an exemplary embodiment, the horizontal trace 90 may be the first initial signal line 41 , the second initial signal line 42 , the third initial signal line 43 , or the power connection line 62 , which is not limited in the present disclosure.

[0426] In an exemplary embodiment, the horizontal trace 90 and the second constant voltage trace 92 may be disposed on the same layer, or the horizontal trace 90 and the second constant voltage trace 92 may be disposed on different layers.

[0427] In an exemplary embodiment, the horizontal trace 90 and the second constant voltage trace 92 are provided in different conductive layers, and the orthographic projection of the horizontal trace 90 on the substrate can be set to at least partially overlap with the orthographic projection of the second constant voltage trace 92 on the substrate.

[0428] Figure 30 FIG. 1 is a structural diagram of another data connection line and constant voltage line according to an exemplary embodiment of the present disclosure. Figure 30 As shown, the main structure of the data connection line and the constant voltage line in this embodiment is similar to Figure 8 The illustrated embodiments are substantially the same, except that a second connection line 82 and a constant voltage connection line 93 are provided in the insertion column, and a constant voltage connection line 93 is provided in the unit column.

[0429] In an exemplary embodiment, a constant voltage connection line 93 can be set in at least one unit column, and two vertical lines can be set in at least one insertion column. The two vertical lines can be a second connection line 82 and a constant voltage connection line 93, or, can be a second power line 92 and a constant voltage connection line 93, that is, the second connection line 82 (second power line 92) is a 3-plug-in-1 structure, and the constant voltage connection line is a 1-plug-in-1 structure, which can further stabilize the constant voltage signal and further reduce power consumption.

[0430] In an exemplary embodiment, the constant voltage connection line 93 may be connected to the first initial signal line, the second initial signal line, or the third initial signal line to form a mesh connection structure for transmitting the initial signal, which is not limited in the present disclosure.

[0431] In an exemplary embodiment, the constant voltage connection line 93 may be disposed between the second connection line 82 and the data signal line 70 , which may effectively prevent crosstalk of the data signal.

[0432] In an exemplary embodiment, for the case where the constant voltage connection line 93 is not set between the second connection line 82 and the data signal line 70, the spacing between the constant voltage connection line 93 and the data signal line 70 can be set to be smaller than the spacing between the constant voltage connection line 93 and the second connection line 82, and the spacing can be the dimension in the first direction X.

[0433] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0434] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0435] The present disclosure also provides a method for preparing a display substrate to prepare the aforementioned display substrate. In an exemplary embodiment, the method for preparing a display substrate may include: forming a driving structure layer on a substrate;

[0436] The driving structure layer includes a plurality of repeating units forming a plurality of repeating unit rows and a plurality of repeating unit columns, and an insertion column is arranged between adjacent repeating unit columns; at least one repeating unit includes a plurality of circuit units arranged in sequence along a first direction, at least one circuit unit includes a pixel driving circuit and a data signal line extending along a second direction, the data signal line is connected to the pixel driving circuit, and the data signal line is configured to provide a data signal to the pixel driving circuit, and the first direction and the second direction intersect; the driving structure layer also includes at least one first connecting line and at least one first constant voltage line extending along the first direction, and at least one second connecting line and at least one second constant voltage line extending along the second direction, the first end of the first connecting line is connected to the data signal line, the second end of the first connecting line is connected to the second connecting line, and at least one second constant voltage line is connected to at least one first constant voltage line to form a meshed connection structure for transmitting a constant voltage signal; the second connecting line and the second constant voltage line are arranged in the insertion column.

[0437] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0438] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: It includes a driving structure layer arranged on a substrate; the driving structure layer includes multiple repeating units forming multiple repeating unit rows and multiple repeating unit columns, and an insertion column is arranged between adjacent repeating unit columns; at least one repeating unit includes multiple circuit units arranged in sequence along a first direction, at least one circuit unit includes a pixel driving circuit and a data signal line extending along a second direction, the data signal line is connected to the pixel driving circuit, and the data signal line is configured to provide a data signal to the pixel driving circuit, and the first direction and the second direction intersect; the driving structure layer also includes at least one first connecting line and at least one first constant voltage line extending along the first direction, and at least one second connecting line and at least one second constant voltage line extending along the second direction, the first end of the first connecting line is connected to the data signal line, the second end of the first connecting line is connected to the second connecting line, and at least one second constant voltage line is connected to at least one first constant voltage line to form a mesh connection structure for transmitting constant voltage signals; the second connecting line and the second constant voltage line are arranged in the insertion column.

2. The display substrate according to claim 1, wherein: At least one repeating unit includes three circuit units.

3. The display substrate according to claim 1, wherein The pixel driving circuit at least includes a storage capacitor, a first transistor serving as a first initialization transistor, and a second transistor serving as a compensation transistor, the first transistor including at least a first gate electrode and a first active layer, the second transistor including at least a second gate electrode and a second active layer, the storage capacitor including a first electrode plate and a second electrode plate, an orthographic projection of the second electrode plate on the substrate at least partially overlapping with an orthographic projection of the first electrode plate on the substrate, the first electrode plate being connected to the second region of the first active layer and the first region of the second active layer, and the second electrode plate being connected to a first power line; At least one circuit unit further includes a shielding electrode, the shielding electrode being connected to the second electrode plate, the orthographic projection of the shielding electrode on the substrate at least partially overlapping with the orthographic projection of the first active layer between the two gate electrodes of the first transistor on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlapping with the orthographic projection of the second active layer between the two gate electrodes of the second transistor on the substrate; An orthographic projection of at least one second connecting line on the substrate at least partially overlaps with an orthographic projection of the shielding electrode on the substrate.

4. The display substrate according to claim 3, wherein: The pixel driving circuit also includes a third transistor serving as a driving transistor and a fourth transistor serving as a data writing transistor, the third transistor including at least a third active layer, the fourth transistor including at least a fourth active layer, the first region of the third active layer being connected to the second region of the fourth active layer; at least one circuit unit also includes a compensation electrode connected to the second electrode plate, an orthographic projection of the compensation electrode on the substrate at least partially overlapping with an orthographic projection of a connection region between the first region of the third active layer and the second region of the fourth active layer on the substrate.

5. The display substrate according to claim 3, wherein: The pixel driving circuit also includes a fourth transistor serving as a data writing transistor, the second gate electrode being connected to the first scanning signal line extending along the first direction, the gate electrode of the fourth transistor being connected to the second scanning signal line extending along the first direction, the first electrode of the fourth transistor being connected to the data signal line, and the second scanning signal line being arranged on a side of the first scanning signal line away from the second electrode plate; in the second direction, the first connecting line and the first constant voltage routing are arranged between the first scanning signal line and the second electrode plate, or the first connecting line and the first constant voltage routing are arranged between the first scanning signal line and the second scanning signal line.

6. The display substrate according to claim 5, wherein: At least one circuit unit further includes a data connection electrode, the data signal line is connected to the data connection electrode through a via, and the data connection electrode is connected to the first electrode of the fourth transistor through a via; at least one repeating unit further includes a data connection block, the data connection block is respectively connected to the first connection line and the data connection electrode in a circuit unit, and the data connection block is arranged on a side of the first scanning signal line close to the second electrode plate.

7. The display substrate according to claim 5, wherein: At least one repeating unit further includes a data connection block connected to the first connection line, the data connection block is connected to the first electrode of the fourth transistor in a circuit unit through a via, the data signal line is connected to the data connection block through a via, and the data connection block is arranged on the side of the first scanning signal line away from the second electrode plate.

8. The display substrate according to claim 3, wherein: The pixel driving circuit also includes a fifth transistor serving as a first light-emitting control transistor, the gate electrode of the fifth transistor being connected to a light-emitting signal line, the first electrode of the fifth transistor being connected to the first power line, and the light-emitting signal line being arranged on one side of the second electrode plate in the second direction; in the second direction, the first connecting line and the first constant voltage trace are arranged on a side of the light-emitting signal line away from the second electrode plate.

9. The display substrate according to claim 1, wherein: The display substrate further includes a light emitting structure layer provided on a side of the driving structure layer away from the substrate, the light emitting structure layer including at least a red light emitting unit, a green light emitting unit, and a blue light emitting unit, the red light emitting unit including at least a first anode, the green light emitting unit including at least a second anode, and the blue light emitting unit including at least a third anode; The orthographic projections of at least one first anode and at least one second anode on the substrate at least partially overlap with the orthographic projections of the second connecting line or the second constant voltage line on the substrate, and the orthographic projection of at least one third anode on the substrate at least partially overlap with the orthographic projection of the data signal line on the substrate.

10. The display substrate according to claim 9, wherein: At least one third anode is provided with an anode groove, which is in the shape of a strip extending along the second direction, and an orthographic projection of the anode groove on the substrate at least partially overlaps with an orthographic projection of the data signal line on the substrate.

11. The display substrate according to claim 1, wherein At least one insertion column is also provided with at least one constant voltage connection line extending along the second direction; in the first direction, the constant voltage connection line is arranged between the second connection line and the data signal line, or the constant voltage connection line is arranged between the second constant voltage routing line and the data signal line.

12. The display substrate according to claim 11, wherein: At least one circuit unit also includes a first initial signal line, a second initial signal line and a third initial signal line extending along the first direction, the pixel driving circuit is connected to the first initial signal line, the second initial signal line and the third initial signal line, respectively, the first initial signal line, the second initial signal line and the third initial signal line are configured to provide the first initial signal, the second initial signal and the third initial signal to the pixel driving circuit, respectively; at least one of the constant voltage connection lines is connected to the first initial signal line, the second initial signal line or the third initial signal line.

13. The display substrate according to any one of claims 1 to 12, characterized in that: The display substrate further includes a light emitting structure layer disposed on a side of the driving structure layer away from the substrate, the light emitting structure layer including a plurality of light emitting units, at least one of which includes a light emitting device, the light emitting device being connected to a second power line, and the second power line being configured to provide a second power signal to the light emitting device; At least one circuit unit also includes a first initial signal line, a second initial signal line, a third initial signal line extending along the first direction, and a first power line extending along the second direction, the pixel driving circuit is respectively connected to the first initial signal line, the second initial signal line, the third initial signal line and the first power line, the first initial signal line, the second initial signal line and the third initial signal line are configured to provide the first initial signal, the second initial signal and the third initial signal to the pixel driving circuit, respectively, and the first power line is configured to provide the first power signal to the pixel driving circuit; the second constant voltage routing is connected to any one or more of the following: the first initial signal line, the second initial signal line, the third initial signal line, the first power line or the second power line.

14. The display substrate according to claim 13, wherein: The display substrate is divided into multiple sub-areas, the second constant voltage routing in one sub-area is connected to the first initial signal line, the second constant voltage routing in another sub-area is connected to the second initial signal line, and the second constant voltage routing in yet another sub-area is connected to the third initial signal line, thereby forming a meshed connectivity structure for transmitting the first initial signal, a meshed connectivity structure for transmitting the second initial signal, and a meshed connectivity structure for transmitting the third initial signal.

15. The display substrate according to claim 13, wherein Multiple second constant voltage lines are respectively connected to the first initial signal line, the second initial signal line and the third initial signal line. In the first direction, the second constant voltage lines connected to the first initial signal line, the second constant voltage lines connected to the second initial signal line, and the second constant voltage lines connected to the third initial signal line are arranged periodically.

16. The display substrate according to claim 13, wherein: Multiple second constant voltage traces are respectively connected to the first initial signal line, the second initial signal line, the third initial signal line and the second power line. In the first direction, the second constant voltage trace connected to the first initial signal line, the second constant voltage trace connected to the second power line, the second constant voltage trace connected to the second initial signal line, the second constant voltage trace connected to the second power line, the second constant voltage trace connected to the third initial signal line, and the second constant voltage trace connected to the second power line are periodically arranged.

17. The display substrate according to claim 13, wherein: The second constant voltage line located in the same insertion column as the second connection line is connected to the first power line or the second power line, and the second constant voltage line separately arranged in the insertion column is connected to the first initial signal line, the second initial signal line or the third initial signal line.

18. The display substrate according to claim 13, wherein: In a direction perpendicular to the base, the display substrate includes multiple conductive layers, the second constant voltage line, the first constant voltage line and at least one initial signal line are arranged in different conductive layers, a portion of the second constant voltage line is connected to the first constant voltage line, and another portion of the second constant voltage line is connected to the initial signal line.

19. A display device, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 18.

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