1553B and CAN bus data conversion device based on FPGA
Through the FPGA-based 1553B and CAN bus data conversion device, the parallel processing and low latency characteristics of FPGA are used to solve the problem of delay and signal loss during data conversion of 1553B bus and CAN bus, and efficient data conversion and system simplification are achieved.
Patent Information
- Application Number
- CN202422287286.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2034-09-19
AI Technical Summary
During data conversion, the 1553B bus and the CAN bus have problems such as large data transmission delay and high signal loss risk. The existing technical solutions such as DSP+CPLD and FPGA+ARM have problems such as insufficient real-time data processing or system complexity.
The FPGA chip is used as the core processing unit, combined with the 1553B bus transceiver, CAN bus controller and CAN bus transceiver, data conversion is realized through the bus data conversion module, the 1553B bus protocol analysis module and the CAN bus controller driver module, and the parallel processing and low latency characteristics of FPGA are used to reduce external devices and simplify the hardware structure.
The data conversion process of 1553B and CAN bus is optimized to meet the needs of high-speed signals and real-time, improve system integration, reduce power consumption and space occupation, and is suitable for application scenarios with power consumption-sensitive and space-constrained.
Smart Images
Figure CN223217858U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of communication, in particular to a 1553B and CAN bus data conversion device based on FPGA. Background Art
[0002] With the development of electronic bus systems, 1553B and CAN bus have become data bus standards. 1553B is primarily used in aerospace and military systems, where stability is paramount. CAN bus is primarily used in automotive, industrial control, and medical equipment, where real-time performance is paramount. 1553B focuses on physical layer protocol specifications, while CAN bus emphasizes link layer protocol specifications. Therefore, each has its own strengths. The 1553B bus's strict physical layer specifications give it an inherent advantage in reliability. Furthermore, its use of short frames and a single master node in the network contributes to its superior control and real-time performance. The CAN bus, on the other hand, features a selectable master node, making it easier to correct errors. Each frame includes error detection features such as CRC, effectively reducing data error rates. The CAN bus uses NRZ encoding and decoding for signal modulation and demodulation, along with bit stuffing technology. This ensures strong signal transmission reliability and interference immunity, making it suitable for control or data transmission in harsh environments.
[0003] The 1553B bus is a command / response type bus. Data transmission is achieved by issuing commands through the master node bus controller. After receiving the commands, the remote nodes return the data to the master node or the corresponding node in a corresponding manner. If a sub-node cannot immediately feedback the signal when an abnormality occurs, the sub-node must wait until the bus controller issues a transmission command, resulting in low transmission efficiency and low flexibility. The CAN bus is a multi-competition bus that can better solve the problems of the 1553B bus. However, the CAN bus does not have a dual-redundant or multi-redundant structure design, which reduces the reliability of signal transmission. Currently, due to the extremely high requirements of aerospace electronic bus systems for reliability and real-time performance, the 1553B bus is adopted in accordance with aerospace design standards. However, some test, launch and control systems are designed using the CAN bus. The two buses have different performance characteristics, such as communication protocols, data formats, transmission rates, and real-time performance. This results in poor communication performance between the two systems, large data transmission delays, and the risk of data loss. There are currently two solutions for implementing 1553B and CAN bus conversion systems:
[0004] The first solution, based on a DSP+CPLD, implements data conversion between 1553B and CAN bus data. Due to the maturity of DSP technology, the design and development of the CAN bus control portion is relatively simple. However, the DSP processes data sequentially, which doesn't take advantage of parallel processing. This significantly limits its real-time performance and, to a certain extent, restricts the data throughput of the bus data conversion system.
[0005] The second solution utilizes an FPGA + ARM dual processor. The FPGA is used for 1553B protocol parsing, while the ARM is used for 1553B and CAN data conversion. The Linux system ported to the ARM increases the reliability and real-time performance of data conversion. However, the ARM only converts two bus signals within the entire conversion system. Furthermore, the ARM is expensive, complicating the overall system design and wasting resources. Utility Model Content
[0006] The purpose of the utility model is to overcome the shortcomings of the prior art in which the data transmission delay is large and signal loss is easily caused when converting data between the 1553B bus and the CAN bus, and to provide a 1553B and CAN bus data conversion device based on FPGA.
[0007] The purpose of this utility model is achieved through the following technical solutions:
[0008] A 1553B and CAN bus data conversion device based on FPGA includes a 1553B bus transceiver, an FPGA chip, a CAN bus controller and a CAN bus transceiver. The 1553B bus transceiver is connected to the FPGA chip via a 1553B interface circuit. The FPGA chip is also connected to the CAN bus controller via a CAN interface circuit. The CAN bus controller is also connected to the CAN bus transceiver. The 1553B bus transceiver is also connected to the 1553B bus. The CAN bus transceiver is also connected to the CAN bus.
[0009] The 1553B bus transceiver receives the 1553B digital signal sent by the 1554B bus and forwards the 1553B digital signal to the FPGA chip, or the 1553B bus transceiver receives the 1553B digital signal sent by the FPGA and then forwards the 1553B digital signal to the 1554B bus; the FPGA chip is the main control chip, which receives the 1553B digital signal sent by the 1553B bus transceiver and the CAN digital signal sent by the CAN bus controller and processes and converts it, converts the 1553B digital signal into a CAN digital signal and sends it to the CAN bus controller, and converts the CAN digital signal into a 1553B digital signal and sends it to the 1553B bus transceiver; the CAN bus controller receives the CAN digital signal sent by the FPGA chip and sends it to the CAN bus transceiver, or the CAN bus controller receives the CAN digital signal sent by the CAN bus transceiver and sends it to the FPGA; the CAN bus transceiver is set between the CAN bus controller and the CAN bus for sending and receiving CAN digital signals.
[0010] Preferably, the FPGA chip includes a bus data conversion module, a 1553B bus protocol analysis module and a CAN bus controller driver module, and the bus data conversion module is connected to the 1553B bus protocol analysis module and the CAN bus controller driver module at the same time.
[0011] The CAN bus is connected at the physical layer through the CAN bus interface circuit and the CAN bus cable, and the CAN bus controller and its driver jointly complete the CAN bus data frame identification, verification, response and other protocol processing, and send the data to the bus data conversion module for data conversion; at the same time, this module can also receive the 1553B bus data after bus data conversion, encapsulate it into the CAN protocol, and send it to the CAN bus.
[0012] The bus data conversion module receives the CAN bus data sent by the CAN bus driver module, converts it into 1553B data and sends it to the 1553B bus protocol analysis module; at the same time, it can also receive data from the 1553B bus protocol analysis module, convert the 1553B bus data into CAN bus data, and send it to the CAN bus driver module for protocol encapsulation.
[0013] The 1553B bus protocol parsing module and the 1553B bus interface circuit constitute an independent RT node, which can communicate with the BC according to the protocol; not only that, this module can also send the received 1553B data to the bus data conversion module for data conversion, and can also receive data sent by the bus data conversion module and send it to the 1553B bus according to the protocol.
[0014] Preferably, the bus data conversion module includes a built-in dual-port RAM of the FPGA chip. The bus data conversion module controls the writing and reading of data of the dual-port RAM by calling the IP core to realize data conversion between CAN bus data and 1553B data.
[0015] Preferably, the FPGA-based 1553B and CAN bus data conversion device further includes an optical coupling chip, which is arranged between the CAN bus controller and the CAN bus transceiver for enhancing the CAN bus data signal.
[0016] Preferably, the 1553B bus transceiver includes a 1553B transceiver chip, a 1553B isolation transformer and a 1553B coupling transformer, the 1554B isolation transformer is connected to the 1554B bus and the 1553B coupling transformer at the same time, the 1553B coupling transformer is also connected to the 1553B transceiver chip, and the 1553B transceiver chip is connected to the FPGA chip.
[0017] Preferably, the 1553B interface circuit is an SPI bus interface circuit, and the 1553B bus transceiver is connected to the FPGA chip via the SPI bus interface circuit.
[0018] The beneficial effects of the present invention are as follows: the present invention uses FPGA as the core processing unit to realize data conversion between the 1553B bus and the CAN bus. Since a large number of logic units, storage units and programmable connection resources are integrated inside the FPGA, more complex functional modules can be realized, thereby reducing the number of required external devices and circuit space, avoiding the hardware complexity caused by the switching of other hardware such as DSP and ARM, streamlining the hardware structure, making the circuit of the entire conversion system simpler, and improving the system integration.
[0019] The utility model makes full use of the parallel processing and low latency characteristics of FPGA, can optimize the data conversion process between 1553B bus and CAN bus, and meet the needs of high-speed signal and real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is an overall implementation framework diagram of the utility model;
[0021] Figure 2 This is a circuit principle connection diagram of the utility model;
[0022] Figure 3 This is a schematic diagram of the internal modules of the FPGA of the present utility model;
[0023] Figure 4 It is a flow chart of data conversion of the present utility model. DETAILED DESCRIPTION
[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0025] Example:
[0026] A 1553B and CAN bus data conversion device based on FPGA, such as Figure 1 、 Figure 2 As shown, it includes a 1553B bus transceiver, an FPGA chip, a CAN bus controller and a CAN bus transceiver. The 1553B bus transceiver is connected to the FPGA chip through a 1553B interface circuit. The FPGA chip is also connected to the CAN bus controller through a CAN interface circuit. The CAN bus controller is also connected to the CAN bus transceiver; the 1553B bus transceiver is also connected to the 1553B bus, and the CAN bus transceiver is also connected to the CAN bus.
[0027] The 1553B and CAN bus data conversion device based on FPGA also includes an optical coupling chip, which is arranged between the CAN bus controller and the CAN bus transceiver and is used to enhance the CAN bus data signal.
[0028] The 1553B bus transceiver includes a 1553B transceiver chip, a 1553B isolation transformer and a 1553B coupling transformer. The 1554B isolation transformer is connected to the 1554B bus and the 1553B coupling transformer at the same time. The 1553B coupling transformer is also connected to the 1553B transceiver chip, and the 1553B transceiver chip is connected to the FPGA chip.
[0029] The 1553B interface circuit is an SPI bus interface circuit, and the 1553B bus transceiver is connected to the FPGA chip via the SPI bus interface circuit.
[0030] In this embodiment, the 1553B bus transceiver receives 1553B signals from two 1553B interfaces through a dual-channel isolation transformer and processes the 1553B signals accordingly. It can also process multiple 1553B signals according to actual needs.
[0031] The 1553B bus transceiver receives the 1553B digital signal sent by the 1554B bus and forwards the 1553B digital signal to the FPGA chip, or the 1553B bus transceiver receives the 1553B digital signal sent by the FPGA and then forwards the 1553B digital signal to the 1554B bus; the FPGA chip is the main control chip, which receives the 1553B digital signal sent by the 1553B bus transceiver and the CAN digital signal sent by the CAN bus controller and processes and converts it, converts the 1553B digital signal into a CAN digital signal and sends it to the CAN bus controller, and converts the CAN digital signal into a 1553B digital signal and sends it to the 1553B bus transceiver; the CAN bus controller receives the CAN digital signal sent by the FPGA chip and sends it to the CAN bus transceiver, or the CAN bus controller receives the CAN digital signal sent by the CAN bus transceiver and sends it to the FPGA; the CAN bus transceiver is set between the CAN bus controller and the CAN bus for sending and receiving CAN digital signals.
[0032] like Figure 3 As shown, the FPGA chip includes a bus data conversion module, a 1553B bus protocol analysis module and a CAN bus controller driver module, and the bus data conversion module is connected to the 1553B bus protocol analysis module and the CAN bus controller driver module at the same time.
[0033] The CAN bus is connected at the physical layer through the CAN bus interface circuit and the CAN bus cable, and the CAN bus controller and its driver jointly complete the CAN bus data frame identification, verification, response and other protocol processing, and send the data to the bus data conversion module for data conversion; at the same time, this module can also receive the 1553B bus data after bus data conversion, encapsulate it into the CAN protocol, and send it to the CAN bus.
[0034] The bus data conversion module receives the CAN bus data sent by the CAN bus driver module, converts it into 1553B data and sends it to the 1553B bus protocol analysis module; at the same time, it can also receive data from the 1553B bus protocol analysis module, convert the 1553B bus data into CAN bus data, and send it to the CAN bus driver module for protocol encapsulation.
[0035] The 1553B bus protocol parsing module and the 1553B bus interface circuit constitute an independent RT node, which can communicate with the BC according to the protocol; not only that, this module can also send the received 1553B data to the bus data conversion module for data conversion, and can also receive data sent by the bus data conversion module and send it to the 1553B bus according to the protocol.
[0036] The bus data conversion module includes a built-in dual-port RAM of the FPGA chip. The bus data conversion module controls the writing and reading of data in the dual-port RAM by calling the IP core to realize data conversion between CAN bus data and 1553B data.
[0037] In order to meet the bidirectional data conversion function implemented by the present invention, Figure 4 As shown in the figure, a bidirectional design is also required in the software. One is the process of the 1553B bus receiving data and converting it into CAN bus data, and the other is the process of the CAN bus receiving data and converting it into 1553B bus data.
[0038] The 1553B bus receives data and converts it into CAN bus data: When the converter receives the receive data command sent by the 1553B bus BC, it returns a status word and stores the data in the data receive RAM of the 1553B bus RT module. After data conversion, the data is written into the transmit buffer of the CAN bus controller. The converter also detects the bus status and sends the data in the transmit buffer to the CAN bus when it detects that the bus is idle or has the highest priority.
[0039] The CAN bus receives data and converts it into 1553B bus data: When the CAN bus controller receives message data on the CAN bus, the CAN bus controller sets the corresponding register. When the CAN bus controller driver module detects that the register is set, it reads the data in the receive buffer of the CAN bus controller for judgment. When it is judged to be a remote frame, it responds according to the CAN bus protocol; when it is judged to be a data frame, it converts the data into 1553B data and stores it in the transmit RAM of the 1553B bus RT module, waiting to be sent to the 1553B bus; when the 1553B bus RT receives the send data command, it sends the data in the transmit RAM to the 1553B bus.
[0040] In this embodiment, the 1553B and CAN bus data conversion systems are configured to configure the frame ID codes of the buses at both ends using the dip switches on the FPGA chip. Generally, the dip switches on the FPGA chip are used as part of the input / output pins or as software configuration to perform some initialization operations. In the present invention, for the 1553B and CAN bus data conversion systems, the frame ID code is an important parameter for distinguishing different data frames. The value of the ID code can be configured by using dip switches. Each dip switch corresponds to a binary bit. Combining the states of multiple dip switches can represent a complete frame ID code. This avoids the traditional software configuration method and eliminates the need to write additional configuration programs, thereby simplifying the configuration process and improving the convenience of operation.
[0041] Compared with traditional hardware solutions, the FPGA used in this embodiment has lower power consumption and smaller size, and is particularly suitable for power-sensitive and space-constrained application scenarios.
[0042] In this embodiment, the CAN interface of the present invention may not be configured with filters and shields according to the actual usage of the CAN interface, so that the present invention is also applicable to the communication between CAN bus devices and 1553B buses, expanding the scope of use of the converter and improving the flexibility of the converter.
[0043] The embodiment described above is only a preferred solution of the present invention and does not limit the present invention in any form. Other variations and modifications are possible without exceeding the technical solutions described in the claims.
Claims
1. A 1553B and CAN bus data conversion device based on FPGA, characterized in that: It includes a 1553B bus transceiver, an FPGA chip, a CAN bus controller and a CAN bus transceiver. The 1553B bus transceiver is connected to the FPGA chip via a 1553B interface circuit. The FPGA chip is also connected to the CAN bus controller via a CAN interface circuit. The CAN bus controller is also connected to the CAN bus transceiver. The 1553B bus transceiver is also connected to the 1553B bus, and the CAN bus transceiver is also connected to the CAN bus.
2. The 1553B and CAN bus data conversion device based on FPGA according to claim 1, characterized in that: The FPGA chip includes a bus data conversion module, a 1553B bus protocol analysis module and a CAN bus controller driver module. The bus data conversion module is connected to the 1553B bus protocol analysis module and the CAN bus controller driver module at the same time.
3. The 1553B and CAN bus data conversion device based on FPGA according to claim 2, characterized in that: The bus data conversion module includes a built-in dual-port RAM of the FPGA chip. The bus data conversion module controls the writing and reading of data in the dual-port RAM by calling the IP core to realize data conversion between CAN bus data and 1553B data.
4. The 1553B and CAN bus data conversion device based on FPGA according to claim 1 is characterized in that: It also includes an optical coupling chip, which is arranged between the CAN bus controller and the CAN bus transceiver and is used to enhance the CAN bus data signal.
5. The 1553B and CAN bus data conversion device based on FPGA according to claim 1 is characterized in that: The 1553B bus transceiver includes a 1553B transceiver chip, a 1553B isolation transformer and a 1553B coupling transformer. The 1554B isolation transformer is connected to the 1554B bus and the 1553B coupling transformer at the same time. The 1553B coupling transformer is also connected to the 1553B transceiver chip, and the 1553B transceiver chip is connected to the FPGA chip.
6. The 1553B and CAN bus data conversion device based on FPGA according to claim 1 is characterized in that: The 1553B interface circuit is an SPI bus interface circuit, and the 1553B bus transceiver is connected to the FPGA chip via the SPI bus interface circuit.